[PATCH 0/4] SKL watermark algorithm updates

[PATCH 0/4] SKL watermark algorithm updates

[Matt Roper]

These patches from Mahesh address places where our SKL-style watermark
programming does not match the current bspec rules, either because the bspec
was updated after the original code was written, or because new display
features (e.g., plane scaling) were added without corresponding updates to the
watermark code.

Mahesh wrote these patches a long time ago, but due to other churn in the
driver they never made it in.  The work here is all orthogonal to the atomic
watermark stuff I've been doing lately, but landing atomic watermarks did
require major changes to the flow of the code in this series, so these patches
have been nearly completely rewritten at this point.  You can thank Mahesh for
any bugs these fix, but blame me for any new bugs they contain.

At the moment I've dropped the final patches here for the arbitrated display
bandwidth workaround that was previously part of this series; I'm working on a
new method of obtaining the data we need for that workaround that's less
fragile than the DMI method previously attempted and will post that workaround
separately after this series lands.

Cc: Kumar, Mahesh <mahesh1.kumar@intel.com>


Kumar, Mahesh (3):
  drm/i915/skl+: calculate ddb minimum allocation (v4)
  drm/i915/skl+: calculate plane pixel rate (v4)
  drm/i915/skl+: Use scaling amount for plane data rate calculation (v3)

Matt Roper (1):
  drm/i915: Don't try to calculate relative data rates during hw readout

 drivers/gpu/drm/i915/intel_pm.c | 166 ++++++++++++++++++++++++++++++++--------
 1 file changed, 136 insertions(+), 30 deletions(-)

-- 
2.1.4

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[PATCH 1/4] drm/i915: Don't try to calculate relative data rates during hw readout

[Matt Roper]

We don't actually read out full plane state during driver startup (only
whether the primary plane is enabled/disabled), so all of the src/dest
rectangles are invalid at this point.  However this calculation was
needless anyway since we re-calculate them from scratch on the very
first atomic transaction after boot anyway.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adb6463..95f9bb5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4042,7 +4042,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
 	struct drm_crtc *crtc;
-	struct intel_crtc *intel_crtc;
 
 	skl_ddb_get_hw_state(dev_priv, ddb);
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
@@ -4055,23 +4054,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
 		/* Easy/common case; just sanitize DDB now if everything off */
 		memset(ddb, 0, sizeof(*ddb));
 	}
-
-	/* Calculate plane data rates */
-	for_each_intel_crtc(dev, intel_crtc) {
-		struct intel_crtc_state *cstate = intel_crtc->config;
-		struct intel_plane *intel_plane;
-
-		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-			const struct drm_plane_state *pstate =
-				intel_plane->base.state;
-			int id = skl_wm_plane_id(intel_plane);
-
-			cstate->wm.skl.plane_data_rate[id] =
-				skl_plane_relative_data_rate(cstate, pstate, 0);
-			cstate->wm.skl.plane_y_data_rate[id] =
-				skl_plane_relative_data_rate(cstate, pstate, 1);
-		}
-	}
 }
 
 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
-- 
2.1.4

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[PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v4)

[Matt Roper]

From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

don't always use 8 ddb as minimum, instead calculate using proper
algorithm.

v2: optimizations as per Matt's comments.

v3 (by Matt):
 - Fix boolean logic for !fb test in skl_ddb_min_alloc()
 - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to
   improve readability.

v4 (by Matt):
 - Rebase onto recent atomic watermark changes
 - Slight tweaks to code flow to make the logic more closely match the
   description in the bspec.

Cc: matthew.d.roper@intel.com
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 62 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 57 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 95f9bb5..d7165b5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3038,6 +3038,61 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
 	return total_data_rate;
 }
 
+static uint16_t
+skl_ddb_min_alloc(const struct drm_plane_state *pstate,
+		  const int y)
+{
+	struct drm_framebuffer *fb = pstate->fb;
+	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
+	uint32_t src_w, src_h;
+	uint32_t min_scanlines = 8;
+	uint8_t plane_bpp;
+
+	if (WARN_ON(!fb))
+		return 0;
+
+	/* For packed formats, no y-plane, return 0 */
+	if (y && fb->pixel_format != DRM_FORMAT_NV12)
+		return 0;
+
+	/* For Non Y-tile return 8-blocks */
+	if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
+	    fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
+		return 8;
+
+	src_w = drm_rect_width(&intel_pstate->src) >> 16;
+	src_h = drm_rect_height(&intel_pstate->src) >> 16;
+
+	if (intel_rotation_90_or_270(pstate->rotation))
+		swap(src_w, src_h);
+
+	/* Halve UV plane width and height for NV12 */
+	if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
+		src_w /= 2;
+		src_h /= 2;
+	}
+
+	plane_bpp = y ? drm_format_plane_cpp(fb->pixel_format, 0) :
+		drm_format_plane_cpp(fb->pixel_format, 1);
+
+	if (intel_rotation_90_or_270(pstate->rotation)) {
+		switch (plane_bpp) {
+		case 1:
+			min_scanlines = 32;
+			break;
+		case 2:
+			min_scanlines = 16;
+			break;
+		default:
+			WARN(1, "Unsupported pixel depth %u for rotation",
+			     plane_bpp);
+			min_scanlines = 32;
+		}
+	}
+
+	return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		      struct skl_ddb_allocation *ddb /* out */)
@@ -3100,11 +3155,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 			continue;
 		}
 
-		minimum[id] = 8;
-		if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
-			y_minimum[id] = 8;
-		else
-			y_minimum[id] = 0;
+		minimum[id] = skl_ddb_min_alloc(pstate, 0);
+		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	for (i = 0; i < PLANE_CURSOR; i++) {
-- 
2.1.4

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[PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v5)

[Matt Roper]

From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

don't always use 8 ddb as minimum, instead calculate using proper
algorithm.

v2: optimizations as per Matt's comments.

v3 (by Matt):
 - Fix boolean logic for !fb test in skl_ddb_min_alloc()
 - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to
   improve readability.

v4 (by Matt):
 - Rebase onto recent atomic watermark changes
 - Slight tweaks to code flow to make the logic more closely match the
   description in the bspec.

v5 (by Matt):
 - Handle minimum scanline calculation properly for 4 & 8 bpp formats.
   8bpp isn't actually possible right now, but it's listed in the bspec
   so I've included it here for forward compatibility (similar to how
   we have logic for NV12).

Cc: matthew.d.roper@intel.com
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 68 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 63 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3cf36dc..00b50bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3042,6 +3042,67 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
 	return total_data_rate;
 }
 
+static uint16_t
+skl_ddb_min_alloc(const struct drm_plane_state *pstate,
+		  const int y)
+{
+	struct drm_framebuffer *fb = pstate->fb;
+	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
+	uint32_t src_w, src_h;
+	uint32_t min_scanlines = 8;
+	uint8_t plane_bpp;
+
+	if (WARN_ON(!fb))
+		return 0;
+
+	/* For packed formats, no y-plane, return 0 */
+	if (y && fb->pixel_format != DRM_FORMAT_NV12)
+		return 0;
+
+	/* For Non Y-tile return 8-blocks */
+	if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
+	    fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
+		return 8;
+
+	src_w = drm_rect_width(&intel_pstate->src) >> 16;
+	src_h = drm_rect_height(&intel_pstate->src) >> 16;
+
+	if (intel_rotation_90_or_270(pstate->rotation))
+		swap(src_w, src_h);
+
+	/* Halve UV plane width and height for NV12 */
+	if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
+		src_w /= 2;
+		src_h /= 2;
+	}
+
+	plane_bpp = y ? drm_format_plane_cpp(fb->pixel_format, 0) :
+		drm_format_plane_cpp(fb->pixel_format, 1);
+
+	if (intel_rotation_90_or_270(pstate->rotation)) {
+		switch (plane_bpp) {
+		case 1:
+			min_scanlines = 32;
+			break;
+		case 2:
+			min_scanlines = 16;
+			break;
+		case 4:
+			min_scanlines = 8;
+			break;
+		case 8:
+			min_scanlines = 4;
+			break;
+		default:
+			WARN(1, "Unsupported pixel depth %u for rotation",
+			     plane_bpp);
+			min_scanlines = 32;
+		}
+	}
+
+	return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		      struct skl_ddb_allocation *ddb /* out */)
@@ -3104,11 +3165,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 			continue;
 		}
 
-		minimum[id] = 8;
-		if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
-			y_minimum[id] = 8;
-		else
-			y_minimum[id] = 0;
+		minimum[id] = skl_ddb_min_alloc(pstate, 0);
+		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	for (i = 0; i < PLANE_CURSOR; i++) {
-- 
2.1.4

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Re: [PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v5)

[Mahesh Kumar]

On Friday 27 May 2016 03:43 AM, Matt Roper wrote:
> From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
>
> don't always use 8 ddb as minimum, instead calculate using proper
> algorithm.
>
> v2: optimizations as per Matt's comments.
>
> v3 (by Matt):
>   - Fix boolean logic for !fb test in skl_ddb_min_alloc()
>   - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to
>     improve readability.
>
> v4 (by Matt):
>   - Rebase onto recent atomic watermark changes
>   - Slight tweaks to code flow to make the logic more closely match the
>     description in the bspec.
>
> v5 (by Matt):
>   - Handle minimum scanline calculation properly for 4 & 8 bpp formats.
>     8bpp isn't actually possible right now, but it's listed in the bspec
>     so I've included it here for forward compatibility (similar to how
>     we have logic for NV12).
>
> Cc: matthew.d.roper@intel.com
> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 68 ++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 63 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3cf36dc..00b50bf 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3042,6 +3042,67 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
>   	return total_data_rate;
>   }
>   
> +static uint16_t
> +skl_ddb_min_alloc(const struct drm_plane_state *pstate,
> +		  const int y)
> +{
> +	struct drm_framebuffer *fb = pstate->fb;
> +	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
> +	uint32_t src_w, src_h;
> +	uint32_t min_scanlines = 8;
> +	uint8_t plane_bpp;
> +
> +	if (WARN_ON(!fb))
> +		return 0;
> +
> +	/* For packed formats, no y-plane, return 0 */
> +	if (y && fb->pixel_format != DRM_FORMAT_NV12)
> +		return 0;
> +
> +	/* For Non Y-tile return 8-blocks */
> +	if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
> +	    fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
> +		return 8;
> +
> +	src_w = drm_rect_width(&intel_pstate->src) >> 16;
> +	src_h = drm_rect_height(&intel_pstate->src) >> 16;
> +
> +	if (intel_rotation_90_or_270(pstate->rotation))
> +		swap(src_w, src_h);
> +
> +	/* Halve UV plane width and height for NV12 */
> +	if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
> +		src_w /= 2;
> +		src_h /= 2;
> +	}
> +
> +	plane_bpp = y ? drm_format_plane_cpp(fb->pixel_format, 0) :
> +		drm_format_plane_cpp(fb->pixel_format, 1);
Here in case of y=0 we should call drm_format_plane_cpp with argument 0, 
(pixel formats which have number of plane 1)
else above function will return zero as plane BPP.

regards,
-Mahesh
> +
> +	if (intel_rotation_90_or_270(pstate->rotation)) {
> +		switch (plane_bpp) {
> +		case 1:
> +			min_scanlines = 32;
> +			break;
> +		case 2:
> +			min_scanlines = 16;
> +			break;
> +		case 4:
> +			min_scanlines = 8;
> +			break;
> +		case 8:
> +			min_scanlines = 4;
> +			break;
> +		default:
> +			WARN(1, "Unsupported pixel depth %u for rotation",
> +			     plane_bpp);
> +			min_scanlines = 32;
> +		}
> +	}
> +
> +	return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
> +}
> +
>   static int
>   skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>   		      struct skl_ddb_allocation *ddb /* out */)
> @@ -3104,11 +3165,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>   			continue;
>   		}
>   
> -		minimum[id] = 8;
> -		if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
> -			y_minimum[id] = 8;
> -		else
> -			y_minimum[id] = 0;
> +		minimum[id] = skl_ddb_min_alloc(pstate, 0);
> +		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
>   	}
>   
>   	for (i = 0; i < PLANE_CURSOR; i++) {

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[PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v6)

[Matt Roper]

From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

don't always use 8 ddb as minimum, instead calculate using proper
algorithm.

v2: optimizations as per Matt's comments.

v3 (by Matt):
 - Fix boolean logic for !fb test in skl_ddb_min_alloc()
 - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to
   improve readability.

v4 (by Matt):
 - Rebase onto recent atomic watermark changes
 - Slight tweaks to code flow to make the logic more closely match the
   description in the bspec.

v5 (by Matt):
 - Handle minimum scanline calculation properly for 4 & 8 bpp formats.
   8bpp isn't actually possible right now, but it's listed in the bspec
   so I've included it here for forward compatibility (similar to how
   we have logic for NV12).

v6 (by Matt):
 - Calculate plane_bpp correctly for non-NV12 formats. (Mahesh)

Cc: matthew.d.roper@intel.com
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 70 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 65 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3cf36dc..4e0a952 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3042,6 +3042,69 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
 	return total_data_rate;
 }
 
+static uint16_t
+skl_ddb_min_alloc(const struct drm_plane_state *pstate,
+		  const int y)
+{
+	struct drm_framebuffer *fb = pstate->fb;
+	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
+	uint32_t src_w, src_h;
+	uint32_t min_scanlines = 8;
+	uint8_t plane_bpp;
+
+	if (WARN_ON(!fb))
+		return 0;
+
+	/* For packed formats, no y-plane, return 0 */
+	if (y && fb->pixel_format != DRM_FORMAT_NV12)
+		return 0;
+
+	/* For Non Y-tile return 8-blocks */
+	if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
+	    fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
+		return 8;
+
+	src_w = drm_rect_width(&intel_pstate->src) >> 16;
+	src_h = drm_rect_height(&intel_pstate->src) >> 16;
+
+	if (intel_rotation_90_or_270(pstate->rotation))
+		swap(src_w, src_h);
+
+	/* Halve UV plane width and height for NV12 */
+	if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
+		src_w /= 2;
+		src_h /= 2;
+	}
+
+	if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
+		plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
+	else
+		plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
+
+	if (intel_rotation_90_or_270(pstate->rotation)) {
+		switch (plane_bpp) {
+		case 1:
+			min_scanlines = 32;
+			break;
+		case 2:
+			min_scanlines = 16;
+			break;
+		case 4:
+			min_scanlines = 8;
+			break;
+		case 8:
+			min_scanlines = 4;
+			break;
+		default:
+			WARN(1, "Unsupported pixel depth %u for rotation",
+			     plane_bpp);
+			min_scanlines = 32;
+		}
+	}
+
+	return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		      struct skl_ddb_allocation *ddb /* out */)
@@ -3104,11 +3167,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 			continue;
 		}
 
-		minimum[id] = 8;
-		if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
-			y_minimum[id] = 8;
-		else
-			y_minimum[id] = 0;
+		minimum[id] = skl_ddb_min_alloc(pstate, 0);
+		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	for (i = 0; i < PLANE_CURSOR; i++) {
-- 
2.1.4

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Re: [PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v6)

[Mahesh Kumar]

Reviewed-by: Kumar Mahesh <mahesh1.kumar@intel.com>

On Tuesday 31 May 2016 10:28 PM, Matt Roper wrote:
> From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
>
> don't always use 8 ddb as minimum, instead calculate using proper
> algorithm.
>
> v2: optimizations as per Matt's comments.
>
> v3 (by Matt):
>   - Fix boolean logic for !fb test in skl_ddb_min_alloc()
>   - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to
>     improve readability.
>
> v4 (by Matt):
>   - Rebase onto recent atomic watermark changes
>   - Slight tweaks to code flow to make the logic more closely match the
>     description in the bspec.
>
> v5 (by Matt):
>   - Handle minimum scanline calculation properly for 4 & 8 bpp formats.
>     8bpp isn't actually possible right now, but it's listed in the bspec
>     so I've included it here for forward compatibility (similar to how
>     we have logic for NV12).
>
> v6 (by Matt):
>   - Calculate plane_bpp correctly for non-NV12 formats. (Mahesh)
>
> Cc: matthew.d.roper@intel.com
> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 70 ++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 65 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3cf36dc..4e0a952 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3042,6 +3042,69 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
>   	return total_data_rate;
>   }
>   
> +static uint16_t
> +skl_ddb_min_alloc(const struct drm_plane_state *pstate,
> +		  const int y)
> +{
> +	struct drm_framebuffer *fb = pstate->fb;
> +	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
> +	uint32_t src_w, src_h;
> +	uint32_t min_scanlines = 8;
> +	uint8_t plane_bpp;
> +
> +	if (WARN_ON(!fb))
> +		return 0;
> +
> +	/* For packed formats, no y-plane, return 0 */
> +	if (y && fb->pixel_format != DRM_FORMAT_NV12)
> +		return 0;
> +
> +	/* For Non Y-tile return 8-blocks */
> +	if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
> +	    fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
> +		return 8;
> +
> +	src_w = drm_rect_width(&intel_pstate->src) >> 16;
> +	src_h = drm_rect_height(&intel_pstate->src) >> 16;
> +
> +	if (intel_rotation_90_or_270(pstate->rotation))
> +		swap(src_w, src_h);
> +
> +	/* Halve UV plane width and height for NV12 */
> +	if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
> +		src_w /= 2;
> +		src_h /= 2;
> +	}
> +
> +	if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
> +		plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
> +	else
> +		plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
> +
> +	if (intel_rotation_90_or_270(pstate->rotation)) {
> +		switch (plane_bpp) {
> +		case 1:
> +			min_scanlines = 32;
> +			break;
> +		case 2:
> +			min_scanlines = 16;
> +			break;
> +		case 4:
> +			min_scanlines = 8;
> +			break;
> +		case 8:
> +			min_scanlines = 4;
> +			break;
> +		default:
> +			WARN(1, "Unsupported pixel depth %u for rotation",
> +			     plane_bpp);
> +			min_scanlines = 32;
> +		}
> +	}
> +
> +	return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
> +}
> +
>   static int
>   skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>   		      struct skl_ddb_allocation *ddb /* out */)
> @@ -3104,11 +3167,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>   			continue;
>   		}
>   
> -		minimum[id] = 8;
> -		if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
> -			y_minimum[id] = 8;
> -		else
> -			y_minimum[id] = 0;
> +		minimum[id] = skl_ddb_min_alloc(pstate, 0);
> +		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
>   	}
>   
>   	for (i = 0; i < PLANE_CURSOR; i++) {

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Re: [PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v6)

[Matt Roper]

On Wed, Jun 01, 2016 at 07:55:18PM +0530, Mahesh Kumar wrote:
> Reviewed-by: Kumar Mahesh <mahesh1.kumar@intel.com>

Merged to dinq; thanks for the review (and thanks for doing the initial
work this series was based on).


Matt

> 
> On Tuesday 31 May 2016 10:28 PM, Matt Roper wrote:
> >From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
> >
> >don't always use 8 ddb as minimum, instead calculate using proper
> >algorithm.
> >
> >v2: optimizations as per Matt's comments.
> >
> >v3 (by Matt):
> >  - Fix boolean logic for !fb test in skl_ddb_min_alloc()
> >  - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to
> >    improve readability.
> >
> >v4 (by Matt):
> >  - Rebase onto recent atomic watermark changes
> >  - Slight tweaks to code flow to make the logic more closely match the
> >    description in the bspec.
> >
> >v5 (by Matt):
> >  - Handle minimum scanline calculation properly for 4 & 8 bpp formats.
> >    8bpp isn't actually possible right now, but it's listed in the bspec
> >    so I've included it here for forward compatibility (similar to how
> >    we have logic for NV12).
> >
> >v6 (by Matt):
> >  - Calculate plane_bpp correctly for non-NV12 formats. (Mahesh)
> >
> >Cc: matthew.d.roper@intel.com
> >Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
> >Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >---
> >  drivers/gpu/drm/i915/intel_pm.c | 70 ++++++++++++++++++++++++++++++++++++++---
> >  1 file changed, 65 insertions(+), 5 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index 3cf36dc..4e0a952 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3042,6 +3042,69 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
> >  	return total_data_rate;
> >  }
> >+static uint16_t
> >+skl_ddb_min_alloc(const struct drm_plane_state *pstate,
> >+		  const int y)
> >+{
> >+	struct drm_framebuffer *fb = pstate->fb;
> >+	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
> >+	uint32_t src_w, src_h;
> >+	uint32_t min_scanlines = 8;
> >+	uint8_t plane_bpp;
> >+
> >+	if (WARN_ON(!fb))
> >+		return 0;
> >+
> >+	/* For packed formats, no y-plane, return 0 */
> >+	if (y && fb->pixel_format != DRM_FORMAT_NV12)
> >+		return 0;
> >+
> >+	/* For Non Y-tile return 8-blocks */
> >+	if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
> >+	    fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
> >+		return 8;
> >+
> >+	src_w = drm_rect_width(&intel_pstate->src) >> 16;
> >+	src_h = drm_rect_height(&intel_pstate->src) >> 16;
> >+
> >+	if (intel_rotation_90_or_270(pstate->rotation))
> >+		swap(src_w, src_h);
> >+
> >+	/* Halve UV plane width and height for NV12 */
> >+	if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
> >+		src_w /= 2;
> >+		src_h /= 2;
> >+	}
> >+
> >+	if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
> >+		plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
> >+	else
> >+		plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
> >+
> >+	if (intel_rotation_90_or_270(pstate->rotation)) {
> >+		switch (plane_bpp) {
> >+		case 1:
> >+			min_scanlines = 32;
> >+			break;
> >+		case 2:
> >+			min_scanlines = 16;
> >+			break;
> >+		case 4:
> >+			min_scanlines = 8;
> >+			break;
> >+		case 8:
> >+			min_scanlines = 4;
> >+			break;
> >+		default:
> >+			WARN(1, "Unsupported pixel depth %u for rotation",
> >+			     plane_bpp);
> >+			min_scanlines = 32;
> >+		}
> >+	}
> >+
> >+	return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
> >+}
> >+
> >  static int
> >  skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> >  		      struct skl_ddb_allocation *ddb /* out */)
> >@@ -3104,11 +3167,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> >  			continue;
> >  		}
> >-		minimum[id] = 8;
> >-		if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
> >-			y_minimum[id] = 8;
> >-		else
> >-			y_minimum[id] = 0;
> >+		minimum[id] = skl_ddb_min_alloc(pstate, 0);
> >+		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
> >  	}
> >  	for (i = 0; i < PLANE_CURSOR; i++) {
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[PATCH 3/4] drm/i915/skl+: calculate plane pixel rate (v4)

[Matt Roper]

From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

Don't use pipe pixel rate for plane pixel rate. Calculate plane pixel according
to formula

adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount

downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w]
if 90/270 rotation use rotated width & height

v2: use intel_plane_state->visible instead of (fb == NULL) as per Matt's
    comment.

v3 (by Matt):
 - Keep downscale amount in 16.16 fixed point rather than converting to
   decimal fixed point.
 - Store adjusted plane pixel rate in plane state instead of the plane
   parameters structure that we no longer use.

v4 (by Matt):
 - Significant rebasing onto latest atomic watermark work
 - Don't bother storing plane pixel rate in state; just calculate it
   right before the calls that make use of it.
 - Fix downscale calculations to actually use width values when
   computing downscale_w rather than copy/pasted height values.

Cc: matthew.d.roper@intel.com
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 73 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 70 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d7165b5..5bd885b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -26,6 +26,7 @@
  */
 
 #include <linux/cpufreq.h>
+#include <drm/drm_plane_helper.h>
 #include "i915_drv.h"
 #include "intel_drv.h"
 #include "../../../platform/x86/intel_ips.h"
@@ -2945,6 +2946,46 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 	}
 }
 
+/*
+ * Determines the downscale amount of a plane for the purposes of watermark calculations.
+ * The bspec defines downscale amount as:
+ *
+ * """
+ * Horizontal down scale amount = maximum[1, Horizontal source size /
+ *                                           Horizontal destination size]
+ * Vertical down scale amount = maximum[1, Vertical source size /
+ *                                         Vertical destination size]
+ * Total down scale amount = Horizontal down scale amount *
+ *                           Vertical down scale amount
+ * """
+ *
+ * Return value is provided in 16.16 fixed point form to retain fractional part.
+ * Caller should take care of dividing & rounding off the value.
+ */
+static uint32_t
+skl_plane_downscale_amount(const struct intel_plane_state *pstate)
+{
+	uint32_t downscale_h, downscale_w;
+	uint32_t src_w, src_h, dst_w, dst_h;
+
+	if (WARN_ON(!pstate->visible))
+		return DRM_PLANE_HELPER_NO_SCALING;
+
+	/* n.b., src is 16.16 fixed point, dst is whole integer */
+	src_w = drm_rect_width(&pstate->src);
+	src_h = drm_rect_height(&pstate->src);
+	dst_w = drm_rect_width(&pstate->dst);
+	dst_h = drm_rect_height(&pstate->dst);
+	if (intel_rotation_90_or_270(pstate->base.rotation))
+		swap(dst_w, dst_h);
+
+	downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
+	downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
+
+	/* Provide result in 16.16 fixed point */
+	return (uint64_t)downscale_w * downscale_h >> 16;
+}
+
 static unsigned int
 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 			     const struct drm_plane_state *pstate,
@@ -3273,6 +3314,30 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
 	return ret;
 }
 
+static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
+					      struct intel_plane_state *pstate)
+{
+	uint64_t adjusted_pixel_rate;
+	uint64_t downscale_amount;
+	uint64_t pixel_rate;
+
+	/* Shouldn't reach here on disabled planes... */
+	if (WARN_ON(!pstate->visible))
+		return 0;
+
+	/*
+	 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
+	 * with additional adjustments for plane-specific scaling.
+	 */
+	adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
+	downscale_amount = skl_plane_downscale_amount(pstate);
+
+	pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
+	WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
+
+	return pixel_rate;
+}
+
 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				struct intel_crtc_state *cstate,
 				struct intel_plane_state *intel_pstate,
@@ -3291,6 +3356,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	uint32_t selected_result;
 	uint8_t cpp;
 	uint32_t width = 0, height = 0;
+	uint32_t plane_pixel_rate;
 
 	if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
 		*enabled = false;
@@ -3304,9 +3370,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		swap(width, height);
 
 	cpp = drm_format_plane_cpp(fb->pixel_format, 0);
-	method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
-				 cpp, latency);
-	method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
+	plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
+
+	method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
+	method2 = skl_wm_method2(plane_pixel_rate,
 				 cstate->base.adjusted_mode.crtc_htotal,
 				 width,
 				 cpp,
-- 
2.1.4

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Re: [PATCH 3/4] drm/i915/skl+: calculate plane pixel rate (v4)

[Mahesh Kumar]

Reviewed-by: Kumar Mahesh <mahesh1.kumar@intel.com>

On Tuesday 17 May 2016 04:22 AM, Matt Roper wrote:
> From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
>
> Don't use pipe pixel rate for plane pixel rate. Calculate plane pixel according
> to formula
>
> adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount
>
> downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w]
> if 90/270 rotation use rotated width & height
>
> v2: use intel_plane_state->visible instead of (fb == NULL) as per Matt's
>      comment.
>
> v3 (by Matt):
>   - Keep downscale amount in 16.16 fixed point rather than converting to
>     decimal fixed point.
>   - Store adjusted plane pixel rate in plane state instead of the plane
>     parameters structure that we no longer use.
>
> v4 (by Matt):
>   - Significant rebasing onto latest atomic watermark work
>   - Don't bother storing plane pixel rate in state; just calculate it
>     right before the calls that make use of it.
>   - Fix downscale calculations to actually use width values when
>     computing downscale_w rather than copy/pasted height values.
>
> Cc: matthew.d.roper@intel.com
> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 73 +++++++++++++++++++++++++++++++++++++++--
>   1 file changed, 70 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d7165b5..5bd885b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -26,6 +26,7 @@
>    */
>   
>   #include <linux/cpufreq.h>
> +#include <drm/drm_plane_helper.h>
>   #include "i915_drv.h"
>   #include "intel_drv.h"
>   #include "../../../platform/x86/intel_ips.h"
> @@ -2945,6 +2946,46 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>   	}
>   }
>   
> +/*
> + * Determines the downscale amount of a plane for the purposes of watermark calculations.
> + * The bspec defines downscale amount as:
> + *
> + * """
> + * Horizontal down scale amount = maximum[1, Horizontal source size /
> + *                                           Horizontal destination size]
> + * Vertical down scale amount = maximum[1, Vertical source size /
> + *                                         Vertical destination size]
> + * Total down scale amount = Horizontal down scale amount *
> + *                           Vertical down scale amount
> + * """
> + *
> + * Return value is provided in 16.16 fixed point form to retain fractional part.
> + * Caller should take care of dividing & rounding off the value.
> + */
> +static uint32_t
> +skl_plane_downscale_amount(const struct intel_plane_state *pstate)
> +{
> +	uint32_t downscale_h, downscale_w;
> +	uint32_t src_w, src_h, dst_w, dst_h;
> +
> +	if (WARN_ON(!pstate->visible))
> +		return DRM_PLANE_HELPER_NO_SCALING;
> +
> +	/* n.b., src is 16.16 fixed point, dst is whole integer */
> +	src_w = drm_rect_width(&pstate->src);
> +	src_h = drm_rect_height(&pstate->src);
> +	dst_w = drm_rect_width(&pstate->dst);
> +	dst_h = drm_rect_height(&pstate->dst);
> +	if (intel_rotation_90_or_270(pstate->base.rotation))
> +		swap(dst_w, dst_h);
> +
> +	downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
> +	downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
> +
> +	/* Provide result in 16.16 fixed point */
> +	return (uint64_t)downscale_w * downscale_h >> 16;
> +}
> +
>   static unsigned int
>   skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>   			     const struct drm_plane_state *pstate,
> @@ -3273,6 +3314,30 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
>   	return ret;
>   }
>   
> +static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
> +					      struct intel_plane_state *pstate)
> +{
> +	uint64_t adjusted_pixel_rate;
> +	uint64_t downscale_amount;
> +	uint64_t pixel_rate;
> +
> +	/* Shouldn't reach here on disabled planes... */
> +	if (WARN_ON(!pstate->visible))
> +		return 0;
> +
> +	/*
> +	 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
> +	 * with additional adjustments for plane-specific scaling.
> +	 */
> +	adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
> +	downscale_amount = skl_plane_downscale_amount(pstate);
> +
> +	pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
> +	WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
> +
> +	return pixel_rate;
> +}
> +
>   static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   				struct intel_crtc_state *cstate,
>   				struct intel_plane_state *intel_pstate,
> @@ -3291,6 +3356,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   	uint32_t selected_result;
>   	uint8_t cpp;
>   	uint32_t width = 0, height = 0;
> +	uint32_t plane_pixel_rate;
>   
>   	if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
>   		*enabled = false;
> @@ -3304,9 +3370,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   		swap(width, height);
>   
>   	cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> -	method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
> -				 cpp, latency);
> -	method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
> +	plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
> +
> +	method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
> +	method2 = skl_wm_method2(plane_pixel_rate,
>   				 cstate->base.adjusted_mode.crtc_htotal,
>   				 width,
>   				 cpp,

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[PATCH 4/4] drm/i915/skl+: Use scaling amount for plane data rate calculation (v3)

[Matt Roper]

From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

if downscaling is enabled plane data rate increases according to scaling
amount. take scaling amount under consideration while calculating plane
data rate

v2: Address Matt's comments, where data rate was overridden because of
missing else.

v3 (by Matt):
 - Add braces to 'else' branch to match kernel coding style
 - Adjust final calculation now that skl_plane_downscale_amount()
   returns 16.16 fixed point value instead of a decimal fixed point

Cc: matthew.d.roper@intel.com
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5bd885b..4d0088c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2993,6 +2993,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 {
 	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
 	struct drm_framebuffer *fb = pstate->fb;
+	uint32_t down_scale_amount, data_rate;
 	uint32_t width = 0, height = 0;
 	unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
 
@@ -3012,15 +3013,19 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 	/* for planar format */
 	if (format == DRM_FORMAT_NV12) {
 		if (y)  /* y-plane data rate */
-			return width * height *
+			data_rate = width * height *
 				drm_format_plane_cpp(format, 0);
 		else    /* uv-plane data rate */
-			return (width / 2) * (height / 2) *
+			data_rate = (width / 2) * (height / 2) *
 				drm_format_plane_cpp(format, 1);
+	} else {
+		/* for packed formats */
+		data_rate = width * height * drm_format_plane_cpp(format, 0);
 	}
 
-	/* for packed formats */
-	return width * height * drm_format_plane_cpp(format, 0);
+	down_scale_amount = skl_plane_downscale_amount(intel_pstate);
+
+	return data_rate * down_scale_amount >> 16;
 }
 
 /*
-- 
2.1.4

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[PATCH 4/4] drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)

[Matt Roper]

From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

if downscaling is enabled plane data rate increases according to scaling
amount. take scaling amount under consideration while calculating plane
data rate

v2: Address Matt's comments, where data rate was overridden because of
missing else.

v3 (by Matt):
 - Add braces to 'else' branch to match kernel coding style
 - Adjust final calculation now that skl_plane_downscale_amount()
   returns 16.16 fixed point value instead of a decimal fixed point

v4 (by Matt):
 - Avoid integer overflow by making sure final multiplication is
   treated as 64-bit.

Cc: matthew.d.roper@intel.com
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5bd885b..7a486e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2993,6 +2993,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 {
 	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
 	struct drm_framebuffer *fb = pstate->fb;
+	uint32_t down_scale_amount, data_rate;
 	uint32_t width = 0, height = 0;
 	unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
 
@@ -3012,15 +3013,19 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 	/* for planar format */
 	if (format == DRM_FORMAT_NV12) {
 		if (y)  /* y-plane data rate */
-			return width * height *
+			data_rate = width * height *
 				drm_format_plane_cpp(format, 0);
 		else    /* uv-plane data rate */
-			return (width / 2) * (height / 2) *
+			data_rate = (width / 2) * (height / 2) *
 				drm_format_plane_cpp(format, 1);
+	} else {
+		/* for packed formats */
+		data_rate = width * height * drm_format_plane_cpp(format, 0);
 	}
 
-	/* for packed formats */
-	return width * height * drm_format_plane_cpp(format, 0);
+	down_scale_amount = skl_plane_downscale_amount(intel_pstate);
+
+	return (uint64_t)data_rate * down_scale_amount >> 16;
 }
 
 /*
-- 
2.1.4

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Re: [PATCH 4/4] drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)

[Mahesh Kumar]

Reviewed-by: Kumar Mahesh <mahesh1.kumar@intel.com>

On Friday 20 May 2016 03:33 AM, Matt Roper wrote:
> From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
>
> if downscaling is enabled plane data rate increases according to scaling
> amount. take scaling amount under consideration while calculating plane
> data rate
>
> v2: Address Matt's comments, where data rate was overridden because of
> missing else.
>
> v3 (by Matt):
>   - Add braces to 'else' branch to match kernel coding style
>   - Adjust final calculation now that skl_plane_downscale_amount()
>     returns 16.16 fixed point value instead of a decimal fixed point
>
> v4 (by Matt):
>   - Avoid integer overflow by making sure final multiplication is
>     treated as 64-bit.
>
> Cc: matthew.d.roper@intel.com
> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++----
>   1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5bd885b..7a486e4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2993,6 +2993,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>   {
>   	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
>   	struct drm_framebuffer *fb = pstate->fb;
> +	uint32_t down_scale_amount, data_rate;
>   	uint32_t width = 0, height = 0;
>   	unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
>   
> @@ -3012,15 +3013,19 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>   	/* for planar format */
>   	if (format == DRM_FORMAT_NV12) {
>   		if (y)  /* y-plane data rate */
> -			return width * height *
> +			data_rate = width * height *
>   				drm_format_plane_cpp(format, 0);
>   		else    /* uv-plane data rate */
> -			return (width / 2) * (height / 2) *
> +			data_rate = (width / 2) * (height / 2) *
>   				drm_format_plane_cpp(format, 1);
> +	} else {
> +		/* for packed formats */
> +		data_rate = width * height * drm_format_plane_cpp(format, 0);
>   	}
>   
> -	/* for packed formats */
> -	return width * height * drm_format_plane_cpp(format, 0);
> +	down_scale_amount = skl_plane_downscale_amount(intel_pstate);
> +
> +	return (uint64_t)data_rate * down_scale_amount >> 16;
>   }
>   
>   /*

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✗ Ro.CI.BAT: warning for SKL watermark algorithm updates

[Patchwork]

== Series Details ==

Series: SKL watermark algorithm updates
URL   : https://patchwork.freedesktop.org/series/7262/
State : warning

== Summary ==

Series 7262v1 SKL watermark algorithm updates
http://patchwork.freedesktop.org/api/1.0/series/7262/revisions/1/mbox

Test drv_hangman:
        Subgroup error-state-basic:
                fail       -> PASS       (ro-ilk1-i5-650)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (ro-hsw-i3-4010u)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-b:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)

ro-bdw-i5-5250u  total:219  pass:181  dwarn:0   dfail:0   fail:0   skip:38 
ro-bdw-i7-5557U  total:219  pass:206  dwarn:0   dfail:0   fail:0   skip:13 
ro-bdw-i7-5600u  total:219  pass:187  dwarn:0   dfail:0   fail:0   skip:32 
ro-bsw-n3050     total:219  pass:175  dwarn:0   dfail:0   fail:2   skip:42 
ro-byt-n2820     total:218  pass:174  dwarn:0   dfail:0   fail:3   skip:41 
ro-hsw-i3-4010u  total:218  pass:193  dwarn:0   dfail:0   fail:0   skip:25 
ro-ilk-i7-620lm  total:219  pass:151  dwarn:0   dfail:0   fail:1   skip:67 
ro-ilk1-i5-650   total:214  pass:152  dwarn:0   dfail:0   fail:1   skip:61 
ro-ivb-i7-3770   total:219  pass:183  dwarn:0   dfail:0   fail:0   skip:36 
ro-ivb2-i7-3770  total:219  pass:186  dwarn:1   dfail:0   fail:0   skip:32 
ro-skl-i7-6700hq total:214  pass:189  dwarn:0   dfail:0   fail:0   skip:25 
ro-snb-i7-2620M  total:219  pass:177  dwarn:0   dfail:0   fail:1   skip:41 

Results at /archive/results/CI_IGT_test/RO_Patchwork_913/

d381724 drm-intel-nightly: 2016y-05m-16d-12h-14m-04s UTC integration manifest
c0706cc drm/i915/skl+: Use scaling amount for plane data rate calculation (v3)
87857a1 drm/i915/skl+: calculate plane pixel rate (v4)
a17643c drm/i915/skl+: calculate ddb minimum allocation (v4)
51cc79c drm/i915: Don't try to calculate relative data rates during hw readout

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✗ Ro.CI.BAT: warning for SKL watermark algorithm updates (rev2)

[Patchwork]

== Series Details ==

Series: SKL watermark algorithm updates (rev2)
URL   : https://patchwork.freedesktop.org/series/7262/
State : warning

== Summary ==

Series 7262v2 SKL watermark algorithm updates
http://patchwork.freedesktop.org/api/1.0/series/7262/revisions/2/mbox

Test drv_module_reload_basic:
                dmesg-warn -> PASS       (ro-bdw-i7-5600u)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (ro-ivb-i7-3770)
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (ro-ivb-i7-3770)

fi-bdw-i7-5557u  total:217  pass:204  dwarn:0   dfail:0   fail:0   skip:13 
fi-bsw-n3050     total:216  pass:172  dwarn:0   dfail:0   fail:2   skip:42 
fi-byt-n2820     total:216  pass:173  dwarn:0   dfail:0   fail:2   skip:41 
fi-hsw-i7-4770r  total:217  pass:191  dwarn:0   dfail:0   fail:0   skip:26 
fi-skl-i7-6700k  total:217  pass:189  dwarn:0   dfail:0   fail:0   skip:28 
ro-bdw-i5-5250u  total:217  pass:179  dwarn:0   dfail:0   fail:0   skip:38 
ro-bdw-i7-5557U  total:217  pass:204  dwarn:0   dfail:0   fail:0   skip:13 
ro-bdw-i7-5600u  total:217  pass:185  dwarn:0   dfail:0   fail:1   skip:31 
ro-bsw-n3050     total:217  pass:173  dwarn:0   dfail:0   fail:2   skip:42 
ro-byt-n2820     total:216  pass:172  dwarn:0   dfail:0   fail:3   skip:41 
ro-hsw-i3-4010u  total:216  pass:191  dwarn:0   dfail:0   fail:0   skip:25 
ro-hsw-i7-4770r  total:217  pass:191  dwarn:0   dfail:0   fail:0   skip:26 
ro-ilk-i7-620lm  total:217  pass:149  dwarn:0   dfail:0   fail:1   skip:67 
ro-ilk1-i5-650   total:212  pass:150  dwarn:0   dfail:0   fail:1   skip:61 
ro-ivb-i7-3770   total:217  pass:180  dwarn:1   dfail:0   fail:0   skip:36 
ro-ivb2-i7-3770  total:217  pass:185  dwarn:0   dfail:0   fail:0   skip:32 
ro-skl-i7-6700hq total:212  pass:188  dwarn:0   dfail:0   fail:0   skip:24 
ro-snb-i7-2620M  total:217  pass:175  dwarn:0   dfail:0   fail:1   skip:41 
fi-hsw-i7-4770k failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_944/

9d15199 drm-intel-nightly: 2016y-05m-20d-07h-54m-59s UTC integration manifest
4a818c0 drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)
fa51434 drm/i915/skl+: calculate plane pixel rate (v4)
c95c5fe drm/i915/skl+: calculate ddb minimum allocation (v4)
c454d27 drm/i915: Don't try to calculate relative data rates during hw readout

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✗ Ro.CI.BAT: warning for SKL watermark algorithm updates (rev3)

[Patchwork]

== Series Details ==

Series: SKL watermark algorithm updates (rev3)
URL   : https://patchwork.freedesktop.org/series/7262/
State : warning

== Summary ==

Series 7262v3 SKL watermark algorithm updates
http://patchwork.freedesktop.org/api/1.0/series/7262/revisions/3/mbox

Test gem_exec_basic:
        Subgroup readonly-bsd:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                fail       -> PASS       (ro-byt-n2820)
Test kms_sink_crc_basic:
                skip       -> PASS       (ro-skl-i7-6700hq)

ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:170  dwarn:0   dfail:0   fail:2   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:180  dwarn:3   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 

Results at /archive/results/CI_IGT_test/RO_Patchwork_1031/

c17d7e8 drm-intel-nightly: 2016y-05m-26d-15h-04m-52s UTC integration manifest
a86d448 drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)
5c09061 drm/i915/skl+: calculate plane pixel rate (v4)
7f72b1b drm/i915/skl+: calculate ddb minimum allocation (v5)
3845bc1 drm/i915: Don't try to calculate relative data rates during hw readout

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✗ Ro.CI.BAT: warning for SKL watermark algorithm updates (rev4)

[Patchwork]

== Series Details ==

Series: SKL watermark algorithm updates (rev4)
URL   : https://patchwork.freedesktop.org/series/7262/
State : warning

== Summary ==

Series 7262v4 SKL watermark algorithm updates
http://patchwork.freedesktop.org/api/1.0/series/7262/revisions/4/mbox

Test gem_busy:
        Subgroup basic-parallel-render:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
        Subgroup basic-render:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_close_race:
        Subgroup basic-process:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_cpu_reloc:
        Subgroup basic:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_ctx_exec:
        Subgroup basic:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_exec_basic:
        Subgroup gtt-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup gtt-vebox:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup readonly-bsd:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_exec_parallel:
        Subgroup basic:
                pass       -> DMESG-WARN (fi-snb-i7-2600)
Test gem_exec_store:
        Subgroup basic-render:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_mmap_gtt:
        Subgroup basic-write-gtt-no-prefault:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_render_tiled_blits:
        Subgroup basic:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_storedw_loop:
        Subgroup basic-bsd:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_tiled_fence_blits:
        Subgroup basic:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_tiled_pread_basic:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup addfb25-modifier-no-flag:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup bad-pitch-0:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup bad-pitch-32:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup bad-pitch-65536:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-y-tiled:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup framebuffer-vs-set-tiling:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup small-bo:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup too-high:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup unused-pitches:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
        Subgroup force-edid:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)

fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-snb-i7-2600   total:209  pass:169  dwarn:1   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-ivb2-i7-3770  total:102  pass:42   dwarn:37  dfail:0   fail:0   skip:22 
ro-skl-i7-6700hq total:204  pass:169  dwarn:14  dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
fi-hsw-i7-4770k failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
ro-ilk-i7-620lm failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1070/

877a1d2 drm-intel-nightly: 2016y-05m-31d-14h-57m-44s UTC integration manifest
3398115 drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)
16399f7 drm/i915/skl+: calculate plane pixel rate (v4)
5e43b98 drm/i915/skl+: calculate ddb minimum allocation (v6)
e87756e drm/i915: Don't try to calculate relative data rates during hw readout

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Re: ✗ Ro.CI.BAT: warning for SKL watermark algorithm updates (rev4)

[Matt Roper]

On Tue, May 31, 2016 at 05:34:41PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: SKL watermark algorithm updates (rev4)
> URL   : https://patchwork.freedesktop.org/series/7262/
> State : warning
> 
> == Summary ==
> 
> Series 7262v4 SKL watermark algorithm updates
> http://patchwork.freedesktop.org/api/1.0/series/7262/revisions/4/mbox
> 
> Test gem_busy:
>         Subgroup basic-parallel-render:
>                 pass       -> DMESG-WARN (ro-ivb2-i7-3770)
>         Subgroup basic-render:
>                 pass       -> DMESG-WARN (ro-ivb2-i7-3770)

Looks like the USB triggered a bug ("BUG: using smp_processor_id() in
preemptible"); not caused by the graphics driver.

I think Chris already wrote a patch to fix this anyway:
   https://patchwork.freedesktop.org/patch/90483/


> Test gem_close_race:
>         Subgroup basic-process:
>                 dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_cpu_reloc:
>         Subgroup basic:
>                 dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_ctx_exec:
>         Subgroup basic:
>                 pass       -> DMESG-WARN (ro-ivb2-i7-3770)

Same USB BUG().

> Test gem_exec_basic:
>         Subgroup gtt-default:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>         Subgroup gtt-vebox:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>         Subgroup readonly-bsd:
>                 dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_exec_parallel:
>         Subgroup basic:
>                 pass       -> DMESG-WARN (fi-snb-i7-2600)

"*ERROR* Hangcheck timer elapsed... render ring idle"

There are a handful of bugzillas about similar issues on various
platforms; https://bugs.freedesktop.org/show_bug.cgi?id=75394 is
reported against SNB.


> Test gem_exec_store:
>         Subgroup basic-render:
>                 dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_mmap_gtt:
>         Subgroup basic-write-gtt-no-prefault:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_render_tiled_blits:
>         Subgroup basic:
>                 pass       -> DMESG-WARN (ro-ivb2-i7-3770)

USB BUG() again.

> Test gem_storedw_loop:
>         Subgroup basic-bsd:
>             pass       -> DMESG-WARN (ro-skl-i7-6700hq)

"Potential atomic update failure on pipe A."

https://bugs.freedesktop.org/show_bug.cgi?id=95632


> Test gem_tiled_fence_blits:
>         Subgroup basic:
>                 dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_tiled_pread_basic:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)

"Potential atomic update failure on pipe A."

https://bugs.freedesktop.org/show_bug.cgi?id=95632

> Test kms_addfb_basic:
>         Subgroup addfb25-modifier-no-flag:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>         Subgroup bad-pitch-0:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>         Subgroup bad-pitch-32:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>         Subgroup bad-pitch-65536:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>         Subgroup basic-y-tiled:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>         Subgroup framebuffer-vs-set-tiling:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>         Subgroup small-bo:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>         Subgroup too-high:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>         Subgroup unused-pitches:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)

All of the DMESG-WARN's above are the

"Potential atomic update failure on pipe A."

https://bugs.freedesktop.org/show_bug.cgi?id=95632


> Test kms_force_connector_basic:
>         Subgroup force-connector-state:
>                 pass       -> DMESG-WARN (ro-ivb2-i7-3770)

USB BUG() again.


>         Subgroup force-edid:
>                 dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> 
> fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> fi-snb-i7-2600   total:209  pass:169  dwarn:1   dfail:0   fail:0   skip:39 
> ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
> ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
> ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
> ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
> ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
> ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
> ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
> ro-ivb2-i7-3770  total:102  pass:42   dwarn:37  dfail:0   fail:0   skip:22 
> ro-skl-i7-6700hq total:204  pass:169  dwarn:14  dfail:0   fail:0   skip:21 
> ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
> fi-hsw-i7-4770k failed to connect after reboot
> ro-bdw-i7-5557U failed to connect after reboot
> ro-ilk-i7-620lm failed to connect after reboot

Not sure what caused these machines to fail reboot, but my patches are
SKL-only so I don't think they're the cause.  Maybe the BUG() that was
causing DMESG-WARN's on IVB hits these platforms as well, but completely
killed them?


Matt

> 
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1070/
> 
> 877a1d2 drm-intel-nightly: 2016y-05m-31d-14h-57m-44s UTC integration manifest
> 3398115 drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)
> 16399f7 drm/i915/skl+: calculate plane pixel rate (v4)
> 5e43b98 drm/i915/skl+: calculate ddb minimum allocation (v6)
> e87756e drm/i915: Don't try to calculate relative data rates during hw readout
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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