[PATCH v3 00/12] drm/i915: DP branch devices

[PATCH v3 00/12] drm/i915: DP branch devices

[Mika Kahola]

Prep work for DP branch device handling

This series of patches reads DPCD register 0x80h for receiver
capabilities for DP branch devices. The branch device types are
converters for the following standards

 - DP to VGA
 - DP to DVI
 - DP to HDMI
 - DP++ dual mode
 - Wireless WiGig
 
DPCD register defines max pixel rate for VGA dongles. This
check is carried out during mode validation. 

What's new in the series:
 - Readout of branch device ID, HW, and SW revisions from DPCD register 

Acronyms:
BD     Brand Device
DFP    Downstream-Facing Port

v2: DPCD register read outs moved to drm (Ville, Daniel)
v3: Max pixel rate computation moved to drm (Daniel)

Mika Kahola (12):
  drm: Add missing DP downstream port types
  drm: Read DPCD receiver capability for DP to VGA converter
  drm: Read DPCD receiver capability for DP to DVI converter
  drm: Read DPCD receiver capability for DP to HDMI converter
  drm: Read DPCD receiver capability for DP++
  drm: Read DPCD receiver capability for DP to Wireless Converter
  drm: Compute max pixel rate for DP sink
  drm/i915: Check pixel rate for DP to VGA dongle
  drm/i915: Read DP branch device id
  drm/i915: Read DP branch device HW revision
  drm/i915: Read DP branch device SW revision
  drm/i915: Add DP branch device info on debugfs

 drivers/gpu/drm/drm_dp_helper.c     | 92 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_debugfs.c | 37 +++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c     | 23 ++++++++++
 drivers/gpu/drm/i915/intel_drv.h    |  2 +
 include/drm/drm_dp_helper.h         | 86 ++++++++++++++++++++++++++++++++++
 5 files changed, 240 insertions(+)

-- 
1.9.1

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[PATCH v3 01/12] drm: Add missing DP downstream port types

[Mika Kahola]

Add missing DisplayPort downstream port types. The introduced
new port types are DP++ and Wireless.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 include/drm/drm_dp_helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5a848e7..e384c7f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -211,6 +211,8 @@
 # define DP_DS_PORT_TYPE_DVI		    2
 # define DP_DS_PORT_TYPE_HDMI		    3
 # define DP_DS_PORT_TYPE_NON_EDID	    4
+# define DP_DS_PORT_TYPE_DP_DUALMODE        5
+# define DP_DS_PORT_TYPE_WIRELESS           6
 # define DP_DS_PORT_HPD			    (1 << 3)
 /* offset 1 for VGA is maximum megapixels per second / 8 */
 /* offset 2 */
-- 
1.9.1

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[PATCH v3 02/12] drm: Read DPCD receiver capability for DP to VGA converter

[Mika Kahola]

Read from DPCD receiver capability field the max allowed
pixel clock and bits per component for DP to VGA converter.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c  | 46 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 include/drm/drm_dp_helper.h      | 21 ++++++++++++++++++
 3 files changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eeaf5a7..c5bec6f 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -412,6 +412,52 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
 }
 EXPORT_SYMBOL(drm_dp_link_power_down);
 
+/*
+ * drm_dp_bd() - read DisplayPort Receiver Capability Fields for
+ * DP branch devices
+ * @aux: DisplayPort AUX channel
+ * @bd: pointer to a structure containing DP branch device information
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd)
+{
+	uint8_t info[4];
+	uint8_t dfp;
+	bool detailed_cap_info;
+	int err, size;
+
+	err = drm_dp_dpcd_read(aux, DP_DOWNSTREAMPORT_PRESENT, &dfp, sizeof(dfp));
+	if (err < 0)
+		return err;
+
+	bd->present = dfp & 0x1;
+
+	if (!bd->present)
+		return 0;
+
+	detailed_cap_info = dfp & DP_DETAILED_CAP_INFO_AVAILABLE;
+
+	size = detailed_cap_info ? 4 : 1;
+
+	err = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, info, size);
+	if (err < 0)
+		return err;
+
+	bd->type = info[0] & DP_DS_PORT_TYPE_MASK;
+	bd->hpd = info[0] & DP_DS_PORT_HPD;
+
+	if (detailed_cap_info) {
+		if (bd->type & DP_DS_PORT_TYPE_VGA) {
+			bd->dfp.vga.dot_clk = info[1] * 8 * 1000;
+			bd->dfp.vga.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_bd);
+
 /**
  * drm_dp_link_configure() - configure a DisplayPort link
  * @aux: DisplayPort AUX channel
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0741b2d..f85914b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -886,6 +886,8 @@ struct intel_dp {
 
 	bool train_set_valid;
 
+	struct drm_dp_bd bd;
+
 	/* Displayport compliance testing */
 	unsigned long compliance_test_type;
 	unsigned long compliance_test_data;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index e384c7f..d3e78a5 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -802,10 +802,31 @@ struct drm_dp_link {
 	unsigned long capabilities;
 };
 
+/*
+ * DP to VGA
+ */
+struct drm_dp_vga {
+	int dot_clk;
+	uint8_t bpc;
+};
+
+/*
+ * Branch device
+ */
+struct drm_dp_bd {
+	bool present;
+	int type;
+	bool hpd;
+	union {
+		struct drm_dp_vga vga;
+	} dfp;
+};
+
 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
+int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd);
 
 int drm_dp_aux_register(struct drm_dp_aux *aux);
 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
-- 
1.9.1

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[PATCH v3 03/12] drm: Read DPCD receiver capability for DP to DVI converter

[Mika Kahola]

Read from DPCD receiver capability field for the following
features:
 - max TMDS clock rate
 - max bits per component
 - single or dual link support
 - high color depth support

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c |  5 +++++
 include/drm/drm_dp_helper.h     | 14 ++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index c5bec6f..f5cf706 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -451,6 +451,11 @@ int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd)
 		if (bd->type & DP_DS_PORT_TYPE_VGA) {
 			bd->dfp.vga.dot_clk = info[1] * 8 * 1000;
 			bd->dfp.vga.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
+		} else if (bd->type & DP_DS_PORT_TYPE_DVI) {
+			bd->dfp.dvi.tmds_clk = info[1] * 2500;
+			bd->dfp.dvi.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
+			bd->dfp.dvi.dual_link = info[3] & DP_DS_DVI_DUAL_LINK;
+			bd->dfp.dvi.hi_color_depth = info[3] & DP_DS_DVI_HI_COLOR_DEPTH;
 		}
 	}
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d3e78a5..1a4e131 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -221,6 +221,9 @@
 # define DP_DS_VGA_10BPC		    1
 # define DP_DS_VGA_12BPC		    2
 # define DP_DS_VGA_16BPC		    3
+/* offset 3 for DVI dual link and high color depth */
+# define DP_DS_DVI_DUAL_LINK                (1<<1)
+# define DP_DS_DVI_HI_COLOR_DEPTH           (1<<2)
 
 /* link configuration */
 #define	DP_LINK_BW_SET		            0x100
@@ -811,6 +814,16 @@ struct drm_dp_vga {
 };
 
 /*
+ * DP to DVI
+ */
+struct drm_dp_dvi {
+	int tmds_clk;
+	uint8_t bpc;
+	bool dual_link;
+	bool hi_color_depth;
+};
+
+/*
  * Branch device
  */
 struct drm_dp_bd {
@@ -819,6 +832,7 @@ struct drm_dp_bd {
 	bool hpd;
 	union {
 		struct drm_dp_vga vga;
+		struct drm_dp_dvi dvi;
 	} dfp;
 };
 
-- 
1.9.1

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[PATCH v3 04/12] drm: Read DPCD receiver capability for DP to HDMI converter

[Mika Kahola]

Read from DPCD receiver capability field for DP to HDMI
converter. The features for DP to HDMI converter are

 - max TMDS characther clock rate
 - max bits per component
 - support for conversion from 3D frame sequential to frame pack
 - support for YCBCR422 pass through
 - support for YCBCR420 pass through
 - support for conversion from YCBCR444 to YCBCR422
 - support for conversion from YCBCR444 to YCBCR420

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c |  8 ++++++++
 include/drm/drm_dp_helper.h     | 19 +++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f5cf706..ccd0fcb 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -456,6 +456,14 @@ int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd)
 			bd->dfp.dvi.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
 			bd->dfp.dvi.dual_link = info[3] & DP_DS_DVI_DUAL_LINK;
 			bd->dfp.dvi.hi_color_depth = info[3] & DP_DS_DVI_HI_COLOR_DEPTH;
+		} else if (bd->type & DP_DS_PORT_TYPE_HDMI) {
+			bd->dfp.hdmi.tmds_clk = info[1] * 2500;
+			bd->dfp.hdmi.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
+			bd->dfp.hdmi.frame_seq_to_frame_pack = info[3] & FRAME_SEQ_TO_FRAME_PACK;
+			bd->dfp.hdmi.ycbcr422_pass_through = info[3] & YCBCR422_PASS_THROUGH;
+			bd->dfp.hdmi.ycbcr420_pass_through = info[3] & YCBCR420_PASS_THROUGH;
+			bd->dfp.hdmi.conversion_from_ycbcr444_to_ycbcr422 = info[3] & YCBCR444_TO_YCBCR422;
+			bd->dfp.hdmi.conversion_from_ycbcr444_to_ycbcr420 = info[3] & YCBCR444_TO_YCBCR420;
 		}
 	}
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1a4e131..b8c4960 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -224,6 +224,12 @@
 /* offset 3 for DVI dual link and high color depth */
 # define DP_DS_DVI_DUAL_LINK                (1<<1)
 # define DP_DS_DVI_HI_COLOR_DEPTH           (1<<2)
+/* offset 3 for HDMI */
+# define FRAME_SEQ_TO_FRAME_PACK            (1<<0)
+# define YCBCR422_PASS_THROUGH              (1<<1)
+# define YCBCR420_PASS_THROUGH              (1<<2)
+# define YCBCR444_TO_YCBCR422               (1<<3)
+# define YCBCR444_TO_YCBCR420               (1<<4)
 
 /* link configuration */
 #define	DP_LINK_BW_SET		            0x100
@@ -822,6 +828,18 @@ struct drm_dp_dvi {
 	bool dual_link;
 	bool hi_color_depth;
 };
+/*
+ * DP to HDMI
+ */
+struct drm_dp_hdmi {
+	int tmds_clk;
+	uint8_t bpc;
+	bool frame_seq_to_frame_pack;
+	bool ycbcr422_pass_through;
+	bool ycbcr420_pass_through;
+	bool conversion_from_ycbcr444_to_ycbcr422;
+	bool conversion_from_ycbcr444_to_ycbcr420;
+};
 
 /*
  * Branch device
@@ -833,6 +851,7 @@ struct drm_dp_bd {
 	union {
 		struct drm_dp_vga vga;
 		struct drm_dp_dvi dvi;
+		struct drm_dp_hdmi hdmi;
 	} dfp;
 };
 
-- 
1.9.1

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[PATCH v3 05/12] drm: Read DPCD receiver capability for DP++

[Mika Kahola]

Read from DPCD receiver capability field for the
DP++ devices. The features are

 - max TMDS charachter clock
 - max bits per component
 - support for conversion from 3D frame sequential to
   frame pack

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c |  4 ++++
 include/drm/drm_dp_helper.h     | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ccd0fcb..f98e4be 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -464,6 +464,10 @@ int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd)
 			bd->dfp.hdmi.ycbcr420_pass_through = info[3] & YCBCR420_PASS_THROUGH;
 			bd->dfp.hdmi.conversion_from_ycbcr444_to_ycbcr422 = info[3] & YCBCR444_TO_YCBCR422;
 			bd->dfp.hdmi.conversion_from_ycbcr444_to_ycbcr420 = info[3] & YCBCR444_TO_YCBCR420;
+		} else if (bd->type & DP_DS_PORT_TYPE_DP_DUALMODE) {
+			bd->dfp.dual_mode.tmds_clk = info[1] * 2500;
+			bd->dfp.dual_mode.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
+			bd->dfp.dual_mode.frame_seq_to_frame_pack = info[3] & FRAME_SEQ_TO_FRAME_PACK;
 		}
 	}
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b8c4960..adf05a1 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -842,6 +842,15 @@ struct drm_dp_hdmi {
 };
 
 /*
+ * DP to DP++
+ */
+struct drm_dp_dual_mode {
+	int tmds_clk;
+	uint8_t bpc;
+	bool frame_seq_to_frame_pack;
+};
+
+/*
  * Branch device
  */
 struct drm_dp_bd {
@@ -852,6 +861,7 @@ struct drm_dp_bd {
 		struct drm_dp_vga vga;
 		struct drm_dp_dvi dvi;
 		struct drm_dp_hdmi hdmi;
+		struct drm_dp_dual_mode dual_mode;
 	} dfp;
 };
 
-- 
1.9.1

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[PATCH v3 06/12] drm: Read DPCD receiver capability for DP to Wireless Converter

[Mika Kahola]

Read from DPCD receiver capability field for the
DP to Wireless converter. The only supported wireless
technology on DP1.3 spec is WiGig display extension. If WiGig
display extension is present, then read out the

 - number of wde tx on device
 - the number of wde txs that can be concurrently active

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c |  7 +++++++
 include/drm/drm_dp_helper.h     | 13 +++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f98e4be..2c91771 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -468,6 +468,13 @@ int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd)
 			bd->dfp.dual_mode.tmds_clk = info[1] * 2500;
 			bd->dfp.dual_mode.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
 			bd->dfp.dual_mode.frame_seq_to_frame_pack = info[3] & FRAME_SEQ_TO_FRAME_PACK;
+		} else if (bd->type & DP_DS_PORT_TYPE_WIRELESS) {
+			bd->dfp.wireless.wireless_tech = info[1] & DP_DS_WIRELESS_TECH_MASK;
+
+			if (bd->dfp.wireless.wireless_tech == 0x0) {
+				bd->dfp.wireless.number_of_wde_tx_on_device = info[2] & WIRELESS_MASK;
+				bd->dfp.wireless.wde_tx_concurrency_cap = (info[2]>>2) & WIRELESS_MASK;
+			}
 		}
 	}
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index adf05a1..831f944 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -230,6 +230,9 @@
 # define YCBCR420_PASS_THROUGH              (1<<2)
 # define YCBCR444_TO_YCBCR422               (1<<3)
 # define YCBCR444_TO_YCBCR420               (1<<4)
+/* offset 3 for Wireless */
+# define DP_DS_WIRELESS_TECH_MASK           0xf
+# define WIRELESS_MASK                      3
 
 /* link configuration */
 #define	DP_LINK_BW_SET		            0x100
@@ -851,6 +854,15 @@ struct drm_dp_dual_mode {
 };
 
 /*
+ * DP to Wireless
+ */
+struct drm_dp_wireless {
+	int wireless_tech;
+	int number_of_wde_tx_on_device;
+	int wde_tx_concurrency_cap;
+};
+
+/*
  * Branch device
  */
 struct drm_dp_bd {
@@ -862,6 +874,7 @@ struct drm_dp_bd {
 		struct drm_dp_dvi dvi;
 		struct drm_dp_hdmi hdmi;
 		struct drm_dp_dual_mode dual_mode;
+		struct drm_dp_wireless wireless;
 	} dfp;
 };
 
-- 
1.9.1

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[PATCH v3 07/12] drm: Compute max pixel rate for DP sink

[Mika Kahola]

For DP branch devices DPCD register may define the max supported
pixel rate for VGA dongles. This patch adds a check if DPCD register
value is less than current setting for pixel rate.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 22 ++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |  1 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c91771..b222aa0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -413,6 +413,28 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
 EXPORT_SYMBOL(drm_dp_link_power_down);
 
 /*
+ * drm_dp_max_sink_dotclock() - Compute max pixel rate
+ * @dotclk: reference pixel rate
+ * @bd: pointer to a structure containing DP branch device information
+ *
+ * Returns max supported pixel rate.
+ */
+int drm_dp_max_sink_dotclock(int dotclk, struct drm_dp_bd *bd)
+{
+	int max_dotclk = dotclk;
+
+	/* DP to VGA dongle may define max pixel rate in DPCD */
+	if (bd->present) {
+		if ((bd->type & DP_DS_PORT_TYPE_VGA) &&
+		    (bd->dfp.vga.dot_clk > 0))
+			max_dotclk = min(dotclk, bd->dfp.vga.dot_clk);
+	}
+
+	return max_dotclk;
+}
+EXPORT_SYMBOL(drm_dp_max_sink_dotclock);
+
+/*
  * drm_dp_bd() - read DisplayPort Receiver Capability Fields for
  * DP branch devices
  * @aux: DisplayPort AUX channel
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 831f944..ee4084d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -882,6 +882,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
+int drm_dp_max_sink_dotclock(int dotclk, struct drm_dp_bd *bd);
 int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd);
 
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
1.9.1

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[PATCH v3 08/12] drm/i915: Check pixel rate for DP to VGA dongle

[Mika Kahola]

Prep work to improve DP branch device handling.

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

v2: DPCD read outs and computation moved to drm (Ville, Daniel)
v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock()
    function (Daniel)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cccf9bc..5e16063 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -201,6 +201,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
+	max_dotclk = drm_dp_max_sink_dotclock(max_dotclk, &intel_dp->bd);
+
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
 			return MODE_PANEL;
@@ -4576,6 +4578,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum intel_display_power_domain power_domain;
 	enum irqreturn ret = IRQ_NONE;
+	int err;
 
 	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
 	    intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
@@ -4600,6 +4603,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	power_domain = intel_display_port_aux_power_domain(intel_encoder);
 	intel_display_power_get(dev_priv, power_domain);
 
+	err = drm_dp_bd(&intel_dp->aux, &intel_dp->bd);
+	if (err < 0)
+		DRM_DEBUG_KMS("error reading DPCD[0x80] for DP branch device\n");
+
 	if (long_hpd) {
 		/* indicate that we need to restart link training */
 		intel_dp->train_set_valid = false;
-- 
1.9.1

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[PATCH v3 09/12] drm/i915: Read DP branch device id

[Mika Kahola]

Read device ID for DisplayPort branch devices. The device
ID is defined in DPCD register 0x503 and it is mandatory field
for DP branch devices.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++++++
 include/drm/drm_dp_helper.h     | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5e16063..2b768da 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3458,6 +3458,12 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
 		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 			      buf[0], buf[1], buf[2]);
+
+	if (intel_dp->bd.present) {
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_ID, intel_dp->bd.id,
+				     sizeof(intel_dp->bd.id)) == sizeof(intel_dp->bd.id))
+			DRM_DEBUG_KMS("Device ID: %s\n", intel_dp->bd.id);
+	}
 }
 
 static bool
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ee4084d..f1fc4e2 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -457,6 +457,7 @@
 #define DP_SOURCE_OUI			    0x300
 #define DP_SINK_OUI			    0x400
 #define DP_BRANCH_OUI			    0x500
+#define DP_BRANCH_ID                        0x503
 
 #define DP_SET_POWER                        0x600
 # define DP_SET_POWER_D0                    0x1
@@ -869,6 +870,7 @@ struct drm_dp_bd {
 	bool present;
 	int type;
 	bool hpd;
+	uint8_t id[6];
 	union {
 		struct drm_dp_vga vga;
 		struct drm_dp_dvi dvi;
-- 
1.9.1

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[PATCH v3 10/12] drm/i915: Read DP branch device HW revision

[Mika Kahola]

HW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x509.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 5 +++++
 include/drm/drm_dp_helper.h     | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2b768da..12ab26b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3463,6 +3463,11 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
 		if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_ID, intel_dp->bd.id,
 				     sizeof(intel_dp->bd.id)) == sizeof(intel_dp->bd.id))
 			DRM_DEBUG_KMS("Device ID: %s\n", intel_dp->bd.id);
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &intel_dp->bd.hw_rev,
+				     sizeof(intel_dp->bd.hw_rev)) == sizeof(intel_dp->bd.hw_rev))
+			DRM_DEBUG_KMS("HW revision: %.2d.%.2d\n",
+				      intel_dp->bd.hw_rev & 0xf, (intel_dp->bd.hw_rev>>4) & 0xf);
 	}
 }
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f1fc4e2..d0965ca 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -458,6 +458,7 @@
 #define DP_SINK_OUI			    0x400
 #define DP_BRANCH_OUI			    0x500
 #define DP_BRANCH_ID                        0x503
+#define DP_BRANCH_HW_REV                    0x509
 
 #define DP_SET_POWER                        0x600
 # define DP_SET_POWER_D0                    0x1
@@ -871,6 +872,7 @@ struct drm_dp_bd {
 	int type;
 	bool hpd;
 	uint8_t id[6];
+	uint8_t hw_rev;
 	union {
 		struct drm_dp_vga vga;
 		struct drm_dp_dvi dvi;
-- 
1.9.1

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[PATCH v3 11/12] drm/i915: Read DP branch device SW revision

[Mika Kahola]

SW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x50A.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 5 +++++
 include/drm/drm_dp_helper.h     | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 12ab26b..7e50d32 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3468,6 +3468,11 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
 				     sizeof(intel_dp->bd.hw_rev)) == sizeof(intel_dp->bd.hw_rev))
 			DRM_DEBUG_KMS("HW revision: %.2d.%.2d\n",
 				      intel_dp->bd.hw_rev & 0xf, (intel_dp->bd.hw_rev>>4) & 0xf);
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_SW_REV, intel_dp->bd.sw_rev,
+				     sizeof(intel_dp->bd.sw_rev)) == sizeof(intel_dp->bd.sw_rev))
+			DRM_DEBUG_KMS("SW revision: %.2d.%.2d\n",
+				      intel_dp->bd.sw_rev[0], intel_dp->bd.sw_rev[1]);
 	}
 }
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d0965ca..c0ca0c9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -459,6 +459,7 @@
 #define DP_BRANCH_OUI			    0x500
 #define DP_BRANCH_ID                        0x503
 #define DP_BRANCH_HW_REV                    0x509
+#define DP_BRANCH_SW_REV                    0x50A
 
 #define DP_SET_POWER                        0x600
 # define DP_SET_POWER_D0                    0x1
@@ -873,6 +874,7 @@ struct drm_dp_bd {
 	bool hpd;
 	uint8_t id[6];
 	uint8_t hw_rev;
+	uint8_t sw_rev[2];
 	union {
 		struct drm_dp_vga vga;
 		struct drm_dp_dvi dvi;
-- 
1.9.1

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[PATCH v3 12/12] drm/i915: Add DP branch device info on debugfs

[Mika Kahola]

Read DisplayPort branch device info from through debugfs
interface.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4c6b48d..74c6aa2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2923,6 +2923,43 @@ static void intel_dp_info(struct seq_file *m,
 
 	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
 	seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
+	seq_printf(m, "\tbranch device: %s\n", yesno(intel_dp->bd.present));
+
+	if (intel_dp->bd.present) {
+		switch (intel_dp->bd.type) {
+		case DP_DS_PORT_TYPE_DP:
+			seq_printf(m, "\ttype: DisplayPort\n");
+			break;
+		case DP_DS_PORT_TYPE_VGA:
+			seq_printf(m, "\ttype: VGA\n");
+			break;
+		case DP_DS_PORT_TYPE_DVI:
+			seq_printf(m, "\ttype: DVI\n");
+			break;
+		case DP_DS_PORT_TYPE_HDMI:
+			seq_printf(m, "\ttype: HDMI\n");
+			break;
+		case DP_DS_PORT_TYPE_NON_EDID:
+			seq_printf(m, "\ttype: others without EDID support\n");
+			break;
+		case DP_DS_PORT_TYPE_DP_DUALMODE:
+			seq_printf(m, "\ttype: DP++\n");
+			break;
+		case DP_DS_PORT_TYPE_WIRELESS:
+			seq_printf(m, "\ttype: Wireless\n");
+			break;
+		default:
+			seq_printf(m, "\ttype: N/A\n");
+		}
+
+		seq_printf(m, "\tHPD aware: %s\n", yesno(intel_dp->bd.hpd));
+		seq_printf(m, "\tDevice id: %s\n", intel_dp->bd.id);
+		seq_printf(m, "\tHW revision: %.2d.%.2d\n",
+			   intel_dp->bd.hw_rev & 0xf, (intel_dp->bd.hw_rev>>4) & 0xf);
+		seq_printf(m, "\tSW revision: %.2d.%.2d\n",
+			   intel_dp->bd.sw_rev[0], intel_dp->bd.sw_rev[1]);
+	}
+
 	if (intel_encoder->type == INTEL_OUTPUT_EDP)
 		intel_panel_info(m, &intel_connector->panel);
 }
-- 
1.9.1

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✓ Ro.CI.BAT: success for drm/i915: DP branch devices (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: DP branch devices (rev3)
URL   : https://patchwork.freedesktop.org/series/6658/
State : success

== Summary ==

Series 6658v3 drm/i915: DP branch devices
http://patchwork.freedesktop.org/api/1.0/series/6658/revisions/3/mbox

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                fail       -> PASS       (ro-byt-n2820)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (ro-bdw-i7-5600u)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (ro-ivb-i7-3770)
Test kms_sink_crc_basic:
                skip       -> PASS       (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-bsw-n3050     total:209  pass:167  dwarn:0   dfail:0   fail:2   skip:40 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:180  dwarn:0   dfail:0   fail:1   skip:28 
ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:170  dwarn:0   dfail:0   fail:2   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:183  dwarn:0   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
fi-byt-n2820 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_968/

eaa075a drm-intel-nightly: 2016y-05m-23d-08h-23m-34s UTC integration manifest
337a561 drm/i915: Add DP branch device info on debugfs
25f58c3 drm/i915: Read DP branch device SW revision
5a103c3 drm/i915: Read DP branch device HW revision
127ce17 drm/i915: Read DP branch device id
7c53d0d drm/i915: Check pixel rate for DP to VGA dongle
595beaf drm: Compute max pixel rate for DP sink
27394e7 drm: Read DPCD receiver capability for DP to Wireless Converter
3042dee drm: Read DPCD receiver capability for DP++
9ffd4f3 drm: Read DPCD receiver capability for DP to HDMI converter
bdb3668 drm: Read DPCD receiver capability for DP to DVI converter
92548e2 drm: Read DPCD receiver capability for DP to VGA converter
722a92f drm: Add missing DP downstream port types

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Re: [PATCH v3 02/12] drm: Read DPCD receiver capability for DP to VGA converter

[Ville Syrjälä]

On Mon, May 23, 2016 at 01:50:47PM +0300, Mika Kahola wrote:
> Read from DPCD receiver capability field the max allowed
> pixel clock and bits per component for DP to VGA converter.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c  | 46 ++++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  2 ++
>  include/drm/drm_dp_helper.h      | 21 ++++++++++++++++++
>  3 files changed, 69 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index eeaf5a7..c5bec6f 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -412,6 +412,52 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
>  }
>  EXPORT_SYMBOL(drm_dp_link_power_down);
>  
> +/*
> + * drm_dp_bd() - read DisplayPort Receiver Capability Fields for
> + * DP branch devices
> + * @aux: DisplayPort AUX channel
> + * @bd: pointer to a structure containing DP branch device information
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd)
> +{
> +	uint8_t info[4];
> +	uint8_t dfp;
> +	bool detailed_cap_info;
> +	int err, size;
> +
> +	err = drm_dp_dpcd_read(aux, DP_DOWNSTREAMPORT_PRESENT, &dfp, sizeof(dfp));
> +	if (err < 0)
> +		return err;
> +
> +	bd->present = dfp & 0x1;
> +
> +	if (!bd->present)
> +		return 0;
> +
> +	detailed_cap_info = dfp & DP_DETAILED_CAP_INFO_AVAILABLE;
> +
> +	size = detailed_cap_info ? 4 : 1;
> +
> +	err = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, info, size);
> +	if (err < 0)
> +		return err;
> +
> +	bd->type = info[0] & DP_DS_PORT_TYPE_MASK;
> +	bd->hpd = info[0] & DP_DS_PORT_HPD;
> +
> +	if (detailed_cap_info) {
> +		if (bd->type & DP_DS_PORT_TYPE_VGA) {
> +			bd->dfp.vga.dot_clk = info[1] * 8 * 1000;
> +			bd->dfp.vga.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
> +		}
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_bd);
> +
>  /**
>   * drm_dp_link_configure() - configure a DisplayPort link
>   * @aux: DisplayPort AUX channel
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 0741b2d..f85914b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -886,6 +886,8 @@ struct intel_dp {
>  
>  	bool train_set_valid;
>  
> +	struct drm_dp_bd bd;
> +
>  	/* Displayport compliance testing */
>  	unsigned long compliance_test_type;
>  	unsigned long compliance_test_data;
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index e384c7f..d3e78a5 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -802,10 +802,31 @@ struct drm_dp_link {
>  	unsigned long capabilities;
>  };
>  
> +/*
> + * DP to VGA
> + */
> +struct drm_dp_vga {
> +	int dot_clk;
> +	uint8_t bpc;
> +};
> +
> +/*
> + * Branch device
> + */
> +struct drm_dp_bd {
> +	bool present;
> +	int type;
> +	bool hpd;
> +	union {
> +		struct drm_dp_vga vga;
> +	} dfp;

I still don't see any real point in adding this thing. I'd just keep
the common dp helper style and pass the port caps to each function
that parses one thing from there. Eg.

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
			      const u8 port_cap[4]);
int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
				const u8 port_cap[4]);
etc.

> +};
> +
>  int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
>  int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
>  int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
>  int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
> +int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd);
>  
>  int drm_dp_aux_register(struct drm_dp_aux *aux);
>  void drm_dp_aux_unregister(struct drm_dp_aux *aux);
> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC
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