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From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
To: Kukjin Kim <kgene@kernel.org>,
	Krzysztof Kozlowski <k.kozlowski@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Javier Martinez Canillas <javier@osg.samsung.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Subject: [PATCH 2/3] clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks
Date: Wed, 01 Jun 2016 11:45:50 +0200	[thread overview]
Message-ID: <1464774351-23604-2-git-send-email-k.kozlowski@samsung.com> (raw)
In-Reply-To: <1464774351-23604-1-git-send-email-k.kozlowski@samsung.com>

Add clock hierarchy for Security SubSystem clock and watchdog.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos5410.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index db9978dc6e83..7e3ffa70d364 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -31,6 +31,7 @@
 #define SRC_CPU			0x200
 #define DIV_CPU0		0x500
 #define SRC_CPERI1		0x4204
+#define GATE_IP_G2D		0x8800
 #define DIV_TOP0		0x10510
 #define DIV_TOP1		0x10514
 #define DIV_FSYS0		0x10548
@@ -154,11 +155,15 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
 	DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
 
 	DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+	DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
 	DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
 };
 
 static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
+	GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
+
 	GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+	GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
 	GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
 	GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
 
-- 
1.9.1

WARNING: multiple messages have this Message-ID (diff)
From: k.kozlowski@samsung.com (Krzysztof Kozlowski)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks
Date: Wed, 01 Jun 2016 11:45:50 +0200	[thread overview]
Message-ID: <1464774351-23604-2-git-send-email-k.kozlowski@samsung.com> (raw)
In-Reply-To: <1464774351-23604-1-git-send-email-k.kozlowski@samsung.com>

Add clock hierarchy for Security SubSystem clock and watchdog.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos5410.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index db9978dc6e83..7e3ffa70d364 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -31,6 +31,7 @@
 #define SRC_CPU			0x200
 #define DIV_CPU0		0x500
 #define SRC_CPERI1		0x4204
+#define GATE_IP_G2D		0x8800
 #define DIV_TOP0		0x10510
 #define DIV_TOP1		0x10514
 #define DIV_FSYS0		0x10548
@@ -154,11 +155,15 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
 	DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
 
 	DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+	DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
 	DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
 };
 
 static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
+	GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
+
 	GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+	GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
 	GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
 	GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
 
-- 
1.9.1

  reply	other threads:[~2016-06-01  9:48 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-01  9:45 [PATCH 1/3] dt-bindings: clock: Add watchdog and SSS clock IDs to Exynos5410 Krzysztof Kozlowski
2016-06-01  9:45 ` Krzysztof Kozlowski
2016-06-01  9:45 ` Krzysztof Kozlowski [this message]
2016-06-01  9:45   ` [PATCH 2/3] clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks Krzysztof Kozlowski
2016-06-01 14:55   ` Javier Martinez Canillas
2016-06-01 14:55     ` Javier Martinez Canillas
2016-06-02  9:20     ` Sylwester Nawrocki
2016-06-02  9:20       ` Sylwester Nawrocki
2016-06-06 11:02   ` Sylwester Nawrocki
2016-06-06 11:02     ` Sylwester Nawrocki
2016-06-06 11:02     ` Sylwester Nawrocki
2016-06-06 11:13     ` Krzysztof Kozlowski
2016-06-06 11:13       ` Krzysztof Kozlowski
2016-06-01  9:45 ` [PATCH 3/3] ARM: dts: exynos: Add watchdog amd Security SubSystem to Exynos5410 Krzysztof Kozlowski
2016-06-01  9:45   ` Krzysztof Kozlowski
2016-06-01 15:16   ` Javier Martinez Canillas
2016-06-01 15:16     ` Javier Martinez Canillas
2016-06-02  6:18     ` Krzysztof Kozlowski
2016-06-02  6:18       ` Krzysztof Kozlowski
2016-06-02 13:27       ` Javier Martinez Canillas
2016-06-02 13:27         ` Javier Martinez Canillas
2016-06-01 14:53 ` [PATCH 1/3] dt-bindings: clock: Add watchdog and SSS clock IDs " Javier Martinez Canillas
2016-06-01 14:53   ` Javier Martinez Canillas

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