[PATCH 0/5] arm64: hibernate: Fix DEBUG_PAGEALLOC and hibernate on non-boot cpu

[PATCH 0/5] arm64: hibernate: Fix DEBUG_PAGEALLOC and hibernate on non-boot cpu

[James Morse]

Hi all,

These patches improve the hibernate support for v4.8.

Patches 1&2 fix the hibernate problem with DEBUG_PAGEALLOC reported by Will.
This also addresses the outstanding comment from Catalin [0] regarding cleaning
of the whole kernel to the PoC. Now we clean just the sections grouped by
'TEXT_TEXT'.

Patch one adds sections.h to avoid duplicate definitions of
__hyp_idmap_text_start. (it looks like kprobes will duplicate this too [1)

The rest of the patches fix hibernate/resume on any CPU as discussed on the
list[2]. Suzuki's maxcpus improvements mean the CPU we hibernated on may be
offline during boot, and kexec will allow the CPUs logical order to be shuffled.
Log output below[3], suspend happens on cpu0, with mpidr 0x103. For
resume, cpu5 is brought up as it has mpidr 0x103, and cpu0 is taken down.
After resume, /proc/cpuinfo shows only the original cpu0.


[0] http://www.spinics.net/lists/arm-kernel/msg499305.html
[1] http://www.spinics.net/lists/arm-kernel/msg506451.html
[2] http://www.spinics.net/lists/arm-kernel/msg499036.html
[3] hotplug cpu0, kexec, hibernate, resume
-------------------------%<-------------------------
root@ubuntu:~# echo disk > /sys/power/state
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.007 seconds) done.
PM: Preallocating image memory... done (allocated 10112 pages)
PM: Allocated 647168 kbytes in 2.69 seconds (240.58 MB/s)
Freezing remaining freezable tasks ... (elapsed 0.005 seconds) done.
PM: freeze of devices complete after 27.013 msecs
PM: late freeze of devices complete after 20.624 msecs
PM: noirq freeze of devices complete after 22.211 msecs
Disabling non-boot CPUs ...
PM: Creating hibernation image:
PM: Need to copy 10103 pages
PM: Hibernation image created (10103 pages copied)
PM: noirq thaw of devices complete after 22.350 msecs
PM: early thaw of devices complete after 23.680 msecs
PM: thaw of devices complete after 98.331 msecs
hibernate: Suspending on cpu 0 [mpidr:0x103]
PM: Using 1 thread(s) for compression.
PM: Compressing and saving image data (10105 pages)...
PM: Image saving progress:   0%
atkbd serio0: keyboard reset failed on 1c060000.kmi
atkbd serio1: keyboard reset failed on 1c070000.kmi
PM: Image saving progress:  10%
PM: Image saving progress:  20%
PM: Image saving progress:  30%
PM: Image saving progress:  40%
PM: Image saving progress:  50%
PM: Image saving progress:  60%
PM: Image saving progress:  70%
PM: Image saving progress:  80%
PM: Image saving progress:  90%
PM: Image saving progress: 100%
PM: Image saving done.
PM: Wrote 646720 kbytes in 93.08 seconds (6.94 MB/s)
PM: S|
reboot: Power down

[ ... ]

Freezing user space processes ... (elapsed 0.000 seconds) done.
PM: Using 1 thread(s) for decompression.
PM: Loading and decompressing image data (10105 pages)...
hibernate: Suspended on cpu 5 [mpidr:0x103]
hibernate: Suspended on a CPU that is offline! Brining CPU up.
Detected VIPT I-cache on CPU5
CPU5: Booted secondary processor [410fd033]
random: nonblocking pool is initialized
PM: Image loading progress:   0%
PM: Image loading progress:  10%
PM: Image loading progress:  20%
PM: Image loading progress:  30%
PM: Image loading progress:  40%
PM: Image loading progress:  50%
PM: Image loading progress:  60%
PM: Image loading progress:  70%
PM: Image loading progress:  80%
PM: Image loading progress:  90%
PM: Image loading progress: 100%
PM: Image loading done.
PM: Read 646720 kbytes in 30.47 seconds (21.22 MB/s)
PM: quiesce of devices complete after 32.958 msecs
PM: late quiesce of devices complete after 11.574 msecs
PM: noirq quiesce of devices complete after 24.918 msecs
hibernate: Disabling secondary CPUs ...
IRQ1 no longer affine to CPU0
IRQ6 no longer affine to CPU0
IRQ28 no longer affine to CPU0
IRQ29 no longer affine to CPU0
IRQ32 no longer affine to CPU0
IRQ34 no longer affine to CPU0
IRQ35 no longer affine to CPU0
IRQ37 no longer affine to CPU0
IRQ41 no longer affine to CPU0
IRQ48 no longer affine to CPU0
CPU0: shutdown

psci: CPU0 killed.
PM: noirq restore of devices complete after 27.419 msecs
PM: early restore of devices complete after 23.554 msecs
PM: restore of devices complete after 113.188 msecs
Restarting tasks ... done.
root@ubuntu:~# atkbd serio0: keyboard reset failed on 1c060000.kmi
atkbd serio1: keyboard reset failed on 1c070000.kmi
root@ubuntu:~# cat /proc/cpuinfo
processor       : 0
BogoMIPS        : 100.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd03
CPU revision    : 3

root@ubuntu:~#
-------------------------%<-------------------------

James Morse (5):
  arm64: Add markers around .text section and create sections.h
  arm64: hibernate: Support DEBUG_PAGEALLOC
  PM / Hibernate: Allow architectures to specify the hibernate/resume
    CPU
  arm64: hibernate: Identify the CPU to resume on by its MPIDR
  Revert "arm64: hibernate: Refuse to hibernate if the boot cpu is
    offline"

 arch/arm64/Kconfig                |   1 -
 arch/arm64/include/asm/Kbuild     |   1 -
 arch/arm64/include/asm/sections.h |  29 ++++++++
 arch/arm64/include/asm/suspend.h  |   1 +
 arch/arm64/include/asm/traps.h    |   3 +-
 arch/arm64/include/asm/virt.h     |   5 +-
 arch/arm64/kernel/alternative.c   |   7 +-
 arch/arm64/kernel/hibernate.c     | 137 ++++++++++++++++++++++++++++----------
 arch/arm64/kernel/vmlinux.lds.S   |   2 +
 arch/arm64/kvm/reset.c            |   3 +-
 arch/arm64/mm/pageattr.c          |  40 ++++++++++-
 kernel/power/hibernate.c          |  16 ++++-
 12 files changed, 191 insertions(+), 54 deletions(-)
 create mode 100644 arch/arm64/include/asm/sections.h

-- 
2.8.0.rc3

[PATCH 0/5] arm64: hibernate: Fix DEBUG_PAGEALLOC and hibernate on non-boot cpu

[James Morse]

Hi all,

These patches improve the hibernate support for v4.8.

Patches 1&2 fix the hibernate problem with DEBUG_PAGEALLOC reported by Will.
This also addresses the outstanding comment from Catalin [0] regarding cleaning
of the whole kernel to the PoC. Now we clean just the sections grouped by
'TEXT_TEXT'.

Patch one adds sections.h to avoid duplicate definitions of
__hyp_idmap_text_start. (it looks like kprobes will duplicate this too [1)

The rest of the patches fix hibernate/resume on any CPU as discussed on the
list[2]. Suzuki's maxcpus improvements mean the CPU we hibernated on may be
offline during boot, and kexec will allow the CPUs logical order to be shuffled.
Log output below[3], suspend happens on cpu0, with mpidr 0x103. For
resume, cpu5 is brought up as it has mpidr 0x103, and cpu0 is taken down.
After resume, /proc/cpuinfo shows only the original cpu0.


[0] http://www.spinics.net/lists/arm-kernel/msg499305.html
[1] http://www.spinics.net/lists/arm-kernel/msg506451.html
[2] http://www.spinics.net/lists/arm-kernel/msg499036.html
[3] hotplug cpu0, kexec, hibernate, resume
-------------------------%<-------------------------
root@ubuntu:~# echo disk > /sys/power/state
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.007 seconds) done.
PM: Preallocating image memory... done (allocated 10112 pages)
PM: Allocated 647168 kbytes in 2.69 seconds (240.58 MB/s)
Freezing remaining freezable tasks ... (elapsed 0.005 seconds) done.
PM: freeze of devices complete after 27.013 msecs
PM: late freeze of devices complete after 20.624 msecs
PM: noirq freeze of devices complete after 22.211 msecs
Disabling non-boot CPUs ...
PM: Creating hibernation image:
PM: Need to copy 10103 pages
PM: Hibernation image created (10103 pages copied)
PM: noirq thaw of devices complete after 22.350 msecs
PM: early thaw of devices complete after 23.680 msecs
PM: thaw of devices complete after 98.331 msecs
hibernate: Suspending on cpu 0 [mpidr:0x103]
PM: Using 1 thread(s) for compression.
PM: Compressing and saving image data (10105 pages)...
PM: Image saving progress:   0%
atkbd serio0: keyboard reset failed on 1c060000.kmi
atkbd serio1: keyboard reset failed on 1c070000.kmi
PM: Image saving progress:  10%
PM: Image saving progress:  20%
PM: Image saving progress:  30%
PM: Image saving progress:  40%
PM: Image saving progress:  50%
PM: Image saving progress:  60%
PM: Image saving progress:  70%
PM: Image saving progress:  80%
PM: Image saving progress:  90%
PM: Image saving progress: 100%
PM: Image saving done.
PM: Wrote 646720 kbytes in 93.08 seconds (6.94 MB/s)
PM: S|
reboot: Power down

[ ... ]

Freezing user space processes ... (elapsed 0.000 seconds) done.
PM: Using 1 thread(s) for decompression.
PM: Loading and decompressing image data (10105 pages)...
hibernate: Suspended on cpu 5 [mpidr:0x103]
hibernate: Suspended on a CPU that is offline! Brining CPU up.
Detected VIPT I-cache on CPU5
CPU5: Booted secondary processor [410fd033]
random: nonblocking pool is initialized
PM: Image loading progress:   0%
PM: Image loading progress:  10%
PM: Image loading progress:  20%
PM: Image loading progress:  30%
PM: Image loading progress:  40%
PM: Image loading progress:  50%
PM: Image loading progress:  60%
PM: Image loading progress:  70%
PM: Image loading progress:  80%
PM: Image loading progress:  90%
PM: Image loading progress: 100%
PM: Image loading done.
PM: Read 646720 kbytes in 30.47 seconds (21.22 MB/s)
PM: quiesce of devices complete after 32.958 msecs
PM: late quiesce of devices complete after 11.574 msecs
PM: noirq quiesce of devices complete after 24.918 msecs
hibernate: Disabling secondary CPUs ...
IRQ1 no longer affine to CPU0
IRQ6 no longer affine to CPU0
IRQ28 no longer affine to CPU0
IRQ29 no longer affine to CPU0
IRQ32 no longer affine to CPU0
IRQ34 no longer affine to CPU0
IRQ35 no longer affine to CPU0
IRQ37 no longer affine to CPU0
IRQ41 no longer affine to CPU0
IRQ48 no longer affine to CPU0
CPU0: shutdown

psci: CPU0 killed.
PM: noirq restore of devices complete after 27.419 msecs
PM: early restore of devices complete after 23.554 msecs
PM: restore of devices complete after 113.188 msecs
Restarting tasks ... done.
root at ubuntu:~# atkbd serio0: keyboard reset failed on 1c060000.kmi
atkbd serio1: keyboard reset failed on 1c070000.kmi
root at ubuntu:~# cat /proc/cpuinfo
processor       : 0
BogoMIPS        : 100.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd03
CPU revision    : 3

root at ubuntu:~#
-------------------------%<-------------------------

James Morse (5):
  arm64: Add markers around .text section and create sections.h
  arm64: hibernate: Support DEBUG_PAGEALLOC
  PM / Hibernate: Allow architectures to specify the hibernate/resume
    CPU
  arm64: hibernate: Identify the CPU to resume on by its MPIDR
  Revert "arm64: hibernate: Refuse to hibernate if the boot cpu is
    offline"

 arch/arm64/Kconfig                |   1 -
 arch/arm64/include/asm/Kbuild     |   1 -
 arch/arm64/include/asm/sections.h |  29 ++++++++
 arch/arm64/include/asm/suspend.h  |   1 +
 arch/arm64/include/asm/traps.h    |   3 +-
 arch/arm64/include/asm/virt.h     |   5 +-
 arch/arm64/kernel/alternative.c   |   7 +-
 arch/arm64/kernel/hibernate.c     | 137 ++++++++++++++++++++++++++++----------
 arch/arm64/kernel/vmlinux.lds.S   |   2 +
 arch/arm64/kvm/reset.c            |   3 +-
 arch/arm64/mm/pageattr.c          |  40 ++++++++++-
 kernel/power/hibernate.c          |  16 ++++-
 12 files changed, 191 insertions(+), 54 deletions(-)
 create mode 100644 arch/arm64/include/asm/sections.h

-- 
2.8.0.rc3

[PATCH 1/5] arm64: Add markers around .text section and create sections.h

[James Morse]

During resume from hibernate, memory containing the kernel text is cleaned
to the PoU. Some parts of the kernel are executed with the MMU off, in
which case these instructions need to be cleaned to the PoC.

To aid the cleaning of this text, add markers around the existing section.

Each time new section markers are added, kernel/vmlinux.ld.S is updated,
and new extern char __start_foo[] definitions are scattered through the
tree.

Create asm/include/sections.h to collect these definitions (and include
the existing asm-generic version).

Signed-off-by: James Morse <james.morse@arm.com>
---
 arch/arm64/include/asm/Kbuild     |  1 -
 arch/arm64/include/asm/sections.h | 29 +++++++++++++++++++++++++++++
 arch/arm64/include/asm/traps.h    |  3 +--
 arch/arm64/include/asm/virt.h     |  5 +----
 arch/arm64/kernel/alternative.c   |  7 +++----
 arch/arm64/kernel/hibernate.c     |  6 ------
 arch/arm64/kernel/vmlinux.lds.S   |  2 ++
 arch/arm64/kvm/reset.c            |  3 +--
 8 files changed, 37 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm64/include/asm/sections.h

diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index cff532a6744e..50c1f646b704 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -33,7 +33,6 @@ generic-y += poll.h
 generic-y += preempt.h
 generic-y += resource.h
 generic-y += rwsem.h
-generic-y += sections.h
 generic-y += segment.h
 generic-y += sembuf.h
 generic-y += serial.h
diff --git a/arch/arm64/include/asm/sections.h b/arch/arm64/include/asm/sections.h
new file mode 100644
index 000000000000..1d9b0149f413
--- /dev/null
+++ b/arch/arm64/include/asm/sections.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2016 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SECTIONS_H
+#define __ASM_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern char __hyp_idmap_text_start[], __hyp_idmap_text_end[];
+extern char __hyp_text_start[], __hyp_text_end[];
+extern char __idmap_text_start[], __idmap_text_end[];
+extern char __hibernate_exit_text_start[], __hibernate_exit_text_end[];
+extern char __text_text_start[], __text_text_end[];
+extern char __exception_text_start[], __exception_text_end[];
+extern char __alt_instructions[], __alt_instructions_end[];
+
+#endif /* __ASM_SECTIONS_H */
diff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h
index 0cc2f29bf9da..90156c803f11 100644
--- a/arch/arm64/include/asm/traps.h
+++ b/arch/arm64/include/asm/traps.h
@@ -19,6 +19,7 @@
 #define __ASM_TRAP_H
 
 #include <linux/list.h>
+#include <asm/sections.h>
 
 struct pt_regs;
 
@@ -52,8 +53,6 @@ static inline int __in_irqentry_text(unsigned long ptr)
 
 static inline int in_exception_text(unsigned long ptr)
 {
-	extern char __exception_text_start[];
-	extern char __exception_text_end[];
 	int in;
 
 	in = ptr >= (unsigned long)&__exception_text_start &&
diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
index dcbcf8dcbefb..b78611157f8b 100644
--- a/arch/arm64/include/asm/virt.h
+++ b/arch/arm64/include/asm/virt.h
@@ -40,6 +40,7 @@
 #ifndef __ASSEMBLY__
 
 #include <asm/ptrace.h>
+#include <asm/sections.h>
 
 /*
  * __boot_cpu_mode records what mode CPUs were booted in.
@@ -82,10 +83,6 @@ extern void verify_cpu_run_el(void);
 static inline void verify_cpu_run_el(void) {}
 #endif
 
-/* The section containing the hypervisor text */
-extern char __hyp_text_start[];
-extern char __hyp_text_end[];
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* ! __ASM__VIRT_H */
diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
index d2ee1b21a10d..4434dabde898 100644
--- a/arch/arm64/kernel/alternative.c
+++ b/arch/arm64/kernel/alternative.c
@@ -25,14 +25,13 @@
 #include <asm/alternative.h>
 #include <asm/cpufeature.h>
 #include <asm/insn.h>
+#include <asm/sections.h>
 #include <linux/stop_machine.h>
 
 #define __ALT_PTR(a,f)		(u32 *)((void *)&(a)->f + (a)->f)
 #define ALT_ORIG_PTR(a)		__ALT_PTR(a, orig_offset)
 #define ALT_REPL_PTR(a)		__ALT_PTR(a, alt_offset)
 
-extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
-
 struct alt_region {
 	struct alt_instr *begin;
 	struct alt_instr *end;
@@ -124,8 +123,8 @@ static int __apply_alternatives_multi_stop(void *unused)
 {
 	static int patched = 0;
 	struct alt_region region = {
-		.begin	= __alt_instructions,
-		.end	= __alt_instructions_end,
+		.begin	= (struct alt_instr *)__alt_instructions,
+		.end	= (struct alt_instr *)__alt_instructions_end,
 	};
 
 	/* We always have a CPU 0 at this point (__init) */
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index f8df75d740f4..56e548fe0386 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -52,12 +52,6 @@ extern int in_suspend;
 /* Do we need to reset el2? */
 #define el2_reset_needed() (is_hyp_mode_available() && !is_kernel_in_hyp_mode())
 
-/*
- * Start/end of the hibernate exit code, this must be copied to a 'safe'
- * location in memory, and executed from there.
- */
-extern char __hibernate_exit_text_start[], __hibernate_exit_text_end[];
-
 /* temporary el2 vectors in the __hibernate_exit_text section. */
 extern char hibernate_el2_vectors[];
 
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 435e820e898d..6b3d2781a9f2 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -118,7 +118,9 @@ SECTIONS
 			__exception_text_end = .;
 			IRQENTRY_TEXT
 			SOFTIRQENTRY_TEXT
+			__text_text_start = .;
 			TEXT_TEXT
+			__text_text_end = .;
 			SCHED_TEXT
 			LOCK_TEXT
 			HYPERVISOR_TEXT
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index b1ad730e1567..c2d3594dd546 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -32,6 +32,7 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_coproc.h>
 #include <asm/kvm_mmu.h>
+#include <asm/sections.h>
 
 /*
  * ARMv8 Reset Values
@@ -133,8 +134,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 	return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
 }
 
-extern char __hyp_idmap_text_start[];
-
 unsigned long kvm_hyp_reset_entry(void)
 {
 	if (!__kvm_cpu_uses_extended_idmap()) {
-- 
2.8.0.rc3

[PATCH 2/5] arm64: hibernate: Support DEBUG_PAGEALLOC

[James Morse]

DEBUG_PAGEALLOC removes the valid bit of page table entries to prevent
any access to unallocated memory. Hibernate uses this as a hint that those
pages don't need to be saved/restored. This patch adds the
kernel_page_present() function it uses.

hibernate.c copies the resume kernel's linear map for use during restore.
Add _copy_pte() to fill-in the holes made by DEBUG_PAGEALLOC in the resume
kernel, so we can restore data the original kernel had at these addresses.

Finally, DEBUG_PAGEALLOC means the linear-map alias of KERNEL_START to
KERNEL_END may have holes in it, so we can't lazily clean this whole
area to the PoC. Only clean the 'text_text' region, and the kernel/kvm
idmaps.

This reverts commit da24eb1f3f9e2c7b75c5f8c40d8e48e2c4789596.

Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
---
 arch/arm64/Kconfig            |  1 -
 arch/arm64/kernel/hibernate.c | 45 ++++++++++++++++++++++++++++++++++---------
 arch/arm64/mm/pageattr.c      | 40 +++++++++++++++++++++++++++++++++++++-
 3 files changed, 75 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 76747d92bc72..00ee83342949 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -577,7 +577,6 @@ source kernel/Kconfig.preempt
 source kernel/Kconfig.hz
 
 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
-	depends on !HIBERNATION
 	def_bool y
 
 config ARCH_HAS_HOLES_MEMORYMODEL
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index 56e548fe0386..c114c405d851 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -235,8 +235,15 @@ int swsusp_arch_suspend(void)
 	if (__cpu_suspend_enter(&state)) {
 		ret = swsusp_save();
 	} else {
-		/* Clean kernel to PoC for secondary core startup */
-		__flush_dcache_area(LMADDR(KERNEL_START), KERNEL_END - KERNEL_START);
+		/* Clean kernel core startup/idle code to PoC*/
+		__flush_dcache_area(__text_text_start,
+				    __text_text_end - __text_text_start);
+		__flush_dcache_area(__idmap_text_start,
+				    __idmap_text_end - __idmap_text_start);
+
+		/* Clean kvm setup code to PoC? */
+		if (el2_reset_needed())
+			__flush_dcache_area(__hyp_idmap_text_start, __hyp_idmap_text_end - __hyp_idmap_text_start);
 
 		/*
 		 * Tell the hibernation core that we've just restored
@@ -252,6 +259,32 @@ int swsusp_arch_suspend(void)
 	return ret;
 }
 
+static void _copy_pte(pte_t *dst_pte, pte_t *src_pte, unsigned long addr)
+{
+	unsigned long pfn = virt_to_pfn(addr);
+
+	if (pte_valid(*src_pte)) {
+		/*
+		 * Resume will overwrite areas that may be marked
+		 * read only (code, rodata). Clear the RDONLY bit from
+		 * the temporary mappings we use during restore.
+		 */
+		set_pte(dst_pte, __pte(pte_val(*src_pte) & ~PTE_RDONLY));
+	} else if (debug_pagealloc_enabled()) {
+		/*
+		 * debug_pagealloc may have removed the PTE_VALID bit if
+		 * the page isn't in use by the resume kernel. It may have
+		 * been in use by the original kernel, in which case we need
+		 * to put it back in our copy to do the restore.
+		 *
+		 * Check for mappable memory that gives us a translation
+		 * like part of the linear map.
+		 */
+		if (pfn_valid(pfn) && pte_pfn(*src_pte) == pfn)
+			set_pte(dst_pte, __pte((pte_val(*src_pte) & ~PTE_RDONLY) | PTE_VALID));
+	}
+}
+
 static int copy_pte(pmd_t *dst_pmd, pmd_t *src_pmd, unsigned long start,
 		    unsigned long end)
 {
@@ -267,13 +300,7 @@ static int copy_pte(pmd_t *dst_pmd, pmd_t *src_pmd, unsigned long start,
 
 	src_pte = pte_offset_kernel(src_pmd, start);
 	do {
-		if (!pte_none(*src_pte))
-			/*
-			 * Resume will overwrite areas that may be marked
-			 * read only (code, rodata). Clear the RDONLY bit from
-			 * the temporary mappings we use during restore.
-			 */
-			set_pte(dst_pte, __pte(pte_val(*src_pte) & ~PTE_RDONLY));
+		_copy_pte(dst_pte, src_pte, addr);
 	} while (dst_pte++, src_pte++, addr += PAGE_SIZE, addr != end);
 
 	return 0;
diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c
index ca6d268e3313..b6c0da84258c 100644
--- a/arch/arm64/mm/pageattr.c
+++ b/arch/arm64/mm/pageattr.c
@@ -139,4 +139,42 @@ void __kernel_map_pages(struct page *page, int numpages, int enable)
 					__pgprot(0),
 					__pgprot(PTE_VALID));
 }
-#endif
+#ifdef CONFIG_HIBERNATION
+/*
+ * When built with CONFIG_DEBUG_PAGEALLOC and CONFIG_HIBERNATION, this function
+ * is used to determine if a linear map page has been marked as not-present by
+ * CONFIG_DEBUG_PAGEALLOC. Walk the page table and check the PTE_VALID bit.
+ * This is based on kern_addr_valid(), which almost does what we need.
+ */
+bool kernel_page_present(struct page *page)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+	unsigned long addr = (unsigned long)page_address(page);
+
+	pgd = pgd_offset_k(addr);
+	if (pgd_none(*pgd))
+		return false;
+
+	pud = pud_offset(pgd, addr);
+	if (pud_none(*pud))
+		return false;
+	if (pud_sect(*pud))
+		return true;
+
+	pmd = pmd_offset(pud, addr);
+	if (pmd_none(*pmd))
+		return false;
+	if (pmd_sect(*pmd))
+		return true;
+
+	pte = pte_offset_kernel(pmd, addr);
+	if (pte_none(*pte))
+		return false;
+
+	return pte_valid(*pte);
+}
+#endif /* CONFIG_HIBERNATION */
+#endif /* CONFIG_DEBUG_PAGEALLOC */
-- 
2.8.0.rc3

[PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[James Morse]

On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
kernel will assign logical id 0 to a different physical CPU.
This breaks hibernate as hibernate and resume will be attempted on different
CPUs.

Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
hotplugged can use this to control which CPU is used for hibernate/resume.

Signed-off-by: James Morse <james.morse@arm.com>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Pavel Machek <pavel@ucw.cz>
---
I would have preferred a macro, but there is no hibernate-relevant header
file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
doesn't.

If this approach is acceptable, this patch should go with 4&5 via the arm64
tree.

 kernel/power/hibernate.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c
index fca9254280ee..0e668a3207ec 100644
--- a/kernel/power/hibernate.c
+++ b/kernel/power/hibernate.c
@@ -70,6 +70,16 @@ bool hibernation_available(void)
 }
 
 /**
+ * arch_hibernation_disable_cpus - Allow architectures to direct which CPU
+ * is used for suspend or resume.
+ * @suspend: True during hibernate, false for resume.
+ */
+int __weak arch_hibernation_disable_cpus(__maybe_unused bool suspend)
+{
+	return disable_nonboot_cpus();
+}
+
+/**
  * hibernation_set_ops - Set the global hibernate operations.
  * @ops: Hibernation operations to use in subsequent hibernation transitions.
  */
@@ -279,7 +289,7 @@ static int create_image(int platform_mode)
 	if (error || hibernation_test(TEST_PLATFORM))
 		goto Platform_finish;
 
-	error = disable_nonboot_cpus();
+	error = arch_hibernation_disable_cpus(true);
 	if (error || hibernation_test(TEST_CPUS))
 		goto Enable_cpus;
 
@@ -433,7 +443,7 @@ static int resume_target_kernel(bool platform_mode)
 	if (error)
 		goto Cleanup;
 
-	error = disable_nonboot_cpus();
+	error = arch_hibernation_disable_cpus(false);
 	if (error)
 		goto Enable_cpus;
 
@@ -551,7 +561,7 @@ int hibernation_platform_enter(void)
 	if (error)
 		goto Platform_finish;
 
-	error = disable_nonboot_cpus();
+	error = arch_hibernation_disable_cpus(true);
 	if (error)
 		goto Enable_cpus;
 
-- 
2.8.0.rc3

[PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[James Morse]

On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
kernel will assign logical id 0 to a different physical CPU.
This breaks hibernate as hibernate and resume will be attempted on different
CPUs.

Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
hotplugged can use this to control which CPU is used for hibernate/resume.

Signed-off-by: James Morse <james.morse@arm.com>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Pavel Machek <pavel@ucw.cz>
---
I would have preferred a macro, but there is no hibernate-relevant header
file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
doesn't.

If this approach is acceptable, this patch should go with 4&5 via the arm64
tree.

 kernel/power/hibernate.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c
index fca9254280ee..0e668a3207ec 100644
--- a/kernel/power/hibernate.c
+++ b/kernel/power/hibernate.c
@@ -70,6 +70,16 @@ bool hibernation_available(void)
 }
 
 /**
+ * arch_hibernation_disable_cpus - Allow architectures to direct which CPU
+ * is used for suspend or resume.
+ * @suspend: True during hibernate, false for resume.
+ */
+int __weak arch_hibernation_disable_cpus(__maybe_unused bool suspend)
+{
+	return disable_nonboot_cpus();
+}
+
+/**
  * hibernation_set_ops - Set the global hibernate operations.
  * @ops: Hibernation operations to use in subsequent hibernation transitions.
  */
@@ -279,7 +289,7 @@ static int create_image(int platform_mode)
 	if (error || hibernation_test(TEST_PLATFORM))
 		goto Platform_finish;
 
-	error = disable_nonboot_cpus();
+	error = arch_hibernation_disable_cpus(true);
 	if (error || hibernation_test(TEST_CPUS))
 		goto Enable_cpus;
 
@@ -433,7 +443,7 @@ static int resume_target_kernel(bool platform_mode)
 	if (error)
 		goto Cleanup;
 
-	error = disable_nonboot_cpus();
+	error = arch_hibernation_disable_cpus(false);
 	if (error)
 		goto Enable_cpus;
 
@@ -551,7 +561,7 @@ int hibernation_platform_enter(void)
 	if (error)
 		goto Platform_finish;
 
-	error = disable_nonboot_cpus();
+	error = arch_hibernation_disable_cpus(true);
 	if (error)
 		goto Enable_cpus;
 
-- 
2.8.0.rc3

[PATCH 4/5] arm64: hibernate: Identify the CPU to resume on by its MPIDR

[James Morse]

On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
kernel will assign logical id 0 to a different physical CPU.
This breaks hibernate as hibernate and resume will be attempted on different
CPUs.

Save the MPIDR of the CPU we hibernated on in the hibernate arch-header,
and provide arch_hibernation_disable_cpus() to switch to that CPU during
resume. During hibernate use disable_nonboot_cpus(), and save the MPIDR of
the CPU it selected, this ensures frozen_cpus is updated correctly.

Booting with maxcpus=1, then bringing additional CPUs up from user space may
cause us to hibernate on a CPU that isn't online during boot. In this case,
bring the CPU online.

Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
 arch/arm64/include/asm/suspend.h |  1 +
 arch/arm64/kernel/hibernate.c    | 70 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/suspend.h
index 024d623f662e..487758882ef3 100644
--- a/arch/arm64/include/asm/suspend.h
+++ b/arch/arm64/include/asm/suspend.h
@@ -46,5 +46,6 @@ int swsusp_arch_suspend(void);
 int swsusp_arch_resume(void);
 int arch_hibernation_header_save(void *addr, unsigned int max_size);
 int arch_hibernation_header_restore(void *addr);
+int arch_hibernation_disable_cpus(bool suspend);
 
 #endif
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index c114c405d851..6b6ea9aca6d0 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -15,6 +15,7 @@
  * License terms: GNU General Public License (GPL) version 2
  */
 #define pr_fmt(x) "hibernate: " x
+#include <linux/cpu.h>
 #include <linux/kvm_host.h>
 #include <linux/mm.h>
 #include <linux/notifier.h>
@@ -26,6 +27,7 @@
 
 #include <asm/barrier.h>
 #include <asm/cacheflush.h>
+#include <asm/cputype.h>
 #include <asm/irqflags.h>
 #include <asm/memory.h>
 #include <asm/mmu_context.h>
@@ -33,6 +35,7 @@
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/sections.h>
+#include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/virt.h>
 
@@ -59,6 +62,12 @@ extern char hibernate_el2_vectors[];
 extern char __hyp_stub_vectors[];
 
 /*
+ * The logical cpu number we should resume on, initialised to a non-cpu
+ * number.
+ */
+static int sleep_cpu = -EINVAL;
+
+/*
  * Values that may not change over hibernate/resume. We put the build number
  * and date in here so that we guarantee not to resume with a different
  * kernel.
@@ -80,6 +89,8 @@ static struct arch_hibernate_hdr {
 	 * re-configure el2.
 	 */
 	phys_addr_t	__hyp_stub_vectors;
+
+	u64		sleep_cpu_mpidr;
 } resume_hdr;
 
 static inline void arch_hdr_invariants(struct arch_hibernate_hdr_invariants *i)
@@ -122,12 +133,18 @@ int arch_hibernation_header_save(void *addr, unsigned int max_size)
 	else
 		hdr->__hyp_stub_vectors = 0;
 
+	/* Save the mpidr of the cpu we called cpu_suspend() on... */
+	hdr->sleep_cpu_mpidr = cpu_logical_map(sleep_cpu);
+	pr_info("Suspending on CPU %d [mpidr:0x%llx]\n", sleep_cpu,
+		hdr->sleep_cpu_mpidr);
+
 	return 0;
 }
 EXPORT_SYMBOL(arch_hibernation_header_save);
 
 int arch_hibernation_header_restore(void *addr)
 {
+	int ret;
 	struct arch_hibernate_hdr_invariants invariants;
 	struct arch_hibernate_hdr *hdr = addr;
 
@@ -137,6 +154,23 @@ int arch_hibernation_header_restore(void *addr)
 		return -EINVAL;
 	}
 
+	sleep_cpu = get_logical_index(hdr->sleep_cpu_mpidr);
+	pr_info("Suspended on CPU %d [mpidr:0x%llx]\n", sleep_cpu,
+		hdr->sleep_cpu_mpidr);
+	if (sleep_cpu < 0) {
+		pr_crit("Suspended on a CPU not known to this kernel!\n");
+		return -EINVAL;
+	}
+	if (!cpu_online(sleep_cpu)) {
+		pr_info("Suspended on a CPU that is offline! Brining CPU up.\n");
+		ret = cpu_up(sleep_cpu);
+		if (ret) {
+			pr_err("Failed to bring suspend-CPU up!\n");
+			sleep_cpu = -EINVAL;
+			return ret;
+		}
+	}
+
 	resume_hdr = *hdr;
 
 	return 0;
@@ -233,6 +267,7 @@ int swsusp_arch_suspend(void)
 	local_dbg_save(flags);
 
 	if (__cpu_suspend_enter(&state)) {
+		sleep_cpu = smp_processor_id();
 		ret = swsusp_save();
 	} else {
 		/* Clean kernel core startup/idle code to PoC*/
@@ -251,6 +286,7 @@ int swsusp_arch_suspend(void)
 		 */
 		in_suspend = 0;
 
+		sleep_cpu = -EINVAL;
 		__cpu_suspend_exit();
 	}
 
@@ -506,3 +542,37 @@ static int __init check_boot_cpu_online_init(void)
 	return 0;
 }
 core_initcall(check_boot_cpu_online_init);
+
+/* This overrides the weak version in kernel/power/hibernate.c */
+int arch_hibernation_disable_cpus(bool suspend)
+{
+	int cpu, ret;
+
+	if (suspend) {
+		/*
+		 * During hibernate we need frozen_cpus to be updated and saved.
+		 */
+		ret = disable_nonboot_cpus();
+	} else {
+		/*
+		 * Resuming from hibernate. From here, we can't race with
+		 * userspace, and don't need to update frozen_cpus.
+		 */
+		pr_info("Disabling secondary CPUs ...\n");
+
+		/* sleep_cpu must have been loaded from the arch header */
+		BUG_ON(sleep_cpu < 0);
+
+		for_each_online_cpu(cpu) {
+			if (cpu == sleep_cpu)
+				continue;
+			ret = cpu_down(cpu);
+			if (ret) {
+				pr_err("Secondary CPUs are not disabled\n");
+				break;
+			}
+		}
+	}
+
+	return ret;
+}
-- 
2.8.0.rc3

[PATCH 5/5] Revert "arm64: hibernate: Refuse to hibernate if the boot cpu is offline"

[James Morse]

Now that we use the MPIDR to resume on the same CPU that we hibernated on,
we no longer need to refuse to hibernate if the boot cpu is offline. (Which
we can't possibly know if kexec causes logical CPUs to be renumbered).

This reverts commit 1fe492ce6482b77807b25d29690a48c46456beee.

Signed-off-by: James Morse <james.morse@arm.com>
---
 arch/arm64/kernel/hibernate.c | 26 --------------------------
 1 file changed, 26 deletions(-)

diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index 6b6ea9aca6d0..9bb3edd0eea6 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -18,7 +18,6 @@
 #include <linux/cpu.h>
 #include <linux/kvm_host.h>
 #include <linux/mm.h>
-#include <linux/notifier.h>
 #include <linux/pm.h>
 #include <linux/sched.h>
 #include <linux/suspend.h>
@@ -518,31 +517,6 @@ out:
 	return rc;
 }
 
-static int check_boot_cpu_online_pm_callback(struct notifier_block *nb,
-					     unsigned long action, void *ptr)
-{
-	if (action == PM_HIBERNATION_PREPARE &&
-	     cpumask_first(cpu_online_mask) != 0) {
-		pr_warn("CPU0 is offline.\n");
-		return notifier_from_errno(-ENODEV);
-	}
-
-	return NOTIFY_OK;
-}
-
-static int __init check_boot_cpu_online_init(void)
-{
-	/*
-	 * Set this pm_notifier callback with a lower priority than
-	 * cpu_hotplug_pm_callback, so that cpu_hotplug_pm_callback will be
-	 * called earlier to disable cpu hotplug before the cpu online check.
-	 */
-	pm_notifier(check_boot_cpu_online_pm_callback, -INT_MAX);
-
-	return 0;
-}
-core_initcall(check_boot_cpu_online_init);
-
 /* This overrides the weak version in kernel/power/hibernate.c */
 int arch_hibernation_disable_cpus(bool suspend)
 {
-- 
2.8.0.rc3

Re: [PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[Rafael J. Wysocki]

On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
> On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
> user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
> kernel will assign logical id 0 to a different physical CPU.
> This breaks hibernate as hibernate and resume will be attempted on different
> CPUs.
> 
> Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
> calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
> hotplugged can use this to control which CPU is used for hibernate/resume.
> 
> Signed-off-by: James Morse <james.morse@arm.com>
> Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
> Cc: Pavel Machek <pavel@ucw.cz>
> ---
> I would have preferred a macro, but there is no hibernate-relevant header
> file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
> doesn't.

What about include/linux/suspend.h?

There are arch_ things declared in there.

Thanks,
Rafael

[PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[Rafael J. Wysocki]

On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
> On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
> user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
> kernel will assign logical id 0 to a different physical CPU.
> This breaks hibernate as hibernate and resume will be attempted on different
> CPUs.
> 
> Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
> calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
> hotplugged can use this to control which CPU is used for hibernate/resume.
> 
> Signed-off-by: James Morse <james.morse@arm.com>
> Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
> Cc: Pavel Machek <pavel@ucw.cz>
> ---
> I would have preferred a macro, but there is no hibernate-relevant header
> file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
> doesn't.

What about include/linux/suspend.h?

There are arch_ things declared in there.

Thanks,
Rafael

Re: [PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[Rafael J. Wysocki]

On Tuesday, June 14, 2016 12:05:28 AM Rafael J. Wysocki wrote:
> On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
> > On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
> > user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
> > kernel will assign logical id 0 to a different physical CPU.
> > This breaks hibernate as hibernate and resume will be attempted on different
> > CPUs.
> > 
> > Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
> > calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
> > hotplugged can use this to control which CPU is used for hibernate/resume.
> > 
> > Signed-off-by: James Morse <james.morse@arm.com>
> > Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
> > Cc: Pavel Machek <pavel@ucw.cz>
> > ---
> > I would have preferred a macro, but there is no hibernate-relevant header
> > file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
> > doesn't.
> 
> What about include/linux/suspend.h?
> 
> There are arch_ things declared in there.

I mean, what about using something like

#ifndef arch_hibernation_disable_cpus
#define arch_hibernation_disable_cpus disable_nonboot_cpus
#endif

in there or in another header file?

Thanks,
Rafael

[PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[Rafael J. Wysocki]

On Tuesday, June 14, 2016 12:05:28 AM Rafael J. Wysocki wrote:
> On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
> > On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
> > user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
> > kernel will assign logical id 0 to a different physical CPU.
> > This breaks hibernate as hibernate and resume will be attempted on different
> > CPUs.
> > 
> > Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
> > calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
> > hotplugged can use this to control which CPU is used for hibernate/resume.
> > 
> > Signed-off-by: James Morse <james.morse@arm.com>
> > Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
> > Cc: Pavel Machek <pavel@ucw.cz>
> > ---
> > I would have preferred a macro, but there is no hibernate-relevant header
> > file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
> > doesn't.
> 
> What about include/linux/suspend.h?
> 
> There are arch_ things declared in there.

I mean, what about using something like

#ifndef arch_hibernation_disable_cpus
#define arch_hibernation_disable_cpus disable_nonboot_cpus
#endif

in there or in another header file?

Thanks,
Rafael

Re: [PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[James Morse]

Hi Rafael,

On 13/06/16 23:10, Rafael J. Wysocki wrote:
> On Tuesday, June 14, 2016 12:05:28 AM Rafael J. Wysocki wrote:
>> On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
>>> On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
>>> user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
>>> kernel will assign logical id 0 to a different physical CPU.
>>> This breaks hibernate as hibernate and resume will be attempted on different
>>> CPUs.
>>>
>>> Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
>>> calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
>>> hotplugged can use this to control which CPU is used for hibernate/resume.
>>>
>>> Signed-off-by: James Morse <james.morse@arm.com>
>>> Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
>>> Cc: Pavel Machek <pavel@ucw.cz>
>>> ---
>>> I would have preferred a macro, but there is no hibernate-relevant header
>>> file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
>>> doesn't.
>>
>> What about include/linux/suspend.h?
>>
>> There are arch_ things declared in there.
> 
> I mean, what about using something like
> 
> #ifndef arch_hibernation_disable_cpus
> #define arch_hibernation_disable_cpus disable_nonboot_cpus
> #endif
> 
> in there or in another header file?

This would work fine for an architecture that doesn't need to use
arch_hibernation_disable_cpus(), but which header file should we use for an
architecture that does?

As a macro it needs to be in an arch-specific header included before the #ifndef
above.

Of those:
include/linux/suspend.h only includes <asm/errno.h>
kernel/power/power.h doesn't include any 'asm' headers.
snapshot.c includes:
> #include <asm/uaccess.h>
> #include <asm/mmu_context.h>
> #include <asm/pgtable.h>
> #include <asm/tlbflush.h>
> #include <asm/io.h>

... but none of those are appropriate.


I initially added an include for <asm/suspend.h> to kernel/power/power.h, but it
broke powerpc, as there is no suspend.h there. I took this as a dead-end for the
macro approach, unless someone has a clever trick?!



Thanks,

James

[PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[James Morse]

Hi Rafael,

On 13/06/16 23:10, Rafael J. Wysocki wrote:
> On Tuesday, June 14, 2016 12:05:28 AM Rafael J. Wysocki wrote:
>> On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
>>> On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
>>> user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
>>> kernel will assign logical id 0 to a different physical CPU.
>>> This breaks hibernate as hibernate and resume will be attempted on different
>>> CPUs.
>>>
>>> Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
>>> calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
>>> hotplugged can use this to control which CPU is used for hibernate/resume.
>>>
>>> Signed-off-by: James Morse <james.morse@arm.com>
>>> Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
>>> Cc: Pavel Machek <pavel@ucw.cz>
>>> ---
>>> I would have preferred a macro, but there is no hibernate-relevant header
>>> file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
>>> doesn't.
>>
>> What about include/linux/suspend.h?
>>
>> There are arch_ things declared in there.
> 
> I mean, what about using something like
> 
> #ifndef arch_hibernation_disable_cpus
> #define arch_hibernation_disable_cpus disable_nonboot_cpus
> #endif
> 
> in there or in another header file?

This would work fine for an architecture that doesn't need to use
arch_hibernation_disable_cpus(), but which header file should we use for an
architecture that does?

As a macro it needs to be in an arch-specific header included before the #ifndef
above.

Of those:
include/linux/suspend.h only includes <asm/errno.h>
kernel/power/power.h doesn't include any 'asm' headers.
snapshot.c includes:
> #include <asm/uaccess.h>
> #include <asm/mmu_context.h>
> #include <asm/pgtable.h>
> #include <asm/tlbflush.h>
> #include <asm/io.h>

... but none of those are appropriate.


I initially added an include for <asm/suspend.h> to kernel/power/power.h, but it
broke powerpc, as there is no suspend.h there. I took this as a dead-end for the
macro approach, unless someone has a clever trick?!



Thanks,

James

[PATCH 1/5] arm64: Add markers around .text section and create sections.h

[Mark Rutland]

On Thu, Jun 02, 2016 at 03:10:53PM +0100, James Morse wrote:
> During resume from hibernate, memory containing the kernel text is cleaned
> to the PoU. Some parts of the kernel are executed with the MMU off, in
> which case these instructions need to be cleaned to the PoC.
> 
> To aid the cleaning of this text, add markers around the existing section.

The new markers here seem to be around TEXT_TEXT, which covers the
majority of kernel text, not just that which needs to execute with the
MMU off.

I see from the next patch that we'll clean the whole TEXT_TEXT area to
the PoC. It feels odd to be selective about the regions we perform
maintenance on while doing so for the largest mixed bag of instructions.

Could we instead create a new section (e.g. .mmuoff.text), and place the
required functions/data in there? That would avoid having to clean more
than necessary.

> Each time new section markers are added, kernel/vmlinux.ld.S is updated,
> and new extern char __start_foo[] definitions are scattered through the
> tree.
> 
> Create asm/include/sections.h to collect these definitions (and include
> the existing asm-generic version).

Nice cleanup!

It might make more sense to only add sections.h in this patch, and move
the TEXT_TEXT section additions to the next patch where they're going to
be used (so as to keep the review comments together).

Thanks,
Mark.

> Signed-off-by: James Morse <james.morse@arm.com>
> ---
>  arch/arm64/include/asm/Kbuild     |  1 -
>  arch/arm64/include/asm/sections.h | 29 +++++++++++++++++++++++++++++
>  arch/arm64/include/asm/traps.h    |  3 +--
>  arch/arm64/include/asm/virt.h     |  5 +----
>  arch/arm64/kernel/alternative.c   |  7 +++----
>  arch/arm64/kernel/hibernate.c     |  6 ------
>  arch/arm64/kernel/vmlinux.lds.S   |  2 ++
>  arch/arm64/kvm/reset.c            |  3 +--
>  8 files changed, 37 insertions(+), 19 deletions(-)
>  create mode 100644 arch/arm64/include/asm/sections.h
> 
> diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
> index cff532a6744e..50c1f646b704 100644
> --- a/arch/arm64/include/asm/Kbuild
> +++ b/arch/arm64/include/asm/Kbuild
> @@ -33,7 +33,6 @@ generic-y += poll.h
>  generic-y += preempt.h
>  generic-y += resource.h
>  generic-y += rwsem.h
> -generic-y += sections.h
>  generic-y += segment.h
>  generic-y += sembuf.h
>  generic-y += serial.h
> diff --git a/arch/arm64/include/asm/sections.h b/arch/arm64/include/asm/sections.h
> new file mode 100644
> index 000000000000..1d9b0149f413
> --- /dev/null
> +++ b/arch/arm64/include/asm/sections.h
> @@ -0,0 +1,29 @@
> +/*
> + * Copyright (C) 2016 ARM Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_SECTIONS_H
> +#define __ASM_SECTIONS_H
> +
> +#include <asm-generic/sections.h>
> +
> +extern char __hyp_idmap_text_start[], __hyp_idmap_text_end[];
> +extern char __hyp_text_start[], __hyp_text_end[];
> +extern char __idmap_text_start[], __idmap_text_end[];
> +extern char __hibernate_exit_text_start[], __hibernate_exit_text_end[];
> +extern char __text_text_start[], __text_text_end[];
> +extern char __exception_text_start[], __exception_text_end[];
> +extern char __alt_instructions[], __alt_instructions_end[];
> +
> +#endif /* __ASM_SECTIONS_H */
> diff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h
> index 0cc2f29bf9da..90156c803f11 100644
> --- a/arch/arm64/include/asm/traps.h
> +++ b/arch/arm64/include/asm/traps.h
> @@ -19,6 +19,7 @@
>  #define __ASM_TRAP_H
>  
>  #include <linux/list.h>
> +#include <asm/sections.h>
>  
>  struct pt_regs;
>  
> @@ -52,8 +53,6 @@ static inline int __in_irqentry_text(unsigned long ptr)
>  
>  static inline int in_exception_text(unsigned long ptr)
>  {
> -	extern char __exception_text_start[];
> -	extern char __exception_text_end[];
>  	int in;
>  
>  	in = ptr >= (unsigned long)&__exception_text_start &&
> diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
> index dcbcf8dcbefb..b78611157f8b 100644
> --- a/arch/arm64/include/asm/virt.h
> +++ b/arch/arm64/include/asm/virt.h
> @@ -40,6 +40,7 @@
>  #ifndef __ASSEMBLY__
>  
>  #include <asm/ptrace.h>
> +#include <asm/sections.h>
>  
>  /*
>   * __boot_cpu_mode records what mode CPUs were booted in.
> @@ -82,10 +83,6 @@ extern void verify_cpu_run_el(void);
>  static inline void verify_cpu_run_el(void) {}
>  #endif
>  
> -/* The section containing the hypervisor text */
> -extern char __hyp_text_start[];
> -extern char __hyp_text_end[];
> -
>  #endif /* __ASSEMBLY__ */
>  
>  #endif /* ! __ASM__VIRT_H */
> diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
> index d2ee1b21a10d..4434dabde898 100644
> --- a/arch/arm64/kernel/alternative.c
> +++ b/arch/arm64/kernel/alternative.c
> @@ -25,14 +25,13 @@
>  #include <asm/alternative.h>
>  #include <asm/cpufeature.h>
>  #include <asm/insn.h>
> +#include <asm/sections.h>
>  #include <linux/stop_machine.h>
>  
>  #define __ALT_PTR(a,f)		(u32 *)((void *)&(a)->f + (a)->f)
>  #define ALT_ORIG_PTR(a)		__ALT_PTR(a, orig_offset)
>  #define ALT_REPL_PTR(a)		__ALT_PTR(a, alt_offset)
>  
> -extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
> -
>  struct alt_region {
>  	struct alt_instr *begin;
>  	struct alt_instr *end;
> @@ -124,8 +123,8 @@ static int __apply_alternatives_multi_stop(void *unused)
>  {
>  	static int patched = 0;
>  	struct alt_region region = {
> -		.begin	= __alt_instructions,
> -		.end	= __alt_instructions_end,
> +		.begin	= (struct alt_instr *)__alt_instructions,
> +		.end	= (struct alt_instr *)__alt_instructions_end,
>  	};
>  
>  	/* We always have a CPU 0 at this point (__init) */
> diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
> index f8df75d740f4..56e548fe0386 100644
> --- a/arch/arm64/kernel/hibernate.c
> +++ b/arch/arm64/kernel/hibernate.c
> @@ -52,12 +52,6 @@ extern int in_suspend;
>  /* Do we need to reset el2? */
>  #define el2_reset_needed() (is_hyp_mode_available() && !is_kernel_in_hyp_mode())
>  
> -/*
> - * Start/end of the hibernate exit code, this must be copied to a 'safe'
> - * location in memory, and executed from there.
> - */
> -extern char __hibernate_exit_text_start[], __hibernate_exit_text_end[];
> -
>  /* temporary el2 vectors in the __hibernate_exit_text section. */
>  extern char hibernate_el2_vectors[];
>  
> diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> index 435e820e898d..6b3d2781a9f2 100644
> --- a/arch/arm64/kernel/vmlinux.lds.S
> +++ b/arch/arm64/kernel/vmlinux.lds.S
> @@ -118,7 +118,9 @@ SECTIONS
>  			__exception_text_end = .;
>  			IRQENTRY_TEXT
>  			SOFTIRQENTRY_TEXT
> +			__text_text_start = .;
>  			TEXT_TEXT
> +			__text_text_end = .;
>  			SCHED_TEXT
>  			LOCK_TEXT
>  			HYPERVISOR_TEXT
> diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
> index b1ad730e1567..c2d3594dd546 100644
> --- a/arch/arm64/kvm/reset.c
> +++ b/arch/arm64/kvm/reset.c
> @@ -32,6 +32,7 @@
>  #include <asm/kvm_asm.h>
>  #include <asm/kvm_coproc.h>
>  #include <asm/kvm_mmu.h>
> +#include <asm/sections.h>
>  
>  /*
>   * ARMv8 Reset Values
> @@ -133,8 +134,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
>  	return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
>  }
>  
> -extern char __hyp_idmap_text_start[];
> -
>  unsigned long kvm_hyp_reset_entry(void)
>  {
>  	if (!__kvm_cpu_uses_extended_idmap()) {
> -- 
> 2.8.0.rc3
> 

[PATCH 4/5] arm64: hibernate: Identify the CPU to resume on by its MPIDR

[Mark Rutland]

On Thu, Jun 02, 2016 at 03:10:56PM +0100, James Morse wrote:
> +		pr_info("Suspended on a CPU that is offline! Brining CPU up.\n");

Nit: typo, should be "Bringing".

Otherwise the patch looks good!

Thanks,
Mark.

Re: [PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[Rafael J. Wysocki]

On Tuesday, June 14, 2016 10:44:47 AM James Morse wrote:
> Hi Rafael,
> 
> On 13/06/16 23:10, Rafael J. Wysocki wrote:
> > On Tuesday, June 14, 2016 12:05:28 AM Rafael J. Wysocki wrote:
> >> On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
> >>> On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
> >>> user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
> >>> kernel will assign logical id 0 to a different physical CPU.
> >>> This breaks hibernate as hibernate and resume will be attempted on different
> >>> CPUs.
> >>>
> >>> Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
> >>> calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
> >>> hotplugged can use this to control which CPU is used for hibernate/resume.
> >>>
> >>> Signed-off-by: James Morse <james.morse@arm.com>
> >>> Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
> >>> Cc: Pavel Machek <pavel@ucw.cz>
> >>> ---
> >>> I would have preferred a macro, but there is no hibernate-relevant header
> >>> file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
> >>> doesn't.
> >>
> >> What about include/linux/suspend.h?
> >>
> >> There are arch_ things declared in there.
> > 
> > I mean, what about using something like
> > 
> > #ifndef arch_hibernation_disable_cpus
> > #define arch_hibernation_disable_cpus disable_nonboot_cpus
> > #endif
> > 
> > in there or in another header file?
> 
> This would work fine for an architecture that doesn't need to use
> arch_hibernation_disable_cpus(), but which header file should we use for an
> architecture that does?
> 
> As a macro it needs to be in an arch-specific header included before the #ifndef
> above.
> 
> Of those:
> include/linux/suspend.h only includes <asm/errno.h>
> kernel/power/power.h doesn't include any 'asm' headers.
> snapshot.c includes:
> > #include <asm/uaccess.h>
> > #include <asm/mmu_context.h>
> > #include <asm/pgtable.h>
> > #include <asm/tlbflush.h>
> > #include <asm/io.h>
> 
> ... but none of those are appropriate.
> 
> 
> I initially added an include for <asm/suspend.h> to kernel/power/power.h, but it
> broke powerpc, as there is no suspend.h there. I took this as a dead-end for the
> macro approach, unless someone has a clever trick?!

OK, let's do the __weak function, then.

After all, it can be changed later if someone has a better idea.

Thanks,
Rafael

[PATCH 3/5] PM / Hibernate: Allow architectures to specify the hibernate/resume CPU

[Rafael J. Wysocki]

On Tuesday, June 14, 2016 10:44:47 AM James Morse wrote:
> Hi Rafael,
> 
> On 13/06/16 23:10, Rafael J. Wysocki wrote:
> > On Tuesday, June 14, 2016 12:05:28 AM Rafael J. Wysocki wrote:
> >> On Thursday, June 02, 2016 03:10:55 PM James Morse wrote:
> >>> On arm64 the cpu with logical id 0 is assumed to be the boot CPU. If a
> >>> user hotplugs this CPU out, then uses kexec to boot a new kernel, the new
> >>> kernel will assign logical id 0 to a different physical CPU.
> >>> This breaks hibernate as hibernate and resume will be attempted on different
> >>> CPUs.
> >>>
> >>> Define a weak symbol arch_hibernation_disable_cpus(), which defaults to
> >>> calling disable_nonboot_cpus). Architectures that allow CPU 0 to be
> >>> hotplugged can use this to control which CPU is used for hibernate/resume.
> >>>
> >>> Signed-off-by: James Morse <james.morse@arm.com>
> >>> Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
> >>> Cc: Pavel Machek <pavel@ucw.cz>
> >>> ---
> >>> I would have preferred a macro, but there is no hibernate-relevant header
> >>> file that all arch's have. arm, arm64 and x86 have a suspend.h, but powerpc
> >>> doesn't.
> >>
> >> What about include/linux/suspend.h?
> >>
> >> There are arch_ things declared in there.
> > 
> > I mean, what about using something like
> > 
> > #ifndef arch_hibernation_disable_cpus
> > #define arch_hibernation_disable_cpus disable_nonboot_cpus
> > #endif
> > 
> > in there or in another header file?
> 
> This would work fine for an architecture that doesn't need to use
> arch_hibernation_disable_cpus(), but which header file should we use for an
> architecture that does?
> 
> As a macro it needs to be in an arch-specific header included before the #ifndef
> above.
> 
> Of those:
> include/linux/suspend.h only includes <asm/errno.h>
> kernel/power/power.h doesn't include any 'asm' headers.
> snapshot.c includes:
> > #include <asm/uaccess.h>
> > #include <asm/mmu_context.h>
> > #include <asm/pgtable.h>
> > #include <asm/tlbflush.h>
> > #include <asm/io.h>
> 
> ... but none of those are appropriate.
> 
> 
> I initially added an include for <asm/suspend.h> to kernel/power/power.h, but it
> broke powerpc, as there is no suspend.h there. I took this as a dead-end for the
> macro approach, unless someone has a clever trick?!

OK, let's do the __weak function, then.

After all, it can be changed later if someone has a better idea.

Thanks,
Rafael