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diff for duplicates of <1465208664-9366-2-git-send-email-mamlinav@gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index f594597..07ca3a1 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,9 +1,9 @@
-From: Boris Brezillon <boris.brezillon@free-electrons.com>
+From: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
 
 Define the NAND controller pin configs.
 
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
+Signed-off-by: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+Signed-off-by: Aleksei Mamlin <mamlinav-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
 ---
  arch/arm/boot/dts/sun4i-a10.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++
  1 file changed, 80 insertions(+)
diff --git a/a/content_digest b/N1/content_digest
index 7073752..2f5f317 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,10 @@
   "ref\0001465208664-9366-1-git-send-email-mamlinav\@gmail.com\0"
 ]
 [
-  "From\0Aleksei Mamlin <mamlinav\@gmail.com>\0"
+  "ref\0001465208664-9366-1-git-send-email-mamlinav-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org\0"
+]
+[
+  "From\0Aleksei Mamlin <mamlinav-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
 ]
 [
   "Subject\0[PATCH 1/7] ARM: dts: sun4i: Add A10 NAND controller pin definitions\0"
@@ -11,20 +14,20 @@
   "Date\0Mon,  6 Jun 2016 13:24:18 +0300\0"
 ]
 [
-  "To\0Maxime Ripard <maxime.ripard\@free-electrons.com>",
-  " Chen-Yu Tsai <wens\@csie.org>",
-  " Boris Brezillon <boris.brezillon\@free-electrons.com>",
-  " Richard Weinberger <richard\@nod.at>",
-  " David Woodhouse <dwmw2\@infradead.org>",
-  " Brian Norris <computersforpeace\@gmail.com>\0"
+  "To\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>",
+  " Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>",
+  " Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>",
+  " Richard Weinberger <richard-/L3Ra7n9ekc\@public.gmane.org>",
+  " David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ\@public.gmane.org>",
+  " Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
 ]
 [
-  "Cc\0linux-mtd\@lists.infradead.org",
-  " linux-kernel\@vger.kernel.org",
-  " linux-arm-kernel\@lists.infradead.org",
-  " devicetree\@vger.kernel.org",
-  " linux-sunxi\@googlegroups.com",
-  " Aleksei Mamlin <mamlinav\@gmail.com>\0"
+  "Cc\0linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
+  " linux-kernel-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
+  " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
+  " devicetree-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
+  " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw\@public.gmane.org",
+  " Aleksei Mamlin <mamlinav-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
 ]
 [
   "\0000:1\0"
@@ -33,12 +36,12 @@
   "b\0"
 ]
 [
-  "From: Boris Brezillon <boris.brezillon\@free-electrons.com>\n",
+  "From: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>\n",
   "\n",
   "Define the NAND controller pin configs.\n",
   "\n",
-  "Signed-off-by: Boris Brezillon <boris.brezillon\@free-electrons.com>\n",
-  "Signed-off-by: Aleksei Mamlin <mamlinav\@gmail.com>\n",
+  "Signed-off-by: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>\n",
+  "Signed-off-by: Aleksei Mamlin <mamlinav-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\n",
   "---\n",
   " arch/arm/boot/dts/sun4i-a10.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++\n",
   " 1 file changed, 80 insertions(+)\n",
@@ -138,4 +141,4 @@
   "2.7.3"
 ]
 
-fdd3d2adf7bc35bca66093e4cd4a76a5e0b9e88ed368acc25c81a328fe8b0d95
+01095d57c6dee269d23c673c175242de52bbfdf8d486fc819fc61e704f00c2fe

diff --git a/a/1.txt b/N2/1.txt
index f594597..ea5ed50 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -17,7 +17,7 @@ index a9c3190..146a08db 100644
  				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  			};
 +
-+			nand_pins_a: nand_base0@0 {
++			nand_pins_a: nand_base0 at 0 {
 +				allwinner,pins = "PC0", "PC1", "PC2",
 +						"PC5", "PC8", "PC9", "PC10",
 +						"PC11", "PC12", "PC13", "PC14",
@@ -27,70 +27,70 @@ index a9c3190..146a08db 100644
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs0_pins_a: nand_cs@0 {
++			nand_cs0_pins_a: nand_cs at 0 {
 +				allwinner,pins = "PC4";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs1_pins_a: nand_cs@1 {
++			nand_cs1_pins_a: nand_cs at 1 {
 +				allwinner,pins = "PC3";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs2_pins_a: nand_cs@2 {
++			nand_cs2_pins_a: nand_cs at 2 {
 +				allwinner,pins = "PC17";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs3_pins_a: nand_cs@3 {
++			nand_cs3_pins_a: nand_cs at 3 {
 +				allwinner,pins = "PC18";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs4_pins_a: nand_cs@4 {
++			nand_cs4_pins_a: nand_cs at 4 {
 +				allwinner,pins = "PC19";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs5_pins_a: nand_cs@5 {
++			nand_cs5_pins_a: nand_cs at 5 {
 +				allwinner,pins = "PC20";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs6_pins_a: nand_cs@6 {
++			nand_cs6_pins_a: nand_cs at 6 {
 +				allwinner,pins = "PC21";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_cs7_pins_a: nand_cs@7 {
++			nand_cs7_pins_a: nand_cs at 7 {
 +				allwinner,pins = "PC22";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_rb0_pins_a: nand_rb@0 {
++			nand_rb0_pins_a: nand_rb at 0 {
 +				allwinner,pins = "PC6";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +			};
 +
-+			nand_rb1_pins_a: nand_rb@1 {
++			nand_rb1_pins_a: nand_rb at 1 {
 +				allwinner,pins = "PC7";
 +				allwinner,function = "nand0";
 +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -98,6 +98,6 @@ index a9c3190..146a08db 100644
 +			};
  		};
  
- 		timer@01c20c00 {
+ 		timer at 01c20c00 {
 -- 
 2.7.3
\ No newline at end of file
diff --git a/a/content_digest b/N2/content_digest
index 7073752..3090d94 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -2,7 +2,7 @@
   "ref\0001465208664-9366-1-git-send-email-mamlinav\@gmail.com\0"
 ]
 [
-  "From\0Aleksei Mamlin <mamlinav\@gmail.com>\0"
+  "From\0mamlinav\@gmail.com (Aleksei Mamlin)\0"
 ]
 [
   "Subject\0[PATCH 1/7] ARM: dts: sun4i: Add A10 NAND controller pin definitions\0"
@@ -11,20 +11,7 @@
   "Date\0Mon,  6 Jun 2016 13:24:18 +0300\0"
 ]
 [
-  "To\0Maxime Ripard <maxime.ripard\@free-electrons.com>",
-  " Chen-Yu Tsai <wens\@csie.org>",
-  " Boris Brezillon <boris.brezillon\@free-electrons.com>",
-  " Richard Weinberger <richard\@nod.at>",
-  " David Woodhouse <dwmw2\@infradead.org>",
-  " Brian Norris <computersforpeace\@gmail.com>\0"
-]
-[
-  "Cc\0linux-mtd\@lists.infradead.org",
-  " linux-kernel\@vger.kernel.org",
-  " linux-arm-kernel\@lists.infradead.org",
-  " devicetree\@vger.kernel.org",
-  " linux-sunxi\@googlegroups.com",
-  " Aleksei Mamlin <mamlinav\@gmail.com>\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
   "\0000:1\0"
@@ -52,7 +39,7 @@
   " \t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n",
   " \t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_pins_a: nand_base0\@0 {\n",
+  "+\t\t\tnand_pins_a: nand_base0 at 0 {\n",
   "+\t\t\t\tallwinner,pins = \"PC0\", \"PC1\", \"PC2\",\n",
   "+\t\t\t\t\t\t\"PC5\", \"PC8\", \"PC9\", \"PC10\",\n",
   "+\t\t\t\t\t\t\"PC11\", \"PC12\", \"PC13\", \"PC14\",\n",
@@ -62,70 +49,70 @@
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs0_pins_a: nand_cs\@0 {\n",
+  "+\t\t\tnand_cs0_pins_a: nand_cs at 0 {\n",
   "+\t\t\t\tallwinner,pins = \"PC4\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs1_pins_a: nand_cs\@1 {\n",
+  "+\t\t\tnand_cs1_pins_a: nand_cs at 1 {\n",
   "+\t\t\t\tallwinner,pins = \"PC3\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs2_pins_a: nand_cs\@2 {\n",
+  "+\t\t\tnand_cs2_pins_a: nand_cs at 2 {\n",
   "+\t\t\t\tallwinner,pins = \"PC17\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs3_pins_a: nand_cs\@3 {\n",
+  "+\t\t\tnand_cs3_pins_a: nand_cs at 3 {\n",
   "+\t\t\t\tallwinner,pins = \"PC18\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs4_pins_a: nand_cs\@4 {\n",
+  "+\t\t\tnand_cs4_pins_a: nand_cs at 4 {\n",
   "+\t\t\t\tallwinner,pins = \"PC19\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs5_pins_a: nand_cs\@5 {\n",
+  "+\t\t\tnand_cs5_pins_a: nand_cs at 5 {\n",
   "+\t\t\t\tallwinner,pins = \"PC20\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs6_pins_a: nand_cs\@6 {\n",
+  "+\t\t\tnand_cs6_pins_a: nand_cs at 6 {\n",
   "+\t\t\t\tallwinner,pins = \"PC21\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_cs7_pins_a: nand_cs\@7 {\n",
+  "+\t\t\tnand_cs7_pins_a: nand_cs at 7 {\n",
   "+\t\t\t\tallwinner,pins = \"PC22\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_rb0_pins_a: nand_rb\@0 {\n",
+  "+\t\t\tnand_rb0_pins_a: nand_rb at 0 {\n",
   "+\t\t\t\tallwinner,pins = \"PC6\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
   "+\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n",
   "+\t\t\t};\n",
   "+\n",
-  "+\t\t\tnand_rb1_pins_a: nand_rb\@1 {\n",
+  "+\t\t\tnand_rb1_pins_a: nand_rb at 1 {\n",
   "+\t\t\t\tallwinner,pins = \"PC7\";\n",
   "+\t\t\t\tallwinner,function = \"nand0\";\n",
   "+\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n",
@@ -133,9 +120,9 @@
   "+\t\t\t};\n",
   " \t\t};\n",
   " \n",
-  " \t\ttimer\@01c20c00 {\n",
+  " \t\ttimer at 01c20c00 {\n",
   "-- \n",
   "2.7.3"
 ]
 
-fdd3d2adf7bc35bca66093e4cd4a76a5e0b9e88ed368acc25c81a328fe8b0d95
+b65b0b5400c8862198754abd64beb48a7bff32961714213fae346a07e0539376

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