From: Matt Redfearn <matt.redfearn@imgtec.com> To: Ralf Baechle <ralf@linux-mips.org> Cc: Matt Redfearn <matt.redfearn@imgtec.com>, <stable@vger.kernel.org>, <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH] MIPS: mm: Fix definition of R6 cache instruction Date: Tue, 14 Jun 2016 14:59:38 +0100 [thread overview] Message-ID: <1465912778-22097-1-git-send-email-matt.redfearn@imgtec.com> (raw) Commit a168b8f1cde6 ("MIPS: mm: Add MIPS R6 instruction encodings") added an incorrect definition of the redefined MIPSr6 cache instruction. Executing any kernel code including this instuction results in a reserved instruction exception and kernel panic. Fix the instruction definition. Fixes: a168b8f1cde6588ff7a67699fa11e01bc77a5ddd Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: <stable@vger.kernel.org> # 4.x- --- arch/mips/mm/uasm-mips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index b4a837893562..5abe51cad899 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c @@ -65,7 +65,7 @@ static struct insn insn_table[] = { #ifndef CONFIG_CPU_MIPSR6 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, #else - { insn_cache, M6(cache_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, + { insn_cache, M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, #endif { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, -- 2.5.0
WARNING: multiple messages have this Message-ID (diff)
From: Matt Redfearn <matt.redfearn@imgtec.com> To: Ralf Baechle <ralf@linux-mips.org> Cc: Matt Redfearn <matt.redfearn@imgtec.com>, stable@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH] MIPS: mm: Fix definition of R6 cache instruction Date: Tue, 14 Jun 2016 14:59:38 +0100 [thread overview] Message-ID: <1465912778-22097-1-git-send-email-matt.redfearn@imgtec.com> (raw) Message-ID: <20160614135938.EKmol3gFsdD89_gXLw5F257s77WUDSY06uSPwPBsW5g@z> (raw) Commit a168b8f1cde6 ("MIPS: mm: Add MIPS R6 instruction encodings") added an incorrect definition of the redefined MIPSr6 cache instruction. Executing any kernel code including this instuction results in a reserved instruction exception and kernel panic. Fix the instruction definition. Fixes: a168b8f1cde6588ff7a67699fa11e01bc77a5ddd Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: <stable@vger.kernel.org> # 4.x- --- arch/mips/mm/uasm-mips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index b4a837893562..5abe51cad899 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c @@ -65,7 +65,7 @@ static struct insn insn_table[] = { #ifndef CONFIG_CPU_MIPSR6 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, #else - { insn_cache, M6(cache_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, + { insn_cache, M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, #endif { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, -- 2.5.0
next reply other threads:[~2016-06-14 13:59 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-14 13:59 Matt Redfearn [this message] 2016-06-14 13:59 ` [PATCH] MIPS: mm: Fix definition of R6 cache instruction Matt Redfearn
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