[PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support

[PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support

[Andy Shevchenko]

Tested on bare metal (Intel Edison) by enumerating I2C GPIO expanders.

In v2:
- leave bus 3 at STD speed for Medfield
- be consistent with workflow, i.e. call ->setup, and _then_ assign to i2c
  properties
- add a comment to explain magic numbers for Merrifield
- add an Ack for patch 3

Andy Shevchenko (3):
  i2c: designware-pci: Make bus number allocation robust
  i2c: designware-pci: Introduce Merrifield support
  i2c: designware-pci: Sort header block alphabetically

 drivers/i2c/busses/i2c-designware-core.h   |   1 +
 drivers/i2c/busses/i2c-designware-pcidrv.c | 143 +++++++++++++++++------------
 2 files changed, 86 insertions(+), 58 deletions(-)

-- 
2.8.1

[PATCH v2 1/3] i2c: designware-pci: Make bus number allocation robust

[Andy Shevchenko]

On some platforms, such as Intel Medfield, the I2C slave devices are enumerated
through SFI tables where bus numbering is expected to be defined in the OS.
Make the bus number allocation robust for such platforms.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/i2c/busses/i2c-designware-core.h   |  1 +
 drivers/i2c/busses/i2c-designware-pcidrv.c | 87 +++++++++++++-----------------
 2 files changed, 38 insertions(+), 50 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index cd409e7..38493a7 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -26,6 +26,7 @@
 #define DW_IC_CON_MASTER		0x1
 #define DW_IC_CON_SPEED_STD		0x2
 #define DW_IC_CON_SPEED_FAST		0x4
+#define DW_IC_CON_SPEED_MASK		0x6
 #define DW_IC_CON_10BITADDR_MASTER	0x10
 #define DW_IC_CON_RESTART_EN		0x20
 #define DW_IC_CON_SLAVE_DISABLE		0x40
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 7368be0..586c8d8 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -41,13 +41,7 @@
 #define DRIVER_NAME "i2c-designware-pci"
 
 enum dw_pci_ctl_id_t {
-	medfield_0,
-	medfield_1,
-	medfield_2,
-	medfield_3,
-	medfield_4,
-	medfield_5,
-
+	medfield,
 	baytrail,
 	haswell,
 };
@@ -68,6 +62,7 @@ struct dw_pci_controller {
 	u32 clk_khz;
 	u32 functionality;
 	struct dw_scl_sda_cfg *scl_sda_cfg;
+	int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
 };
 
 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |			\
@@ -98,48 +93,33 @@ static struct dw_scl_sda_cfg hsw_config = {
 	.sda_hold = 0x9,
 };
 
+static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
+{
+	switch (pdev->device) {
+	case 0x0817:
+		c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
+		c->bus_cfg |= DW_IC_CON_SPEED_STD;
+	case 0x0818:
+	case 0x0819:
+		c->bus_num = pdev->device - 0x817 + 3;
+		return 0;
+	case 0x082C:
+	case 0x082D:
+	case 0x082E:
+		c->bus_num = pdev->device - 0x82C + 0;
+		return 0;
+	}
+	return -ENODEV;
+}
+
 static struct dw_pci_controller dw_pci_controllers[] = {
-	[medfield_0] = {
-		.bus_num     = 0,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_1] = {
-		.bus_num     = 1,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_2] = {
-		.bus_num     = 2,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_3] = {
-		.bus_num     = 3,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_4] = {
-		.bus_num     = 4,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_5] = {
-		.bus_num     = 5,
+	[medfield] = {
+		.bus_num = -1,
 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
 		.clk_khz      = 25000,
+		.setup = mfld_setup,
 	},
 	[baytrail] = {
 		.bus_num = -1,
@@ -224,6 +204,13 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
 	dev->base = pcim_iomap_table(pdev)[0];
 	dev->dev = &pdev->dev;
 	dev->irq = pdev->irq;
+
+	if (controller->setup) {
+		r = controller->setup(pdev, controller);
+		if (r)
+			return r;
+	}
+
 	dev->functionality = controller->functionality |
 				DW_DEFAULT_FUNCTIONALITY;
 
@@ -276,12 +263,12 @@ MODULE_ALIAS("i2c_designware-pci");
 
 static const struct pci_device_id i2_designware_pci_ids[] = {
 	/* Medfield */
-	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3 },
-	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
-	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
-	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
-	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
-	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
+	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
+	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
+	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
 	/* Baytrail */
 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
-- 
2.8.1

[PATCH v2 2/3] i2c: designware-pci: Introduce Merrifield support

[Andy Shevchenko]

This patch enables I2C controllers found on Intel Edison board.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 39 ++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 586c8d8..a7aab10 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -42,6 +42,7 @@
 
 enum dw_pci_ctl_id_t {
 	medfield,
+	merrifield,
 	baytrail,
 	haswell,
 };
@@ -75,6 +76,14 @@ struct dw_pci_controller {
 					I2C_FUNC_SMBUS_WORD_DATA |	\
 					I2C_FUNC_SMBUS_I2C_BLOCK)
 
+/* Merrifield HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg mrfld_config = {
+	.ss_hcnt = 0x2f8,
+	.fs_hcnt = 0x87,
+	.ss_lcnt = 0x37b,
+	.fs_lcnt = 0x10a,
+};
+
 /* BayTrail HCNT/LCNT/SDA hold time */
 static struct dw_scl_sda_cfg byt_config = {
 	.ss_hcnt = 0x200,
@@ -112,6 +121,25 @@ static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
 	return -ENODEV;
 }
 
+static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
+{
+	/*
+	 * On Intel Merrifield the i2c busses are enumerated [1..7]. So, we add
+	 * 1 to shift the default range. Besides that the first PCI slot
+	 * provides 4 functions, that's why we have to add 0 to the head slot
+	 * and 4 to the tail one.
+	 */
+	switch (PCI_SLOT(pdev->devfn)) {
+	case 8:
+		c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
+		return 0;
+	case 9:
+		c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
+		return 0;
+	}
+	return -ENODEV;
+}
+
 static struct dw_pci_controller dw_pci_controllers[] = {
 	[medfield] = {
 		.bus_num = -1,
@@ -121,6 +149,14 @@ static struct dw_pci_controller dw_pci_controllers[] = {
 		.clk_khz      = 25000,
 		.setup = mfld_setup,
 	},
+	[merrifield] = {
+		.bus_num = -1,
+		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
+		.tx_fifo_depth = 64,
+		.rx_fifo_depth = 64,
+		.scl_sda_cfg = &mrfld_config,
+		.setup = mrfld_setup,
+	},
 	[baytrail] = {
 		.bus_num = -1,
 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
@@ -269,6 +305,9 @@ static const struct pci_device_id i2_designware_pci_ids[] = {
 	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
 	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
 	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
+	/* Merrifield */
+	{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
+	{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
 	/* Baytrail */
 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
-- 
2.8.1

[PATCH v2 3/3] i2c: designware-pci: Sort header block alphabetically

[Andy Shevchenko]

Simply sort header block alphabetically.

While here fix an indentation in one place and update a copyright line for
Intel.

Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index a7aab10..b66c31a 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -6,7 +6,7 @@
  * Copyright (C) 2006 Texas Instruments.
  * Copyright (C) 2007 MontaVista Software Inc.
  * Copyright (C) 2009 Provigent Ltd.
- * Copyright (C) 2011, 2015 Intel Corporation.
+ * Copyright (C) 2011, 2015, 2016 Intel Corporation.
  *
  * ----------------------------------------------------------------------------
  *
@@ -23,19 +23,20 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/acpi.h>
 #include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
 #include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/pm_runtime.h>
-#include <linux/acpi.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
 #include "i2c-designware-core.h"
 
 #define DRIVER_NAME "i2c-designware-pci"
@@ -206,7 +207,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
 	struct dw_i2c_dev *dev;
 	struct i2c_adapter *adap;
 	int r;
-	struct  dw_pci_controller *controller;
+	struct dw_pci_controller *controller;
 	struct dw_scl_sda_cfg *cfg;
 
 	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
-- 
2.8.1

Re: [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support

[Jarkko Nikula]

On 06/15/2016 06:05 PM, Andy Shevchenko wrote:
> Tested on bare metal (Intel Edison) by enumerating I2C GPIO expanders.
>
> In v2:
> - leave bus 3 at STD speed for Medfield
> - be consistent with workflow, i.e. call ->setup, and _then_ assign to i2c
>   properties
> - add a comment to explain magic numbers for Merrifield
> - add an Ack for patch 3
>
> Andy Shevchenko (3):
>   i2c: designware-pci: Make bus number allocation robust
>   i2c: designware-pci: Introduce Merrifield support
>   i2c: designware-pci: Sort header block alphabetically
>
>  drivers/i2c/busses/i2c-designware-core.h   |   1 +
>  drivers/i2c/busses/i2c-designware-pcidrv.c | 143 +++++++++++++++++------------
>  2 files changed, 86 insertions(+), 58 deletions(-)
>
> --
> 2.8.1
>
To the series (patch 3 has my ack already):

Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>

Re: [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 811 bytes --]

On Wed, Jun 15, 2016 at 06:05:04PM +0300, Andy Shevchenko wrote:
> Tested on bare metal (Intel Edison) by enumerating I2C GPIO expanders.
> 
> In v2:
> - leave bus 3 at STD speed for Medfield
> - be consistent with workflow, i.e. call ->setup, and _then_ assign to i2c
>   properties
> - add a comment to explain magic numbers for Merrifield
> - add an Ack for patch 3
> 
> Andy Shevchenko (3):
>   i2c: designware-pci: Make bus number allocation robust
>   i2c: designware-pci: Introduce Merrifield support
>   i2c: designware-pci: Sort header block alphabetically
> 
>  drivers/i2c/busses/i2c-designware-core.h   |   1 +
>  drivers/i2c/busses/i2c-designware-pcidrv.c | 143 +++++++++++++++++------------
>  2 files changed, 86 insertions(+), 58 deletions(-)

Applied to for-next, thanks!


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Re: [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support

[Andy Shevchenko]

On Sun, 2016-06-19 at 19:42 +0200, Wolfram Sang wrote:
> On Wed, Jun 15, 2016 at 06:05:04PM +0300, Andy Shevchenko wrote:
> > Tested on bare metal (Intel Edison) by enumerating I2C GPIO
> > expanders.
> > 
> > In v2:
> > - leave bus 3 at STD speed for Medfield
> > - be consistent with workflow, i.e. call ->setup, and _then_ assign
> > to i2c
> >   properties
> > - add a comment to explain magic numbers for Merrifield
> > - add an Ack for patch 3
> > 
> > Andy Shevchenko (3):
> >   i2c: designware-pci: Make bus number allocation robust
> >   i2c: designware-pci: Introduce Merrifield support
> >   i2c: designware-pci: Sort header block alphabetically
> > 
> >  drivers/i2c/busses/i2c-designware-core.h   |   1 +
> >  drivers/i2c/busses/i2c-designware-pcidrv.c | 143 +++++++++++++++++-
> > -----------
> >  2 files changed, 86 insertions(+), 58 deletions(-)
> 
> Applied to for-next, thanks!

Thanks.

Wolfram, just noticed that comment message in the second patch is not
fully clear. I would update it as follows

--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -125,10 +125,10 @@ static int mfld_setup(struct pci_dev *pdev, struct
dw_pci_controller *c)
 static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller
*c)
 {
        /*
-        * On Intel Merrifield the i2c busses are enumerated [1..7]. So,
we add
-        * 1 to shift the default range. Besides that the first PCI slot
-        * provides 4 functions, that's why we have to add 0 to the head
slot
-        * and 4 to the tail one.
+        * On Intel Merrifield the user visible i2c busses are
enumerated
+        * [1..7]. So, we add 1 to shift the default range. Besides that
the
+        * first PCI slot provides 4 functions, that's why we have to
add 0 to
+        * the fisrt slot and 4 to the next one.
         */
        switch (PCI_SLOT(pdev->devfn)) {
        case 8:

Should I send a new patch or you can fold it?

-- 

Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 904 bytes --]

> -        * On Intel Merrifield the i2c busses are enumerated [1..7]. So,
> we add
> -        * 1 to shift the default range. Besides that the first PCI slot
> -        * provides 4 functions, that's why we have to add 0 to the head
> slot
> -        * and 4 to the tail one.
> +        * On Intel Merrifield the user visible i2c busses are
> enumerated
> +        * [1..7]. So, we add 1 to shift the default range. Besides that
> the
> +        * first PCI slot provides 4 functions, that's why we have to
> add 0 to
> +        * the fisrt slot and 4 to the next one.
>          */
>         switch (PCI_SLOT(pdev->devfn)) {
>         case 8:
> 
> Should I send a new patch or you can fold it?

I already pushed out. Also, this patch has line break problems.

So, send an incremental one.


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