* [PATCH V2] coresight: document binding acronyms
@ 2016-06-22 15:01 ` Mathieu Poirier
0 siblings, 0 replies; 8+ messages in thread
From: Mathieu Poirier @ 2016-06-22 15:01 UTC (permalink / raw)
To: linux-arm-kernel
It can be hard for people not familiar with the CoreSight IP blocks
to make sense of the acronyms found in the current bindings. As such
this patch expands each acronym in the hope of providing a better
description of the IP block they represent.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../devicetree/bindings/arm/coresight.txt | 35 +++++++++++++++++-----
1 file changed, 27 insertions(+), 8 deletions(-)
Changes since V1:
- Expanded ETB, ETF and ETR acronyms.
- Added note about using the same binding
for all 3 modes (ETB, ETF, ETR).
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 93147c0c8a0e..fcbae6a5e6c1 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -12,14 +12,33 @@ its hardware characteristcs.
* compatible: These have to be supplemented with "arm,primecell" as
drivers are using the AMBA bus interface. Possible values include:
- - "arm,coresight-etb10", "arm,primecell";
- - "arm,coresight-tpiu", "arm,primecell";
- - "arm,coresight-tmc", "arm,primecell";
- - "arm,coresight-funnel", "arm,primecell";
- - "arm,coresight-etm3x", "arm,primecell";
- - "arm,coresight-etm4x", "arm,primecell";
- - "qcom,coresight-replicator1x", "arm,primecell";
- - "arm,coresight-stm", "arm,primecell"; [1]
+ - Embedded Trace Buffer (version 1.0):
+ "arm,coresight-etb10", "arm,primecell";
+
+ - Trace Port Interface Unit:
+ "arm,coresight-tpiu", "arm,primecell";
+
+ - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
+ Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
+ configuration. The configuration mode (ETB, ETF, ETR) is
+ discovered at boot time when the device is probed.
+ "arm,coresight-tmc", "arm,primecell";
+
+ - Trace Funnel:
+ "arm,coresight-funnel", "arm,primecell";
+
+ - Embedded Trace Macrocell (version 3.x) and
+ Program Flow Trace Macrocell:
+ "arm,coresight-etm3x", "arm,primecell";
+
+ - Embedded Trace Macrocell (version 4.x):
+ "arm,coresight-etm4x", "arm,primecell";
+
+ - Qualcomm Configurable Replicator (version 1.x):
+ "qcom,coresight-replicator1x", "arm,primecell";
+
+ - System Trace Macrocell:
+ "arm,coresight-stm", "arm,primecell"; [1]
* reg: physical base address and length of the register
set(s) of the component.
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH V2] coresight: document binding acronyms
@ 2016-06-22 15:01 ` Mathieu Poirier
0 siblings, 0 replies; 8+ messages in thread
From: Mathieu Poirier @ 2016-06-22 15:01 UTC (permalink / raw)
To: robh+dt, mark.rutland
Cc: devicetree, Suzuki.Poulose, linux-kernel, sudeep.holla, olof,
linux-arm-kernel
It can be hard for people not familiar with the CoreSight IP blocks
to make sense of the acronyms found in the current bindings. As such
this patch expands each acronym in the hope of providing a better
description of the IP block they represent.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../devicetree/bindings/arm/coresight.txt | 35 +++++++++++++++++-----
1 file changed, 27 insertions(+), 8 deletions(-)
Changes since V1:
- Expanded ETB, ETF and ETR acronyms.
- Added note about using the same binding
for all 3 modes (ETB, ETF, ETR).
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 93147c0c8a0e..fcbae6a5e6c1 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -12,14 +12,33 @@ its hardware characteristcs.
* compatible: These have to be supplemented with "arm,primecell" as
drivers are using the AMBA bus interface. Possible values include:
- - "arm,coresight-etb10", "arm,primecell";
- - "arm,coresight-tpiu", "arm,primecell";
- - "arm,coresight-tmc", "arm,primecell";
- - "arm,coresight-funnel", "arm,primecell";
- - "arm,coresight-etm3x", "arm,primecell";
- - "arm,coresight-etm4x", "arm,primecell";
- - "qcom,coresight-replicator1x", "arm,primecell";
- - "arm,coresight-stm", "arm,primecell"; [1]
+ - Embedded Trace Buffer (version 1.0):
+ "arm,coresight-etb10", "arm,primecell";
+
+ - Trace Port Interface Unit:
+ "arm,coresight-tpiu", "arm,primecell";
+
+ - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
+ Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
+ configuration. The configuration mode (ETB, ETF, ETR) is
+ discovered at boot time when the device is probed.
+ "arm,coresight-tmc", "arm,primecell";
+
+ - Trace Funnel:
+ "arm,coresight-funnel", "arm,primecell";
+
+ - Embedded Trace Macrocell (version 3.x) and
+ Program Flow Trace Macrocell:
+ "arm,coresight-etm3x", "arm,primecell";
+
+ - Embedded Trace Macrocell (version 4.x):
+ "arm,coresight-etm4x", "arm,primecell";
+
+ - Qualcomm Configurable Replicator (version 1.x):
+ "qcom,coresight-replicator1x", "arm,primecell";
+
+ - System Trace Macrocell:
+ "arm,coresight-stm", "arm,primecell"; [1]
* reg: physical base address and length of the register
set(s) of the component.
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH V2] coresight: document binding acronyms
@ 2016-06-22 16:40 ` Sudeep Holla
0 siblings, 0 replies; 8+ messages in thread
From: Sudeep Holla @ 2016-06-22 16:40 UTC (permalink / raw)
To: Mathieu Poirier, robh+dt, mark.rutland
Cc: Sudeep Holla, Suzuki.Poulose, olof, linux-arm-kernel, devicetree,
linux-kernel
On 22/06/16 16:01, Mathieu Poirier wrote:
> It can be hard for people not familiar with the CoreSight IP blocks
> to make sense of the acronyms found in the current bindings. As such
> this patch expands each acronym in the hope of providing a better
> description of the IP block they represent.
>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> .../devicetree/bindings/arm/coresight.txt | 35 +++++++++++++++++-----
> 1 file changed, 27 insertions(+), 8 deletions(-)
>
> Changes since V1:
> - Expanded ETB, ETF and ETR acronyms.
> - Added note about using the same binding
> for all 3 modes (ETB, ETF, ETR).
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 93147c0c8a0e..fcbae6a5e6c1 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -12,14 +12,33 @@ its hardware characteristcs.
>
> * compatible: These have to be supplemented with "arm,primecell" as
> drivers are using the AMBA bus interface. Possible values include:
> - - "arm,coresight-etb10", "arm,primecell";
> - - "arm,coresight-tpiu", "arm,primecell";
> - - "arm,coresight-tmc", "arm,primecell";
> - - "arm,coresight-funnel", "arm,primecell";
> - - "arm,coresight-etm3x", "arm,primecell";
> - - "arm,coresight-etm4x", "arm,primecell";
> - - "qcom,coresight-replicator1x", "arm,primecell";
> - - "arm,coresight-stm", "arm,primecell"; [1]
> + - Embedded Trace Buffer (version 1.0):
> + "arm,coresight-etb10", "arm,primecell";
> +
> + - Trace Port Interface Unit:
> + "arm,coresight-tpiu", "arm,primecell";
> +
> + - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
> + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
> + configuration. The configuration mode (ETB, ETF, ETR) is
> + discovered at boot time when the device is probed.
> + "arm,coresight-tmc", "arm,primecell";
> +
> + - Trace Funnel:
> + "arm,coresight-funnel", "arm,primecell";
> +
> + - Embedded Trace Macrocell (version 3.x) and
> + Program Flow Trace Macrocell:
> + "arm,coresight-etm3x", "arm,primecell";
> +
> + - Embedded Trace Macrocell (version 4.x):
> + "arm,coresight-etm4x", "arm,primecell";
> +
> + - Qualcomm Configurable Replicator (version 1.x):
> + "qcom,coresight-replicator1x", "arm,primecell";
> +
> + - System Trace Macrocell:
> + "arm,coresight-stm", "arm,primecell"; [1]
Looks good to me.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH V2] coresight: document binding acronyms
@ 2016-06-22 16:40 ` Sudeep Holla
0 siblings, 0 replies; 8+ messages in thread
From: Sudeep Holla @ 2016-06-22 16:40 UTC (permalink / raw)
To: linux-arm-kernel
On 22/06/16 16:01, Mathieu Poirier wrote:
> It can be hard for people not familiar with the CoreSight IP blocks
> to make sense of the acronyms found in the current bindings. As such
> this patch expands each acronym in the hope of providing a better
> description of the IP block they represent.
>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> .../devicetree/bindings/arm/coresight.txt | 35 +++++++++++++++++-----
> 1 file changed, 27 insertions(+), 8 deletions(-)
>
> Changes since V1:
> - Expanded ETB, ETF and ETR acronyms.
> - Added note about using the same binding
> for all 3 modes (ETB, ETF, ETR).
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 93147c0c8a0e..fcbae6a5e6c1 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -12,14 +12,33 @@ its hardware characteristcs.
>
> * compatible: These have to be supplemented with "arm,primecell" as
> drivers are using the AMBA bus interface. Possible values include:
> - - "arm,coresight-etb10", "arm,primecell";
> - - "arm,coresight-tpiu", "arm,primecell";
> - - "arm,coresight-tmc", "arm,primecell";
> - - "arm,coresight-funnel", "arm,primecell";
> - - "arm,coresight-etm3x", "arm,primecell";
> - - "arm,coresight-etm4x", "arm,primecell";
> - - "qcom,coresight-replicator1x", "arm,primecell";
> - - "arm,coresight-stm", "arm,primecell"; [1]
> + - Embedded Trace Buffer (version 1.0):
> + "arm,coresight-etb10", "arm,primecell";
> +
> + - Trace Port Interface Unit:
> + "arm,coresight-tpiu", "arm,primecell";
> +
> + - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
> + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
> + configuration. The configuration mode (ETB, ETF, ETR) is
> + discovered at boot time when the device is probed.
> + "arm,coresight-tmc", "arm,primecell";
> +
> + - Trace Funnel:
> + "arm,coresight-funnel", "arm,primecell";
> +
> + - Embedded Trace Macrocell (version 3.x) and
> + Program Flow Trace Macrocell:
> + "arm,coresight-etm3x", "arm,primecell";
> +
> + - Embedded Trace Macrocell (version 4.x):
> + "arm,coresight-etm4x", "arm,primecell";
> +
> + - Qualcomm Configurable Replicator (version 1.x):
> + "qcom,coresight-replicator1x", "arm,primecell";
> +
> + - System Trace Macrocell:
> + "arm,coresight-stm", "arm,primecell"; [1]
Looks good to me.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V2] coresight: document binding acronyms
@ 2016-06-22 16:40 ` Sudeep Holla
0 siblings, 0 replies; 8+ messages in thread
From: Sudeep Holla @ 2016-06-22 16:40 UTC (permalink / raw)
To: Mathieu Poirier, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: Sudeep Holla, Suzuki.Poulose-5wv7dgnIgG8,
olof-nZhT3qVonbNeoWH0uzbU5w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 22/06/16 16:01, Mathieu Poirier wrote:
> It can be hard for people not familiar with the CoreSight IP blocks
> to make sense of the acronyms found in the current bindings. As such
> this patch expands each acronym in the hope of providing a better
> description of the IP block they represent.
>
> Signed-off-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../devicetree/bindings/arm/coresight.txt | 35 +++++++++++++++++-----
> 1 file changed, 27 insertions(+), 8 deletions(-)
>
> Changes since V1:
> - Expanded ETB, ETF and ETR acronyms.
> - Added note about using the same binding
> for all 3 modes (ETB, ETF, ETR).
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 93147c0c8a0e..fcbae6a5e6c1 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -12,14 +12,33 @@ its hardware characteristcs.
>
> * compatible: These have to be supplemented with "arm,primecell" as
> drivers are using the AMBA bus interface. Possible values include:
> - - "arm,coresight-etb10", "arm,primecell";
> - - "arm,coresight-tpiu", "arm,primecell";
> - - "arm,coresight-tmc", "arm,primecell";
> - - "arm,coresight-funnel", "arm,primecell";
> - - "arm,coresight-etm3x", "arm,primecell";
> - - "arm,coresight-etm4x", "arm,primecell";
> - - "qcom,coresight-replicator1x", "arm,primecell";
> - - "arm,coresight-stm", "arm,primecell"; [1]
> + - Embedded Trace Buffer (version 1.0):
> + "arm,coresight-etb10", "arm,primecell";
> +
> + - Trace Port Interface Unit:
> + "arm,coresight-tpiu", "arm,primecell";
> +
> + - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
> + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
> + configuration. The configuration mode (ETB, ETF, ETR) is
> + discovered at boot time when the device is probed.
> + "arm,coresight-tmc", "arm,primecell";
> +
> + - Trace Funnel:
> + "arm,coresight-funnel", "arm,primecell";
> +
> + - Embedded Trace Macrocell (version 3.x) and
> + Program Flow Trace Macrocell:
> + "arm,coresight-etm3x", "arm,primecell";
> +
> + - Embedded Trace Macrocell (version 4.x):
> + "arm,coresight-etm4x", "arm,primecell";
> +
> + - Qualcomm Configurable Replicator (version 1.x):
> + "qcom,coresight-replicator1x", "arm,primecell";
> +
> + - System Trace Macrocell:
> + "arm,coresight-stm", "arm,primecell"; [1]
Looks good to me.
Acked-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
--
Regards,
Sudeep
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V2] coresight: document binding acronyms
2016-06-22 15:01 ` Mathieu Poirier
@ 2016-06-22 17:15 ` Suzuki K Poulose
-1 siblings, 0 replies; 8+ messages in thread
From: Suzuki K Poulose @ 2016-06-22 17:15 UTC (permalink / raw)
To: Mathieu Poirier, robh+dt, mark.rutland
Cc: sudeep.holla, olof, linux-arm-kernel, devicetree, linux-kernel
On 22/06/16 16:01, Mathieu Poirier wrote:
> It can be hard for people not familiar with the CoreSight IP blocks
> to make sense of the acronyms found in the current bindings. As such
> this patch expands each acronym in the hope of providing a better
> description of the IP block they represent.
>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suzuki
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH V2] coresight: document binding acronyms
@ 2016-06-22 17:15 ` Suzuki K Poulose
0 siblings, 0 replies; 8+ messages in thread
From: Suzuki K Poulose @ 2016-06-22 17:15 UTC (permalink / raw)
To: linux-arm-kernel
On 22/06/16 16:01, Mathieu Poirier wrote:
> It can be hard for people not familiar with the CoreSight IP blocks
> to make sense of the acronyms found in the current bindings. As such
> this patch expands each acronym in the hope of providing a better
> description of the IP block they represent.
>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suzuki
^ permalink raw reply [flat|nested] 8+ messages in thread