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* [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX
@ 2016-06-30  2:18 ` Xing Zheng
  0 siblings, 0 replies; 5+ messages in thread
From: Xing Zheng @ 2016-06-30  2:18 UTC (permalink / raw)
  To: heiko
  Cc: dianders, zhangqing, huangtao, briannorris, zyw, Xing Zheng,
	Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
	linux-rockchip, linux-kernel

The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.

Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index b6742fa..78e51cb 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(8), 15, GFLAGS),
 
 	COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
-			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
+			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
 			RK3399_CLKGATE_CON(10), 6, GFLAGS),
 	/* i2s */
 	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
-- 
1.7.9.5

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX
@ 2016-06-30  2:18 ` Xing Zheng
  0 siblings, 0 replies; 5+ messages in thread
From: Xing Zheng @ 2016-06-30  2:18 UTC (permalink / raw)
  To: linux-arm-kernel

The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.

Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index b6742fa..78e51cb 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(8), 15, GFLAGS),
 
 	COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
-			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
+			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
 			RK3399_CLKGATE_CON(10), 6, GFLAGS),
 	/* i2s */
 	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
-- 
1.7.9.5

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX
@ 2016-07-01  8:31   ` Heiko Stuebner
  0 siblings, 0 replies; 5+ messages in thread
From: Heiko Stuebner @ 2016-07-01  8:31 UTC (permalink / raw)
  To: Xing Zheng
  Cc: dianders, zhangqing, huangtao, briannorris, zyw,
	Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
	linux-rockchip, linux-kernel

Am Donnerstag, 30. Juni 2016, 10:18:59 schrieb Xing Zheng:
> The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
> it should be bit_8, let's fix it.
> 
> Reported-by: Chris Zhong <zyw@rock-chips.com>
> Tested-by: Chris Zhong <zyw@rock-chips.com>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk branch for 4.8

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX
@ 2016-07-01  8:31   ` Heiko Stuebner
  0 siblings, 0 replies; 5+ messages in thread
From: Heiko Stuebner @ 2016-07-01  8:31 UTC (permalink / raw)
  To: Xing Zheng
  Cc: huangtao-TNX95d0MmH7DzftRWevZcw,
	zhangqing-TNX95d0MmH7DzftRWevZcw, Michael Turquette,
	briannorris-F7+t8E8rja9g9hUCZPvPmw, Stephen Boyd,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	zyw-TNX95d0MmH7DzftRWevZcw, linux-clk-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Am Donnerstag, 30. Juni 2016, 10:18:59 schrieb Xing Zheng:
> The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
> it should be bit_8, let's fix it.
> 
> Reported-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Tested-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

applied to my clk branch for 4.8

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX
@ 2016-07-01  8:31   ` Heiko Stuebner
  0 siblings, 0 replies; 5+ messages in thread
From: Heiko Stuebner @ 2016-07-01  8:31 UTC (permalink / raw)
  To: linux-arm-kernel

Am Donnerstag, 30. Juni 2016, 10:18:59 schrieb Xing Zheng:
> The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
> it should be bit_8, let's fix it.
> 
> Reported-by: Chris Zhong <zyw@rock-chips.com>
> Tested-by: Chris Zhong <zyw@rock-chips.com>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk branch for 4.8

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2016-07-01  8:34 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-06-30  2:18 [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX Xing Zheng
2016-06-30  2:18 ` Xing Zheng
2016-07-01  8:31 ` Heiko Stuebner
2016-07-01  8:31   ` Heiko Stuebner
2016-07-01  8:31   ` Heiko Stuebner

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