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* [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together
@ 2016-07-01  8:18 Chris Wilson
  2016-07-01  8:18 ` [PATCH 2/2] drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func Chris Wilson
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2016-07-01  8:18 UTC (permalink / raw)
  To: intel-gfx

Consolidate the block of default vfuncs for dispatching the batchbuffer.
Just a minor tweak on top of Tvrtko's great job of tidying up the vfunc
initialisation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4d61ea923154..caebe812d10f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2991,25 +2991,29 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 	engine->get_seqno = ring_get_seqno;
 	engine->set_seqno = ring_set_seqno;
 
-	if (INTEL_GEN(dev_priv) >= 8) {
-		engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
+	engine->add_request = i9xx_add_request;
+	if (INTEL_GEN(dev_priv) >= 6)
 		engine->add_request = gen6_add_request;
-		engine->irq_seqno_barrier = gen6_seqno_barrier;
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+
+	if (INTEL_GEN(dev_priv) >= 8)
+		engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
+	else if (INTEL_GEN(dev_priv) >= 6)
 		engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
-		engine->add_request = gen6_add_request;
-		engine->irq_seqno_barrier = gen6_seqno_barrier;
-	} else {
+	else if (INTEL_GEN(dev_priv) >= 4)
 		engine->dispatch_execbuffer = i965_dispatch_execbuffer;
-		engine->add_request = i9xx_add_request;
-	}
+	else if (IS_I830(dev_priv) || IS_845G(dev_priv))
+		engine->dispatch_execbuffer = i830_dispatch_execbuffer;
+	else
+		engine->dispatch_execbuffer = i915_dispatch_execbuffer;
 
 	if (INTEL_GEN(dev_priv) >= 8) {
 		engine->irq_get = gen8_ring_get_irq;
 		engine->irq_put = gen8_ring_put_irq;
+		engine->irq_seqno_barrier = gen6_seqno_barrier;
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		engine->irq_get = gen6_ring_get_irq;
 		engine->irq_put = gen6_ring_put_irq;
+		engine->irq_seqno_barrier = gen6_seqno_barrier;
 	} else if (INTEL_GEN(dev_priv) >= 5) {
 		engine->irq_get = gen5_ring_get_irq;
 		engine->irq_put = gen5_ring_put_irq;
@@ -3069,10 +3073,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 
 	if (IS_HASWELL(dev_priv))
 		engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
-	else if (IS_I830(dev_priv) || IS_845G(dev_priv))
-		engine->dispatch_execbuffer = i830_dispatch_execbuffer;
-	else if (INTEL_GEN(dev_priv) <= 3)
-		engine->dispatch_execbuffer = i915_dispatch_execbuffer;
+
 	engine->init_hw = init_render_ring;
 	engine->cleanup = render_ring_cleanup;
 
-- 
2.8.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func
  2016-07-01  8:18 [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together Chris Wilson
@ 2016-07-01  8:18 ` Chris Wilson
  2016-07-01  8:41   ` Tvrtko Ursulin
  2016-07-01  8:40 ` [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together Tvrtko Ursulin
  2016-07-01  8:41 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] " Patchwork
  2 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2016-07-01  8:18 UTC (permalink / raw)
  To: intel-gfx

Just plonk all the default irq vfuncs together in one function to keep
the initialisers of reasonable size.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 43 ++++++++++++++++++---------------
 1 file changed, 24 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index caebe812d10f..24cdc920f4b4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2983,6 +2983,29 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
+				struct intel_engine_cs *engine)
+{
+	if (INTEL_GEN(dev_priv) >= 8) {
+		engine->irq_get = gen8_ring_get_irq;
+		engine->irq_put = gen8_ring_put_irq;
+		engine->irq_seqno_barrier = gen6_seqno_barrier;
+	} else if (INTEL_GEN(dev_priv) >= 6) {
+		engine->irq_get = gen6_ring_get_irq;
+		engine->irq_put = gen6_ring_put_irq;
+		engine->irq_seqno_barrier = gen6_seqno_barrier;
+	} else if (INTEL_GEN(dev_priv) >= 5) {
+		engine->irq_get = gen5_ring_get_irq;
+		engine->irq_put = gen5_ring_put_irq;
+	} else if (INTEL_GEN(dev_priv) >= 3) {
+		engine->irq_get = i9xx_ring_get_irq;
+		engine->irq_put = i9xx_ring_put_irq;
+	} else {
+		engine->irq_get = i8xx_ring_get_irq;
+		engine->irq_put = i8xx_ring_put_irq;
+	}
+}
+
 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 				      struct intel_engine_cs *engine)
 {
@@ -3006,25 +3029,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 	else
 		engine->dispatch_execbuffer = i915_dispatch_execbuffer;
 
-	if (INTEL_GEN(dev_priv) >= 8) {
-		engine->irq_get = gen8_ring_get_irq;
-		engine->irq_put = gen8_ring_put_irq;
-		engine->irq_seqno_barrier = gen6_seqno_barrier;
-	} else if (INTEL_GEN(dev_priv) >= 6) {
-		engine->irq_get = gen6_ring_get_irq;
-		engine->irq_put = gen6_ring_put_irq;
-		engine->irq_seqno_barrier = gen6_seqno_barrier;
-	} else if (INTEL_GEN(dev_priv) >= 5) {
-		engine->irq_get = gen5_ring_get_irq;
-		engine->irq_put = gen5_ring_put_irq;
-	} else if (INTEL_GEN(dev_priv) >= 3) {
-		engine->irq_get = i9xx_ring_get_irq;
-		engine->irq_put = i9xx_ring_put_irq;
-	} else {
-		engine->irq_get = i8xx_ring_get_irq;
-		engine->irq_put = i8xx_ring_put_irq;
-	}
-
+	intel_ring_init_irq(dev_priv, engine);
 	intel_ring_init_semaphores(dev_priv, engine);
 }
 
-- 
2.8.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together
  2016-07-01  8:18 [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together Chris Wilson
  2016-07-01  8:18 ` [PATCH 2/2] drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func Chris Wilson
@ 2016-07-01  8:40 ` Tvrtko Ursulin
  2016-07-01  8:41 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] " Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Tvrtko Ursulin @ 2016-07-01  8:40 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx


On 01/07/16 09:18, Chris Wilson wrote:
> Consolidate the block of default vfuncs for dispatching the batchbuffer.
> Just a minor tweak on top of Tvrtko's great job of tidying up the vfunc
> initialisation.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 27 ++++++++++++++-------------
>   1 file changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4d61ea923154..caebe812d10f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2991,25 +2991,29 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>   	engine->get_seqno = ring_get_seqno;
>   	engine->set_seqno = ring_set_seqno;
>
> -	if (INTEL_GEN(dev_priv) >= 8) {
> -		engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> +	engine->add_request = i9xx_add_request;
> +	if (INTEL_GEN(dev_priv) >= 6)
>   		engine->add_request = gen6_add_request;
> -		engine->irq_seqno_barrier = gen6_seqno_barrier;
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> +
> +	if (INTEL_GEN(dev_priv) >= 8)
> +		engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> +	else if (INTEL_GEN(dev_priv) >= 6)
>   		engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> -		engine->add_request = gen6_add_request;
> -		engine->irq_seqno_barrier = gen6_seqno_barrier;
> -	} else {
> +	else if (INTEL_GEN(dev_priv) >= 4)
>   		engine->dispatch_execbuffer = i965_dispatch_execbuffer;
> -		engine->add_request = i9xx_add_request;
> -	}
> +	else if (IS_I830(dev_priv) || IS_845G(dev_priv))
> +		engine->dispatch_execbuffer = i830_dispatch_execbuffer;
> +	else
> +		engine->dispatch_execbuffer = i915_dispatch_execbuffer;
>
>   	if (INTEL_GEN(dev_priv) >= 8) {
>   		engine->irq_get = gen8_ring_get_irq;
>   		engine->irq_put = gen8_ring_put_irq;
> +		engine->irq_seqno_barrier = gen6_seqno_barrier;
>   	} else if (INTEL_GEN(dev_priv) >= 6) {
>   		engine->irq_get = gen6_ring_get_irq;
>   		engine->irq_put = gen6_ring_put_irq;
> +		engine->irq_seqno_barrier = gen6_seqno_barrier;
>   	} else if (INTEL_GEN(dev_priv) >= 5) {
>   		engine->irq_get = gen5_ring_get_irq;
>   		engine->irq_put = gen5_ring_put_irq;
> @@ -3069,10 +3073,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>
>   	if (IS_HASWELL(dev_priv))
>   		engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
> -	else if (IS_I830(dev_priv) || IS_845G(dev_priv))
> -		engine->dispatch_execbuffer = i830_dispatch_execbuffer;
> -	else if (INTEL_GEN(dev_priv) <= 3)
> -		engine->dispatch_execbuffer = i915_dispatch_execbuffer;
> +
>   	engine->init_hw = init_render_ring;
>   	engine->cleanup = render_ring_cleanup;

I was planning to do this today after your comment from yesterday, which 
I was agreeing with, but you beat me to it. No complaints about that. :)

Looks correct.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko




_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together
  2016-07-01  8:18 [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together Chris Wilson
  2016-07-01  8:18 ` [PATCH 2/2] drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func Chris Wilson
  2016-07-01  8:40 ` [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together Tvrtko Ursulin
@ 2016-07-01  8:41 ` Patchwork
  2016-07-01  8:46   ` Chris Wilson
  2 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2016-07-01  8:41 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together
URL   : https://patchwork.freedesktop.org/series/9357/
State : failure

== Summary ==

Series 9357v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/9357/revisions/1/mbox

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                pass       -> FAIL       (ro-byt-n2820)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> INCOMPLETE (fi-skl-i5-6260u)
        Subgroup hang-read-crc-pipe-b:
                pass       -> INCOMPLETE (fi-skl-i7-6700k)
        Subgroup suspend-read-crc-pipe-a:
                dmesg-warn -> SKIP       (ro-bdw-i5-5250u)
        Subgroup suspend-read-crc-pipe-b:
                pass       -> INCOMPLETE (fi-hsw-i7-4770k)
                dmesg-warn -> SKIP       (ro-bdw-i5-5250u)

fi-hsw-i7-4770k  total:197  pass:178  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-qkkr      total:229  pass:160  dwarn:29  dfail:0   fail:0   skip:40 
fi-skl-i5-6260u  total:192  pass:181  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-i7-6700k  total:198  pass:173  dwarn:0   dfail:0   fail:0   skip:24 
fi-snb-i7-2600   total:229  pass:176  dwarn:0   dfail:0   fail:0   skip:53 
ro-bdw-i5-5250u  total:229  pass:204  dwarn:2   dfail:1   fail:0   skip:22 
ro-bdw-i7-5557U  total:229  pass:204  dwarn:1   dfail:1   fail:0   skip:23 
ro-bdw-i7-5600u  total:229  pass:190  dwarn:0   dfail:1   fail:0   skip:38 
ro-bsw-n3050     total:229  pass:176  dwarn:1   dfail:1   fail:2   skip:49 
ro-byt-n2820     total:229  pass:180  dwarn:0   dfail:1   fail:3   skip:45 
ro-hsw-i7-4770r  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31 
ro-ilk-i7-620lm  total:229  pass:157  dwarn:0   dfail:1   fail:1   skip:70 
ro-ilk1-i5-650   total:224  pass:157  dwarn:0   dfail:1   fail:1   skip:65 
ro-ivb-i7-3770   total:229  pass:188  dwarn:0   dfail:1   fail:0   skip:40 
ro-ivb2-i7-3770  total:229  pass:192  dwarn:0   dfail:1   fail:0   skip:36 
ro-skl3-i5-6260u total:229  pass:208  dwarn:1   dfail:1   fail:0   skip:19 
ro-snb-i7-2620M  total:229  pass:179  dwarn:0   dfail:1   fail:1   skip:48 
ro-hsw-i3-4010u failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1351/

b538380 drm-intel-nightly: 2016y-06m-30d-16h-21m-05s UTC integration manifest
fd4430f8 drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func
8c46988 drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func
  2016-07-01  8:18 ` [PATCH 2/2] drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func Chris Wilson
@ 2016-07-01  8:41   ` Tvrtko Ursulin
  0 siblings, 0 replies; 6+ messages in thread
From: Tvrtko Ursulin @ 2016-07-01  8:41 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx


On 01/07/16 09:18, Chris Wilson wrote:
> Just plonk all the default irq vfuncs together in one function to keep
> the initialisers of reasonable size.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 43 ++++++++++++++++++---------------
>   1 file changed, 24 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index caebe812d10f..24cdc920f4b4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2983,6 +2983,29 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
>   	}
>   }
>
> +static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
> +				struct intel_engine_cs *engine)
> +{
> +	if (INTEL_GEN(dev_priv) >= 8) {
> +		engine->irq_get = gen8_ring_get_irq;
> +		engine->irq_put = gen8_ring_put_irq;
> +		engine->irq_seqno_barrier = gen6_seqno_barrier;
> +	} else if (INTEL_GEN(dev_priv) >= 6) {
> +		engine->irq_get = gen6_ring_get_irq;
> +		engine->irq_put = gen6_ring_put_irq;
> +		engine->irq_seqno_barrier = gen6_seqno_barrier;
> +	} else if (INTEL_GEN(dev_priv) >= 5) {
> +		engine->irq_get = gen5_ring_get_irq;
> +		engine->irq_put = gen5_ring_put_irq;
> +	} else if (INTEL_GEN(dev_priv) >= 3) {
> +		engine->irq_get = i9xx_ring_get_irq;
> +		engine->irq_put = i9xx_ring_put_irq;
> +	} else {
> +		engine->irq_get = i8xx_ring_get_irq;
> +		engine->irq_put = i8xx_ring_put_irq;
> +	}
> +}
> +
>   static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>   				      struct intel_engine_cs *engine)
>   {
> @@ -3006,25 +3029,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>   	else
>   		engine->dispatch_execbuffer = i915_dispatch_execbuffer;
>
> -	if (INTEL_GEN(dev_priv) >= 8) {
> -		engine->irq_get = gen8_ring_get_irq;
> -		engine->irq_put = gen8_ring_put_irq;
> -		engine->irq_seqno_barrier = gen6_seqno_barrier;
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> -		engine->irq_get = gen6_ring_get_irq;
> -		engine->irq_put = gen6_ring_put_irq;
> -		engine->irq_seqno_barrier = gen6_seqno_barrier;
> -	} else if (INTEL_GEN(dev_priv) >= 5) {
> -		engine->irq_get = gen5_ring_get_irq;
> -		engine->irq_put = gen5_ring_put_irq;
> -	} else if (INTEL_GEN(dev_priv) >= 3) {
> -		engine->irq_get = i9xx_ring_get_irq;
> -		engine->irq_put = i9xx_ring_put_irq;
> -	} else {
> -		engine->irq_get = i8xx_ring_get_irq;
> -		engine->irq_put = i8xx_ring_put_irq;
> -	}
> -
> +	intel_ring_init_irq(dev_priv, engine);
>   	intel_ring_init_semaphores(dev_priv, engine);
>   }
>
>

Yes thats better.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together
  2016-07-01  8:41 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] " Patchwork
@ 2016-07-01  8:46   ` Chris Wilson
  0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2016-07-01  8:46 UTC (permalink / raw)
  To: intel-gfx

On Fri, Jul 01, 2016 at 08:41:03AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together
> URL   : https://patchwork.freedesktop.org/series/9357/
> State : failure
> 
> == Summary ==
> 
> Series 9357v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/9357/revisions/1/mbox
> 
> Test gem_exec_flush:
>         Subgroup basic-batch-kernel-default-cmd:
>                 pass       -> FAIL       (ro-byt-n2820)
> Test kms_pipe_crc_basic:
>         Subgroup hang-read-crc-pipe-a:
>                 pass       -> INCOMPLETE (fi-skl-i5-6260u)
>         Subgroup hang-read-crc-pipe-b:
>                 pass       -> INCOMPLETE (fi-skl-i7-6700k)
>         Subgroup suspend-read-crc-pipe-a:
>                 dmesg-warn -> SKIP       (ro-bdw-i5-5250u)
>         Subgroup suspend-read-crc-pipe-b:
>                 pass       -> INCOMPLETE (fi-hsw-i7-4770k)
>                 dmesg-warn -> SKIP       (ro-bdw-i5-5250u)

Oh, today's going to be one of those days where kms_pipe_crc_basic
randomly explodes.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
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2016-07-01  8:18 [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together Chris Wilson
2016-07-01  8:18 ` [PATCH 2/2] drm/i915/ringbuffer: Move all default irq vfuncs init to a separate func Chris Wilson
2016-07-01  8:41   ` Tvrtko Ursulin
2016-07-01  8:40 ` [PATCH 1/2] drm/i915/ringbuffer: Move all generic engine->dispatch_batchbuffer together Tvrtko Ursulin
2016-07-01  8:41 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] " Patchwork
2016-07-01  8:46   ` Chris Wilson

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