* [U-Boot] [Patch v2 0/4] armv8: fsl-layerscape: Add LS1046A SoC support
@ 2016-07-01 10:48 Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection Gong Qianyu
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Gong Qianyu @ 2016-07-01 10:48 UTC (permalink / raw)
To: u-boot
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Change history:
[Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection
v2:
- Add commit messages.
[Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support
v2:
- Move serdes 2 support to a new patch.
- Fix SVR and add LS1026A SVR.
- Add SoC descriptions in README.soc.
- Remove ls1046a errata.
[Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support
v2:
- New patch.
[Patch v2 4/4] drivers: net/fm: Add Fman support for LS1046A
v2:
- Add commit messages.
Regards,
Qianyu
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection
2016-07-01 10:48 [U-Boot] [Patch v2 0/4] armv8: fsl-layerscape: Add LS1046A SoC support Gong Qianyu
@ 2016-07-01 10:48 ` Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support Gong Qianyu
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Gong Qianyu @ 2016-07-01 10:48 UTC (permalink / raw)
To: u-boot
From: Alison Wang <b18965@freescale.com>
Add support to detect Cortex-A72 core for printing it out.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
---
v2:
- Added commit messages.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 ++-
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8062106..b810d01 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -558,7 +558,8 @@ int print_cpuinfo(void)
printf("CPU%d(%s):%-4s MHz ", core,
type == TY_ITYP_VER_A7 ? "A7 " :
(type == TY_ITYP_VER_A53 ? "A53" :
- (type == TY_ITYP_VER_A57 ? "A57" : " ")),
+ (type == TY_ITYP_VER_A57 ? "A57" :
+ (type == TY_ITYP_VER_A72 ? "A72" : " "))),
strmhz(buf, sysinfo.freq_processor[core]));
}
printf("\n Bus: %-4s MHz ",
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8b8a7c1..cbb252c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -94,6 +94,7 @@
#define TY_ITYP_VER_A7 0x1
#define TY_ITYP_VER_A53 0x2
#define TY_ITYP_VER_A57 0x3
+#define TY_ITYP_VER_A72 0x4
#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3ad46eb..4d54ab2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -156,6 +156,7 @@
#define TY_ITYP_VER_A7 0x1
#define TY_ITYP_VER_A53 0x2
#define TY_ITYP_VER_A57 0x3
+#define TY_ITYP_VER_A72 0x4
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support
2016-07-01 10:48 [U-Boot] [Patch v2 0/4] armv8: fsl-layerscape: Add LS1046A SoC support Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection Gong Qianyu
@ 2016-07-01 10:48 ` Gong Qianyu
2016-07-04 3:15 ` Prabhakar Kushwaha
2016-07-01 10:48 ` [U-Boot] [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 4/4] drivers: net/fm: Add Fman support for LS1046A Gong Qianyu
3 siblings, 1 reply; 7+ messages in thread
From: Gong Qianyu @ 2016-07-01 10:48 UTC (permalink / raw)
To: u-boot
From: Mingkai Hu <mingkai.hu@nxp.com>
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
---
v2:
- Move serdes 2 support to a new patch.
- Fix SVR and add LS1026A SVR.
- Add SoC descriptions in README.soc.
- Remove ls1046a errata.
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 +
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 42 +++++++++
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 25 +++++-
arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 99 ++++++++++++++++++++++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 45 ++++++++++
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +
.../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 +
8 files changed, 218 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index eb2cbc3..4df467d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -32,3 +32,7 @@ endif
ifneq ($(CONFIG_LS1012A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
endif
+
+ifneq ($(CONFIG_LS1046A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index 8eee016..f7b949a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -3,6 +3,7 @@ SoC overview
1. LS1043A
2. LS2080A
3. LS1012A
+ 4. LS1046A
LS1043A
---------
@@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and features:
- Two WatchDog timers
- ARM generic timer
- QorIQ platform's trust architecture 2.1
+
+LS1046A
+--------
+The LS1046A integrated multicore processor combines four ARM Cortex-A72
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1046A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A72 CPUs
+ - 2 MB unified L2 Cache
+ - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+ the following functions:
+ - Packet parsing, classification, and distribution (FMan)
+ - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+ - Hardware buffer management for buffer allocation and de-allocation (BMan)
+ - Cryptography acceleration (SEC)
+ - Two Configurable x4 SerDes
+ - Two PLLs per four-lane SerDes
+ - Support for 10G operation
+ - Ethernet interfaces by FMan
+ - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+ - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
+ - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
+ - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
+ - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
+ - High-speed peripheral interfaces
+ - Three PCIe 3.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+ - Three high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Serial peripheral interface (SPI) controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC) supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index d0dc58d..8922197 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
case 3:
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
break;
+ case 4:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+ break;
+ case 5:
+ sys_info->freq_fman[0] = sys_info->freq_systembus;
+ break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
break;
@@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info)
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
- rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
- sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+ switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_sdhc = freq_c_pll[1];
+ break;
+ case 2:
+ sys_info->freq_sdhc = freq_c_pll[1] / 2;
+ break;
+ case 3:
+ sys_info->freq_sdhc = freq_c_pll[1] / 3;
+ break;
+ case 6:
+ sys_info->freq_sdhc = freq_c_pll[0] / 2;
+ break;
+ default:
+ printf("Error: Unknown ESDHC clock select!\n");
+ break;
+ }
#else
sys_info->freq_sdhc = sys_info->freq_systembus;
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
new file mode 100644
index 0000000..1da6b71
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
+ {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
+ {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
+ {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
+ SGMII_FM1_DTSEC6} },
+ {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
+ SGMII_FM1_DTSEC6} },
+ {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
+ SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {}
+};
+
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
+ {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
+ {0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
+ {0x0506, {NONE, PCIE2, NONE, PCIE3} },
+ {0x0559, {NONE, PCIE2, PCIE3, SATA1} },
+ {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
+ {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 44fe0c0..cb11d4a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -229,6 +229,51 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_SEC_BE
+#elif defined(CONFIG_LS1046A)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES 4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SEC_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x01410000
+#define GICC_BASE 0x01420000
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 197b0eb..56dd722 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -13,6 +13,8 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 487cba8..606b667 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -150,7 +150,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
-#ifdef CONFIG_LS1043A
+#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 39e8c7a..8d4a7ad 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -44,6 +44,8 @@ struct cpu_type {
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
+#define SVR_LS1046A 0x870700
+#define SVR_LS1026A 0x870708
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support
2016-07-01 10:48 [U-Boot] [Patch v2 0/4] armv8: fsl-layerscape: Add LS1046A SoC support Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support Gong Qianyu
@ 2016-07-01 10:48 ` Gong Qianyu
2016-07-01 11:10 ` Qianyu Gong
2016-07-01 10:48 ` [U-Boot] [Patch v2 4/4] drivers: net/fm: Add Fman support for LS1046A Gong Qianyu
3 siblings, 1 reply; 7+ messages in thread
From: Gong Qianyu @ 2016-07-01 10:48 UTC (permalink / raw)
To: u-boot
This patch adds serdes 2 support for FSL_LSCH2.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
---
v2:
- New patch.
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 19 +++++++++++++++++++
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
.../arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++
3 files changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index fe3444a..f73092a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -13,6 +13,9 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
int is_serdes_configured(enum srds_prtcl device)
{
@@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device)
#ifdef CONFIG_SYS_FSL_SRDS_1
ret |= serdes1_prtcl_map[device];
#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ ret |= serdes2_prtcl_map[device];
+#endif
return !!ret;
}
@@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
break;
#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ case FSL_SRDS_2:
+ cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ break;
+#endif
default:
printf("invalid SerDes%d\n", sd);
break;
@@ -114,4 +126,11 @@ void fsl_serdes_init(void)
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ serdes_init(FSL_SRDS_2,
+ CONFIG_SYS_FSL_SERDES_ADDR,
+ FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
+ FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
+ serdes2_prtcl_map);
+#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 606b667..e1b3f44 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -140,6 +140,7 @@ enum srds_prtcl {
enum srds {
FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
};
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index cbb252c..05f497c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -228,6 +228,8 @@ struct ccsr_gur {
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
#define RCW_SB_EN_REG_INDEX 7
#define RCW_SB_EN_MASK 0x00200000
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [Patch v2 4/4] drivers: net/fm: Add Fman support for LS1046A
2016-07-01 10:48 [U-Boot] [Patch v2 0/4] armv8: fsl-layerscape: Add LS1046A SoC support Gong Qianyu
` (2 preceding siblings ...)
2016-07-01 10:48 ` [U-Boot] [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support Gong Qianyu
@ 2016-07-01 10:48 ` Gong Qianyu
3 siblings, 0 replies; 7+ messages in thread
From: Gong Qianyu @ 2016-07-01 10:48 UTC (permalink / raw)
To: u-boot
From: Mingkai Hu <mingkai.hu@nxp.com>
This patch adds Fman support for LS1046A SoC.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
---
v2:
- Add commit messages.
drivers/net/fm/Makefile | 1 +
drivers/net/fm/ls1046.c | 123 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 124 insertions(+)
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 493cdc6..344fbe2 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
obj-$(CONFIG_LS1043A) += ls1043.o
+obj-$(CONFIG_LS1046A) += ls1046.o
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
new file mode 100644
index 0000000..bf55554
--- /dev/null
+++ b/drivers/net/fm/ls1046.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+
+#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
+#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
+#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+ [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+ [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+ [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+ [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+ [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+ [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+ [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+ [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ if (is_device_disabled(port))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if (port == FM1_DTSEC3)
+ if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+ FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if (port == FM1_DTSEC4)
+ if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+ FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
+ return PHY_INTERFACE_MODE_RGMII;
+
+ /* handle SGMII, only MAC 2/5/6/9/10 available */
+ switch (port) {
+ case FM1_DTSEC2:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ break;
+ }
+
+ /* handle 2.5G SGMII, only MAC 5/9/10 available */
+ switch (port) {
+ case FM1_DTSEC5:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
+ port - FM1_DTSEC5))
+ return PHY_INTERFACE_MODE_SGMII_2500;
+ break;
+ default:
+ break;
+ }
+
+ /* handle QSGMII, only MAC 1/5/6/10 available */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC10:
+ if (is_serdes_configured(QSGMII_FM1_A))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ default:
+ break;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support
2016-07-01 10:48 ` [U-Boot] [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support Gong Qianyu
@ 2016-07-01 11:10 ` Qianyu Gong
0 siblings, 0 replies; 7+ messages in thread
From: Qianyu Gong @ 2016-07-01 11:10 UTC (permalink / raw)
To: u-boot
Sorry...this should be put before the second patch.
I'll fix it in the next version.
Regards,
Qianyu
> -----Original Message-----
> From: Gong Qianyu [mailto:Qianyu.Gong at nxp.com]
> Sent: Friday, July 01, 2016 6:49 PM
> To: york sun <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; Zhiqiang Hou <zhiqiang.hou@nxp.com>;
> Shaohui Xie <shaohui.xie@nxp.com>; Wenbin Song <wenbin.song@nxp.com>;
> Qianyu Gong <qianyu.gong@nxp.com>
> Subject: [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support
>
> This patch adds serdes 2 support for FSL_LSCH2.
>
> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
> ---
> v2:
> - New patch.
>
> arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 19
> +++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h |
> 1 + .../arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++
> 3 files changed, 22 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
> index fe3444a..f73092a 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
> @@ -13,6 +13,9 @@
> #ifdef CONFIG_SYS_FSL_SRDS_1
> static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
> #endif
> +#ifdef CONFIG_SYS_FSL_SRDS_2
> +static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
> +#endif
>
> int is_serdes_configured(enum srds_prtcl device) { @@ -21,6 +24,9 @@ int
> is_serdes_configured(enum srds_prtcl device) #ifdef CONFIG_SYS_FSL_SRDS_1
> ret |= serdes1_prtcl_map[device];
> #endif
> +#ifdef CONFIG_SYS_FSL_SRDS_2
> + ret |= serdes2_prtcl_map[device];
> +#endif
>
> return !!ret;
> }
> @@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
> cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
> break;
> #endif
> +#ifdef CONFIG_SYS_FSL_SRDS_2
> + case FSL_SRDS_2:
> + cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
> + cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
> + break;
> +#endif
> default:
> printf("invalid SerDes%d\n", sd);
> break;
> @@ -114,4 +126,11 @@ void fsl_serdes_init(void)
> FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
> serdes1_prtcl_map);
> #endif
> +#ifdef CONFIG_SYS_FSL_SRDS_2
> + serdes_init(FSL_SRDS_2,
> + CONFIG_SYS_FSL_SERDES_ADDR,
> + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
> + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
> + serdes2_prtcl_map);
> +#endif
> }
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> index 606b667..e1b3f44 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> @@ -140,6 +140,7 @@ enum srds_prtcl {
>
> enum srds {
> FSL_SRDS_1 = 0,
> + FSL_SRDS_2 = 1,
> };
>
> #endif
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index cbb252c..05f497c 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -228,6 +228,8 @@ struct ccsr_gur {
> #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
> #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
> +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
> +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
> #define RCW_SB_EN_REG_INDEX 7
> #define RCW_SB_EN_MASK 0x00200000
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support
2016-07-01 10:48 ` [U-Boot] [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support Gong Qianyu
@ 2016-07-04 3:15 ` Prabhakar Kushwaha
0 siblings, 0 replies; 7+ messages in thread
From: Prabhakar Kushwaha @ 2016-07-04 3:15 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Gong Qianyu [mailto:Qianyu.Gong at nxp.com]
> Sent: Friday, July 01, 2016 4:19 PM
> To: york sun <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; Zhiqiang Hou
> <zhiqiang.hou@nxp.com>; Shaohui Xie <shaohui.xie@nxp.com>; Wenbin
> Song <wenbin.song@nxp.com>; Zhiqiang Hou <zhiqiang.hou@nxp.com>;
> Mihai Bantea <mihai.bantea@freescale.com>; Qianyu Gong
> <qianyu.gong@nxp.com>
> Subject: [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support
>
> From: Mingkai Hu <mingkai.hu@nxp.com>
>
> The LS1046A processor is built on the QorIQ LS series architecture combining
> four ARM A72 processor cores with DPAA 1.0 support.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
> ---
> v2:
> - Move serdes 2 support to a new patch.
> - Fix SVR and add LS1026A SVR.
> - Add SoC descriptions in README.soc.
> - Remove ls1046a errata.
>
> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 +
> arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 42 +++++++++
> .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 25 +++++-
> arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 99
> ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-
> layerscape/config.h | 45 ++++++++++
> arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +
> .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
> arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 +
> 8 files changed, 218 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index eb2cbc3..4df467d 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -32,3 +32,7 @@ endif
> ifneq ($(CONFIG_LS1012A),)
> obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o endif
> +
> +ifneq ($(CONFIG_LS1046A),)
> +obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o endif
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> index 8eee016..f7b949a 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> @@ -3,6 +3,7 @@ SoC overview
> 1. LS1043A
> 2. LS2080A
> 3. LS1012A
> + 4. LS1046A
>
> LS1043A
> ---------
> @@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and
> features:
> - Two WatchDog timers
> - ARM generic timer
> - QorIQ platform's trust architecture 2.1
> +
> +LS1046A
> +--------
> +The LS1046A integrated multicore processor combines four ARM Cortex-
> A72
> +processor cores with datapath acceleration optimized for L2/3 packet
> +processing, single pass security offload and robust traffic management
> +and quality of service.
> +
> +The LS1046A SoC includes the following function and features:
> + - Four 64-bit ARM Cortex-A72 CPUs
> + - 2 MB unified L2 Cache
> + - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
> + support
> + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
> + the following functions:
> + - Packet parsing, classification, and distribution (FMan)
> + - Queue management for scheduling, packet sequencing, and congestion
> + management (QMan)
> + - Hardware buffer management for buffer allocation and de-allocation
> (BMan)
> + - Cryptography acceleration (SEC)
> + - Two Configurable x4 SerDes
> + - Two PLLs per four-lane SerDes
> + - Support for 10G operation
> + - Ethernet interfaces by FMan
> + - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
> + - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
> + - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
> + - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
> + - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
> + - High-speed peripheral interfaces
> + - Three PCIe 3.0 controllers, one supporting x4 operation
> + - One serial ATA (SATA 3.0) controllers
> + - Additional peripheral interfaces
> + - Three high-speed USB 3.0 controllers with integrated PHY
> + - Enhanced secure digital host controller (eSDXC/eMMC)
> + - Quad Serial Peripheral Interface (QSPI) Controller
> + - Serial peripheral interface (SPI) controller
> + - Four I2C controllers
> + - Two DUARTs
> + - Integrated flash controller (IFC) supporting NAND and NOR flash
> + - QorIQ platform's trust architecture 2.1
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> index d0dc58d..8922197 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> @@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
> case 3:
> sys_info->freq_fman[0] = freq_c_pll[0] / 3;
> break;
> + case 4:
> + sys_info->freq_fman[0] = freq_c_pll[0] / 4;
> + break;
> + case 5:
> + sys_info->freq_fman[0] = sys_info->freq_systembus;
> + break;
> case 6:
> sys_info->freq_fman[0] = freq_c_pll[1] / 2;
> break;
> @@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info) #ifdef
> CONFIG_FSL_ESDHC #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
> rcw_tmp = in_be32(&gur->rcwsr[15]);
> - rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >>
> HWA_CGA_M2_CLK_SHIFT;
> - sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
> + switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >>
> HWA_CGA_M2_CLK_SHIFT) {
> + case 1:
> + sys_info->freq_sdhc = freq_c_pll[1];
> + break;
> + case 2:
> + sys_info->freq_sdhc = freq_c_pll[1] / 2;
> + break;
> + case 3:
> + sys_info->freq_sdhc = freq_c_pll[1] / 3;
> + break;
> + case 6:
> + sys_info->freq_sdhc = freq_c_pll[0] / 2;
> + break;
> + default:
> + printf("Error: Unknown ESDHC clock select!\n");
> + break;
> + }
> #else
> sys_info->freq_sdhc = sys_info->freq_systembus; #endif diff --git
> a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
> new file mode 100644
> index 0000000..1da6b71
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
> @@ -0,0 +1,99 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/fsl_serdes.h>
> +#include <asm/arch/immap_lsch2.h>
> +
> +struct serdes_config {
> + u32 protocol;
> + u8 lanes[SRDS_MAX_LANES];
> +};
> +
> +static struct serdes_config serdes1_cfg_tbl[] = {
> + /* SerDes 1 */
> + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
> SGMII_FM1_DTSEC5,
> + SGMII_FM1_DTSEC6} },
> + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
> + SGMII_FM1_DTSEC6} },
> + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10,
> SGMII_FM1_DTSEC5,
> + SGMII_FM1_DTSEC6} },
> + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10,
> SGMII_FM1_DTSEC5,
> + SGMII_FM1_DTSEC6} },
> + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
> + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
> + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
> + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE}
> },
> + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1,
> SGMII_FM1_DTSEC6} },
> + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
> PCIE1,
> + SGMII_FM1_DTSEC6} },
> + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
> + SGMII_FM1_DTSEC6} },
> + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
> + SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
> + {}
> +};
> +
> +static struct serdes_config serdes2_cfg_tbl[] = {
> + /* SerDes 2 */
> + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
> + {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
> + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
> + {0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
> + {0x0506, {NONE, PCIE2, NONE, PCIE3} },
> + {0x0559, {NONE, PCIE2, PCIE3, SATA1} },
> + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
> + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
> + {}
> +};
> +
> +static struct serdes_config *serdes_cfg_tbl[] = {
> + serdes1_cfg_tbl,
> + serdes2_cfg_tbl,
> +};
> +
> +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) {
> + struct serdes_config *ptr;
> +
> + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
> + return 0;
> +
> + ptr = serdes_cfg_tbl[serdes];
> + while (ptr->protocol) {
> + if (ptr->protocol == cfg)
> + return ptr->lanes[lane];
> + ptr++;
> + }
> +
> + return 0;
> +}
> +
> +int is_serdes_prtcl_valid(int serdes, u32 prtcl) {
> + int i;
> + struct serdes_config *ptr;
> +
> + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
> + return 0;
> +
> + ptr = serdes_cfg_tbl[serdes];
> + while (ptr->protocol) {
> + if (ptr->protocol == prtcl)
> + break;
> + ptr++;
> + }
> +
> + if (!ptr->protocol)
> + return 0;
> +
> + for (i = 0; i < SRDS_MAX_LANES; i++) {
> + if (ptr->lanes[i] != NONE)
> + return 1;
> + }
> +
> + return 0;
> +}
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index 44fe0c0..cb11d4a 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -229,6 +229,51 @@
> #define CONFIG_SYS_FSL_SRDS_1
> #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
> #define CONFIG_SYS_FSL_SEC_BE
> +#elif defined(CONFIG_LS1046A)
> +#define CONFIG_MAX_CPUS 4
> +#define CONFIG_SYS_CACHELINE_SIZE 64
> +#define CONFIG_SYS_FMAN_V3
> +#define CONFIG_SYS_NUM_FMAN 1
> +#define CONFIG_SYS_NUM_FM1_DTSEC 8
> +#define CONFIG_SYS_NUM_FM1_10GEC 2
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
> +#define CONFIG_NUM_DDR_CONTROLLERS 1
> +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
> +#define CONFIG_SYS_FSL_SEC_COMPAT 5
> +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial
> RAM */
> +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
> +#define CONFIG_SYS_FSL_DDR_BE
> +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
> +#define CONFIG_MAX_MEM_MAPPED
> CONFIG_SYS_DDR_BLOCK1_SIZE
> +
> +#define CONFIG_SYS_FSL_CCSR_GUR_BE
> +#define CONFIG_SYS_FSL_CCSR_SCFG_BE
> +#define CONFIG_SYS_FSL_IFC_BE
> +#define CONFIG_SYS_FSL_ESDHC_BE
> +#define CONFIG_SYS_FSL_WDOG_BE
> +#define CONFIG_SYS_FSL_DSPI_BE
> +#define CONFIG_SYS_FSL_QSPI_BE
> +#define CONFIG_SYS_FSL_PEX_LUT_BE
> +
> +#define SRDS_MAX_LANES 4
> +#define CONFIG_SYS_FSL_SRDS_1
> +#define CONFIG_SYS_FSL_SRDS_2
> +
> +#define CONFIG_SYS_FSL_SFP_VER_3_2
> +#define CONFIG_SYS_FSL_SNVS_LE
> +#define CONFIG_SYS_FSL_SEC_BE
> +#define CONFIG_SYS_FSL_SFP_BE
> +#define CONFIG_SYS_FSL_SRK_LE
> +#define CONFIG_KEY_REVOCATION
> +
> +/* SMMU Defintions */
> +#define SMMU_BASE 0x09000000
> +
> +/* Generic Interrupt Controller Definitions */
> +#define GICD_BASE 0x01410000
> +#define GICC_BASE 0x01420000
> +
> +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
> #else
> #error SoC not defined
> #endif
Most of the defines are common across LS1043, LS1012A and LS1046.
Will it be possible to create a new patch moving common defines to one place within this file.
It will increase readability.
Please use chassis specific config.
I can help you with testing on LS1012A.
--prabhakar
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-07-04 3:15 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-01 10:48 [U-Boot] [Patch v2 0/4] armv8: fsl-layerscape: Add LS1046A SoC support Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection Gong Qianyu
2016-07-01 10:48 ` [U-Boot] [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support Gong Qianyu
2016-07-04 3:15 ` Prabhakar Kushwaha
2016-07-01 10:48 ` [U-Boot] [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support Gong Qianyu
2016-07-01 11:10 ` Qianyu Gong
2016-07-01 10:48 ` [U-Boot] [Patch v2 4/4] drivers: net/fm: Add Fman support for LS1046A Gong Qianyu
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.