* [PATCH v2 0/6] HuC Loading Patches
@ 2016-07-01 13:15 Peter Antoine
2016-07-01 13:15 ` [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general Peter Antoine
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Peter Antoine @ 2016-07-01 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
This patch series enables the HuC loading. These patches are a port of the
patches that were created by Yu Dai (Alex) and have been ported to work with
the new GuC patches.
The series include a patch to enable the HuC on BXT. This is a separate patch
as the state of the BXT HuC firmware is still in flux, so the patch can be
dropped without delaying the series.
v2: rebased onto drm-intel-nightly.
Also, patch 1 has been recreated as the upstream version of the function
had change significantly making the old patch obsolete.
Also, due to a code move i915_dma.c -> i915_drv.c some code was being
applied to a deleted file.
Also HuC file versions and formats changed.
Feedback from D.Gordon and R.Vivi (Thanks).
Peter Antoine (6):
drm/i915/guc: Make the GuC fw loading helper functions general
drm/i915/huc: Unified css_header struct for GuC and HuC
drm/i915/huc: Add HuC fw loading support
drm/i915/huc: Add debugfs for HuC loading status check
drm/i915/huc: Support HuC authentication
drm/i915/huc: Add BXT HuC Loading Support
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 44 ++++-
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/i915_guc_submission.c | 69 +++++++-
drivers/gpu/drm/i915/intel_guc.h | 46 ++---
drivers/gpu/drm/i915/intel_guc_fwif.h | 17 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 202 +++++++++++----------
drivers/gpu/drm/i915/intel_huc.h | 44 +++++
drivers/gpu/drm/i915/intel_huc_loader.c | 274 +++++++++++++++++++++++++++++
11 files changed, 583 insertions(+), 123 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
@ 2016-07-01 13:15 ` Peter Antoine
2016-07-05 14:44 ` Dave Gordon
2016-07-01 13:15 ` [PATCH v2 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC Peter Antoine
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Peter Antoine @ 2016-07-01 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.
v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_guc.h | 39 ++++----
drivers/gpu/drm/i915/intel_guc_loader.c | 142 ++++++++++++++---------------
4 files changed, 99 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f664884..3883df5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2483,7 +2483,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
u32 tmp, i;
if (!HAS_GUC_UCODE(dev_priv))
@@ -2491,15 +2491,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
- guc_fw->guc_fw_path);
+ guc_fw->uc_fw_path);
seq_printf(m, "\tfetch: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+ guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 355b647..2bfa86e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1038,7 +1038,7 @@ int intel_guc_suspend(struct drm_device *dev)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
ctx = dev_priv->kernel_context;
@@ -1064,7 +1064,7 @@ int intel_guc_resume(struct drm_device *dev)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
ctx = dev_priv->kernel_context;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 3e3e743..02adcfc 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -90,29 +90,29 @@ struct i915_guc_client {
uint64_t submissions[I915_NUM_ENGINES];
};
-enum intel_guc_fw_status {
- GUC_FIRMWARE_FAIL = -1,
- GUC_FIRMWARE_NONE = 0,
- GUC_FIRMWARE_PENDING,
- GUC_FIRMWARE_SUCCESS
+enum intel_uc_fw_status {
+ UC_FIRMWARE_FAIL = -1,
+ UC_FIRMWARE_NONE = 0,
+ UC_FIRMWARE_PENDING,
+ UC_FIRMWARE_SUCCESS
};
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
*/
-struct intel_guc_fw {
- struct drm_device * guc_dev;
- const char * guc_fw_path;
- size_t guc_fw_size;
- struct drm_i915_gem_object * guc_fw_obj;
- enum intel_guc_fw_status guc_fw_fetch_status;
- enum intel_guc_fw_status guc_fw_load_status;
-
- uint16_t guc_fw_major_wanted;
- uint16_t guc_fw_minor_wanted;
- uint16_t guc_fw_major_found;
- uint16_t guc_fw_minor_found;
+struct intel_uc_fw {
+ struct drm_device *uc_dev;
+ const char *uc_fw_path;
+ size_t uc_fw_size;
+ struct drm_i915_gem_object *uc_fw_obj;
+ enum intel_uc_fw_status fetch_status;
+ enum intel_uc_fw_status load_status;
+
+ uint16_t major_ver_wanted;
+ uint16_t minor_ver_wanted;
+ uint16_t major_ver_found;
+ uint16_t minor_ver_found;
uint32_t header_size;
uint32_t header_offset;
@@ -123,7 +123,7 @@ struct intel_guc_fw {
};
struct intel_guc {
- struct intel_guc_fw guc_fw;
+ struct intel_uc_fw guc_fw;
uint32_t log_flags;
struct drm_i915_gem_object *log_obj;
@@ -152,9 +152,10 @@ struct intel_guc {
extern void intel_guc_init(struct drm_device *dev);
extern int intel_guc_setup(struct drm_device *dev);
extern void intel_guc_fini(struct drm_device *dev);
-extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 4f6311a..1424c42 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -66,16 +66,16 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
/* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
switch (status) {
- case GUC_FIRMWARE_FAIL:
+ case UC_FIRMWARE_FAIL:
return "FAIL";
- case GUC_FIRMWARE_NONE:
+ case UC_FIRMWARE_NONE:
return "NONE";
- case GUC_FIRMWARE_PENDING:
+ case UC_FIRMWARE_PENDING:
return "PENDING";
- case GUC_FIRMWARE_SUCCESS:
+ case UC_FIRMWARE_SUCCESS:
return "SUCCESS";
default:
return "UNKNOWN!";
@@ -237,8 +237,8 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
*/
static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
- struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct drm_i915_gem_object *fw_obj = guc_fw->uc_fw_obj;
unsigned long offset;
struct sg_table *sg = fw_obj->pages;
u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
@@ -310,17 +310,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
*/
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
struct drm_device *dev = dev_priv->dev;
int ret;
- ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
+ ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
if (ret) {
DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
return ret;
}
- ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
+ ret = i915_gem_obj_ggtt_pin(guc_fw->uc_fw_obj, 0, 0);
if (ret) {
DRM_DEBUG_DRIVER("pin failed %d\n", ret);
return ret;
@@ -372,7 +372,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
* We keep the object pages for reuse during resume. But we can unpin it
* now that DMA has completed, so it doesn't continue to take up space.
*/
- i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
+ i915_gem_object_ggtt_unpin(guc_fw->uc_fw_obj);
return ret;
}
@@ -411,14 +411,14 @@ static int i915_reset_guc(struct drm_i915_private *dev_priv)
int intel_guc_setup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
- const char *fw_path = guc_fw->guc_fw_path;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ const char *fw_path = guc_fw->uc_fw_path;
int retries, ret, err;
DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
fw_path,
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
/* Loading forbidden, or no firmware to load? */
if (!i915.enable_guc_loading) {
@@ -436,21 +436,21 @@ int intel_guc_setup(struct drm_device *dev)
}
/* Fetch failed, or already fetched but failed to load? */
- if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
+ if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
err = -EIO;
goto fail;
- } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
+ } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
err = -ENOEXEC;
goto fail;
}
direct_interrupts_to_host(dev_priv);
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+ guc_fw->load_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
err = i915_guc_submission_init(dev_priv);
if (err)
@@ -484,11 +484,11 @@ int intel_guc_setup(struct drm_device *dev)
"retry %d more time(s)\n", err, retries);
}
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
+ guc_fw->load_status = UC_FIRMWARE_SUCCESS;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
if (i915.enable_guc_submission) {
err = i915_guc_submission_enable(dev_priv);
@@ -500,8 +500,8 @@ int intel_guc_setup(struct drm_device *dev)
return 0;
fail:
- if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
+ if (guc_fw->load_status == UC_FIRMWARE_PENDING)
+ guc_fw->load_status = UC_FIRMWARE_FAIL;
direct_interrupts_to_host(dev_priv);
i915_guc_submission_disable(dev_priv);
@@ -546,7 +546,7 @@ fail:
return ret;
}
-static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
{
struct drm_i915_gem_object *obj;
const struct firmware *fw;
@@ -555,16 +555,16 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
int err;
DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ intel_uc_fw_status_repr(uc_fw->fetch_status));
- err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
+ err = request_firmware(&fw, uc_fw->uc_fw_path, &dev->pdev->dev);
if (err)
goto fail;
if (!fw)
goto fail;
DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
- guc_fw->guc_fw_path, fw);
+ uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
if (fw->size < sizeof(struct guc_css_header)) {
@@ -575,36 +575,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
css = (struct guc_css_header *)fw->data;
/* Firmware bits always start from header */
- guc_fw->header_offset = 0;
- guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+ uc_fw->header_offset = 0;
+ uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct guc_css_header)) {
DRM_ERROR("CSS header definition mismatch\n");
goto fail;
}
/* then, uCode */
- guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
- guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+ uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
+ uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
/* now RSA */
if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
DRM_ERROR("RSA key size is bad\n");
goto fail;
}
- guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
- guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+ uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
+ uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
/* At least, it should have header, uCode and RSA. Size of all three. */
- size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+ size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
if (fw->size < size) {
DRM_ERROR("Missing firmware components\n");
goto fail;
}
/* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = guc_fw->header_size + guc_fw->ucode_size;
+ size = uc_fw->header_size + uc_fw->ucode_size;
if (size > guc_wopcm_size(dev->dev_private)) {
DRM_ERROR("Firmware is too large to fit in WOPCM\n");
goto fail;
@@ -616,21 +616,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
- guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
- if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
- guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
+ if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
+ uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
err = -ENOEXEC;
goto fail;
}
DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
mutex_lock(&dev->struct_mutex);
obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
@@ -640,31 +640,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
goto fail;
}
- guc_fw->guc_fw_obj = obj;
- guc_fw->guc_fw_size = fw->size;
+ uc_fw->uc_fw_obj = obj;
+ uc_fw->uc_fw_size = fw->size;
DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
- guc_fw->guc_fw_obj);
+ uc_fw->uc_fw_obj);
release_firmware(fw);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
+ uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
return;
fail:
DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
- err, fw, guc_fw->guc_fw_obj);
+ err, fw, uc_fw->uc_fw_obj);
DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
- guc_fw->guc_fw_path, err);
+ uc_fw->uc_fw_path, err);
mutex_lock(&dev->struct_mutex);
- obj = guc_fw->guc_fw_obj;
+ obj = uc_fw->uc_fw_obj;
if (obj)
drm_gem_object_unreference(&obj->base);
- guc_fw->guc_fw_obj = NULL;
+ uc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
release_firmware(fw); /* OK even if fw is NULL */
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+ uc_fw->fetch_status = UC_FIRMWARE_FAIL;
}
/**
@@ -679,7 +679,7 @@ fail:
void intel_guc_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
const char *fw_path;
/* A negative value means "use platform default" */
@@ -692,20 +692,20 @@ void intel_guc_init(struct drm_device *dev)
fw_path = NULL;
} else if (IS_SKYLAKE(dev)) {
fw_path = I915_SKL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = 6;
- guc_fw->guc_fw_minor_wanted = 1;
+ guc_fw->major_ver_wanted = 6;
+ guc_fw->minor_ver_wanted = 1;
} else if (IS_BROXTON(dev)) {
fw_path = I915_BXT_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = 8;
- guc_fw->guc_fw_minor_wanted = 7;
+ guc_fw->major_ver_wanted = 8;
+ guc_fw->minor_ver_wanted = 7;
} else {
fw_path = ""; /* unknown device */
}
- guc_fw->guc_dev = dev;
- guc_fw->guc_fw_path = fw_path;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
+ guc_fw->uc_dev = dev;
+ guc_fw->uc_fw_path = fw_path;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
+ guc_fw->load_status = UC_FIRMWARE_NONE;
/* Early (and silent) return if GuC loading is disabled */
if (!i915.enable_guc_loading)
@@ -715,9 +715,9 @@ void intel_guc_init(struct drm_device *dev)
if (*fw_path == '\0')
return;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
+ guc_fw->fetch_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
- guc_fw_fetch(dev, guc_fw);
+ intel_uc_fw_fetch(dev, guc_fw);
/* status must now be FAIL or SUCCESS */
}
@@ -728,17 +728,17 @@ void intel_guc_init(struct drm_device *dev)
void intel_guc_fini(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
mutex_lock(&dev->struct_mutex);
direct_interrupts_to_host(dev_priv);
i915_guc_submission_disable(dev_priv);
i915_guc_submission_fini(dev_priv);
- if (guc_fw->guc_fw_obj)
- drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
- guc_fw->guc_fw_obj = NULL;
+ if (guc_fw->uc_fw_obj)
+ drm_gem_object_unreference(&guc_fw->uc_fw_obj->base);
+ guc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
2016-07-01 13:15 ` [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general Peter Antoine
@ 2016-07-01 13:15 ` Peter Antoine
2016-07-01 13:15 ` [PATCH v2 3/6] drm/i915/huc: Add HuC fw loading support Peter Antoine
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Peter Antoine @ 2016-07-01 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.
v2: rebased on-top of drn-intel-nightly
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/intel_guc.h | 4 ++++
drivers/gpu/drm/i915/intel_guc_fwif.h | 16 ++++++++++---
drivers/gpu/drm/i915/intel_guc_loader.c | 40 ++++++++++++++++++++++-----------
3 files changed, 44 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 02adcfc..ebf9c8d 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -97,6 +97,9 @@ enum intel_uc_fw_status {
UC_FIRMWARE_SUCCESS
};
+#define UC_FW_TYPE_GUC 0
+#define UC_FW_TYPE_HUC 1
+
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
@@ -114,6 +117,7 @@ struct intel_uc_fw {
uint16_t major_ver_found;
uint16_t minor_ver_found;
+ uint32_t fw_type;
uint32_t header_size;
uint32_t header_offset;
uint32_t rsa_size;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 944786d..a69ee36 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -154,7 +154,7 @@
* The GuC firmware layout looks like this:
*
* +-------------------------------+
- * | guc_css_header |
+ * | uc_css_header |
* | contains major/minor version |
* +-------------------------------+
* | uCode |
@@ -180,9 +180,16 @@
* 3. Length info of each component can be found in header, in dwords.
* 4. Modulus and exponent key are not required by driver. They may not appear
* in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
*/
-struct guc_css_header {
+struct uc_css_header {
uint32_t module_type;
/* header_size includes all non-uCode bits, including css_header, rsa
* key, modulus key and exponent data. */
@@ -213,7 +220,10 @@ struct guc_css_header {
char username[8];
char buildnumber[12];
- uint32_t device_id;
+ union {
+ uint32_t device_id;
+ uint32_t huc_sw_version;
+ };
uint32_t guc_sw_version;
uint32_t prod_preprod_fw;
uint32_t reserved[12];
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 1424c42..3e8e17a 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -550,7 +550,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
{
struct drm_i915_gem_object *obj;
const struct firmware *fw;
- struct guc_css_header *css;
+ struct uc_css_header *css;
size_t size;
int err;
@@ -567,19 +567,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
- if (fw->size < sizeof(struct guc_css_header)) {
+ if (fw->size < sizeof(struct uc_css_header)) {
DRM_ERROR("Firmware header is missing\n");
goto fail;
}
- css = (struct guc_css_header *)fw->data;
+ css = (struct uc_css_header *)fw->data;
/* Firmware bits always start from header */
uc_fw->header_offset = 0;
uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct uc_css_header)) {
DRM_ERROR("CSS header definition mismatch\n");
goto fail;
}
@@ -603,21 +603,35 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
goto fail;
}
- /* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = uc_fw->header_size + uc_fw->ucode_size;
- if (size > guc_wopcm_size(dev->dev_private)) {
- DRM_ERROR("Firmware is too large to fit in WOPCM\n");
- goto fail;
- }
-
/*
* The GuC firmware image has the version number embedded at a well-known
* offset within the firmware blob; note that major / minor version are
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- uc_fw->major_ver_found = css->guc_sw_version >> 16;
- uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ switch (uc_fw->fw_type) {
+ case UC_FW_TYPE_GUC:
+ /* Header and uCode will be loaded to WOPCM. Size of the two. */
+ size = uc_fw->header_size + uc_fw->ucode_size;
+
+ /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
+ if (size > guc_wopcm_size(dev->dev_private)) {
+ DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+ goto fail;
+ }
+
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ break;
+ case UC_FW_TYPE_HUC:
+ uc_fw->major_ver_found = css->huc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
+ break;
+ default:
+ DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+ err = -ENOEXEC;
+ goto fail;
+ }
if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/6] drm/i915/huc: Add HuC fw loading support
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
2016-07-01 13:15 ` [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general Peter Antoine
2016-07-01 13:15 ` [PATCH v2 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC Peter Antoine
@ 2016-07-01 13:15 ` Peter Antoine
2016-07-01 13:15 ` [PATCH v2 4/6] drm/i915/huc: Add debugfs for HuC loading status check Peter Antoine
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Peter Antoine @ 2016-07-01 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 26 ++--
drivers/gpu/drm/i915/intel_huc.h | 44 ++++++
drivers/gpu/drm/i915/intel_huc_loader.c | 267 ++++++++++++++++++++++++++++++++
8 files changed, 336 insertions(+), 12 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a3d2b78..32af66e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -45,6 +45,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_guc_loader.o \
+ intel_huc_loader.o \
i915_guc_submission.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c580e24..ae5093a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -639,6 +639,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
* working irqs for e.g. gmbus and dp aux transfers. */
intel_modeset_init(dev);
+ intel_huc_init(dev);
intel_guc_init(dev);
ret = i915_gem_init(dev);
@@ -664,6 +665,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
cleanup_gem:
i915_gem_fini(dev);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1714,6 +1716,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
flush_workqueue(dev_priv->wq);
+ intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 485ab11..783934e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,6 +55,7 @@
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
#include "intel_guc.h"
+#include "intel_huc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
@@ -1754,6 +1755,7 @@ struct drm_i915_private {
struct intel_gvt gvt;
+ struct intel_huc huc;
struct intel_guc guc;
struct intel_csr csr;
@@ -2851,6 +2853,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
#define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
+#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
INTEL_INFO(dev)->gen >= 8)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index cf5a65b..51533f1 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
#define DMA_ADDRESS_SPACE_GTT (8 << 16)
#define DMA_COPY_SIZE _MMIO(0xc310)
#define DMA_CTRL _MMIO(0xc314)
+#define HUC_UKERNEL (1<<9)
#define UOS_MOVE (1<<4)
#define START_DMA (1<<0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
+#define HUC_LOADING_AGENT_VCR (0<<1)
+#define HUC_LOADING_AGENT_GUC (1<<1)
#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index ebf9c8d..c7b2745 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -160,6 +160,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 3e8e17a..c7206d8 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -82,6 +82,17 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
}
};
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+{
+ u32 wopcm_size = GUC_WOPCM_TOP;
+
+ /* On BXT, the top of WOPCM is reserved for RC6 context */
+ if (IS_BROXTON(dev_priv))
+ wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
+
+ return wopcm_size;
+}
+
static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
@@ -269,7 +280,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/* Finally start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
+ _MASKED_BIT_DISABLE(HUC_UKERNEL));
/*
* Wait for the DMA to complete & the GuC to start up.
@@ -294,17 +306,6 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
return ret;
}
-static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
-{
- u32 wopcm_size = GUC_WOPCM_TOP;
-
- /* On BXT, the top of WOPCM is reserved for RC6 context */
- if (IS_BROXTON(dev_priv))
- wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
-
- return wopcm_size;
-}
-
/*
* Load the GuC firmware blob into the MinuteIA.
*/
@@ -473,6 +474,7 @@ int intel_guc_setup(struct drm_device *dev)
goto fail;
}
+ intel_huc_load(dev);
err = guc_ucode_xfer(dev_priv);
if (!err)
break;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
new file mode 100644
index 0000000..946caa7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_HUC_H_
+#define _INTEL_HUC_H_
+
+#include "intel_guc.h"
+
+#define HUC_STATUS2 _MMIO(0xD3B0)
+#define HUC_FW_VERIFIED (1<<7)
+
+struct intel_huc {
+ /* Generic uC firmware management */
+ struct intel_uc_fw huc_fw;
+
+ /* HuC-specific additions */
+};
+
+extern void intel_huc_init(struct drm_device *dev);
+extern int intel_huc_load(struct drm_device *dev);
+extern void intel_huc_auth(struct drm_device *dev);
+extern void intel_huc_fini(struct drm_device *dev);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
new file mode 100644
index 0000000..98ef8df
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_huc.h"
+
+/**
+ * DOC: HuC Firmware
+ *
+ * Motivation:
+ * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ *
+ * Implementation:
+ * On supported platforms, i915's job is to load the firmware stored on the
+ * file system and assist with authentication. It is up to userspace to
+ * detect the presence of HuC support on a platform, on their own.
+ * For debugging, i915 provides a debugfs file, i915_huc_load_status_info
+ * which displays the firmware load status.
+ *
+ * The unified uC firmware loader is used. Firmware binary is fetched by the
+ * loader asynchronously from the driver init process. However, the actual
+ * loading to HW is deferred until GEM initialization is done. Be note that HuC
+ * firmware loading must be done before GuC loading.
+ */
+
+#define I915_SKL_HUC_UCODE "i915/skl_huc_ver1_7.bin"
+MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+
+/**
+ * intel_huc_load_ucode() - DMA's the firmware
+ * @dev: the drm device
+ *
+ * This function takes the gem object containing the firmware, sets up the DMA
+ * engine MMIO, triggers the DMA operation and waits for it to finish.
+ *
+ * Transfer the firmware image to RAM for execution by the microcontroller.
+ *
+ * Return: 0 on success, non-zero on failure
+ */
+
+static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
+{
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ unsigned long offset = 0;
+ u32 size;
+ int ret;
+
+ ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
+ if (ret) {
+ DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
+ return ret;
+ }
+
+ ret = i915_gem_obj_ggtt_pin(huc_fw->uc_fw_obj, 0, 0);
+ if (ret) {
+ DRM_DEBUG_DRIVER("pin failed %d\n", ret);
+ return ret;
+ }
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* init WOPCM */
+ I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
+ I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
+ HUC_LOADING_AGENT_GUC);
+
+ /* Set the source address for the uCode */
+ offset = i915_gem_obj_ggtt_offset(huc_fw->uc_fw_obj) +
+ huc_fw->header_offset;
+ I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
+ I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+
+ /* Hardware doesn't look at destination address for HuC. Set it to 0,
+ * but still program the correct address space.
+ */
+ I915_WRITE(DMA_ADDR_1_LOW, 0);
+ I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+
+ size = huc_fw->header_size + huc_fw->ucode_size;
+ I915_WRITE(DMA_COPY_SIZE, size);
+
+ /* Start the DMA */
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
+
+ /* Wait for DMA to finish */
+ ret = wait_for_atomic((I915_READ(DMA_CTRL) & START_DMA) == 0, 50);
+
+ DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ /*
+ * We keep the object pages for reuse during resume. But we can unpin it
+ * now that DMA has completed, so it doesn't continue to take up space.
+ */
+ i915_gem_object_ggtt_unpin(huc_fw->uc_fw_obj);
+
+ return ret;
+}
+
+/**
+ * intel_huc_init() - initiate HuC firmware loading request
+ * @dev: the drm device
+ *
+ * Called early during driver load, but after GEM is initialised. The loading
+ * will continue only when driver explicitly specify firmware name and version.
+ * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
+ * capable or driver yet support it. And there will be no error message for
+ * UC_FIRMWARE_NONE cases.
+ *
+ * The DMA-copying to HW is done later when intel_huc_ucode_load() is called.
+ */
+void intel_huc_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_huc *huc = &dev_priv->huc;
+ struct intel_uc_fw *huc_fw = &huc->huc_fw;
+ const char *fw_path = NULL;
+
+ huc_fw->uc_dev = dev;
+ huc_fw->uc_fw_path = NULL;
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+ huc_fw->load_status = UC_FIRMWARE_NONE;
+ huc_fw->fw_type = UC_FW_TYPE_HUC;
+
+ if (!HAS_HUC_UCODE(dev_priv))
+ return;
+
+ if (IS_SKYLAKE(dev_priv)) {
+ fw_path = I915_SKL_HUC_UCODE;
+ huc_fw->major_ver_wanted = 1;
+ huc_fw->minor_ver_wanted = 7;
+ }
+
+ if (fw_path == NULL)
+ return;
+
+ huc_fw->uc_fw_path = fw_path;
+ huc_fw->fetch_status = UC_FIRMWARE_PENDING;
+
+ DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
+
+ intel_uc_fw_fetch(dev, huc_fw);
+}
+
+/**
+ * intel_huc_load() - load HuC uCode to device
+ * @dev: the drm device
+ *
+ * Called from gem_init_hw() during driver loading and also after a GPU reset.
+ * Be note that HuC loading must be done before GuC loading.
+ *
+ * The firmware image should have already been fetched into memory by the
+ * earlier call to intel_huc_ucode_init(), so here we need only check that
+ * is succeeded, and then transfer the image to the h/w.
+ *
+ * Return: non-zero code on error
+ */
+int intel_huc_load(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ int err;
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
+ return 0;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
+ huc_fw->load_status == UC_FIRMWARE_FAIL)
+ return -ENOEXEC;
+
+ huc_fw->load_status = UC_FIRMWARE_PENDING;
+
+ switch (huc_fw->fetch_status) {
+ case UC_FIRMWARE_FAIL:
+ /* something went wrong :( */
+ err = -EIO;
+ goto fail;
+
+ case UC_FIRMWARE_NONE:
+ case UC_FIRMWARE_PENDING:
+ default:
+ /* "can't happen" */
+ WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ huc_fw->fetch_status);
+ err = -ENXIO;
+ goto fail;
+
+ case UC_FIRMWARE_SUCCESS:
+ break;
+ }
+
+ err = huc_ucode_xfer(dev_priv);
+ if (err)
+ goto fail;
+
+ huc_fw->load_status = UC_FIRMWARE_SUCCESS;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ return 0;
+
+fail:
+ if (huc_fw->load_status == UC_FIRMWARE_PENDING)
+ huc_fw->load_status = UC_FIRMWARE_FAIL;
+
+ DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
+
+ return err;
+}
+
+/**
+ * intel_huc_fini() - clean up resources allocated for HuC
+ * @dev: the drm device
+ *
+ * Cleans up by releasing the huc firmware GEM obj.
+ */
+void intel_huc_fini(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ mutex_lock(&dev->struct_mutex);
+ if (huc_fw->uc_fw_obj)
+ drm_gem_object_unreference(&huc_fw->uc_fw_obj->base);
+ huc_fw->uc_fw_obj = NULL;
+ mutex_unlock(&dev->struct_mutex);
+
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/6] drm/i915/huc: Add debugfs for HuC loading status check
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
` (2 preceding siblings ...)
2016-07-01 13:15 ` [PATCH v2 3/6] drm/i915/huc: Add HuC fw loading support Peter Antoine
@ 2016-07-01 13:15 ` Peter Antoine
2016-07-01 13:15 ` [PATCH v2 5/6] drm/i915/huc: Support HuC authentication Peter Antoine
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Peter Antoine @ 2016-07-01 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Add debugfs entry for HuC loading status check.
v2: rebase on-top of drm-intel-nightly.
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3883df5..c1f92e2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2479,6 +2479,37 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
}
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ if (!HAS_HUC_UCODE(dev_priv->dev))
+ return 0;
+
+ seq_puts(m, "HuC firmware status:\n");
+ seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+ seq_printf(m, "\tfetch: %s\n",
+ intel_uc_fw_status_repr(huc_fw->fetch_status));
+ seq_printf(m, "\tload: %s\n",
+ intel_uc_fw_status_repr(huc_fw->load_status));
+ seq_printf(m, "\tversion wanted: %d.%d\n",
+ huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+ seq_printf(m, "\tversion found: %d.%d\n",
+ huc_fw->major_ver_found, huc_fw->minor_ver_found);
+ seq_printf(m, "\theader: offset is %d; size = %d\n",
+ huc_fw->header_offset, huc_fw->header_size);
+ seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+ huc_fw->ucode_offset, huc_fw->ucode_size);
+ seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+ huc_fw->rsa_offset, huc_fw->rsa_size);
+
+ seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+ return 0;
+}
+
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
@@ -5433,6 +5464,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 5/6] drm/i915/huc: Support HuC authentication
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
` (3 preceding siblings ...)
2016-07-01 13:15 ` [PATCH v2 4/6] drm/i915/huc: Add debugfs for HuC loading status check Peter Antoine
@ 2016-07-01 13:15 ` Peter Antoine
2016-07-01 13:15 ` [PATCH v2 6/6] drm/i915/huc: Add BXT HuC Loading Support Peter Antoine
2016-07-01 14:04 ` ✗ Ro.CI.BAT: warning for HuC Loading Patches (rev2) Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Peter Antoine @ 2016-07-01 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 65 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +
3 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 2bfa86e..3bb8c25 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -25,6 +25,7 @@
#include <linux/circ_buf.h>
#include "i915_drv.h"
#include "intel_guc.h"
+#include "intel_huc.h"
/**
* DOC: GuC-based command submission
@@ -1076,3 +1077,67 @@ int intel_guc_resume(struct drm_device *dev)
return host2guc_action(guc, data, ARRAY_SIZE(data));
}
+
+/**
+ * intel_huc_auth() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_huc_auth(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_guc *guc = &dev_priv->guc;
+ struct intel_huc *huc = &dev_priv->huc;
+ int ret;
+ u32 data[2];
+
+ /* Bypass the case where there is no HuC firmware */
+ if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+ huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+ return;
+
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+ return;
+ }
+
+ if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+ return;
+ }
+
+ ret = i915_gem_obj_ggtt_pin(huc->huc_fw.uc_fw_obj, 0, 0);
+ if (ret) {
+ DRM_ERROR("HuC: Pin failed");
+ return;
+ }
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ /* Specify auth action and where public signature is. It's stored
+ * at the beginning of the gem object, before the fw bits
+ */
+ data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
+ data[1] = i915_gem_obj_ggtt_offset(huc->huc_fw.uc_fw_obj) +
+ huc->huc_fw.rsa_offset;
+
+ ret = host2guc_action(guc, data, ARRAY_SIZE(data));
+ if (ret) {
+ DRM_ERROR("HuC: GuC did not ack Auth request\n");
+ goto out;
+ }
+
+ /* Check authentication status, it should be done by now */
+ ret = wait_for_atomic(
+ (I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+ if (ret) {
+ DRM_ERROR("HuC: Authentication failed\n");
+ goto out;
+ }
+
+out:
+ i915_gem_object_ggtt_unpin(huc->huc_fw.uc_fw_obj);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index a69ee36..c5a6227 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -437,6 +437,7 @@ enum host2guc_action {
HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
+ HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
HOST2GUC_ACTION_LIMIT
};
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index c7206d8..7d085fb 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -492,6 +492,8 @@ int intel_guc_setup(struct drm_device *dev)
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
+ intel_huc_auth(dev);
+
if (i915.enable_guc_submission) {
err = i915_guc_submission_enable(dev_priv);
if (err)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 6/6] drm/i915/huc: Add BXT HuC Loading Support
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
` (4 preceding siblings ...)
2016-07-01 13:15 ` [PATCH v2 5/6] drm/i915/huc: Support HuC authentication Peter Antoine
@ 2016-07-01 13:15 ` Peter Antoine
2016-07-01 14:04 ` ✗ Ro.CI.BAT: warning for HuC Loading Patches (rev2) Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Peter Antoine @ 2016-07-01 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
This patch adds the HuC Loading for the BXT.
Version 1.7 of the HuC firmware.
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 98ef8df..23df639 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -49,6 +49,9 @@
#define I915_SKL_HUC_UCODE "i915/skl_huc_ver1_7.bin"
MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver1_7.bin"
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
/**
* intel_huc_load_ucode() - DMA's the firmware
* @dev: the drm device
@@ -157,6 +160,10 @@ void intel_huc_init(struct drm_device *dev)
fw_path = I915_SKL_HUC_UCODE;
huc_fw->major_ver_wanted = 1;
huc_fw->minor_ver_wanted = 7;
+ } else if (IS_BROXTON(dev_priv)) {
+ fw_path = I915_BXT_HUC_UCODE;
+ huc_fw->major_ver_wanted = 1;
+ huc_fw->minor_ver_wanted = 7;
}
if (fw_path == NULL)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Ro.CI.BAT: warning for HuC Loading Patches (rev2)
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
` (5 preceding siblings ...)
2016-07-01 13:15 ` [PATCH v2 6/6] drm/i915/huc: Add BXT HuC Loading Support Peter Antoine
@ 2016-07-01 14:04 ` Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2016-07-01 14:04 UTC (permalink / raw)
To: Peter Antoine; +Cc: intel-gfx
== Series Details ==
Series: HuC Loading Patches (rev2)
URL : https://patchwork.freedesktop.org/series/9011/
State : warning
== Summary ==
Series 9011v2 HuC Loading Patches
http://patchwork.freedesktop.org/api/1.0/series/9011/revisions/2/mbox
Test drv_hangman:
Subgroup error-state-basic:
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Test drv_module_reload_basic:
pass -> DMESG-WARN (ro-byt-n2820)
pass -> DMESG-WARN (ro-bdw-i7-5600u)
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
fail -> PASS (ro-byt-n2820)
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Test gem_ringfill:
Subgroup basic-default-hang:
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Subgroup hang-read-crc-pipe-b:
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Subgroup hang-read-crc-pipe-c:
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> SKIP (ro-bdw-i5-5250u)
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Subgroup suspend-read-crc-pipe-b:
pass -> SKIP (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (fi-skl-i5-6260u)
pass -> DMESG-WARN (fi-skl-i7-6700k)
fi-hsw-i7-4770k total:229 pass:196 dwarn:0 dfail:0 fail:0 skip:33
fi-kbl-qkkr total:229 pass:161 dwarn:28 dfail:1 fail:0 skip:39
fi-skl-i5-6260u total:229 pass:194 dwarn:9 dfail:0 fail:0 skip:26
fi-skl-i7-6700k total:229 pass:180 dwarn:10 dfail:0 fail:0 skip:39
fi-snb-i7-2600 total:229 pass:176 dwarn:0 dfail:0 fail:0 skip:53
ro-bdw-i5-5250u total:229 pass:204 dwarn:2 dfail:1 fail:0 skip:22
ro-bdw-i7-5557U total:229 pass:204 dwarn:1 dfail:1 fail:0 skip:23
ro-bdw-i7-5600u total:229 pass:189 dwarn:1 dfail:1 fail:0 skip:38
ro-byt-n2820 total:229 pass:180 dwarn:1 dfail:1 fail:2 skip:45
ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31
ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31
ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70
ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65
ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40
ro-skl3-i5-6260u total:229 pass:208 dwarn:1 dfail:1 fail:0 skip:19
ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48
ro-bsw-n3050 failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1360/
8f8910b drm-intel-nightly: 2016y-07m-01d-11h-59m-32s UTC integration manifest
a3e90b6 drm/i915/huc: Add BXT HuC Loading Support
3c8f963 drm/i915/huc: Support HuC authentication
b889fbd drm/i915/huc: Add debugfs for HuC loading status check
cf95443 drm/i915/huc: Add HuC fw loading support
a9dada1 drm/i915/huc: Unified css_header struct for GuC and HuC
f0188e1 drm/i915/guc: Make the GuC fw loading helper functions general
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general
2016-07-01 13:15 ` [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general Peter Antoine
@ 2016-07-05 14:44 ` Dave Gordon
0 siblings, 0 replies; 11+ messages in thread
From: Dave Gordon @ 2016-07-05 14:44 UTC (permalink / raw)
To: Peter Antoine, intel-gfx; +Cc: Alex Dai, rodrigo.vivi
On 01/07/16 14:15, Peter Antoine wrote:
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
> s/intel_guc_fw/intel_uc_fw/g
> s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> v2: rebased on top of nightly.
> reapplied the search/replace as upstream code as changed.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
This didn't apply cleanly, so it will need rebasing (again), but it's
only a simple conflict with recent patches. Apart from that, its OK now, so:
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
(which you can carry over to the rebased version).
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
> drivers/gpu/drm/i915/intel_guc.h | 39 ++++----
> drivers/gpu/drm/i915/intel_guc_loader.c | 142 ++++++++++++++---------------
> 4 files changed, 99 insertions(+), 98 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index f664884..3883df5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2483,7 +2483,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_info_node *node = m->private;
> struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> u32 tmp, i;
>
> if (!HAS_GUC_UCODE(dev_priv))
> @@ -2491,15 +2491,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
>
> seq_printf(m, "GuC firmware status:\n");
> seq_printf(m, "\tpath: %s\n",
> - guc_fw->guc_fw_path);
> + guc_fw->uc_fw_path);
> seq_printf(m, "\tfetch: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status));
> seq_printf(m, "\tload: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->load_status));
> seq_printf(m, "\tversion wanted: %d.%d\n",
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> seq_printf(m, "\tversion found: %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> seq_printf(m, "\theader: offset is %d; size = %d\n",
> guc_fw->header_offset, guc_fw->header_size);
> seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 355b647..2bfa86e 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1038,7 +1038,7 @@ int intel_guc_suspend(struct drm_device *dev)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> ctx = dev_priv->kernel_context;
> @@ -1064,7 +1064,7 @@ int intel_guc_resume(struct drm_device *dev)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> ctx = dev_priv->kernel_context;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 3e3e743..02adcfc 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -90,29 +90,29 @@ struct i915_guc_client {
> uint64_t submissions[I915_NUM_ENGINES];
> };
>
> -enum intel_guc_fw_status {
> - GUC_FIRMWARE_FAIL = -1,
> - GUC_FIRMWARE_NONE = 0,
> - GUC_FIRMWARE_PENDING,
> - GUC_FIRMWARE_SUCCESS
> +enum intel_uc_fw_status {
> + UC_FIRMWARE_FAIL = -1,
> + UC_FIRMWARE_NONE = 0,
> + UC_FIRMWARE_PENDING,
> + UC_FIRMWARE_SUCCESS
> };
>
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> */
> -struct intel_guc_fw {
> - struct drm_device * guc_dev;
> - const char * guc_fw_path;
> - size_t guc_fw_size;
> - struct drm_i915_gem_object * guc_fw_obj;
> - enum intel_guc_fw_status guc_fw_fetch_status;
> - enum intel_guc_fw_status guc_fw_load_status;
> -
> - uint16_t guc_fw_major_wanted;
> - uint16_t guc_fw_minor_wanted;
> - uint16_t guc_fw_major_found;
> - uint16_t guc_fw_minor_found;
> +struct intel_uc_fw {
> + struct drm_device *uc_dev;
> + const char *uc_fw_path;
> + size_t uc_fw_size;
> + struct drm_i915_gem_object *uc_fw_obj;
> + enum intel_uc_fw_status fetch_status;
> + enum intel_uc_fw_status load_status;
> +
> + uint16_t major_ver_wanted;
> + uint16_t minor_ver_wanted;
> + uint16_t major_ver_found;
> + uint16_t minor_ver_found;
>
> uint32_t header_size;
> uint32_t header_offset;
> @@ -123,7 +123,7 @@ struct intel_guc_fw {
> };
>
> struct intel_guc {
> - struct intel_guc_fw guc_fw;
> + struct intel_uc_fw guc_fw;
> uint32_t log_flags;
> struct drm_i915_gem_object *log_obj;
>
> @@ -152,9 +152,10 @@ struct intel_guc {
> extern void intel_guc_init(struct drm_device *dev);
> extern int intel_guc_setup(struct drm_device *dev);
> extern void intel_guc_fini(struct drm_device *dev);
> -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_device *dev);
> extern int intel_guc_resume(struct drm_device *dev);
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 4f6311a..1424c42 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -66,16 +66,16 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
> MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
>
> /* User-friendly representation of an enum */
> -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> {
> switch (status) {
> - case GUC_FIRMWARE_FAIL:
> + case UC_FIRMWARE_FAIL:
> return "FAIL";
> - case GUC_FIRMWARE_NONE:
> + case UC_FIRMWARE_NONE:
> return "NONE";
> - case GUC_FIRMWARE_PENDING:
> + case UC_FIRMWARE_PENDING:
> return "PENDING";
> - case GUC_FIRMWARE_SUCCESS:
> + case UC_FIRMWARE_SUCCESS:
> return "SUCCESS";
> default:
> return "UNKNOWN!";
> @@ -237,8 +237,8 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> */
> static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct drm_i915_gem_object *fw_obj = guc_fw->uc_fw_obj;
> unsigned long offset;
> struct sg_table *sg = fw_obj->pages;
> u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> @@ -310,17 +310,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> */
> static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> struct drm_device *dev = dev_priv->dev;
> int ret;
>
> - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
> if (ret) {
> DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> return ret;
> }
>
> - ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
> + ret = i915_gem_obj_ggtt_pin(guc_fw->uc_fw_obj, 0, 0);
> if (ret) {
> DRM_DEBUG_DRIVER("pin failed %d\n", ret);
> return ret;
> @@ -372,7 +372,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> * We keep the object pages for reuse during resume. But we can unpin it
> * now that DMA has completed, so it doesn't continue to take up space.
> */
> - i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
> + i915_gem_object_ggtt_unpin(guc_fw->uc_fw_obj);
>
> return ret;
> }
> @@ -411,14 +411,14 @@ static int i915_reset_guc(struct drm_i915_private *dev_priv)
> int intel_guc_setup(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - const char *fw_path = guc_fw->guc_fw_path;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + const char *fw_path = guc_fw->uc_fw_path;
> int retries, ret, err;
>
> DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
> fw_path,
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> /* Loading forbidden, or no firmware to load? */
> if (!i915.enable_guc_loading) {
> @@ -436,21 +436,21 @@ int intel_guc_setup(struct drm_device *dev)
> }
>
> /* Fetch failed, or already fetched but failed to load? */
> - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
> err = -EIO;
> goto fail;
> - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
> err = -ENOEXEC;
> goto fail;
> }
>
> direct_interrupts_to_host(dev_priv);
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> + guc_fw->load_status = UC_FIRMWARE_PENDING;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> err = i915_guc_submission_init(dev_priv);
> if (err)
> @@ -484,11 +484,11 @@ int intel_guc_setup(struct drm_device *dev)
> "retry %d more time(s)\n", err, retries);
> }
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> if (i915.enable_guc_submission) {
> err = i915_guc_submission_enable(dev_priv);
> @@ -500,8 +500,8 @@ int intel_guc_setup(struct drm_device *dev)
> return 0;
>
> fail:
> - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> + guc_fw->load_status = UC_FIRMWARE_FAIL;
>
> direct_interrupts_to_host(dev_priv);
> i915_guc_submission_disable(dev_priv);
> @@ -546,7 +546,7 @@ fail:
> return ret;
> }
>
> -static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> {
> struct drm_i915_gem_object *obj;
> const struct firmware *fw;
> @@ -555,16 +555,16 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> int err;
>
> DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + intel_uc_fw_status_repr(uc_fw->fetch_status));
>
> - err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
> + err = request_firmware(&fw, uc_fw->uc_fw_path, &dev->pdev->dev);
> if (err)
> goto fail;
> if (!fw)
> goto fail;
>
> DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> - guc_fw->guc_fw_path, fw);
> + uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> if (fw->size < sizeof(struct guc_css_header)) {
> @@ -575,36 +575,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> css = (struct guc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> - guc_fw->header_offset = 0;
> - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> + uc_fw->header_offset = 0;
> + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> DRM_ERROR("CSS header definition mismatch\n");
> goto fail;
> }
>
> /* then, uCode */
> - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>
> /* now RSA */
> if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> DRM_ERROR("RSA key size is bad\n");
> goto fail;
> }
> - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>
> /* At least, it should have header, uCode and RSA. Size of all three. */
> - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
> if (fw->size < size) {
> DRM_ERROR("Missing firmware components\n");
> goto fail;
> }
>
> /* Header and uCode will be loaded to WOPCM. Size of the two. */
> - size = guc_fw->header_size + guc_fw->ucode_size;
> + size = uc_fw->header_size + uc_fw->ucode_size;
> if (size > guc_wopcm_size(dev->dev_private)) {
> DRM_ERROR("Firmware is too large to fit in WOPCM\n");
> goto fail;
> @@ -616,21 +616,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> * in terms of bytes (u8).
> */
> - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>
> - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> err = -ENOEXEC;
> goto fail;
> }
>
> DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>
> mutex_lock(&dev->struct_mutex);
> obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
> @@ -640,31 +640,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> goto fail;
> }
>
> - guc_fw->guc_fw_obj = obj;
> - guc_fw->guc_fw_size = fw->size;
> + uc_fw->uc_fw_obj = obj;
> + uc_fw->uc_fw_size = fw->size;
>
> DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> - guc_fw->guc_fw_obj);
> + uc_fw->uc_fw_obj);
>
> release_firmware(fw);
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> return;
>
> fail:
> DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> - err, fw, guc_fw->guc_fw_obj);
> + err, fw, uc_fw->uc_fw_obj);
> DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
> - guc_fw->guc_fw_path, err);
> + uc_fw->uc_fw_path, err);
>
> mutex_lock(&dev->struct_mutex);
> - obj = guc_fw->guc_fw_obj;
> + obj = uc_fw->uc_fw_obj;
> if (obj)
> drm_gem_object_unreference(&obj->base);
> - guc_fw->guc_fw_obj = NULL;
> + uc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> release_firmware(fw); /* OK even if fw is NULL */
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> }
>
> /**
> @@ -679,7 +679,7 @@ fail:
> void intel_guc_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> const char *fw_path;
>
> /* A negative value means "use platform default" */
> @@ -692,20 +692,20 @@ void intel_guc_init(struct drm_device *dev)
> fw_path = NULL;
> } else if (IS_SKYLAKE(dev)) {
> fw_path = I915_SKL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = 6;
> - guc_fw->guc_fw_minor_wanted = 1;
> + guc_fw->major_ver_wanted = 6;
> + guc_fw->minor_ver_wanted = 1;
> } else if (IS_BROXTON(dev)) {
> fw_path = I915_BXT_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = 8;
> - guc_fw->guc_fw_minor_wanted = 7;
> + guc_fw->major_ver_wanted = 8;
> + guc_fw->minor_ver_wanted = 7;
> } else {
> fw_path = ""; /* unknown device */
> }
>
> - guc_fw->guc_dev = dev;
> - guc_fw->guc_fw_path = fw_path;
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> + guc_fw->uc_dev = dev;
> + guc_fw->uc_fw_path = fw_path;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> + guc_fw->load_status = UC_FIRMWARE_NONE;
>
> /* Early (and silent) return if GuC loading is disabled */
> if (!i915.enable_guc_loading)
> @@ -715,9 +715,9 @@ void intel_guc_init(struct drm_device *dev)
> if (*fw_path == '\0')
> return;
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> - guc_fw_fetch(dev, guc_fw);
> + intel_uc_fw_fetch(dev, guc_fw);
> /* status must now be FAIL or SUCCESS */
> }
>
> @@ -728,17 +728,17 @@ void intel_guc_init(struct drm_device *dev)
> void intel_guc_fini(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>
> mutex_lock(&dev->struct_mutex);
> direct_interrupts_to_host(dev_priv);
> i915_guc_submission_disable(dev_priv);
> i915_guc_submission_fini(dev_priv);
>
> - if (guc_fw->guc_fw_obj)
> - drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
> - guc_fw->guc_fw_obj = NULL;
> + if (guc_fw->uc_fw_obj)
> + drm_gem_object_unreference(&guc_fw->uc_fw_obj->base);
> + guc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general
2016-02-08 23:02 ` [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general yu.dai
@ 2016-02-16 15:37 ` Daniel Vetter
0 siblings, 0 replies; 11+ messages in thread
From: Daniel Vetter @ 2016-02-16 15:37 UTC (permalink / raw)
To: yu.dai; +Cc: intel-gfx
On Mon, Feb 08, 2016 at 03:02:48PM -0800, yu.dai@intel.com wrote:
> From: Alex Dai <yu.dai@intel.com>
>
> Rename some of the GuC fw loading code to make them more general. We
> will utilize them for HuC loading as well.
> s/intel_guc_fw/intel_uc_fw/g
> s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
I still don't see what this firmware loader wrapper around the mainline
firmware loader provide. It has a complicated status matrix for one, that
doesn't really seem to be required - either the firmware is there or not.
All that *_status stuff seems unecessary to me.
Can we instead just reduce this? And then use plain old firmware loader
like for dmc, maybe with a small convenience function that loads it into a
gem bo. In case of doubt I think open-coding using a set of helpers (to
load firmware, throw it into a gem obj and then just use core gem function
to bind the vma somewhere) is much better.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> drivers/gpu/drm/i915/intel_guc.h | 39 +++----
> drivers/gpu/drm/i915/intel_guc_loader.c | 177 +++++++++++++++++---------------
> 3 files changed, 120 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ec0c2a05e..873f1b2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2402,7 +2402,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_info_node *node = m->private;
> struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> u32 tmp, i;
>
> if (!HAS_GUC_UCODE(dev_priv->dev))
> @@ -2410,15 +2410,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
>
> seq_printf(m, "GuC firmware status:\n");
> seq_printf(m, "\tpath: %s\n",
> - guc_fw->guc_fw_path);
> + guc_fw->uc_fw_path);
> seq_printf(m, "\tfetch: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status));
> seq_printf(m, "\tload: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->load_status));
> seq_printf(m, "\tversion wanted: %d.%d\n",
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> seq_printf(m, "\tversion found: %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> seq_printf(m, "\theader: offset is %d; size = %d\n",
> guc_fw->header_offset, guc_fw->header_size);
> seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 73002e9..4e20b0c 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -52,29 +52,29 @@ struct i915_guc_client {
> int retcode;
> };
>
> -enum intel_guc_fw_status {
> - GUC_FIRMWARE_FAIL = -1,
> - GUC_FIRMWARE_NONE = 0,
> - GUC_FIRMWARE_PENDING,
> - GUC_FIRMWARE_SUCCESS
> +enum intel_uc_fw_status {
> + UC_FIRMWARE_FAIL = -1,
> + UC_FIRMWARE_NONE = 0,
> + UC_FIRMWARE_PENDING,
> + UC_FIRMWARE_SUCCESS
> };
>
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> */
> -struct intel_guc_fw {
> - struct drm_device * guc_dev;
> - const char * guc_fw_path;
> - size_t guc_fw_size;
> - struct drm_i915_gem_object * guc_fw_obj;
> - enum intel_guc_fw_status guc_fw_fetch_status;
> - enum intel_guc_fw_status guc_fw_load_status;
> -
> - uint16_t guc_fw_major_wanted;
> - uint16_t guc_fw_minor_wanted;
> - uint16_t guc_fw_major_found;
> - uint16_t guc_fw_minor_found;
> +struct intel_uc_fw {
> + struct drm_device * uc_dev;
> + const char * uc_fw_path;
> + size_t uc_fw_size;
> + struct drm_i915_gem_object * uc_fw_obj;
> + enum intel_uc_fw_status fetch_status;
> + enum intel_uc_fw_status load_status;
> +
> + uint16_t major_ver_wanted;
> + uint16_t minor_ver_wanted;
> + uint16_t major_ver_found;
> + uint16_t minor_ver_found;
>
> uint32_t header_size;
> uint32_t header_offset;
> @@ -85,7 +85,7 @@ struct intel_guc_fw {
> };
>
> struct intel_guc {
> - struct intel_guc_fw guc_fw;
> + struct intel_uc_fw guc_fw;
> uint32_t log_flags;
> struct drm_i915_gem_object *log_obj;
>
> @@ -114,9 +114,10 @@ struct intel_guc {
> extern void intel_guc_ucode_init(struct drm_device *dev);
> extern int intel_guc_ucode_load(struct drm_device *dev);
> extern void intel_guc_ucode_fini(struct drm_device *dev);
> -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_device *dev);
> extern int intel_guc_resume(struct drm_device *dev);
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 3accd91..318b5fd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -63,16 +63,16 @@
> MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
>
> /* User-friendly representation of an enum */
> -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> {
> switch (status) {
> - case GUC_FIRMWARE_FAIL:
> + case UC_FIRMWARE_FAIL:
> return "FAIL";
> - case GUC_FIRMWARE_NONE:
> + case UC_FIRMWARE_NONE:
> return "NONE";
> - case GUC_FIRMWARE_PENDING:
> + case UC_FIRMWARE_PENDING:
> return "PENDING";
> - case GUC_FIRMWARE_SUCCESS:
> + case UC_FIRMWARE_SUCCESS:
> return "SUCCESS";
> default:
> return "UNKNOWN!";
> @@ -224,8 +224,8 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> */
> static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct drm_i915_gem_object *fw_obj = guc_fw->uc_fw_obj;
> unsigned long offset;
> struct sg_table *sg = fw_obj->pages;
> u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> @@ -286,17 +286,17 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
> */
> static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> struct drm_device *dev = dev_priv->dev;
> int ret;
>
> - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
> if (ret) {
> DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> return ret;
> }
>
> - ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
> + ret = i915_gem_obj_ggtt_pin(guc_fw->uc_fw_obj, 0, 0);
> if (ret) {
> DRM_DEBUG_DRIVER("pin failed %d\n", ret);
> return ret;
> @@ -348,7 +348,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> * We keep the object pages for reuse during resume. But we can unpin it
> * now that DMA has completed, so it doesn't continue to take up space.
> */
> - i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
> + i915_gem_object_ggtt_unpin(guc_fw->uc_fw_obj);
>
> return ret;
> }
> @@ -368,48 +368,48 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> int intel_guc_ucode_load(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> int err = 0;
>
> if (!i915.enable_guc_submission)
> return 0;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> direct_interrupts_to_host(dev_priv);
>
> - if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
> + if (guc_fw->fetch_status == UC_FIRMWARE_NONE)
> return 0;
>
> - if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
> - guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
> + if (guc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> + guc_fw->load_status == UC_FIRMWARE_FAIL)
> return -ENOEXEC;
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> + guc_fw->load_status = UC_FIRMWARE_PENDING;
>
> DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status));
>
> - switch (guc_fw->guc_fw_fetch_status) {
> - case GUC_FIRMWARE_FAIL:
> + switch (guc_fw->fetch_status) {
> + case UC_FIRMWARE_FAIL:
> /* something went wrong :( */
> err = -EIO;
> goto fail;
>
> - case GUC_FIRMWARE_NONE:
> - case GUC_FIRMWARE_PENDING:
> + case UC_FIRMWARE_NONE:
> + case UC_FIRMWARE_PENDING:
> default:
> /* "can't happen" */
> - WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
> - guc_fw->guc_fw_path,
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - guc_fw->guc_fw_fetch_status);
> + WARN_ONCE(1, "GuC fw %s invalid fetch_status %s [%d]\n",
> + guc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + guc_fw->fetch_status);
> err = -ENXIO;
> goto fail;
>
> - case GUC_FIRMWARE_SUCCESS:
> + case UC_FIRMWARE_SUCCESS:
> break;
> }
>
> @@ -421,11 +421,11 @@ int intel_guc_ucode_load(struct drm_device *dev)
> if (err)
> goto fail;
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> if (i915.enable_guc_submission) {
> /* The execbuf_client will be recreated. Release it first. */
> @@ -440,8 +440,8 @@ int intel_guc_ucode_load(struct drm_device *dev)
> return 0;
>
> fail:
> - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> + guc_fw->load_status = UC_FIRMWARE_FAIL;
>
> direct_interrupts_to_host(dev_priv);
> i915_guc_submission_disable(dev);
> @@ -450,7 +450,18 @@ fail:
> return err;
> }
>
> -static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> +/**
> + * intel_uc_fw_fetch() - fetch fw blob and save it to internal obj
> + * @dev: drm device
> + * @uc_fw: the intel_uc_fw to be setup
> + *
> + * The caller should have setup fw path and fw version required. This function
> + * first fetch the fw blob from file system. If succeed, it will do some basic
> + * check based on css header information. At last, a GEM obj is created and
> + * filled with the fw data. This obj will be loaded to HW at later stage of
> + * driver init process.
> + */
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> {
> struct drm_i915_gem_object *obj;
> const struct firmware *fw;
> @@ -458,17 +469,17 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> size_t size;
> int err;
>
> - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
> + intel_uc_fw_status_repr(uc_fw->fetch_status));
>
> - err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
> + err = request_firmware(&fw, uc_fw->uc_fw_path, &dev->pdev->dev);
> if (err)
> goto fail;
> if (!fw)
> goto fail;
>
> - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> - guc_fw->guc_fw_path, fw);
> + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> + uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> if (fw->size < sizeof(struct guc_css_header)) {
> @@ -479,36 +490,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> css = (struct guc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> - guc_fw->header_offset = 0;
> - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> + uc_fw->header_offset = 0;
> + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> DRM_ERROR("CSS header definition mismatch\n");
> goto fail;
> }
>
> /* then, uCode */
> - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>
> /* now RSA */
> if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> DRM_ERROR("RSA key size is bad\n");
> goto fail;
> }
> - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>
> /* At least, it should have header, uCode and RSA. Size of all three. */
> - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
> if (fw->size < size) {
> DRM_ERROR("Missing firmware components\n");
> goto fail;
> }
>
> /* Header and uCode will be loaded to WOPCM. Size of the two. */
> - size = guc_fw->header_size + guc_fw->ucode_size;
> + size = uc_fw->header_size + uc_fw->ucode_size;
>
> /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
> if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) {
> @@ -517,26 +528,26 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> }
>
> /*
> - * The GuC firmware image has the version number embedded at a well-known
> + * The uC firmware image has the version number embedded at a well-known
> * offset within the firmware blob; note that major / minor version are
> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> * in terms of bytes (u8).
> */
> - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> -
> - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> - DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> +
> + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> + DRM_ERROR("Firmware version %d.%d, required %d.%d\n",
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> err = -ENOEXEC;
> goto fail;
> }
>
> DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>
> mutex_lock(&dev->struct_mutex);
> obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
> @@ -546,31 +557,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> goto fail;
> }
>
> - guc_fw->guc_fw_obj = obj;
> - guc_fw->guc_fw_size = fw->size;
> + uc_fw->uc_fw_obj = obj;
> + uc_fw->uc_fw_size = fw->size;
>
> DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> - guc_fw->guc_fw_obj);
> + uc_fw->uc_fw_obj);
>
> release_firmware(fw);
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> return;
>
> fail:
> DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> - err, fw, guc_fw->guc_fw_obj);
> + err, fw, uc_fw->uc_fw_obj);
> DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
> - guc_fw->guc_fw_path, err);
> + uc_fw->uc_fw_path, err);
>
> mutex_lock(&dev->struct_mutex);
> - obj = guc_fw->guc_fw_obj;
> + obj = uc_fw->uc_fw_obj;
> if (obj)
> drm_gem_object_unreference(&obj->base);
> - guc_fw->guc_fw_obj = NULL;
> + uc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> release_firmware(fw); /* OK even if fw is NULL */
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> }
>
> /**
> @@ -585,7 +596,7 @@ fail:
> void intel_guc_ucode_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> const char *fw_path;
>
> if (!HAS_GUC_SCHED(dev))
> @@ -595,8 +606,8 @@ void intel_guc_ucode_init(struct drm_device *dev)
> fw_path = NULL;
> } else if (IS_SKYLAKE(dev)) {
> fw_path = I915_SKL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = 4;
> - guc_fw->guc_fw_minor_wanted = 3;
> + guc_fw->major_ver_wanted = 4;
> + guc_fw->minor_ver_wanted = 3;
> } else {
> i915.enable_guc_submission = false;
> fw_path = ""; /* unknown device */
> @@ -605,23 +616,23 @@ void intel_guc_ucode_init(struct drm_device *dev)
> if (!i915.enable_guc_submission)
> return;
>
> - guc_fw->guc_dev = dev;
> - guc_fw->guc_fw_path = fw_path;
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> + guc_fw->uc_dev = dev;
> + guc_fw->uc_fw_path = fw_path;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> + guc_fw->load_status = UC_FIRMWARE_NONE;
>
> if (fw_path == NULL)
> return;
>
> if (*fw_path == '\0') {
> DRM_ERROR("No GuC firmware known for this platform\n");
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> + guc_fw->fetch_status = UC_FIRMWARE_FAIL;
> return;
> }
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> - guc_fw_fetch(dev, guc_fw);
> + intel_uc_fw_fetch(dev, guc_fw);
> /* status must now be FAIL or SUCCESS */
> }
>
> @@ -632,17 +643,17 @@ void intel_guc_ucode_init(struct drm_device *dev)
> void intel_guc_ucode_fini(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>
> mutex_lock(&dev->struct_mutex);
> direct_interrupts_to_host(dev_priv);
> i915_guc_submission_disable(dev);
> i915_guc_submission_fini(dev);
>
> - if (guc_fw->guc_fw_obj)
> - drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
> - guc_fw->guc_fw_obj = NULL;
> + if (guc_fw->uc_fw_obj)
> + drm_gem_object_unreference(&guc_fw->uc_fw_obj->base);
> + guc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general
2016-02-08 23:02 [PATCH v2 0/6] Add HuC loading and authentication support yu.dai
@ 2016-02-08 23:02 ` yu.dai
2016-02-16 15:37 ` Daniel Vetter
0 siblings, 1 reply; 11+ messages in thread
From: yu.dai @ 2016-02-08 23:02 UTC (permalink / raw)
To: intel-gfx
From: Alex Dai <yu.dai@intel.com>
Rename some of the GuC fw loading code to make them more general. We
will utilize them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/intel_guc.h | 39 +++----
drivers/gpu/drm/i915/intel_guc_loader.c | 177 +++++++++++++++++---------------
3 files changed, 120 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ec0c2a05e..873f1b2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2402,7 +2402,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
u32 tmp, i;
if (!HAS_GUC_UCODE(dev_priv->dev))
@@ -2410,15 +2410,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
- guc_fw->guc_fw_path);
+ guc_fw->uc_fw_path);
seq_printf(m, "\tfetch: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+ guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 73002e9..4e20b0c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -52,29 +52,29 @@ struct i915_guc_client {
int retcode;
};
-enum intel_guc_fw_status {
- GUC_FIRMWARE_FAIL = -1,
- GUC_FIRMWARE_NONE = 0,
- GUC_FIRMWARE_PENDING,
- GUC_FIRMWARE_SUCCESS
+enum intel_uc_fw_status {
+ UC_FIRMWARE_FAIL = -1,
+ UC_FIRMWARE_NONE = 0,
+ UC_FIRMWARE_PENDING,
+ UC_FIRMWARE_SUCCESS
};
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
*/
-struct intel_guc_fw {
- struct drm_device * guc_dev;
- const char * guc_fw_path;
- size_t guc_fw_size;
- struct drm_i915_gem_object * guc_fw_obj;
- enum intel_guc_fw_status guc_fw_fetch_status;
- enum intel_guc_fw_status guc_fw_load_status;
-
- uint16_t guc_fw_major_wanted;
- uint16_t guc_fw_minor_wanted;
- uint16_t guc_fw_major_found;
- uint16_t guc_fw_minor_found;
+struct intel_uc_fw {
+ struct drm_device * uc_dev;
+ const char * uc_fw_path;
+ size_t uc_fw_size;
+ struct drm_i915_gem_object * uc_fw_obj;
+ enum intel_uc_fw_status fetch_status;
+ enum intel_uc_fw_status load_status;
+
+ uint16_t major_ver_wanted;
+ uint16_t minor_ver_wanted;
+ uint16_t major_ver_found;
+ uint16_t minor_ver_found;
uint32_t header_size;
uint32_t header_offset;
@@ -85,7 +85,7 @@ struct intel_guc_fw {
};
struct intel_guc {
- struct intel_guc_fw guc_fw;
+ struct intel_uc_fw guc_fw;
uint32_t log_flags;
struct drm_i915_gem_object *log_obj;
@@ -114,9 +114,10 @@ struct intel_guc {
extern void intel_guc_ucode_init(struct drm_device *dev);
extern int intel_guc_ucode_load(struct drm_device *dev);
extern void intel_guc_ucode_fini(struct drm_device *dev);
-extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 3accd91..318b5fd 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -63,16 +63,16 @@
MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
/* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
switch (status) {
- case GUC_FIRMWARE_FAIL:
+ case UC_FIRMWARE_FAIL:
return "FAIL";
- case GUC_FIRMWARE_NONE:
+ case UC_FIRMWARE_NONE:
return "NONE";
- case GUC_FIRMWARE_PENDING:
+ case UC_FIRMWARE_PENDING:
return "PENDING";
- case GUC_FIRMWARE_SUCCESS:
+ case UC_FIRMWARE_SUCCESS:
return "SUCCESS";
default:
return "UNKNOWN!";
@@ -224,8 +224,8 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
*/
static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
- struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct drm_i915_gem_object *fw_obj = guc_fw->uc_fw_obj;
unsigned long offset;
struct sg_table *sg = fw_obj->pages;
u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
@@ -286,17 +286,17 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
*/
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
struct drm_device *dev = dev_priv->dev;
int ret;
- ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
+ ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
if (ret) {
DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
return ret;
}
- ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
+ ret = i915_gem_obj_ggtt_pin(guc_fw->uc_fw_obj, 0, 0);
if (ret) {
DRM_DEBUG_DRIVER("pin failed %d\n", ret);
return ret;
@@ -348,7 +348,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
* We keep the object pages for reuse during resume. But we can unpin it
* now that DMA has completed, so it doesn't continue to take up space.
*/
- i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
+ i915_gem_object_ggtt_unpin(guc_fw->uc_fw_obj);
return ret;
}
@@ -368,48 +368,48 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
int intel_guc_ucode_load(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
int err = 0;
if (!i915.enable_guc_submission)
return 0;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
direct_interrupts_to_host(dev_priv);
- if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
+ if (guc_fw->fetch_status == UC_FIRMWARE_NONE)
return 0;
- if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
- guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
+ if (guc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
+ guc_fw->load_status == UC_FIRMWARE_FAIL)
return -ENOEXEC;
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+ guc_fw->load_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status));
- switch (guc_fw->guc_fw_fetch_status) {
- case GUC_FIRMWARE_FAIL:
+ switch (guc_fw->fetch_status) {
+ case UC_FIRMWARE_FAIL:
/* something went wrong :( */
err = -EIO;
goto fail;
- case GUC_FIRMWARE_NONE:
- case GUC_FIRMWARE_PENDING:
+ case UC_FIRMWARE_NONE:
+ case UC_FIRMWARE_PENDING:
default:
/* "can't happen" */
- WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
- guc_fw->guc_fw_path,
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- guc_fw->guc_fw_fetch_status);
+ WARN_ONCE(1, "GuC fw %s invalid fetch_status %s [%d]\n",
+ guc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ guc_fw->fetch_status);
err = -ENXIO;
goto fail;
- case GUC_FIRMWARE_SUCCESS:
+ case UC_FIRMWARE_SUCCESS:
break;
}
@@ -421,11 +421,11 @@ int intel_guc_ucode_load(struct drm_device *dev)
if (err)
goto fail;
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
+ guc_fw->load_status = UC_FIRMWARE_SUCCESS;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
if (i915.enable_guc_submission) {
/* The execbuf_client will be recreated. Release it first. */
@@ -440,8 +440,8 @@ int intel_guc_ucode_load(struct drm_device *dev)
return 0;
fail:
- if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
+ if (guc_fw->load_status == UC_FIRMWARE_PENDING)
+ guc_fw->load_status = UC_FIRMWARE_FAIL;
direct_interrupts_to_host(dev_priv);
i915_guc_submission_disable(dev);
@@ -450,7 +450,18 @@ fail:
return err;
}
-static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
+/**
+ * intel_uc_fw_fetch() - fetch fw blob and save it to internal obj
+ * @dev: drm device
+ * @uc_fw: the intel_uc_fw to be setup
+ *
+ * The caller should have setup fw path and fw version required. This function
+ * first fetch the fw blob from file system. If succeed, it will do some basic
+ * check based on css header information. At last, a GEM obj is created and
+ * filled with the fw data. This obj will be loaded to HW at later stage of
+ * driver init process.
+ */
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
{
struct drm_i915_gem_object *obj;
const struct firmware *fw;
@@ -458,17 +469,17 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
size_t size;
int err;
- DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
+ intel_uc_fw_status_repr(uc_fw->fetch_status));
- err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
+ err = request_firmware(&fw, uc_fw->uc_fw_path, &dev->pdev->dev);
if (err)
goto fail;
if (!fw)
goto fail;
- DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
- guc_fw->guc_fw_path, fw);
+ DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
+ uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
if (fw->size < sizeof(struct guc_css_header)) {
@@ -479,36 +490,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
css = (struct guc_css_header *)fw->data;
/* Firmware bits always start from header */
- guc_fw->header_offset = 0;
- guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+ uc_fw->header_offset = 0;
+ uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct guc_css_header)) {
DRM_ERROR("CSS header definition mismatch\n");
goto fail;
}
/* then, uCode */
- guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
- guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+ uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
+ uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
/* now RSA */
if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
DRM_ERROR("RSA key size is bad\n");
goto fail;
}
- guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
- guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+ uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
+ uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
/* At least, it should have header, uCode and RSA. Size of all three. */
- size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+ size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
if (fw->size < size) {
DRM_ERROR("Missing firmware components\n");
goto fail;
}
/* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = guc_fw->header_size + guc_fw->ucode_size;
+ size = uc_fw->header_size + uc_fw->ucode_size;
/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) {
@@ -517,26 +528,26 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
}
/*
- * The GuC firmware image has the version number embedded at a well-known
+ * The uC firmware image has the version number embedded at a well-known
* offset within the firmware blob; note that major / minor version are
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
- guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
-
- if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
- guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
- DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+
+ if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
+ uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
+ DRM_ERROR("Firmware version %d.%d, required %d.%d\n",
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
err = -ENOEXEC;
goto fail;
}
DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
mutex_lock(&dev->struct_mutex);
obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
@@ -546,31 +557,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
goto fail;
}
- guc_fw->guc_fw_obj = obj;
- guc_fw->guc_fw_size = fw->size;
+ uc_fw->uc_fw_obj = obj;
+ uc_fw->uc_fw_size = fw->size;
DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
- guc_fw->guc_fw_obj);
+ uc_fw->uc_fw_obj);
release_firmware(fw);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
+ uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
return;
fail:
DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
- err, fw, guc_fw->guc_fw_obj);
+ err, fw, uc_fw->uc_fw_obj);
DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
- guc_fw->guc_fw_path, err);
+ uc_fw->uc_fw_path, err);
mutex_lock(&dev->struct_mutex);
- obj = guc_fw->guc_fw_obj;
+ obj = uc_fw->uc_fw_obj;
if (obj)
drm_gem_object_unreference(&obj->base);
- guc_fw->guc_fw_obj = NULL;
+ uc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
release_firmware(fw); /* OK even if fw is NULL */
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+ uc_fw->fetch_status = UC_FIRMWARE_FAIL;
}
/**
@@ -585,7 +596,7 @@ fail:
void intel_guc_ucode_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
const char *fw_path;
if (!HAS_GUC_SCHED(dev))
@@ -595,8 +606,8 @@ void intel_guc_ucode_init(struct drm_device *dev)
fw_path = NULL;
} else if (IS_SKYLAKE(dev)) {
fw_path = I915_SKL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = 4;
- guc_fw->guc_fw_minor_wanted = 3;
+ guc_fw->major_ver_wanted = 4;
+ guc_fw->minor_ver_wanted = 3;
} else {
i915.enable_guc_submission = false;
fw_path = ""; /* unknown device */
@@ -605,23 +616,23 @@ void intel_guc_ucode_init(struct drm_device *dev)
if (!i915.enable_guc_submission)
return;
- guc_fw->guc_dev = dev;
- guc_fw->guc_fw_path = fw_path;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
+ guc_fw->uc_dev = dev;
+ guc_fw->uc_fw_path = fw_path;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
+ guc_fw->load_status = UC_FIRMWARE_NONE;
if (fw_path == NULL)
return;
if (*fw_path == '\0') {
DRM_ERROR("No GuC firmware known for this platform\n");
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+ guc_fw->fetch_status = UC_FIRMWARE_FAIL;
return;
}
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
+ guc_fw->fetch_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
- guc_fw_fetch(dev, guc_fw);
+ intel_uc_fw_fetch(dev, guc_fw);
/* status must now be FAIL or SUCCESS */
}
@@ -632,17 +643,17 @@ void intel_guc_ucode_init(struct drm_device *dev)
void intel_guc_ucode_fini(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
mutex_lock(&dev->struct_mutex);
direct_interrupts_to_host(dev_priv);
i915_guc_submission_disable(dev);
i915_guc_submission_fini(dev);
- if (guc_fw->guc_fw_obj)
- drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
- guc_fw->guc_fw_obj = NULL;
+ if (guc_fw->uc_fw_obj)
+ drm_gem_object_unreference(&guc_fw->uc_fw_obj->base);
+ guc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
}
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-07-05 14:44 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-01 13:15 [PATCH v2 0/6] HuC Loading Patches Peter Antoine
2016-07-01 13:15 ` [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general Peter Antoine
2016-07-05 14:44 ` Dave Gordon
2016-07-01 13:15 ` [PATCH v2 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC Peter Antoine
2016-07-01 13:15 ` [PATCH v2 3/6] drm/i915/huc: Add HuC fw loading support Peter Antoine
2016-07-01 13:15 ` [PATCH v2 4/6] drm/i915/huc: Add debugfs for HuC loading status check Peter Antoine
2016-07-01 13:15 ` [PATCH v2 5/6] drm/i915/huc: Support HuC authentication Peter Antoine
2016-07-01 13:15 ` [PATCH v2 6/6] drm/i915/huc: Add BXT HuC Loading Support Peter Antoine
2016-07-01 14:04 ` ✗ Ro.CI.BAT: warning for HuC Loading Patches (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2016-02-08 23:02 [PATCH v2 0/6] Add HuC loading and authentication support yu.dai
2016-02-08 23:02 ` [PATCH v2 1/6] drm/i915/guc: Make the GuC fw loading helper functions general yu.dai
2016-02-16 15:37 ` Daniel Vetter
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