[PATCH v3 1/6] drm/i915/guc: Make the GuC fw loading helper functions general

[PATCH v3 1/6] drm/i915/guc: Make the GuC fw loading helper functions general

[Peter Antoine]

Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
     s/intel_guc_fw/intel_uc_fw/g
     s/GUC_FIRMWARE/UC_FIRMWARE/g

Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.

v2: rebased on top of nightly.
    reapplied the search/replace as upstream code as changed.
v3: rebased again on drm-nightly.

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc.h           |  39 ++++----
 drivers/gpu/drm/i915/intel_guc_loader.c    | 146 ++++++++++++++---------------
 4 files changed, 101 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3d05cae..9a6deff 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2498,7 +2498,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
 	struct drm_info_node *node = m->private;
 	struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	u32 tmp, i;
 
 	if (!HAS_GUC_UCODE(dev_priv))
@@ -2506,15 +2506,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
 
 	seq_printf(m, "GuC firmware status:\n");
 	seq_printf(m, "\tpath: %s\n",
-		guc_fw->guc_fw_path);
+		guc_fw->uc_fw_path);
 	seq_printf(m, "\tfetch: %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status));
 	seq_printf(m, "\tload: %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->load_status));
 	seq_printf(m, "\tversion wanted: %d.%d\n",
-		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+		guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
 	seq_printf(m, "\tversion found: %d.%d\n",
-		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+		guc_fw->major_ver_found, guc_fw->minor_ver_found);
 	seq_printf(m, "\theader: offset is %d; size = %d\n",
 		guc_fw->header_offset, guc_fw->header_size);
 	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index bfc8bf6..5f88500 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1038,7 +1038,7 @@ int intel_guc_suspend(struct drm_device *dev)
 	struct i915_gem_context *ctx;
 	u32 data[3];
 
-	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
 		return 0;
 
 	ctx = dev_priv->kernel_context;
@@ -1064,7 +1064,7 @@ int intel_guc_resume(struct drm_device *dev)
 	struct i915_gem_context *ctx;
 	u32 data[3];
 
-	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
 		return 0;
 
 	ctx = dev_priv->kernel_context;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 3e3e743..02adcfc 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -90,29 +90,29 @@ struct i915_guc_client {
 	uint64_t submissions[I915_NUM_ENGINES];
 };
 
-enum intel_guc_fw_status {
-	GUC_FIRMWARE_FAIL = -1,
-	GUC_FIRMWARE_NONE = 0,
-	GUC_FIRMWARE_PENDING,
-	GUC_FIRMWARE_SUCCESS
+enum intel_uc_fw_status {
+	UC_FIRMWARE_FAIL = -1,
+	UC_FIRMWARE_NONE = 0,
+	UC_FIRMWARE_PENDING,
+	UC_FIRMWARE_SUCCESS
 };
 
 /*
  * This structure encapsulates all the data needed during the process
  * of fetching, caching, and loading the firmware image into the GuC.
  */
-struct intel_guc_fw {
-	struct drm_device *		guc_dev;
-	const char *			guc_fw_path;
-	size_t				guc_fw_size;
-	struct drm_i915_gem_object *	guc_fw_obj;
-	enum intel_guc_fw_status	guc_fw_fetch_status;
-	enum intel_guc_fw_status	guc_fw_load_status;
-
-	uint16_t			guc_fw_major_wanted;
-	uint16_t			guc_fw_minor_wanted;
-	uint16_t			guc_fw_major_found;
-	uint16_t			guc_fw_minor_found;
+struct intel_uc_fw {
+	struct drm_device *uc_dev;
+	const char *uc_fw_path;
+	size_t uc_fw_size;
+	struct drm_i915_gem_object *uc_fw_obj;
+	enum intel_uc_fw_status fetch_status;
+	enum intel_uc_fw_status load_status;
+
+	uint16_t major_ver_wanted;
+	uint16_t minor_ver_wanted;
+	uint16_t major_ver_found;
+	uint16_t minor_ver_found;
 
 	uint32_t header_size;
 	uint32_t header_offset;
@@ -123,7 +123,7 @@ struct intel_guc_fw {
 };
 
 struct intel_guc {
-	struct intel_guc_fw guc_fw;
+	struct intel_uc_fw guc_fw;
 	uint32_t log_flags;
 	struct drm_i915_gem_object *log_obj;
 
@@ -152,9 +152,10 @@ struct intel_guc {
 extern void intel_guc_init(struct drm_device *dev);
 extern int intel_guc_setup(struct drm_device *dev);
 extern void intel_guc_fini(struct drm_device *dev);
-extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
 extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
 
 /* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 605c696..1afa49b 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -69,16 +69,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
 /* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
 	switch (status) {
-	case GUC_FIRMWARE_FAIL:
+	case UC_FIRMWARE_FAIL:
 		return "FAIL";
-	case GUC_FIRMWARE_NONE:
+	case UC_FIRMWARE_NONE:
 		return "NONE";
-	case GUC_FIRMWARE_PENDING:
+	case UC_FIRMWARE_PENDING:
 		return "PENDING";
-	case GUC_FIRMWARE_SUCCESS:
+	case UC_FIRMWARE_SUCCESS:
 		return "SUCCESS";
 	default:
 		return "UNKNOWN!";
@@ -240,8 +240,8 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
  */
 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 {
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
-	struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct drm_i915_gem_object *fw_obj = guc_fw->uc_fw_obj;
 	unsigned long offset;
 	struct sg_table *sg = fw_obj->pages;
 	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
@@ -313,17 +313,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
  */
 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 {
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	struct drm_device *dev = &dev_priv->drm;
 	int ret;
 
-	ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
+	ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
 	if (ret) {
 		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 		return ret;
 	}
 
-	ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
+	ret = i915_gem_obj_ggtt_pin(guc_fw->uc_fw_obj, 0, 0);
 	if (ret) {
 		DRM_DEBUG_DRIVER("pin failed %d\n", ret);
 		return ret;
@@ -375,7 +375,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	 * We keep the object pages for reuse during resume. But we can unpin it
 	 * now that DMA has completed, so it doesn't continue to take up space.
 	 */
-	i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
+	i915_gem_object_ggtt_unpin(guc_fw->uc_fw_obj);
 
 	return ret;
 }
@@ -414,14 +414,14 @@ static int i915_reset_guc(struct drm_i915_private *dev_priv)
 int intel_guc_setup(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
-	const char *fw_path = guc_fw->guc_fw_path;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	const char *fw_path = guc_fw->uc_fw_path;
 	int retries, ret, err;
 
 	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 		fw_path,
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status),
+		intel_uc_fw_status_repr(guc_fw->load_status));
 
 	/* Loading forbidden, or no firmware to load? */
 	if (!i915.enable_guc_loading) {
@@ -439,21 +439,21 @@ int intel_guc_setup(struct drm_device *dev)
 	}
 
 	/* Fetch failed, or already fetched but failed to load? */
-	if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
+	if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
 		err = -EIO;
 		goto fail;
-	} else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
+	} else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
 		err = -ENOEXEC;
 		goto fail;
 	}
 
 	direct_interrupts_to_host(dev_priv);
 
-	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+	guc_fw->load_status = UC_FIRMWARE_PENDING;
 
 	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status),
+		intel_uc_fw_status_repr(guc_fw->load_status));
 
 	err = i915_guc_submission_init(dev_priv);
 	if (err)
@@ -487,11 +487,11 @@ int intel_guc_setup(struct drm_device *dev)
 			 "retry %d more time(s)\n", err, retries);
 	}
 
-	guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
+	guc_fw->load_status = UC_FIRMWARE_SUCCESS;
 
 	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status),
+		intel_uc_fw_status_repr(guc_fw->load_status));
 
 	if (i915.enable_guc_submission) {
 		err = i915_guc_submission_enable(dev_priv);
@@ -503,8 +503,8 @@ int intel_guc_setup(struct drm_device *dev)
 	return 0;
 
 fail:
-	if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
-		guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
+	if (guc_fw->load_status == UC_FIRMWARE_PENDING)
+		guc_fw->load_status = UC_FIRMWARE_FAIL;
 
 	direct_interrupts_to_host(dev_priv);
 	i915_guc_submission_disable(dev_priv);
@@ -549,7 +549,7 @@ fail:
 	return ret;
 }
 
-static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 {
 	struct drm_i915_gem_object *obj;
 	const struct firmware *fw;
@@ -558,16 +558,16 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 	int err;
 
 	DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+		intel_uc_fw_status_repr(uc_fw->fetch_status));
 
-	err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
+	err = request_firmware(&fw, uc_fw->uc_fw_path, &dev->pdev->dev);
 	if (err)
 		goto fail;
 	if (!fw)
 		goto fail;
 
 	DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
-		guc_fw->guc_fw_path, fw);
+		uc_fw->uc_fw_path, fw);
 
 	/* Check the size of the blob before examining buffer contents */
 	if (fw->size < sizeof(struct guc_css_header)) {
@@ -578,36 +578,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 	css = (struct guc_css_header *)fw->data;
 
 	/* Firmware bits always start from header */
-	guc_fw->header_offset = 0;
-	guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+	uc_fw->header_offset = 0;
+	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
-	if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
 		DRM_ERROR("CSS header definition mismatch\n");
 		goto fail;
 	}
 
 	/* then, uCode */
-	guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
-	guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
+	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 
 	/* now RSA */
 	if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 		DRM_ERROR("RSA key size is bad\n");
 		goto fail;
 	}
-	guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
-	guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+	uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
+	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 
 	/* At least, it should have header, uCode and RSA. Size of all three. */
-	size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+	size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
 	if (fw->size < size) {
 		DRM_ERROR("Missing firmware components\n");
 		goto fail;
 	}
 
 	/* Header and uCode will be loaded to WOPCM. Size of the two. */
-	size = guc_fw->header_size + guc_fw->ucode_size;
+	size = uc_fw->header_size + uc_fw->ucode_size;
 	if (size > guc_wopcm_size(to_i915(dev))) {
 		DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 		goto fail;
@@ -619,21 +619,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 	 * in terms of bytes (u8).
 	 */
-	guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
-	guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
+	uc_fw->major_ver_found = css->guc_sw_version >> 16;
+	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
 
-	if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
-	    guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
+	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
+	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
 		DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
-			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
-			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+			uc_fw->major_ver_found, uc_fw->minor_ver_found,
+			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 		err = -ENOEXEC;
 		goto fail;
 	}
 
 	DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
-			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
-			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+			uc_fw->major_ver_found, uc_fw->minor_ver_found,
+			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 
 	mutex_lock(&dev->struct_mutex);
 	obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
@@ -643,31 +643,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 		goto fail;
 	}
 
-	guc_fw->guc_fw_obj = obj;
-	guc_fw->guc_fw_size = fw->size;
+	uc_fw->uc_fw_obj = obj;
+	uc_fw->uc_fw_size = fw->size;
 
 	DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
-			guc_fw->guc_fw_obj);
+			uc_fw->uc_fw_obj);
 
 	release_firmware(fw);
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
+	uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
 	return;
 
 fail:
 	DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
-		err, fw, guc_fw->guc_fw_obj);
+		err, fw, uc_fw->uc_fw_obj);
 	DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
-		  guc_fw->guc_fw_path, err);
+		  uc_fw->uc_fw_path, err);
 
 	mutex_lock(&dev->struct_mutex);
-	obj = guc_fw->guc_fw_obj;
+	obj = uc_fw->uc_fw_obj;
 	if (obj)
 		drm_gem_object_unreference(&obj->base);
-	guc_fw->guc_fw_obj = NULL;
+	uc_fw->uc_fw_obj = NULL;
 	mutex_unlock(&dev->struct_mutex);
 
 	release_firmware(fw);		/* OK even if fw is NULL */
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+	uc_fw->fetch_status = UC_FIRMWARE_FAIL;
 }
 
 /**
@@ -682,7 +682,7 @@ fail:
 void intel_guc_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	const char *fw_path;
 
 	/* A negative value means "use platform default" */
@@ -695,24 +695,24 @@ void intel_guc_init(struct drm_device *dev)
 		fw_path = NULL;
 	} else if (IS_SKYLAKE(dev)) {
 		fw_path = I915_SKL_GUC_UCODE;
-		guc_fw->guc_fw_major_wanted = 6;
-		guc_fw->guc_fw_minor_wanted = 1;
+		guc_fw->major_ver_wanted = 6;
+		guc_fw->minor_ver_wanted = 1;
 	} else if (IS_BROXTON(dev)) {
 		fw_path = I915_BXT_GUC_UCODE;
-		guc_fw->guc_fw_major_wanted = 8;
-		guc_fw->guc_fw_minor_wanted = 7;
+		guc_fw->major_ver_wanted = 8;
+		guc_fw->minor_ver_wanted = 7;
 	} else if (IS_KABYLAKE(dev)) {
 		fw_path = I915_KBL_GUC_UCODE;
-		guc_fw->guc_fw_major_wanted = 9;
-		guc_fw->guc_fw_minor_wanted = 14;
+		guc_fw->major_ver_wanted = 9;
+		guc_fw->minor_ver_wanted = 14;
 	} else {
 		fw_path = "";	/* unknown device */
 	}
 
-	guc_fw->guc_dev = dev;
-	guc_fw->guc_fw_path = fw_path;
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
-	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
+	guc_fw->uc_dev = dev;
+	guc_fw->uc_fw_path = fw_path;
+	guc_fw->fetch_status = UC_FIRMWARE_NONE;
+	guc_fw->load_status = UC_FIRMWARE_NONE;
 
 	/* Early (and silent) return if GuC loading is disabled */
 	if (!i915.enable_guc_loading)
@@ -722,9 +722,9 @@ void intel_guc_init(struct drm_device *dev)
 	if (*fw_path == '\0')
 		return;
 
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
+	guc_fw->fetch_status = UC_FIRMWARE_PENDING;
 	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
-	guc_fw_fetch(dev, guc_fw);
+	intel_uc_fw_fetch(dev, guc_fw);
 	/* status must now be FAIL or SUCCESS */
 }
 
@@ -735,17 +735,17 @@ void intel_guc_init(struct drm_device *dev)
 void intel_guc_fini(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
 
 	mutex_lock(&dev->struct_mutex);
 	direct_interrupts_to_host(dev_priv);
 	i915_guc_submission_disable(dev_priv);
 	i915_guc_submission_fini(dev_priv);
 
-	if (guc_fw->guc_fw_obj)
-		drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
-	guc_fw->guc_fw_obj = NULL;
+	if (guc_fw->uc_fw_obj)
+		drm_gem_object_unreference(&guc_fw->uc_fw_obj->base);
+	guc_fw->uc_fw_obj = NULL;
 	mutex_unlock(&dev->struct_mutex);
 
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
+	guc_fw->fetch_status = UC_FIRMWARE_NONE;
 }
-- 
1.9.1

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[PATCH v3 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC

[Peter Antoine]

HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.

v2: rebased on-top of drm-intel-nightly
v3: rebased on-top of drm-intel-nightly (again).

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.h        |  4 ++++
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 16 ++++++++++---
 drivers/gpu/drm/i915/intel_guc_loader.c | 40 ++++++++++++++++++++++-----------
 3 files changed, 44 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 02adcfc..ebf9c8d 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -97,6 +97,9 @@ enum intel_uc_fw_status {
 	UC_FIRMWARE_SUCCESS
 };
 
+#define UC_FW_TYPE_GUC		0
+#define UC_FW_TYPE_HUC		1
+
 /*
  * This structure encapsulates all the data needed during the process
  * of fetching, caching, and loading the firmware image into the GuC.
@@ -114,6 +117,7 @@ struct intel_uc_fw {
 	uint16_t major_ver_found;
 	uint16_t minor_ver_found;
 
+	uint32_t fw_type;
 	uint32_t header_size;
 	uint32_t header_offset;
 	uint32_t rsa_size;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 944786d..a69ee36 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -154,7 +154,7 @@
  * The GuC firmware layout looks like this:
  *
  *     +-------------------------------+
- *     |        guc_css_header         |
+ *     |         uc_css_header         |
  *     | contains major/minor version  |
  *     +-------------------------------+
  *     |             uCode             |
@@ -180,9 +180,16 @@
  * 3. Length info of each component can be found in header, in dwords.
  * 4. Modulus and exponent key are not required by driver. They may not appear
  * in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
  */
 
-struct guc_css_header {
+struct uc_css_header {
 	uint32_t module_type;
 	/* header_size includes all non-uCode bits, including css_header, rsa
 	 * key, modulus key and exponent data. */
@@ -213,7 +220,10 @@ struct guc_css_header {
 
 	char username[8];
 	char buildnumber[12];
-	uint32_t device_id;
+	union {
+		uint32_t device_id;
+		uint32_t huc_sw_version;
+	};
 	uint32_t guc_sw_version;
 	uint32_t prod_preprod_fw;
 	uint32_t reserved[12];
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 1afa49b..42b6509 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -553,7 +553,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 {
 	struct drm_i915_gem_object *obj;
 	const struct firmware *fw;
-	struct guc_css_header *css;
+	struct uc_css_header *css;
 	size_t size;
 	int err;
 
@@ -570,19 +570,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 		uc_fw->uc_fw_path, fw);
 
 	/* Check the size of the blob before examining buffer contents */
-	if (fw->size < sizeof(struct guc_css_header)) {
+	if (fw->size < sizeof(struct uc_css_header)) {
 		DRM_ERROR("Firmware header is missing\n");
 		goto fail;
 	}
 
-	css = (struct guc_css_header *)fw->data;
+	css = (struct uc_css_header *)fw->data;
 
 	/* Firmware bits always start from header */
 	uc_fw->header_offset = 0;
 	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
-	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
 		DRM_ERROR("CSS header definition mismatch\n");
 		goto fail;
 	}
@@ -606,21 +606,35 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 		goto fail;
 	}
 
-	/* Header and uCode will be loaded to WOPCM. Size of the two. */
-	size = uc_fw->header_size + uc_fw->ucode_size;
-	if (size > guc_wopcm_size(to_i915(dev))) {
-		DRM_ERROR("Firmware is too large to fit in WOPCM\n");
-		goto fail;
-	}
-
 	/*
 	 * The GuC firmware image has the version number embedded at a well-known
 	 * offset within the firmware blob; note that major / minor version are
 	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 	 * in terms of bytes (u8).
 	 */
-	uc_fw->major_ver_found = css->guc_sw_version >> 16;
-	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+	switch (uc_fw->fw_type) {
+	case UC_FW_TYPE_GUC:
+		/* Header and uCode will be loaded to WOPCM. Size of the two. */
+		size = uc_fw->header_size + uc_fw->ucode_size;
+
+		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
+		if (size > guc_wopcm_size(to_i915(dev))) {
+			DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+			goto fail;
+		}
+
+		uc_fw->major_ver_found = css->guc_sw_version >> 16;
+		uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+		break;
+	case UC_FW_TYPE_HUC:
+		uc_fw->major_ver_found = css->huc_sw_version >> 16;
+		uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
+		break;
+	default:
+		DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+		err = -ENOEXEC;
+		goto fail;
+	}
 
 	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
 	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
-- 
1.9.1

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[PATCH v3 3/6] drm/i915/huc: Add HuC fw loading support

[Peter Antoine]

The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.

HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.

v2: rebased on-top of drm-intel-nightly.
    removed if(HAS_GUC()) before the guc call. (D.Gordon)
    update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
    match the one in the huc package.
    Changed dev->dev_provate to to_i915()

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/Makefile           |   1 +
 drivers/gpu/drm/i915/i915_drv.c         |   3 +
 drivers/gpu/drm/i915/i915_drv.h         |   3 +
 drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
 drivers/gpu/drm/i915/intel_guc.h        |   1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  26 ++--
 drivers/gpu/drm/i915/intel_huc.h        |  44 ++++++
 drivers/gpu/drm/i915/intel_huc_loader.c | 267 ++++++++++++++++++++++++++++++++
 8 files changed, 336 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.h
 create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 684fc1c..0939b90 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -47,6 +47,7 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
+	  intel_huc_loader.o \
 	  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 694edac..72655bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -645,6 +645,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	 * working irqs for e.g. gmbus and dp aux transfers. */
 	intel_modeset_init(dev);
 
+	intel_huc_init(dev);
 	intel_guc_init(dev);
 
 	ret = i915_gem_init(dev);
@@ -670,6 +671,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 cleanup_gem:
 	i915_gem_fini(dev);
 cleanup_irq:
+	intel_huc_fini(dev);
 	intel_guc_fini(dev);
 	drm_irq_uninstall(dev);
 	intel_teardown_gmbus(dev);
@@ -1341,6 +1343,7 @@ void i915_driver_unload(struct drm_device *dev)
 	/* Flush any outstanding unpin_work. */
 	flush_workqueue(dev_priv->wq);
 
+	intel_huc_fini(dev);
 	intel_guc_fini(dev);
 	i915_gem_fini(dev);
 	intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d2c6099..77039b9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,6 +55,7 @@
 #include "intel_bios.h"
 #include "intel_dpll_mgr.h"
 #include "intel_guc.h"
+#include "intel_huc.h"
 #include "intel_lrc.h"
 #include "intel_ringbuffer.h"
 
@@ -1739,6 +1740,7 @@ struct drm_i915_private {
 
 	struct intel_gvt gvt;
 
+	struct intel_huc huc;
 	struct intel_guc guc;
 
 	struct intel_csr csr;
@@ -2865,6 +2867,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev)		(IS_GEN9(dev))
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
+#define HAS_HUC_UCODE(dev)	(HAS_GUC(dev))
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index cf5a65b..51533f1 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
 #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
 #define DMA_COPY_SIZE			_MMIO(0xc310)
 #define DMA_CTRL			_MMIO(0xc314)
+#define   HUC_UKERNEL			  (1<<9)
 #define   UOS_MOVE			  (1<<4)
 #define   START_DMA			  (1<<0)
 #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
+#define   HUC_LOADING_AGENT_VCR		  (0<<1)
+#define   HUC_LOADING_AGENT_GUC		  (1<<1)
 #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index ebf9c8d..c7b2745 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -160,6 +160,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
 extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
 
 /* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 42b6509..d76451c 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -85,6 +85,17 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 	}
 };
 
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+{
+	u32 wopcm_size = GUC_WOPCM_TOP;
+
+	/* On BXT, the top of WOPCM is reserved for RC6 context */
+	if (IS_BROXTON(dev_priv))
+		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
+
+	return wopcm_size;
+}
+
 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
 {
 	struct intel_engine_cs *engine;
@@ -272,7 +283,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 
 	/* Finally start the DMA */
-	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
+	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
+			_MASKED_BIT_DISABLE(HUC_UKERNEL));
 
 	/*
 	 * Wait for the DMA to complete & the GuC to start up.
@@ -297,17 +309,6 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
-static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
-{
-	u32 wopcm_size = GUC_WOPCM_TOP;
-
-	/* On BXT, the top of WOPCM is reserved for RC6 context */
-	if (IS_BROXTON(dev_priv))
-		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
-
-	return wopcm_size;
-}
-
 /*
  * Load the GuC firmware blob into the MinuteIA.
  */
@@ -476,6 +477,7 @@ int intel_guc_setup(struct drm_device *dev)
 			goto fail;
 		}
 
+		intel_huc_load(dev);
 		err = guc_ucode_xfer(dev_priv);
 		if (!err)
 			break;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
new file mode 100644
index 0000000..946caa7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_HUC_H_
+#define _INTEL_HUC_H_
+
+#include "intel_guc.h"
+
+#define HUC_STATUS2		_MMIO(0xD3B0)
+#define   HUC_FW_VERIFIED	(1<<7)
+
+struct intel_huc {
+	/* Generic uC firmware management */
+	struct intel_uc_fw huc_fw;
+
+	/* HuC-specific additions */
+};
+
+extern void intel_huc_init(struct drm_device *dev);
+extern int intel_huc_load(struct drm_device *dev);
+extern void intel_huc_auth(struct drm_device *dev);
+extern void intel_huc_fini(struct drm_device *dev);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
new file mode 100644
index 0000000..96cd9d8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_huc.h"
+
+/**
+ * DOC: HuC Firmware
+ *
+ * Motivation:
+ * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ *
+ * Implementation:
+ * On supported platforms, i915's job is to load the firmware stored on the
+ * file system and assist with authentication. It is up to userspace to
+ * detect the presence of HuC support on a platform, on their own.
+ * For debugging, i915 provides a debugfs file, i915_huc_load_status_info
+ * which displays the firmware load status.
+ *
+ * The unified uC firmware loader is used. Firmware binary is fetched by the
+ * loader asynchronously from the driver init process. However, the actual
+ * loading to HW is deferred until GEM initialization is done. Be note that HuC
+ * firmware loading must be done before GuC loading.
+ */
+
+#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
+MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+
+/**
+ * intel_huc_load_ucode() - DMA's the firmware
+ * @dev: the drm device
+ *
+ * This function takes the gem object containing the firmware, sets up the DMA
+ * engine MMIO, triggers the DMA operation and waits for it to finish.
+ *
+ * Transfer the firmware image to RAM for execution by the microcontroller.
+ *
+ * Return: 0 on success, non-zero on failure
+ */
+
+static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
+{
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+	unsigned long offset = 0;
+	u32 size;
+	int ret;
+
+	ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
+	if (ret) {
+		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
+		return ret;
+	}
+
+	ret = i915_gem_obj_ggtt_pin(huc_fw->uc_fw_obj, 0, 0);
+	if (ret) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", ret);
+		return ret;
+	}
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	WARN_ON(!mutex_is_locked(&dev_priv->drm.struct_mutex));
+	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+	/* init WOPCM */
+	I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
+	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
+			HUC_LOADING_AGENT_GUC);
+
+	/* Set the source address for the uCode */
+	offset = i915_gem_obj_ggtt_offset(huc_fw->uc_fw_obj) +
+			huc_fw->header_offset;
+	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
+	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+
+	/* Hardware doesn't look at destination address for HuC. Set it to 0,
+	 * but still program the correct address space.
+	 */
+	I915_WRITE(DMA_ADDR_1_LOW, 0);
+	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+
+	size = huc_fw->header_size + huc_fw->ucode_size;
+	I915_WRITE(DMA_COPY_SIZE, size);
+
+	/* Start the DMA */
+	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
+
+	/* Wait for DMA to finish */
+	ret = wait_for_atomic((I915_READ(DMA_CTRL) & START_DMA) == 0, 50);
+
+	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
+
+	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	/*
+	 * We keep the object pages for reuse during resume. But we can unpin it
+	 * now that DMA has completed, so it doesn't continue to take up space.
+	 */
+	i915_gem_object_ggtt_unpin(huc_fw->uc_fw_obj);
+
+	return ret;
+}
+
+/**
+ * intel_huc_init() - initiate HuC firmware loading request
+ * @dev: the drm device
+ *
+ * Called early during driver load, but after GEM is initialised. The loading
+ * will continue only when driver explicitly specify firmware name and version.
+ * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
+ * capable or driver yet support it. And there will be no error message for
+ * UC_FIRMWARE_NONE cases.
+ *
+ * The DMA-copying to HW is done later when intel_huc_ucode_load() is called.
+ */
+void intel_huc_init(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_huc *huc = &dev_priv->huc;
+	struct intel_uc_fw *huc_fw = &huc->huc_fw;
+	const char *fw_path = NULL;
+
+	huc_fw->uc_dev = dev;
+	huc_fw->uc_fw_path = NULL;
+	huc_fw->fetch_status = UC_FIRMWARE_NONE;
+	huc_fw->load_status = UC_FIRMWARE_NONE;
+	huc_fw->fw_type = UC_FW_TYPE_HUC;
+
+	if (!HAS_HUC_UCODE(dev_priv))
+		return;
+
+	if (IS_SKYLAKE(dev_priv)) {
+		fw_path = I915_SKL_HUC_UCODE;
+		huc_fw->major_ver_wanted = 1;
+		huc_fw->minor_ver_wanted = 7;
+	}
+
+	if (fw_path == NULL)
+		return;
+
+	huc_fw->uc_fw_path = fw_path;
+	huc_fw->fetch_status = UC_FIRMWARE_PENDING;
+
+	DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
+
+	intel_uc_fw_fetch(dev, huc_fw);
+}
+
+/**
+ * intel_huc_load() - load HuC uCode to device
+ * @dev: the drm device
+ *
+ * Called from gem_init_hw() during driver loading and also after a GPU reset.
+ * Be note that HuC loading must be done before GuC loading.
+ *
+ * The firmware image should have already been fetched into memory by the
+ * earlier call to intel_huc_ucode_init(), so here we need only check that
+ * is succeeded, and then transfer the image to the h/w.
+ *
+ * Return:	non-zero code on error
+ */
+int intel_huc_load(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+	int err;
+
+	if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
+		return 0;
+
+	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+		huc_fw->uc_fw_path,
+		intel_uc_fw_status_repr(huc_fw->fetch_status),
+		intel_uc_fw_status_repr(huc_fw->load_status));
+
+	if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
+	    huc_fw->load_status == UC_FIRMWARE_FAIL)
+		return -ENOEXEC;
+
+	huc_fw->load_status = UC_FIRMWARE_PENDING;
+
+	switch (huc_fw->fetch_status) {
+	case UC_FIRMWARE_FAIL:
+		/* something went wrong :( */
+		err = -EIO;
+		goto fail;
+
+	case UC_FIRMWARE_NONE:
+	case UC_FIRMWARE_PENDING:
+	default:
+		/* "can't happen" */
+		WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
+			huc_fw->uc_fw_path,
+			intel_uc_fw_status_repr(huc_fw->fetch_status),
+			huc_fw->fetch_status);
+		err = -ENXIO;
+		goto fail;
+
+	case UC_FIRMWARE_SUCCESS:
+		break;
+	}
+
+	err = huc_ucode_xfer(dev_priv);
+	if (err)
+		goto fail;
+
+	huc_fw->load_status = UC_FIRMWARE_SUCCESS;
+
+	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+		huc_fw->uc_fw_path,
+		intel_uc_fw_status_repr(huc_fw->fetch_status),
+		intel_uc_fw_status_repr(huc_fw->load_status));
+
+	return 0;
+
+fail:
+	if (huc_fw->load_status == UC_FIRMWARE_PENDING)
+		huc_fw->load_status = UC_FIRMWARE_FAIL;
+
+	DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
+
+	return err;
+}
+
+/**
+ * intel_huc_fini() - clean up resources allocated for HuC
+ * @dev: the drm device
+ *
+ * Cleans up by releasing the huc firmware GEM obj.
+ */
+void intel_huc_fini(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+	mutex_lock(&dev->struct_mutex);
+	if (huc_fw->uc_fw_obj)
+		drm_gem_object_unreference(&huc_fw->uc_fw_obj->base);
+	huc_fw->uc_fw_obj = NULL;
+	mutex_unlock(&dev->struct_mutex);
+
+	huc_fw->fetch_status = UC_FIRMWARE_NONE;
+}
-- 
1.9.1

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[PATCH v3 4/6] drm/i915/huc: Add debugfs for HuC loading status check

[Peter Antoine]

Add debugfs entry for HuC loading status check.

v2: rebase on-top of drm-intel-nightly.
v3: rebased again.

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9a6deff..de596c5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2494,6 +2494,38 @@ static int i915_llc(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+	if (!HAS_HUC_UCODE(dev_priv))
+		return 0;
+
+	seq_puts(m, "HuC firmware status:\n");
+	seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+	seq_printf(m, "\tfetch: %s\n",
+		intel_uc_fw_status_repr(huc_fw->fetch_status));
+	seq_printf(m, "\tload: %s\n",
+		intel_uc_fw_status_repr(huc_fw->load_status));
+	seq_printf(m, "\tversion wanted: %d.%d\n",
+		huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+	seq_printf(m, "\tversion found: %d.%d\n",
+		huc_fw->major_ver_found, huc_fw->minor_ver_found);
+	seq_printf(m, "\theader: offset is %d; size = %d\n",
+		huc_fw->header_offset, huc_fw->header_size);
+	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+		huc_fw->ucode_offset, huc_fw->ucode_size);
+	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+		huc_fw->rsa_offset, huc_fw->rsa_size);
+
+	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+	return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
 	struct drm_info_node *node = m->private;
@@ -5407,6 +5439,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
-- 
1.9.1

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[PATCH v3 5/6] drm/i915/huc: Support HuC authentication

[Peter Antoine]

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 65 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  2 +
 3 files changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 5f88500..1ec16a4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -25,6 +25,7 @@
 #include <linux/circ_buf.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
+#include "intel_huc.h"
 
 /**
  * DOC: GuC-based command submission
@@ -1076,3 +1077,67 @@ int intel_guc_resume(struct drm_device *dev)
 
 	return host2guc_action(guc, data, ARRAY_SIZE(data));
 }
+
+/**
+ * intel_huc_auth() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_huc_auth(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+	    huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+		return;
+	}
+
+	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+		return;
+	}
+
+	ret = i915_gem_obj_ggtt_pin(huc->huc_fw.uc_fw_obj, 0, 0);
+	if (ret) {
+		DRM_ERROR("HuC: Pin failed");
+		return;
+	}
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. It's stored
+	 * at the beginning of the gem object, before the fw bits
+	 */
+	data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_gem_obj_ggtt_offset(huc->huc_fw.uc_fw_obj) +
+			huc->huc_fw.rsa_offset;
+
+	ret = host2guc_action(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for_atomic(
+		(I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_gem_object_ggtt_unpin(huc->huc_fw.uc_fw_obj);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index a69ee36..c5a6227 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -437,6 +437,7 @@ enum host2guc_action {
 	HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
 	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
 	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
+	HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	HOST2GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index d76451c..e3d2e69 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -495,6 +495,8 @@ int intel_guc_setup(struct drm_device *dev)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_huc_auth(dev);
+
 	if (i915.enable_guc_submission) {
 		err = i915_guc_submission_enable(dev_priv);
 		if (err)
-- 
1.9.1

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[PATCH v3 6/6] drm/i915/huc: Add BXT HuC Loading Support

[Peter Antoine]

This patch adds the HuC Loading for the BXT.
Version 1.7 of the HuC firmware.

v2: rebased.
v3: rebased.
    changed file name to match the install package format.

Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 96cd9d8..c6d53b3 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -49,6 +49,9 @@
 #define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 
+#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
 /**
  * intel_huc_load_ucode() - DMA's the firmware
  * @dev: the drm device
@@ -157,6 +160,10 @@ void intel_huc_init(struct drm_device *dev)
 		fw_path = I915_SKL_HUC_UCODE;
 		huc_fw->major_ver_wanted = 1;
 		huc_fw->minor_ver_wanted = 7;
+	} else if (IS_BROXTON(dev_priv)) {
+		fw_path = I915_BXT_HUC_UCODE;
+		huc_fw->major_ver_wanted = 1;
+		huc_fw->minor_ver_wanted = 7;
 	}
 
 	if (fw_path == NULL)
-- 
1.9.1

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✗ Ro.CI.BAT: warning for series starting with [v3,1/6] drm/i915/guc: Make the GuC fw loading helper functions general

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/6] drm/i915/guc: Make the GuC fw loading helper functions general
URL   : https://patchwork.freedesktop.org/series/9564/
State : warning

== Summary ==

Series 9564v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/9564/revisions/1/mbox

Test drv_hangman:
        Subgroup error-state-basic:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
Test drv_module_reload_basic:
                skip       -> PASS       (ro-snb-i7-2620M)
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
Test gem_ringfill:
        Subgroup basic-default-hang:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
        Subgroup hang-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
        Subgroup hang-read-crc-pipe-c:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
        Subgroup suspend-read-crc-pipe-a:
                dmesg-warn -> SKIP       (ro-bdw-i7-5557U)
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (fi-skl-i5-6260u)
Test prime_busy:
        Subgroup basic-after-default:
                fail       -> DMESG-FAIL (fi-skl-i5-6260u)
        Subgroup basic-before-default:
                fail       -> DMESG-FAIL (fi-skl-i5-6260u)

fi-kbl-qkkr      total:235  pass:164  dwarn:29  dfail:0   fail:2   skip:40 
fi-skl-i5-6260u  total:235  pass:197  dwarn:10  dfail:2   fail:0   skip:26 
fi-snb-i7-2600   total:235  pass:179  dwarn:0   dfail:0   fail:2   skip:54 
ro-bdw-i5-5250u  total:229  pass:204  dwarn:1   dfail:1   fail:0   skip:23 
ro-bdw-i7-5557U  total:229  pass:204  dwarn:1   dfail:1   fail:0   skip:23 
ro-bdw-i7-5600u  total:229  pass:190  dwarn:0   dfail:1   fail:0   skip:38 
ro-bsw-n3050     total:229  pass:177  dwarn:0   dfail:1   fail:2   skip:49 
ro-byt-n2820     total:229  pass:180  dwarn:0   dfail:1   fail:3   skip:45 
ro-hsw-i3-4010u  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31 
ro-hsw-i7-4770r  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31 
ro-ilk-i7-620lm  total:229  pass:157  dwarn:0   dfail:1   fail:1   skip:70 
ro-ilk1-i5-650   total:224  pass:157  dwarn:0   dfail:1   fail:1   skip:65 
ro-ivb-i7-3770   total:229  pass:188  dwarn:0   dfail:1   fail:0   skip:40 
ro-skl3-i5-6260u total:229  pass:208  dwarn:1   dfail:1   fail:0   skip:19 
ro-snb-i7-2620M  total:229  pass:179  dwarn:0   dfail:1   fail:1   skip:48 

Results at /archive/results/CI_IGT_test/RO_Patchwork_1437/

39b147d drm-intel-nightly: 2016y-07m-06d-12h-15m-56s UTC integration manifest
b989dea drm/i915/huc: Add BXT HuC Loading Support
6db0136 drm/i915/huc: Support HuC authentication
41abdd6 drm/i915/huc: Add debugfs for HuC loading status check
1570368 drm/i915/huc: Add HuC fw loading support
6e311bd drm/i915/huc: Unified css_header struct for GuC and HuC
e5ca66a drm/i915/guc: Make the GuC fw loading helper functions general

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Re: [PATCH v3 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC

[Vivi, Rodrigo]

On Wed, 2016-07-06 at 15:24 +0100, Peter Antoine wrote:
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
> 
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> 
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc.h        |  4 ++++
>  drivers/gpu/drm/i915/intel_guc_fwif.h   | 16 ++++++++++---
>  drivers/gpu/drm/i915/intel_guc_loader.c | 40 ++++++++++++++++++++++-
> ----------
>  3 files changed, 44 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.h
> b/drivers/gpu/drm/i915/intel_guc.h
> index 02adcfc..ebf9c8d 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -97,6 +97,9 @@ enum intel_uc_fw_status {
>  	UC_FIRMWARE_SUCCESS
>  };
>  
> +#define UC_FW_TYPE_GUC		0
> +#define UC_FW_TYPE_HUC		1
> +

couldn't this be an enum?

>  /*
>   * This structure encapsulates all the data needed during the
> process
>   * of fetching, caching, and loading the firmware image into the
> GuC.
> @@ -114,6 +117,7 @@ struct intel_uc_fw {
>  	uint16_t major_ver_found;
>  	uint16_t minor_ver_found;
>  
> +	uint32_t fw_type;
>  	uint32_t header_size;
>  	uint32_t header_offset;
>  	uint32_t rsa_size;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 944786d..a69ee36 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -154,7 +154,7 @@
>   * The GuC firmware layout looks like this:
>   *
>   *     +-------------------------------+
> - *     |        guc_css_header         |
> + *     |         uc_css_header         |
>   *     | contains major/minor version  |
>   *     +-------------------------------+
>   *     |             uCode             |
> @@ -180,9 +180,16 @@
>   * 3. Length info of each component can be found in header, in
> dwords.
>   * 4. Modulus and exponent key are not required by driver. They may
> not appear
>   * in fw. So driver will load a truncated firmware in this case.
> + *
> + * HuC firmware layout is same as GuC firmware.
> + *
> + * HuC firmware css header is different. However, the only
> difference is where
> + * the version information is saved. The uc_css_header is unified to
> support
> + * both. Driver should get HuC version from
> uc_css_header.huc_sw_version, while
> + * uc_css_header.guc_sw_version for GuC.
>   */
>  
> -struct guc_css_header {
> +struct uc_css_header {
>  	uint32_t module_type;
>  	/* header_size includes all non-uCode bits, including
> css_header, rsa
>  	 * key, modulus key and exponent data. */
> @@ -213,7 +220,10 @@ struct guc_css_header {
>  
>  	char username[8];
>  	char buildnumber[12];
> -	uint32_t device_id;
> +	union {
> +		uint32_t device_id;
> +		uint32_t huc_sw_version;
> +	};
>  	uint32_t guc_sw_version;
>  	uint32_t prod_preprod_fw;
>  	uint32_t reserved[12];
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 1afa49b..42b6509 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -553,7 +553,7 @@ void intel_uc_fw_fetch(struct drm_device *dev,
> struct intel_uc_fw *uc_fw)
>  {
>  	struct drm_i915_gem_object *obj;
>  	const struct firmware *fw;
> -	struct guc_css_header *css;
> +	struct uc_css_header *css;
>  	size_t size;
>  	int err;
>  
> @@ -570,19 +570,19 @@ void intel_uc_fw_fetch(struct drm_device *dev,
> struct intel_uc_fw *uc_fw)
>  		uc_fw->uc_fw_path, fw);
>  
>  	/* Check the size of the blob before examining buffer
> contents */
> -	if (fw->size < sizeof(struct guc_css_header)) {
> +	if (fw->size < sizeof(struct uc_css_header)) {
>  		DRM_ERROR("Firmware header is missing\n");
>  		goto fail;
>  	}
>  
> -	css = (struct guc_css_header *)fw->data;
> +	css = (struct uc_css_header *)fw->data;
>  
>  	/* Firmware bits always start from header */
>  	uc_fw->header_offset = 0;
>  	uc_fw->header_size = (css->header_size_dw - css-
> >modulus_size_dw -
>  		css->key_size_dw - css->exponent_size_dw) *
> sizeof(u32);
>  
> -	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> +	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
>  		DRM_ERROR("CSS header definition mismatch\n");
>  		goto fail;
>  	}
> @@ -606,21 +606,35 @@ void intel_uc_fw_fetch(struct drm_device *dev,
> struct intel_uc_fw *uc_fw)
>  		goto fail;
>  	}
>  
> -	/* Header and uCode will be loaded to WOPCM. Size of the
> two. */
> -	size = uc_fw->header_size + uc_fw->ucode_size;
> -	if (size > guc_wopcm_size(to_i915(dev))) {
> -		DRM_ERROR("Firmware is too large to fit in
> WOPCM\n");
> -		goto fail;
> -	}
> -
>  	/*
>  	 * The GuC firmware image has the version number embedded at
> a well-known
>  	 * offset within the firmware blob; note that major / minor
> version are
>  	 * TWO bytes each (i.e. u16), although all pointers and
> offsets are defined
>  	 * in terms of bytes (u8).
>  	 */
> -	uc_fw->major_ver_found = css->guc_sw_version >> 16;
> -	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> +	switch (uc_fw->fw_type) {
> +	case UC_FW_TYPE_GUC:
> +		/* Header and uCode will be loaded to WOPCM. Size of
> the two. */
> +		size = uc_fw->header_size + uc_fw->ucode_size;
> +
> +		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6
> context). */
> +		if (size > guc_wopcm_size(to_i915(dev))) {
> +			DRM_ERROR("Firmware is too large to fit in
> WOPCM\n");
> +			goto fail;
> +		}
> +
> +		uc_fw->major_ver_found = css->guc_sw_version >> 16;
> +		uc_fw->minor_ver_found = css->guc_sw_version &
> 0xFFFF;
> +		break;
> +	case UC_FW_TYPE_HUC:
> +		uc_fw->major_ver_found = css->huc_sw_version >> 16;
> +		uc_fw->minor_ver_found = css->huc_sw_version &
> 0xFFFF;
> +		break;
> +	default:
> +		DRM_ERROR("Unknown firmware type %d\n", uc_fw-
> >fw_type);
> +		err = -ENOEXEC;
> +		goto fail;
> +	}
>  
>  	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>  	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
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Re: [PATCH v3 6/6] drm/i915/huc: Add BXT HuC Loading Support

[Vivi, Rodrigo]

vaapi-intel-driver, the userspace component here is only using HuC for
SKL for now, so I believe this one will be on hold for now, right?



On Wed, 2016-07-06 at 15:24 +0100, Peter Antoine wrote:
> This patch adds the HuC Loading for the BXT.
> Version 1.7 of the HuC firmware.
> 
> v2: rebased.
> v3: rebased.
>     changed file name to match the install package format.
> 
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 96cd9d8..c6d53b3 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -49,6 +49,9 @@
>  #define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
>  MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>  
> +#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
> +MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
> +
>  /**
>   * intel_huc_load_ucode() - DMA's the firmware
>   * @dev: the drm device
> @@ -157,6 +160,10 @@ void intel_huc_init(struct drm_device *dev)
>  		fw_path = I915_SKL_HUC_UCODE;
>  		huc_fw->major_ver_wanted = 1;
>  		huc_fw->minor_ver_wanted = 7;
> +	} else if (IS_BROXTON(dev_priv)) {
> +		fw_path = I915_BXT_HUC_UCODE;
> +		huc_fw->major_ver_wanted = 1;
> +		huc_fw->minor_ver_wanted = 7;
>  	}
>  
>  	if (fw_path == NULL)
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Re: [PATCH v3 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC

[Peter Antoine]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 7207 bytes --]

On Wed, 6 Jul 2016, Vivi, Rodrigo wrote:

> On Wed, 2016-07-06 at 15:24 +0100, Peter Antoine wrote:
>> HuC firmware css header has almost exactly same definition as GuC
>> firmware except for the sw_version. Also, add a new member fw_type
>> into intel_uc_fw to indicate what kind of fw it is. So, the loader
>> will pull right sw_version from header.
>>
>> v2: rebased on-top of drm-intel-nightly
>> v3: rebased on-top of drm-intel-nightly (again).
>>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_guc.h        |  4 ++++
>>  drivers/gpu/drm/i915/intel_guc_fwif.h   | 16 ++++++++++---
>>  drivers/gpu/drm/i915/intel_guc_loader.c | 40 ++++++++++++++++++++++-
>> ----------
>>  3 files changed, 44 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h
>> b/drivers/gpu/drm/i915/intel_guc.h
>> index 02adcfc..ebf9c8d 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -97,6 +97,9 @@ enum intel_uc_fw_status {
>>  	UC_FIRMWARE_SUCCESS
>>  };
>>  
>> +#define UC_FW_TYPE_GUC		0
>> +#define UC_FW_TYPE_HUC		1
>> +
Yes.
I'll change it.

Peter.

>
> couldn't this be an enum?
>
>>  /*
>>   * This structure encapsulates all the data needed during the
>> process
>>   * of fetching, caching, and loading the firmware image into the
>> GuC.
>> @@ -114,6 +117,7 @@ struct intel_uc_fw {
>>  	uint16_t major_ver_found;
>>  	uint16_t minor_ver_found;
>>  
>> +	uint32_t fw_type;
>>  	uint32_t header_size;
>>  	uint32_t header_offset;
>>  	uint32_t rsa_size;
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index 944786d..a69ee36 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -154,7 +154,7 @@
>>   * The GuC firmware layout looks like this:
>>   *
>>   *     +-------------------------------+
>> - *     |        guc_css_header         |
>> + *     |         uc_css_header         |
>>   *     | contains major/minor version  |
>>   *     +-------------------------------+
>>   *     |             uCode             |
>> @@ -180,9 +180,16 @@
>>   * 3. Length info of each component can be found in header, in
>> dwords.
>>   * 4. Modulus and exponent key are not required by driver. They may
>> not appear
>>   * in fw. So driver will load a truncated firmware in this case.
>> + *
>> + * HuC firmware layout is same as GuC firmware.
>> + *
>> + * HuC firmware css header is different. However, the only
>> difference is where
>> + * the version information is saved. The uc_css_header is unified to
>> support
>> + * both. Driver should get HuC version from
>> uc_css_header.huc_sw_version, while
>> + * uc_css_header.guc_sw_version for GuC.
>>   */
>>  
>> -struct guc_css_header {
>> +struct uc_css_header {
>>  	uint32_t module_type;
>>  	/* header_size includes all non-uCode bits, including
>> css_header, rsa
>>  	 * key, modulus key and exponent data. */
>> @@ -213,7 +220,10 @@ struct guc_css_header {
>>  
>>  	char username[8];
>>  	char buildnumber[12];
>> -	uint32_t device_id;
>> +	union {
>> +		uint32_t device_id;
>> +		uint32_t huc_sw_version;
>> +	};
>>  	uint32_t guc_sw_version;
>>  	uint32_t prod_preprod_fw;
>>  	uint32_t reserved[12];
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 1afa49b..42b6509 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -553,7 +553,7 @@ void intel_uc_fw_fetch(struct drm_device *dev,
>> struct intel_uc_fw *uc_fw)
>>  {
>>  	struct drm_i915_gem_object *obj;
>>  	const struct firmware *fw;
>> -	struct guc_css_header *css;
>> +	struct uc_css_header *css;
>>  	size_t size;
>>  	int err;
>>  
>> @@ -570,19 +570,19 @@ void intel_uc_fw_fetch(struct drm_device *dev,
>> struct intel_uc_fw *uc_fw)
>>  		uc_fw->uc_fw_path, fw);
>>  
>>  	/* Check the size of the blob before examining buffer
>> contents */
>> -	if (fw->size < sizeof(struct guc_css_header)) {
>> +	if (fw->size < sizeof(struct uc_css_header)) {
>>  		DRM_ERROR("Firmware header is missing\n");
>>  		goto fail;
>>  	}
>>  
>> -	css = (struct guc_css_header *)fw->data;
>> +	css = (struct uc_css_header *)fw->data;
>>  
>>  	/* Firmware bits always start from header */
>>  	uc_fw->header_offset = 0;
>>  	uc_fw->header_size = (css->header_size_dw - css-
>>> modulus_size_dw -
>>  		css->key_size_dw - css->exponent_size_dw) *
>> sizeof(u32);
>>  
>> -	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
>> +	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
>>  		DRM_ERROR("CSS header definition mismatch\n");
>>  		goto fail;
>>  	}
>> @@ -606,21 +606,35 @@ void intel_uc_fw_fetch(struct drm_device *dev,
>> struct intel_uc_fw *uc_fw)
>>  		goto fail;
>>  	}
>>  
>> -	/* Header and uCode will be loaded to WOPCM. Size of the
>> two. */
>> -	size = uc_fw->header_size + uc_fw->ucode_size;
>> -	if (size > guc_wopcm_size(to_i915(dev))) {
>> -		DRM_ERROR("Firmware is too large to fit in
>> WOPCM\n");
>> -		goto fail;
>> -	}
>> -
>>  	/*
>>  	 * The GuC firmware image has the version number embedded at
>> a well-known
>>  	 * offset within the firmware blob; note that major / minor
>> version are
>>  	 * TWO bytes each (i.e. u16), although all pointers and
>> offsets are defined
>>  	 * in terms of bytes (u8).
>>  	 */
>> -	uc_fw->major_ver_found = css->guc_sw_version >> 16;
>> -	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>> +	switch (uc_fw->fw_type) {
>> +	case UC_FW_TYPE_GUC:
>> +		/* Header and uCode will be loaded to WOPCM. Size of
>> the two. */
>> +		size = uc_fw->header_size + uc_fw->ucode_size;
>> +
>> +		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6
>> context). */
>> +		if (size > guc_wopcm_size(to_i915(dev))) {
>> +			DRM_ERROR("Firmware is too large to fit in
>> WOPCM\n");
>> +			goto fail;
>> +		}
>> +
>> +		uc_fw->major_ver_found = css->guc_sw_version >> 16;
>> +		uc_fw->minor_ver_found = css->guc_sw_version &
>> 0xFFFF;
>> +		break;
>> +	case UC_FW_TYPE_HUC:
>> +		uc_fw->major_ver_found = css->huc_sw_version >> 16;
>> +		uc_fw->minor_ver_found = css->huc_sw_version &
>> 0xFFFF;
>> +		break;
>> +	default:
>> +		DRM_ERROR("Unknown firmware type %d\n", uc_fw-
>>> fw_type);
>> +		err = -ENOEXEC;
>> +		goto fail;
>> +	}
>>  
>>  	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>>  	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {

--
    Peter Antoine (Android Graphics Driver Software Engineer)
    ---------------------------------------------------------------------
    Intel Corporation (UK) Limited
    Registered No. 1134945 (England)
    Registered Office: Pipers Way, Swindon SN3 1RJ
    VAT No: 860 2173 47

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH v3 6/6] drm/i915/huc: Add BXT HuC Loading Support

[Xiang, Haihao]

Hi Rodrigo,

We will use HuC on BXT.

Thanks
Haihao

> vaapi-intel-driver, the userspace component here is only using HuC
> for
> SKL for now, so I believe this one will be on hold for now, right?
> 
> 
> 
> On Wed, 2016-07-06 at 15:24 +0100, Peter Antoine wrote:
> > This patch adds the HuC Loading for the BXT.
> > Version 1.7 of the HuC firmware.
> > 
> > v2: rebased.
> > v3: rebased.
> >     changed file name to match the install package format.
> > 
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> > b/drivers/gpu/drm/i915/intel_huc_loader.c
> > index 96cd9d8..c6d53b3 100644
> > --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > @@ -49,6 +49,9 @@
> >  #define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> >  MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> >  
> > +#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
> > +MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
> > +
> >  /**
> >   * intel_huc_load_ucode() - DMA's the firmware
> >   * @dev: the drm device
> > @@ -157,6 +160,10 @@ void intel_huc_init(struct drm_device *dev)
> >  		fw_path = I915_SKL_HUC_UCODE;
> >  		huc_fw->major_ver_wanted = 1;
> >  		huc_fw->minor_ver_wanted = 7;
> > +	} else if (IS_BROXTON(dev_priv)) {
> > +		fw_path = I915_BXT_HUC_UCODE;
> > +		huc_fw->major_ver_wanted = 1;
> > +		huc_fw->minor_ver_wanted = 7;
> >  	}
> >  
> >  	if (fw_path == NULL)
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Re: [PATCH v3 1/6] drm/i915/guc: Make the GuC fw loading helper functions general

[Dave Gordon]

[-- Attachment #1: Type: text/plain, Size: 1574 bytes --]

On 06/07/16 15:24, Peter Antoine wrote:
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
>      s/intel_guc_fw/intel_uc_fw/g
>      s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> v2: rebased on top of nightly.
>     reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
>  drivers/gpu/drm/i915/intel_guc.h           |  39 ++++----
>  drivers/gpu/drm/i915/intel_guc_loader.c    | 146 ++++++++++++++---------------
>  4 files changed, 101 insertions(+), 100 deletions(-)

As of yesterday, the odd-numbered patches 1 & 3 no longer apply cleanly 
and will need rebasing (again).

Also (as of last week's Tech Forum) any series containing more than a 
single patch should preferably have a cover letter that at least gives a 
summary of the patchset as a whole.

However the main problem with this patch it not what it changes, as what 
it fails to change. As I previously suggested (and provided code for) 
you need to change all the messages so they don't say "GuC" when we're 
actually dealing with the HuC. Updated fixup-patch attached ...

.Dave.

[-- Attachment #2: v3-0007-Tweaks-to-GuC-HuC-loader-code.patch --]
[-- Type: text/x-patch, Size: 9537 bytes --]

>From 8a2e98098ff48ed1a9abec3159e630b3a8c18f64 Mon Sep 17 00:00:00 2001
From: Dave Gordon <david.s.gordon@intel.com>
Date: Tue, 28 Jun 2016 13:09:54 +0100
Subject: [PATCH v3] Tweaks to GuC/HuC loader code
Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ

1. Add uc_name to intel_uc_fw structure, so we can use the appropriate
name ("GuC" or "HuC") everywhere (obviously, it should match the fw_type
field).

2. Change all messages in intel_uc_fw_fetch() to use the uc_name.

3. Validate fw_type at the beginning to intel_uc_fw_fetch() rather than
midway. Is there a firmware type in the CSS header -- if so we should
use that and the relevant definitions.

4. Refactor printing the firmware fetch/load status into a macro.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.h        |  3 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 84 +++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_huc_loader.c |  3 +-
 3 files changed, 57 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c7b2745..c04aef8 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -106,9 +106,10 @@ enum intel_uc_fw_status {
  */
 struct intel_uc_fw {
 	struct drm_device *uc_dev;
+	const char *uc_name;
 	const char *uc_fw_path;
-	size_t uc_fw_size;
 	struct drm_i915_gem_object *uc_fw_obj;
+	size_t uc_fw_size;
 	enum intel_uc_fw_status fetch_status;
 	enum intel_uc_fw_status load_status;
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index c08b81a..b8c0df7 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -68,6 +68,15 @@
 #define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
+#define	DEBUG_UC_FW_STATUS(uc_fw)					\
+	{								\
+		DRM_DEBUG_DRIVER("%s fw status: path %s, fetch %s, load %s\n",	\
+			uc_fw->uc_name,					\
+			uc_fw->uc_fw_path,				\
+			intel_uc_fw_status_repr(uc_fw->fetch_status),	\
+			intel_uc_fw_status_repr(uc_fw->load_status));	\
+	}
+
 /* User-friendly representation of an enum */
 const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
@@ -156,7 +165,7 @@ static u32 get_core_family(struct drm_i915_private *dev_priv)
 		return GFXCORE_FAMILY_GEN9;
 
 	default:
-		DRM_ERROR("GUC: unsupported core family\n");
+		DRM_ERROR("GuC: unsupported core family\n");
 		return GFXCORE_FAMILY_UNKNOWN;
 	}
 }
@@ -421,10 +430,7 @@ int intel_guc_setup(struct drm_device *dev)
 	const char *fw_path = guc_fw->uc_fw_path;
 	int retries, ret, err;
 
-	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
-		fw_path,
-		intel_uc_fw_status_repr(guc_fw->fetch_status),
-		intel_uc_fw_status_repr(guc_fw->load_status));
+	DEBUG_UC_FW_STATUS(guc_fw);
 
 	/* Loading forbidden, or no firmware to load? */
 	if (!i915.enable_guc_loading) {
@@ -454,9 +460,7 @@ int intel_guc_setup(struct drm_device *dev)
 
 	guc_fw->load_status = UC_FIRMWARE_PENDING;
 
-	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
-		intel_uc_fw_status_repr(guc_fw->fetch_status),
-		intel_uc_fw_status_repr(guc_fw->load_status));
+	DEBUG_UC_FW_STATUS(guc_fw);
 
 	err = i915_guc_submission_init(dev_priv);
 	if (err)
@@ -493,9 +497,7 @@ int intel_guc_setup(struct drm_device *dev)
 
 	guc_fw->load_status = UC_FIRMWARE_SUCCESS;
 
-	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
-		intel_uc_fw_status_repr(guc_fw->fetch_status),
-		intel_uc_fw_status_repr(guc_fw->load_status));
+	DEBUG_UC_FW_STATUS(guc_fw);
 
 	intel_huc_auth(dev);
 
@@ -563,8 +565,20 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 	size_t size;
 	int err;
 
-	DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
-		intel_uc_fw_status_repr(uc_fw->fetch_status));
+	/* Validate fw_type first of all, so we can name the uC */
+	switch (uc_fw->fw_type) {
+	case UC_FW_TYPE_GUC:
+	case UC_FW_TYPE_HUC:
+		break;
+
+	default:
+		DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+		err = -ENOEXEC;
+		goto fail;
+	}
+
+	DRM_DEBUG_DRIVER("%s fw fetch status %s before requesting firmware\n",
+		uc_fw->uc_name, intel_uc_fw_status_repr(uc_fw->fetch_status));
 
 	err = request_firmware(&fw, uc_fw->uc_fw_path, &dev->pdev->dev);
 	if (err)
@@ -572,12 +586,12 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 	if (!fw)
 		goto fail;
 
-	DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
-		uc_fw->uc_fw_path, fw);
+	DRM_DEBUG_DRIVER("%s fw fetch from %s succeeded, fw %p\n",
+		uc_fw->uc_name, uc_fw->uc_fw_path, fw);
 
 	/* Check the size of the blob before examining buffer contents */
 	if (fw->size < sizeof(struct uc_css_header)) {
-		DRM_ERROR("Firmware header is missing\n");
+		DRM_ERROR("%s firmware header is missing\n", uc_fw->uc_name);
 		goto fail;
 	}
 
@@ -589,7 +603,8 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
 	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
-		DRM_ERROR("CSS header definition mismatch\n");
+		DRM_ERROR("%s firmware CSS header definition mismatch\n",
+			uc_fw->uc_name);
 		goto fail;
 	}
 
@@ -599,7 +614,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 
 	/* now RSA */
 	if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
-		DRM_ERROR("RSA key size is bad\n");
+		DRM_ERROR("%s firmware RSA key size is bad\n", uc_fw->uc_name);
 		goto fail;
 	}
 	uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
@@ -608,7 +623,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 	/* At least, it should have header, uCode and RSA. Size of all three. */
 	size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
 	if (fw->size < size) {
-		DRM_ERROR("Missing firmware components\n");
+		DRM_ERROR("%s firmware missing components\n", uc_fw->uc_name);
 		goto fail;
 	}
 
@@ -625,35 +640,40 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 
 		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
 		if (size > guc_wopcm_size(to_i915(dev))) {
-			DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+			DRM_ERROR("%s firmware is too large to fit in WOPCM\n",
+				uc_fw->uc_name);
 			goto fail;
 		}
 
 		uc_fw->major_ver_found = css->guc_sw_version >> 16;
 		uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
 		break;
+
 	case UC_FW_TYPE_HUC:
 		uc_fw->major_ver_found = css->huc_sw_version >> 16;
 		uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
 		break;
+
 	default:
-		DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+		/*NOTREACHED*/
 		err = -ENOEXEC;
 		goto fail;
 	}
 
 	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
 	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
-		DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
+		DRM_ERROR("Found %s firmware version %d.%d, required version %d.%d\n",
+			uc_fw->uc_name,
 			uc_fw->major_ver_found, uc_fw->minor_ver_found,
 			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 		err = -ENOEXEC;
 		goto fail;
 	}
 
-	DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
-			uc_fw->major_ver_found, uc_fw->minor_ver_found,
-			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
+	DRM_DEBUG_DRIVER("%s firmware version %d.%d OK (minimum %d.%d)\n",
+		uc_fw->uc_name,
+		uc_fw->major_ver_found, uc_fw->minor_ver_found,
+		uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 
 	mutex_lock(&dev->struct_mutex);
 	obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
@@ -666,18 +686,18 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
 	uc_fw->uc_fw_obj = obj;
 	uc_fw->uc_fw_size = fw->size;
 
-	DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
-			uc_fw->uc_fw_obj);
+	DRM_DEBUG_DRIVER("%s fw fetch status SUCCESS, obj %p\n",
+		uc_fw->uc_name, uc_fw->uc_fw_obj);
 
 	release_firmware(fw);
 	uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
 	return;
 
 fail:
-	DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
-		err, fw, uc_fw->uc_fw_obj);
-	DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
-		  uc_fw->uc_fw_path, err);
+	DRM_DEBUG_DRIVER("%s fw fetch status FAIL; err %d, fw %p, obj %p\n",
+		uc_fw->uc_name, err, fw, uc_fw->uc_fw_obj);
+	DRM_ERROR("Failed to fetch %s firmware from %s (error %d)\n",
+		uc_fw->uc_name, uc_fw->uc_fw_path, err);
 
 	mutex_lock(&dev->struct_mutex);
 	obj = uc_fw->uc_fw_obj;
@@ -730,6 +750,8 @@ void intel_guc_init(struct drm_device *dev)
 	}
 
 	guc_fw->uc_dev = dev;
+	guc_fw->uc_name = "GuC";
+	guc_fw->fw_type = UC_FW_TYPE_GUC;
 	guc_fw->uc_fw_path = fw_path;
 	guc_fw->fetch_status = UC_FIRMWARE_NONE;
 	guc_fw->load_status = UC_FIRMWARE_NONE;
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index c6d53b3..2ae0542 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -148,10 +148,11 @@ void intel_huc_init(struct drm_device *dev)
 	const char *fw_path = NULL;
 
 	huc_fw->uc_dev = dev;
+	huc_fw->uc_name = "HuC";
+	huc_fw->fw_type = UC_FW_TYPE_HUC;
 	huc_fw->uc_fw_path = NULL;
 	huc_fw->fetch_status = UC_FIRMWARE_NONE;
 	huc_fw->load_status = UC_FIRMWARE_NONE;
-	huc_fw->fw_type = UC_FW_TYPE_HUC;
 
 	if (!HAS_HUC_UCODE(dev_priv))
 		return;
-- 
1.9.1


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✗ Ro.CI.BAT: failure for series starting with [v3,1/6] drm/i915/guc: Make the GuC fw loading helper functions general (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/6] drm/i915/guc: Make the GuC fw loading helper functions general (rev2)
URL   : https://patchwork.freedesktop.org/series/9564/
State : failure

== Summary ==

Applying: drm/i915/guc: Make the GuC fw loading helper functions general
fatal: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_guc_loader.c).
error: could not build fake ancestor
Patch failed at 0001 drm/i915/guc: Make the GuC fw loading helper functions general
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH v3 3/6] drm/i915/huc: Add HuC fw loading support

[Dave Gordon]

On 06/07/16 15:24, Peter Antoine wrote:
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
>
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
>
> v2: rebased on-top of drm-intel-nightly.
>     removed if(HAS_GUC()) before the guc call. (D.Gordon)
>     update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
>     match the one in the huc package.
>     Changed dev->dev_provate to to_i915()
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile           |   1 +
>  drivers/gpu/drm/i915/i915_drv.c         |   3 +
>  drivers/gpu/drm/i915/i915_drv.h         |   3 +
>  drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
>  drivers/gpu/drm/i915/intel_guc.h        |   1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  26 ++--
>  drivers/gpu/drm/i915/intel_huc.h        |  44 ++++++
>  drivers/gpu/drm/i915/intel_huc_loader.c | 267 ++++++++++++++++++++++++++++++++
>  8 files changed, 336 insertions(+), 12 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_huc.h
>  create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 684fc1c..0939b90 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -47,6 +47,7 @@ i915-y += i915_cmd_parser.o \
>
>  # general-purpose microcontroller (GuC) support
>  i915-y += intel_guc_loader.o \
> +	  intel_huc_loader.o \
>  	  i915_guc_submission.o
>
>  # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 694edac..72655bf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -645,6 +645,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  	 * working irqs for e.g. gmbus and dp aux transfers. */
>  	intel_modeset_init(dev);
>
> +	intel_huc_init(dev);
>  	intel_guc_init(dev);
>
>  	ret = i915_gem_init(dev);
> @@ -670,6 +671,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  cleanup_gem:
>  	i915_gem_fini(dev);
>  cleanup_irq:
> +	intel_huc_fini(dev);
>  	intel_guc_fini(dev);
>  	drm_irq_uninstall(dev);
>  	intel_teardown_gmbus(dev);
> @@ -1341,6 +1343,7 @@ void i915_driver_unload(struct drm_device *dev)
>  	/* Flush any outstanding unpin_work. */
>  	flush_workqueue(dev_priv->wq);
>
> +	intel_huc_fini(dev);
>  	intel_guc_fini(dev);
>  	i915_gem_fini(dev);
>  	intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d2c6099..77039b9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -55,6 +55,7 @@
>  #include "intel_bios.h"
>  #include "intel_dpll_mgr.h"
>  #include "intel_guc.h"
> +#include "intel_huc.h"
>  #include "intel_lrc.h"
>  #include "intel_ringbuffer.h"
>
> @@ -1739,6 +1740,7 @@ struct drm_i915_private {
>
>  	struct intel_gvt gvt;
>
> +	struct intel_huc huc;
>  	struct intel_guc guc;
>
>  	struct intel_csr csr;
> @@ -2865,6 +2867,7 @@ struct drm_i915_cmd_table {
>  #define HAS_GUC(dev)		(IS_GEN9(dev))
>  #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
>  #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
> +#define HAS_HUC_UCODE(dev)	(HAS_GUC(dev))
>
>  #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
>  				    INTEL_INFO(dev)->gen >= 8)
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index cf5a65b..51533f1 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -61,9 +61,12 @@
>  #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
>  #define DMA_COPY_SIZE			_MMIO(0xc310)
>  #define DMA_CTRL			_MMIO(0xc314)
> +#define   HUC_UKERNEL			  (1<<9)
>  #define   UOS_MOVE			  (1<<4)
>  #define   START_DMA			  (1<<0)
>  #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
> +#define   HUC_LOADING_AGENT_VCR		  (0<<1)
> +#define   HUC_LOADING_AGENT_GUC		  (1<<1)
>  #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index ebf9c8d..c7b2745 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -160,6 +160,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
>  extern int intel_guc_suspend(struct drm_device *dev);
>  extern int intel_guc_resume(struct drm_device *dev);
>  void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
>
>  /* i915_guc_submission.c */
>  int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 42b6509..d76451c 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -85,6 +85,17 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
>  	}
>  };
>
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> +{
> +	u32 wopcm_size = GUC_WOPCM_TOP;
> +
> +	/* On BXT, the top of WOPCM is reserved for RC6 context */
> +	if (IS_BROXTON(dev_priv))
> +		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
> +
> +	return wopcm_size;
> +}

I know this function is being made visible externally, but I don't think 
that requires it to be moved to the top of the file.

>  static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_engine_cs *engine;
> @@ -272,7 +283,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
>  	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>
>  	/* Finally start the DMA */
> -	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
> +			_MASKED_BIT_DISABLE(HUC_UKERNEL));
>
>  	/*
>  	 * Wait for the DMA to complete & the GuC to start up.
> @@ -297,17 +309,6 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
>  	return ret;
>  }
>
> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> -{
> -	u32 wopcm_size = GUC_WOPCM_TOP;
> -
> -	/* On BXT, the top of WOPCM is reserved for RC6 context */
> -	if (IS_BROXTON(dev_priv))
> -		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
> -
> -	return wopcm_size;
> -}

This function was perfectly OK where it was.

Otherwise generally OK.

.Dave.

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Re: [PATCH v3 5/6] drm/i915/huc: Support HuC authentication

[Dave Gordon]

On 06/07/16 15:24, Peter Antoine wrote:
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_submission.c | 65 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c    |  2 +
>  3 files changed, 68 insertions(+)

No obvious problems here.

Reviewed-by: Dave Gordon <david.s.gordon@intel.com>

> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 5f88500..1ec16a4 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -25,6 +25,7 @@
>  #include <linux/circ_buf.h>
>  #include "i915_drv.h"
>  #include "intel_guc.h"
> +#include "intel_huc.h"
>
>  /**
>   * DOC: GuC-based command submission
> @@ -1076,3 +1077,67 @@ int intel_guc_resume(struct drm_device *dev)
>
>  	return host2guc_action(guc, data, ARRAY_SIZE(data));
>  }
> +
> +/**
> + * intel_huc_auth() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_huc_auth(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> +	    huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> +		return;
> +
> +	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
> +		return;
> +	}
> +
> +	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> +		return;
> +	}
> +
> +	ret = i915_gem_obj_ggtt_pin(huc->huc_fw.uc_fw_obj, 0, 0);
> +	if (ret) {
> +		DRM_ERROR("HuC: Pin failed");
> +		return;
> +	}
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. It's stored
> +	 * at the beginning of the gem object, before the fw bits
> +	 */
> +	data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_gem_obj_ggtt_offset(huc->huc_fw.uc_fw_obj) +
> +			huc->huc_fw.rsa_offset;
> +
> +	ret = host2guc_action(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for_atomic(
> +		(I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed\n");
> +		goto out;
> +	}
> +
> +out:
> +	i915_gem_object_ggtt_unpin(huc->huc_fw.uc_fw_obj);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index a69ee36..c5a6227 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -437,6 +437,7 @@ enum host2guc_action {
>  	HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
>  	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
>  	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
> +	HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>  	HOST2GUC_ACTION_LIMIT
>  };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index d76451c..e3d2e69 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -495,6 +495,8 @@ int intel_guc_setup(struct drm_device *dev)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>
> +	intel_huc_auth(dev);
> +
>  	if (i915.enable_guc_submission) {
>  		err = i915_guc_submission_enable(dev_priv);
>  		if (err)
>

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Re: [PATCH v3 3/6] drm/i915/huc: Add HuC fw loading support

[Dave Gordon]

On 06/07/16 15:24, Peter Antoine wrote:
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
>
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
>
> v2: rebased on-top of drm-intel-nightly.
>     removed if(HAS_GUC()) before the guc call. (D.Gordon)
>     update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
>     match the one in the huc package.
>     Changed dev->dev_provate to to_i915()
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile           |   1 +
>  drivers/gpu/drm/i915/i915_drv.c         |   3 +
>  drivers/gpu/drm/i915/i915_drv.h         |   3 +
>  drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
>  drivers/gpu/drm/i915/intel_guc.h        |   1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  26 ++--
>  drivers/gpu/drm/i915/intel_huc.h        |  44 ++++++
>  drivers/gpu/drm/i915/intel_huc_loader.c | 267 ++++++++++++++++++++++++++++++++
>  8 files changed, 336 insertions(+), 12 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_huc.h
>  create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c

I found another problem, which at root is because this was *copied* from 
the GuC loading code some time ago, rather than being implemented in a 
single generic function. The GuC code has been changed since it was 
cloned, but of course the corresponding updates are missing from the HuC 
version.

[snip]

> +
> +	/* Start the DMA */
> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> +
> +	/* Wait for DMA to finish */
> +	ret = wait_for_atomic((I915_READ(DMA_CTRL) & START_DMA) == 0, 50);

Can't use wait_for_atomic() here. The GuC version now reads:

         /*
          * Wait for the DMA to complete & the GuC to start up.
          * NB: Docs recommend not using the interrupt for completion.
          * Measurements indicate this should take no more than 20ms,
	 * so a timeout here indicates that the GuC has is unusable.
          * (Higher levels of the driver will attempt to fall back to
          * execlist mode if this happens.)
          */
         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);

.Dave.

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Re: [PATCH v3 5/6] drm/i915/huc: Support HuC authentication

[Dave Gordon]

On 29/07/16 12:33, Dave Gordon wrote:
> On 06/07/16 15:24, Peter Antoine wrote:
>> The HuC authentication is done by host2guc call. The HuC RSA keys
>> are sent to GuC for authentication.
>>
>> v2: rebased on top of drm-intel-nightly.
>>     changed name format and upped version 1.7.
>> v3: rebased on top of drm-intel-nightly.
>>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_guc_submission.c | 65
>> ++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 +
>>  drivers/gpu/drm/i915/intel_guc_loader.c    |  2 +
>>  3 files changed, 68 insertions(+)
>
> No obvious problems here.

On second thoughts ...

>> +    ret = host2guc_action(guc, data, ARRAY_SIZE(data));
>> +    if (ret) {
>> +        DRM_ERROR("HuC: GuC did not ack Auth request\n");
>> +        goto out;
>> +    }
>> +
>> +    /* Check authentication status, it should be done by now */
>> +    ret = wait_for_atomic(
>> +        (I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
>> +    if (ret) {
>> +        DRM_ERROR("HuC: Authentication failed\n");
>> +        goto out;
>> +    }

... there's another wait_for_atomic() here :(

.Dave.
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Re: [PATCH v3 1/6] drm/i915/guc: Make the GuC fw loading helper functions general

[Antoine, Peter]

This patch has nothing to do with HuC. It is changing the GuC code to allow for generic usage.
But, I will change the "GuC" in the messages for "uC".

I'll let you  add  the patch yourself as you seem to have other renames/refactors on the mailing list.

Peter.

-----Original Message-----
From: Gordon, David S 
Sent: Friday, July 29, 2016 12:19 PM
To: Antoine, Peter <peter.antoine@intel.com>; intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 1/6] drm/i915/guc: Make the GuC fw loading helper functions general

On 06/07/16 15:24, Peter Antoine wrote:
> Rename some of the GuC fw loading code to make them more general. We 
> will utilise them for HuC loading as well.
>      s/intel_guc_fw/intel_uc_fw/g
>      s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members, 
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for 
> same purpose.
>
> v2: rebased on top of nightly.
>     reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
>  drivers/gpu/drm/i915/intel_guc.h           |  39 ++++----
>  drivers/gpu/drm/i915/intel_guc_loader.c    | 146 ++++++++++++++---------------
>  4 files changed, 101 insertions(+), 100 deletions(-)

As of yesterday, the odd-numbered patches 1 & 3 no longer apply cleanly and will need rebasing (again).

Also (as of last week's Tech Forum) any series containing more than a single patch should preferably have a cover letter that at least gives a summary of the patchset as a whole.

However the main problem with this patch it not what it changes, as what it fails to change. As I previously suggested (and provided code for) you need to change all the messages so they don't say "GuC" when we're actually dealing with the HuC. Updated fixup-patch attached ...

.Dave.
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Re: [PATCH v3 1/6] drm/i915/guc: Make the GuC fw loading helper functions general

[Dave Gordon]

On 06/07/16 15:24, Peter Antoine wrote:
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
>      s/intel_guc_fw/intel_uc_fw/g
>      s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> v2: rebased on top of nightly.
>     reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>

R-b can carry over again, but this will need (ANOTHER!) rebase as Chris 
has nuked one of the functions called below.

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
>  drivers/gpu/drm/i915/intel_guc.h           |  39 ++++----
>  drivers/gpu/drm/i915/intel_guc_loader.c    | 146 ++++++++++++++---------------
>  4 files changed, 101 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3d05cae..9a6deff 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2498,7 +2498,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
>  {
>  	struct drm_info_node *node = m->private;
>  	struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>  	u32 tmp, i;
>
>  	if (!HAS_GUC_UCODE(dev_priv))
> @@ -2506,15 +2506,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
>
>  	seq_printf(m, "GuC firmware status:\n");
>  	seq_printf(m, "\tpath: %s\n",
> -		guc_fw->guc_fw_path);
> +		guc_fw->uc_fw_path);
>  	seq_printf(m, "\tfetch: %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status));
>  	seq_printf(m, "\tload: %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>  	seq_printf(m, "\tversion wanted: %d.%d\n",
> -		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> +		guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
>  	seq_printf(m, "\tversion found: %d.%d\n",
> -		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> +		guc_fw->major_ver_found, guc_fw->minor_ver_found);
>  	seq_printf(m, "\theader: offset is %d; size = %d\n",
>  		guc_fw->header_offset, guc_fw->header_size);
>  	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index bfc8bf6..5f88500 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1038,7 +1038,7 @@ int intel_guc_suspend(struct drm_device *dev)
>  	struct i915_gem_context *ctx;
>  	u32 data[3];
>
> -	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> +	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
>  		return 0;
>
>  	ctx = dev_priv->kernel_context;
> @@ -1064,7 +1064,7 @@ int intel_guc_resume(struct drm_device *dev)
>  	struct i915_gem_context *ctx;
>  	u32 data[3];
>
> -	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> +	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
>  		return 0;
>
>  	ctx = dev_priv->kernel_context;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 3e3e743..02adcfc 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -90,29 +90,29 @@ struct i915_guc_client {
>  	uint64_t submissions[I915_NUM_ENGINES];
>  };
>
> -enum intel_guc_fw_status {
> -	GUC_FIRMWARE_FAIL = -1,
> -	GUC_FIRMWARE_NONE = 0,
> -	GUC_FIRMWARE_PENDING,
> -	GUC_FIRMWARE_SUCCESS
> +enum intel_uc_fw_status {
> +	UC_FIRMWARE_FAIL = -1,
> +	UC_FIRMWARE_NONE = 0,
> +	UC_FIRMWARE_PENDING,
> +	UC_FIRMWARE_SUCCESS
>  };
>
>  /*
>   * This structure encapsulates all the data needed during the process
>   * of fetching, caching, and loading the firmware image into the GuC.
>   */
> -struct intel_guc_fw {
> -	struct drm_device *		guc_dev;
> -	const char *			guc_fw_path;
> -	size_t				guc_fw_size;
> -	struct drm_i915_gem_object *	guc_fw_obj;
> -	enum intel_guc_fw_status	guc_fw_fetch_status;
> -	enum intel_guc_fw_status	guc_fw_load_status;
> -
> -	uint16_t			guc_fw_major_wanted;
> -	uint16_t			guc_fw_minor_wanted;
> -	uint16_t			guc_fw_major_found;
> -	uint16_t			guc_fw_minor_found;
> +struct intel_uc_fw {
> +	struct drm_device *uc_dev;
> +	const char *uc_fw_path;
> +	size_t uc_fw_size;
> +	struct drm_i915_gem_object *uc_fw_obj;
> +	enum intel_uc_fw_status fetch_status;
> +	enum intel_uc_fw_status load_status;
> +
> +	uint16_t major_ver_wanted;
> +	uint16_t minor_ver_wanted;
> +	uint16_t major_ver_found;
> +	uint16_t minor_ver_found;
>
>  	uint32_t header_size;
>  	uint32_t header_offset;
> @@ -123,7 +123,7 @@ struct intel_guc_fw {
>  };
>
>  struct intel_guc {
> -	struct intel_guc_fw guc_fw;
> +	struct intel_uc_fw guc_fw;
>  	uint32_t log_flags;
>  	struct drm_i915_gem_object *log_obj;
>
> @@ -152,9 +152,10 @@ struct intel_guc {
>  extern void intel_guc_init(struct drm_device *dev);
>  extern int intel_guc_setup(struct drm_device *dev);
>  extern void intel_guc_fini(struct drm_device *dev);
> -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
>  extern int intel_guc_suspend(struct drm_device *dev);
>  extern int intel_guc_resume(struct drm_device *dev);
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
>
>  /* i915_guc_submission.c */
>  int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 605c696..1afa49b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -69,16 +69,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
>  MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>
>  /* User-friendly representation of an enum */
> -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
>  {
>  	switch (status) {
> -	case GUC_FIRMWARE_FAIL:
> +	case UC_FIRMWARE_FAIL:
>  		return "FAIL";
> -	case GUC_FIRMWARE_NONE:
> +	case UC_FIRMWARE_NONE:
>  		return "NONE";
> -	case GUC_FIRMWARE_PENDING:
> +	case UC_FIRMWARE_PENDING:
>  		return "PENDING";
> -	case GUC_FIRMWARE_SUCCESS:
> +	case UC_FIRMWARE_SUCCESS:
>  		return "SUCCESS";
>  	default:
>  		return "UNKNOWN!";
> @@ -240,8 +240,8 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
>   */
>  static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> -	struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct drm_i915_gem_object *fw_obj = guc_fw->uc_fw_obj;
>  	unsigned long offset;
>  	struct sg_table *sg = fw_obj->pages;
>  	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> @@ -313,17 +313,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>   */
>  static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>  	struct drm_device *dev = &dev_priv->drm;
>  	int ret;
>
> -	ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> +	ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
>  	if (ret) {
>  		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>  		return ret;
>  	}
>
> -	ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
> +	ret = i915_gem_obj_ggtt_pin(guc_fw->uc_fw_obj, 0, 0);

This now has to be:

   ret = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);

Otherwise OK :)

.Dave.

>  	if (ret) {
>  		DRM_DEBUG_DRIVER("pin failed %d\n", ret);
>  		return ret;
> @@ -375,7 +375,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  	 * We keep the object pages for reuse during resume. But we can unpin it
>  	 * now that DMA has completed, so it doesn't continue to take up space.
>  	 */
> -	i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
> +	i915_gem_object_ggtt_unpin(guc_fw->uc_fw_obj);
>
>  	return ret;
>  }
> @@ -414,14 +414,14 @@ static int i915_reset_guc(struct drm_i915_private *dev_priv)
>  int intel_guc_setup(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> -	const char *fw_path = guc_fw->guc_fw_path;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	const char *fw_path = guc_fw->uc_fw_path;
>  	int retries, ret, err;
>
>  	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
>  		fw_path,
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>
>  	/* Loading forbidden, or no firmware to load? */
>  	if (!i915.enable_guc_loading) {
> @@ -439,21 +439,21 @@ int intel_guc_setup(struct drm_device *dev)
>  	}
>
>  	/* Fetch failed, or already fetched but failed to load? */
> -	if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> +	if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
>  		err = -EIO;
>  		goto fail;
> -	} else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> +	} else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
>  		err = -ENOEXEC;
>  		goto fail;
>  	}
>
>  	direct_interrupts_to_host(dev_priv);
>
> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> +	guc_fw->load_status = UC_FIRMWARE_PENDING;
>
>  	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>
>  	err = i915_guc_submission_init(dev_priv);
>  	if (err)
> @@ -487,11 +487,11 @@ int intel_guc_setup(struct drm_device *dev)
>  			 "retry %d more time(s)\n", err, retries);
>  	}
>
> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> +	guc_fw->load_status = UC_FIRMWARE_SUCCESS;
>
>  	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>
>  	if (i915.enable_guc_submission) {
>  		err = i915_guc_submission_enable(dev_priv);
> @@ -503,8 +503,8 @@ int intel_guc_setup(struct drm_device *dev)
>  	return 0;
>
>  fail:
> -	if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> -		guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> +	if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> +		guc_fw->load_status = UC_FIRMWARE_FAIL;
>
>  	direct_interrupts_to_host(dev_priv);
>  	i915_guc_submission_disable(dev_priv);
> @@ -549,7 +549,7 @@ fail:
>  	return ret;
>  }
>
> -static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
>  {
>  	struct drm_i915_gem_object *obj;
>  	const struct firmware *fw;
> @@ -558,16 +558,16 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
>  	int err;
>
>  	DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> +		intel_uc_fw_status_repr(uc_fw->fetch_status));
>
> -	err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
> +	err = request_firmware(&fw, uc_fw->uc_fw_path, &dev->pdev->dev);
>  	if (err)
>  		goto fail;
>  	if (!fw)
>  		goto fail;
>
>  	DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> -		guc_fw->guc_fw_path, fw);
> +		uc_fw->uc_fw_path, fw);
>
>  	/* Check the size of the blob before examining buffer contents */
>  	if (fw->size < sizeof(struct guc_css_header)) {
> @@ -578,36 +578,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
>  	css = (struct guc_css_header *)fw->data;
>
>  	/* Firmware bits always start from header */
> -	guc_fw->header_offset = 0;
> -	guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> +	uc_fw->header_offset = 0;
> +	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>  		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> -	if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> +	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
>  		DRM_ERROR("CSS header definition mismatch\n");
>  		goto fail;
>  	}
>
>  	/* then, uCode */
> -	guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> -	guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> +	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> +	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>
>  	/* now RSA */
>  	if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
>  		DRM_ERROR("RSA key size is bad\n");
>  		goto fail;
>  	}
> -	guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> -	guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> +	uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> +	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>
>  	/* At least, it should have header, uCode and RSA. Size of all three. */
> -	size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> +	size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
>  	if (fw->size < size) {
>  		DRM_ERROR("Missing firmware components\n");
>  		goto fail;
>  	}
>
>  	/* Header and uCode will be loaded to WOPCM. Size of the two. */
> -	size = guc_fw->header_size + guc_fw->ucode_size;
> +	size = uc_fw->header_size + uc_fw->ucode_size;
>  	if (size > guc_wopcm_size(to_i915(dev))) {
>  		DRM_ERROR("Firmware is too large to fit in WOPCM\n");
>  		goto fail;
> @@ -619,21 +619,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
>  	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
>  	 * in terms of bytes (u8).
>  	 */
> -	guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> -	guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> +	uc_fw->major_ver_found = css->guc_sw_version >> 16;
> +	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>
> -	if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> -	    guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> +	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> +	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
>  		DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
> -			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> -			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> +			uc_fw->major_ver_found, uc_fw->minor_ver_found,
> +			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>  		err = -ENOEXEC;
>  		goto fail;
>  	}
>
>  	DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> -			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> -			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> +			uc_fw->major_ver_found, uc_fw->minor_ver_found,
> +			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>
>  	mutex_lock(&dev->struct_mutex);
>  	obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
> @@ -643,31 +643,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
>  		goto fail;
>  	}
>
> -	guc_fw->guc_fw_obj = obj;
> -	guc_fw->guc_fw_size = fw->size;
> +	uc_fw->uc_fw_obj = obj;
> +	uc_fw->uc_fw_size = fw->size;
>
>  	DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> -			guc_fw->guc_fw_obj);
> +			uc_fw->uc_fw_obj);
>
>  	release_firmware(fw);
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> +	uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
>  	return;
>
>  fail:
>  	DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> -		err, fw, guc_fw->guc_fw_obj);
> +		err, fw, uc_fw->uc_fw_obj);
>  	DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
> -		  guc_fw->guc_fw_path, err);
> +		  uc_fw->uc_fw_path, err);
>
>  	mutex_lock(&dev->struct_mutex);
> -	obj = guc_fw->guc_fw_obj;
> +	obj = uc_fw->uc_fw_obj;
>  	if (obj)
>  		drm_gem_object_unreference(&obj->base);
> -	guc_fw->guc_fw_obj = NULL;
> +	uc_fw->uc_fw_obj = NULL;
>  	mutex_unlock(&dev->struct_mutex);
>
>  	release_firmware(fw);		/* OK even if fw is NULL */
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> +	uc_fw->fetch_status = UC_FIRMWARE_FAIL;
>  }
>
>  /**
> @@ -682,7 +682,7 @@ fail:
>  void intel_guc_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>  	const char *fw_path;
>
>  	/* A negative value means "use platform default" */
> @@ -695,24 +695,24 @@ void intel_guc_init(struct drm_device *dev)
>  		fw_path = NULL;
>  	} else if (IS_SKYLAKE(dev)) {
>  		fw_path = I915_SKL_GUC_UCODE;
> -		guc_fw->guc_fw_major_wanted = 6;
> -		guc_fw->guc_fw_minor_wanted = 1;
> +		guc_fw->major_ver_wanted = 6;
> +		guc_fw->minor_ver_wanted = 1;
>  	} else if (IS_BROXTON(dev)) {
>  		fw_path = I915_BXT_GUC_UCODE;
> -		guc_fw->guc_fw_major_wanted = 8;
> -		guc_fw->guc_fw_minor_wanted = 7;
> +		guc_fw->major_ver_wanted = 8;
> +		guc_fw->minor_ver_wanted = 7;
>  	} else if (IS_KABYLAKE(dev)) {
>  		fw_path = I915_KBL_GUC_UCODE;
> -		guc_fw->guc_fw_major_wanted = 9;
> -		guc_fw->guc_fw_minor_wanted = 14;
> +		guc_fw->major_ver_wanted = 9;
> +		guc_fw->minor_ver_wanted = 14;
>  	} else {
>  		fw_path = "";	/* unknown device */
>  	}
>
> -	guc_fw->guc_dev = dev;
> -	guc_fw->guc_fw_path = fw_path;
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> +	guc_fw->uc_dev = dev;
> +	guc_fw->uc_fw_path = fw_path;
> +	guc_fw->fetch_status = UC_FIRMWARE_NONE;
> +	guc_fw->load_status = UC_FIRMWARE_NONE;
>
>  	/* Early (and silent) return if GuC loading is disabled */
>  	if (!i915.enable_guc_loading)
> @@ -722,9 +722,9 @@ void intel_guc_init(struct drm_device *dev)
>  	if (*fw_path == '\0')
>  		return;
>
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> +	guc_fw->fetch_status = UC_FIRMWARE_PENDING;
>  	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> -	guc_fw_fetch(dev, guc_fw);
> +	intel_uc_fw_fetch(dev, guc_fw);
>  	/* status must now be FAIL or SUCCESS */
>  }
>
> @@ -735,17 +735,17 @@ void intel_guc_init(struct drm_device *dev)
>  void intel_guc_fini(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>
>  	mutex_lock(&dev->struct_mutex);
>  	direct_interrupts_to_host(dev_priv);
>  	i915_guc_submission_disable(dev_priv);
>  	i915_guc_submission_fini(dev_priv);
>
> -	if (guc_fw->guc_fw_obj)
> -		drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
> -	guc_fw->guc_fw_obj = NULL;
> +	if (guc_fw->uc_fw_obj)
> +		drm_gem_object_unreference(&guc_fw->uc_fw_obj->base);
> +	guc_fw->uc_fw_obj = NULL;
>  	mutex_unlock(&dev->struct_mutex);
>
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> +	guc_fw->fetch_status = UC_FIRMWARE_NONE;
>  }
>

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Re: [PATCH v3 1/6] drm/i915/guc: Make the GuC fw loading helper functions general

[Dave Gordon]

On 11/08/16 11:49, Dave Gordon wrote:
> On 06/07/16 15:24, Peter Antoine wrote:
>> Rename some of the GuC fw loading code to make them more general. We
>> will utilise them for HuC loading as well.
>>      s/intel_guc_fw/intel_uc_fw/g
>>      s/GUC_FIRMWARE/UC_FIRMWARE/g
>>
>> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
>> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
>> same purpose.
>>
>> v2: rebased on top of nightly.
>>     reapplied the search/replace as upstream code as changed.
>> v3: rebased again on drm-nightly.
>>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
>
> R-b can carry over again, but this will need (ANOTHER!) rebase as Chris
> has nuked one of the functions called below.
>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
>>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
>>  drivers/gpu/drm/i915/intel_guc.h           |  39 ++++----
>>  drivers/gpu/drm/i915/intel_guc_loader.c    | 146
>> ++++++++++++++---------------
>>  4 files changed, 101 insertions(+), 100 deletions(-)

Ignore previous message, replied to wrong version :(

.Dave.

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