* [RFC] msm8992/msm8994: Google Nexus 5X/6P initial board support
@ 2016-07-08 0:41 ` Jeremy McNicoll
0 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-08 0:41 UTC (permalink / raw)
To: linux-arm-msm, linux-arm-kernel; +Cc: andy.gross, stephen.boyd, mail, jeremymc
[RFC] msm8992/msm8994: Google Nexus 5X/6P initial board support
This is a pure msm8992/msm8994 SOC (BullHead/Angler) forward port from [1].
Only 1 CPU of 6(5X)/8(6P) is supported currently, running an initrd[4]. Serial
console output is fully functional through the earjack debug cable on both. [3]
This will allow others to start testing and porting other pieces of the SOC.
Myself and others are planning on submitting more functionality as more
common SOC components are mainlined and have been tested. Gotta start some where!
Now that the initial basic board port is complete it should make it easier
for others to be able to help with additional functionality and testing.
Global clock is common between both msm8992 and msm8994.
Layout and structure of the original 3.10 DTS was maintained and only changes
needed for mainline were made everything else got stripped out as it was
not validated. Further more there were no bindings and thus would not
function as expected.
The initrd/image creation instructions used for testing is available here [4].
Maintainers file update was omitted and will be updated once we get acceptance of
these changes.
Updates and additions were made in boot/dts/lge rather than boot/dts/lg as this
was the location for 3.10.
Alternatively the original 3.10 DTS SOC changes could have gone through
gregKH's staging tree as is, followed by a number of patches to make it
work correctly. But greg's tree is for drivers only, not SOCs. ;-(
SOC info:
---------
(Nexus 5X/bullhead):
msm8992, msm808 [see 2 below]
tested CPU: AArch64 Processor [410fd033] revision 3
(Nexus 6P/Angler):
msm8994, msm810 [see 5 below]
tested CPU: AArch64 Processor [410fd032] revision 2
================
[1] https://android.googlesource.com/kernel/msm.git
(Nexus 5X) branch: android-msm-bullhead-3.10-marshmallow-dr1.6
Change-Id: I3d1ca38d518e5705b653487bfa95085873247f1c
(Nexus 6P) branch: android-msm-angler-3.10-marshmallow-mr1
Commit ID: 3a7f5a4e9c0f5fd4f8ee7bc3f3a204bba9dab60a
[2] http://system-on-a-chip.specout.com/l/1107/Qualcomm-Snapdragon-808-MSM8992
[3] http://people.redhat.com/jmcnicol/nexus_debug/
[4] http://people.redhat.com/~jmcnicol/InitRD.txt
[5] http://system-on-a-chip.specout.com/l/1106/Qualcomm-Snapdragon-810-MSM8994
================
Bastian Köcher (2):
msm8994 clocks: global clock support Global clock support for the
msm8994 SOC.
arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
Jeremy McNicoll (2):
arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
arm64: dts: msm8992 default serial config
.../devicetree/bindings/clock/qcom,gcc.txt | 2 +
arch/arm64/Kconfig.platforms | 25 +
arch/arm64/boot/dts/Makefile | 2 +
arch/arm64/boot/dts/huawei/Makefile | 5 +
.../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 +
arch/arm64/boot/dts/lge/Makefile | 5 +
.../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +
arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 +
arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++
arch/arm64/configs/angler_defconfig | 666 ++++++
arch/arm64/configs/bullhead_defconfig | 377 +++
arch/arm64/configs/msm8992_defconfig | 5 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-msm8994.c | 2501 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8994.h | 145 ++
19 files changed, 4390 insertions(+)
create mode 100644 arch/arm64/boot/dts/huawei/Makefile
create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
create mode 100644 arch/arm64/boot/dts/lge/Makefile
create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
create mode 100644 arch/arm64/configs/angler_defconfig
create mode 100644 arch/arm64/configs/bullhead_defconfig
create mode 100644 arch/arm64/configs/msm8992_defconfig
create mode 100644 drivers/clk/qcom/gcc-msm8994.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8994.h
--
2.6.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC] msm8992/msm8994: Google Nexus 5X/6P initial board support
@ 2016-07-08 0:41 ` Jeremy McNicoll
0 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-08 0:41 UTC (permalink / raw)
To: linux-arm-kernel
[RFC] msm8992/msm8994: Google Nexus 5X/6P initial board support
This is a pure msm8992/msm8994 SOC (BullHead/Angler) forward port from [1].
Only 1 CPU of 6(5X)/8(6P) is supported currently, running an initrd[4]. Serial
console output is fully functional through the earjack debug cable on both. [3]
This will allow others to start testing and porting other pieces of the SOC.
Myself and others are planning on submitting more functionality as more
common SOC components are mainlined and have been tested. Gotta start some where!
Now that the initial basic board port is complete it should make it easier
for others to be able to help with additional functionality and testing.
Global clock is common between both msm8992 and msm8994.
Layout and structure of the original 3.10 DTS was maintained and only changes
needed for mainline were made everything else got stripped out as it was
not validated. Further more there were no bindings and thus would not
function as expected.
The initrd/image creation instructions used for testing is available here [4].
Maintainers file update was omitted and will be updated once we get acceptance of
these changes.
Updates and additions were made in boot/dts/lge rather than boot/dts/lg as this
was the location for 3.10.
Alternatively the original 3.10 DTS SOC changes could have gone through
gregKH's staging tree as is, followed by a number of patches to make it
work correctly. But greg's tree is for drivers only, not SOCs. ;-(
SOC info:
---------
(Nexus 5X/bullhead):
msm8992, msm808 [see 2 below]
tested CPU: AArch64 Processor [410fd033] revision 3
(Nexus 6P/Angler):
msm8994, msm810 [see 5 below]
tested CPU: AArch64 Processor [410fd032] revision 2
================
[1] https://android.googlesource.com/kernel/msm.git
(Nexus 5X) branch: android-msm-bullhead-3.10-marshmallow-dr1.6
Change-Id: I3d1ca38d518e5705b653487bfa95085873247f1c
(Nexus 6P) branch: android-msm-angler-3.10-marshmallow-mr1
Commit ID: 3a7f5a4e9c0f5fd4f8ee7bc3f3a204bba9dab60a
[2] http://system-on-a-chip.specout.com/l/1107/Qualcomm-Snapdragon-808-MSM8992
[3] http://people.redhat.com/jmcnicol/nexus_debug/
[4] http://people.redhat.com/~jmcnicol/InitRD.txt
[5] http://system-on-a-chip.specout.com/l/1106/Qualcomm-Snapdragon-810-MSM8994
================
Bastian K?cher (2):
msm8994 clocks: global clock support Global clock support for the
msm8994 SOC.
arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
Jeremy McNicoll (2):
arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
arm64: dts: msm8992 default serial config
.../devicetree/bindings/clock/qcom,gcc.txt | 2 +
arch/arm64/Kconfig.platforms | 25 +
arch/arm64/boot/dts/Makefile | 2 +
arch/arm64/boot/dts/huawei/Makefile | 5 +
.../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 +
arch/arm64/boot/dts/lge/Makefile | 5 +
.../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +
arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 +
arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++
arch/arm64/configs/angler_defconfig | 666 ++++++
arch/arm64/configs/bullhead_defconfig | 377 +++
arch/arm64/configs/msm8992_defconfig | 5 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-msm8994.c | 2501 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8994.h | 145 ++
19 files changed, 4390 insertions(+)
create mode 100644 arch/arm64/boot/dts/huawei/Makefile
create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
create mode 100644 arch/arm64/boot/dts/lge/Makefile
create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
create mode 100644 arch/arm64/configs/angler_defconfig
create mode 100644 arch/arm64/configs/bullhead_defconfig
create mode 100644 arch/arm64/configs/msm8992_defconfig
create mode 100644 drivers/clk/qcom/gcc-msm8994.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8994.h
--
2.6.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
2016-07-08 0:41 ` Jeremy McNicoll
(?)
@ 2016-07-08 0:41 ` Jeremy McNicoll
2016-07-08 17:41 ` Andy Gross
-1 siblings, 1 reply; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-08 0:41 UTC (permalink / raw)
To: linux-arm-msm, linux-arm-kernel; +Cc: andy.gross, stephen.boyd, mail, jeremymc
Initial device tree support for Qualcomm MSM8992 SoC and
LG Bullhead / Google Nexus 5X support.
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
---
arch/arm64/Kconfig.platforms | 12 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/lge/Makefile | 5 +
.../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +++
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +++
arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++++++++++++
arch/arm64/configs/bullhead_defconfig | 377 +++++++++++++++++++++
arch/arm64/configs/msm8992_defconfig | 5 +
8 files changed, 700 insertions(+)
create mode 100644 arch/arm64/boot/dts/lge/Makefile
create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
create mode 100644 arch/arm64/configs/bullhead_defconfig
create mode 100644 arch/arm64/configs/msm8992_defconfig
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 7ef1d05..515e669 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -86,6 +86,18 @@ config ARCH_QCOM
help
This enables support for the ARMv8 based Qualcomm chipsets.
+config ARCH_MSM8992
+ bool "Qualcomm MSM8992"
+ depends on ARCH_QCOM
+ help
+ This enables support for the Qualcomm MSM8992 SoC.
+
+config MACH_LGE
+ bool "LGE BullHead (MSM8992)"
+ depends on ARCH_QCOM
+ help
+ This enables support for the LGE Nexus 5X - BullHead MSM8992.
+
config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 6e199c9..bde90fb 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ dts-dirs += marvell
dts-dirs += mediatek
dts-dirs += nvidia
dts-dirs += qcom
+dts-dirs += lge
dts-dirs += renesas
dts-dirs += rockchip
dts-dirs += socionext
diff --git a/arch/arm64/boot/dts/lge/Makefile b/arch/arm64/boot/dts/lge/Makefile
new file mode 100644
index 0000000..f4e7860
--- /dev/null
+++ b/arch/arm64/boot/dts/lge/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_MACH_LGE) += msm8992-bullhead-rev-101.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
new file mode 100644
index 0000000..860cded
--- /dev/null
+++ b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
@@ -0,0 +1,41 @@
+/* Copyright (c) 2015, LGE Inc. All rights reserved.
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "../qcom/msm8992.dtsi"
+
+/ {
+ model = "LGE MSM8992 BULLHEAD rev-1.01";
+ compatible = "qcom,msm8992";
+ qcom,board-id = <0xb64 0>;
+};
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ soc {
+ serial@f991e000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
new file mode 100644
index 0000000..d2a26f0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&msmgpio {
+ blsp1_uart2_default: blsp1_uart2_default {
+ pinmux {
+ function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ };
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart2_sleep: blsp1_uart2_sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ };
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
new file mode 100644
index 0000000..fa92a1a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -0,0 +1,221 @@
+/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/memreserve/ 0x00000000 0x00001000;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8994.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM 8992";
+ compatible = "qcom,msm8992";
+ qcom,msm-id = <251 0>, <252 0>;
+ qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ };
+ };
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ next-level-cache = <&L2_0>;
+ // The currents(uA) correspond to the frequencies in the
+ // frequency table.
+ current = < 18250 //384000 kHZ
+ 24330 //460800 kHZ
+ 26920 //600000 kHZ
+ 34600 //672000 kHz
+ 38150 //787200 kHZ
+ 46880 //864000 kHZ
+ 55940 //960000 kHZ
+ 81740 //1248000 kHZ
+ 105870>; //1440000 kHZ
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+ };
+
+ soc: soc { };
+
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ device_type = "memory";
+ reg = <0 0 0 0>;
+
+ peripheral_mem: peripheral_region@0 {
+ linux,reserve-contiguous-region;
+ linux,reserve-region;
+ linux,remove-completely;
+ reg = <0 0x07400000 0 0x1c00000>;
+ label = "peripheral_mem";
+ };
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@f9000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xf9000000 0x1000>,
+ <0xf9002000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 4 0xf08>,
+ <1 1 0xf08>;
+ clock-frequency = <19200000>;
+ };
+
+ timer@f9020000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xf9020000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@f9021000 {
+ frame-number = <0>;
+ interrupts = <0 9 0x4>,
+ <0 8 0x4>;
+ reg = <0xf9021000 0x1000>,
+ <0xf9022000 0x1000>;
+ };
+
+ frame@f9023000 {
+ frame-number = <1>;
+ interrupts = <0 10 0x4>;
+ reg = <0xf9023000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9024000 {
+ frame-number = <2>;
+ interrupts = <0 11 0x4>;
+ reg = <0xf9024000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9025000 {
+ frame-number = <3>;
+ interrupts = <0 12 0x4>;
+ reg = <0xf9025000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9026000 {
+ frame-number = <4>;
+ interrupts = <0 13 0x4>;
+ reg = <0xf9026000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9027000 {
+ frame-number = <5>;
+ interrupts = <0 14 0x4>;
+ reg = <0xf9027000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9028000 {
+ frame-number = <6>;
+ interrupts = <0 15 0x4>;
+ reg = <0xf9028000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ restart@fc4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
+
+ msmgpio: pinctrl@fd510000 {
+ compatible = "qcom,msm8994-pinctrl", "qcom,msm8974-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ blsp1_uart2: serial@f991e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991e000 0x1000>;
+ interrupts = <0 108 0>;
+ status = "disabled";
+ clock-names = "core", "iface";
+ clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ };
+
+ clock_gcc: qcom,gcc@fc400000 {
+ compatible = "qcom,gcc-8994";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xfc400000 0x2000>;
+ clock-names = "xo", "xo_a_clk";
+ };
+
+ clock_rpm: qcom,rpmcc@fc401880 {
+ compatible = "qcom,rpmcc";
+ reg = <0xfc401880 0x4>;
+ reg-names = "cc_base";
+ #clock-cells = <1>;
+ };
+
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+#include "msm8992-pins.dtsi"
diff --git a/arch/arm64/configs/bullhead_defconfig b/arch/arm64/configs/bullhead_defconfig
new file mode 100644
index 0000000..5c082e6
--- /dev/null
+++ b/arch/arm64/configs/bullhead_defconfig
@@ -0,0 +1,377 @@
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_SCHED_HMP=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_PROFILING=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_MSM=y
+CONFIG_ARCH_MSM8994=y
+CONFIG_ARCH_MSM8994_V1_TLBI_WA=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_MSM8992=y
+CONFIG_MACH_LGE=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_MSM_GCC_8994=y
+# CONFIG_PCIE_QCOM is not set
+CONFIG_ARM64_A57_ERRATA_832075=y
+# CONFIG_SMP is not set
+CONFIG_SCHED_MC=y
+CONFIG_ARCH_WANTS_CTXSW_LOGGING=y
+CONFIG_NR_CPUS=1
+CONFIG_PREEMPT=y
+CONFIG_HZ_300=y
+CONFIG_ARMV7_COMPAT=y
+CONFIG_BALANCE_ANON_FILE_RECLAIM=y
+CONFIG_ZSMALLOC=y
+CONFIG_SECCOMP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_COMPAT=y
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=0
+CONFIG_PM_RUNTIME=y
+CONFIG_SUSPEND_TIME=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+CONFIG_CPU_BOOST=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+# CONFIG_CPU_IDLE_GOV_MENU is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_REJECT_SKERR=y
+CONFIG_NF_NAT_IPV4=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_L2TP=y
+CONFIG_L2TP_DEBUGFS=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
+CONFIG_BRIDGE=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_RMNET_DATA=y
+CONFIG_RMNET_DATA_FC=y
+CONFIG_SOCKEV_NLMCAST=y
+CONFIG_BT=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+CONFIG_RFKILL=y
+CONFIG_NFC=y
+CONFIG_NFC_PN548=y
+CONFIG_IPC_ROUTER=y
+CONFIG_IPC_ROUTER_SECURITY=y
+CONFIG_CMA=y
+CONFIG_ARM_CCI=y
+CONFIG_ZRAM=y
+CONFIG_ZRAM_LZ4_COMPRESS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_UID_STAT=y
+CONFIG_QSEECOM=y
+CONFIG_TI_DRV2667=y
+CONFIG_EARJACK_DEBUGGER=y
+CONFIG_UID_CPUTIME=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_REQ_CRYPT=y
+CONFIG_DM_VERITY=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_RNDIS_IPA=y
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_CDC_EEM=y
+CONFIG_USB_NET_CDC_MBIM=y
+CONFIG_USB_NET_DM9601=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_GL620A=y
+CONFIG_USB_NET_PLUSB=y
+CONFIG_USB_NET_MCS7830=y
+CONFIG_USB_NET_RNDIS_HOST=y
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_CX82310_ETH=y
+CONFIG_USB_NET_KALMIA=y
+CONFIG_USB_NET_QMI_WWAN=y
+CONFIG_USB_HSO=y
+CONFIG_USB_NET_INT51X1=y
+CONFIG_USB_IPHETH=y
+CONFIG_USB_SIERRA_NET=y
+CONFIG_USB_VL600=y
+CONFIG_CNSS=y
+CONFIG_BUS_AUTO_SUSPEND=y
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
+CONFIG_CLD_LL_CORE=y
+CONFIG_ATH_CARDS=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_v21 is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_GPIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_MSM_ADSPRPC=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_CONTEXTHUB=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_PINCTRL=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_PINCTRL_MSM=y
+CONFIG_PINCTRL_MSM8X74=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_QPNP_PIN=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_MSM_DLOAD_MODE=y
+CONFIG_MSM_PM=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PROXY_CONSUMER=y
+CONFIG_REGULATOR_MEM_ACC=y
+CONFIG_REGULATOR_TPS65132=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_REGULATOR_RPM_SMD=y
+CONFIG_REGULATOR_QPNP=y
+CONFIG_REGULATOR_QPNP_LABIBB=y
+CONFIG_REGULATOR_SPM=y
+CONFIG_REGULATOR_CPR=y
+CONFIG_REGULATOR_DW8768=y
+# CONFIG_MEDIA_SUPPORT is not set
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_SOUND is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_SOC is not set
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_PHY=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+# CONFIG_USB_DWC3_MSM is not set
+CONFIG_USB_G_ANDROID=y
+# CONFIG_MMC is not set
+CONFIG_RTC_CLASS=y
+# CONFIG_UIO=y
+CONFIG_STAGING=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_MSM_EVENT_TIMER=y
+CONFIG_MSM_COMMON_LOG=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_FS_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_OOPS_LOG_BUFFER=y
+CONFIG_PANIC_ON_DATA_CORRUPTION=y
+CONFIG_ARM64_PTDUMP=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_PID_IN_CONTEXTIDR=y
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_SELINUX is not set
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
diff --git a/arch/arm64/configs/msm8992_defconfig b/arch/arm64/configs/msm8992_defconfig
new file mode 100644
index 0000000..f673a27
--- /dev/null
+++ b/arch/arm64/configs/msm8992_defconfig
@@ -0,0 +1,5 @@
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SCHED_HMP=y
+CONFIG_NAMESPACES=y
+# CONFIG_CORESIGHT is not set
--
2.6.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [RFC 2/4] msm8994 clocks: global clock support Global clock support for the msm8994 SOC.
2016-07-08 0:41 ` Jeremy McNicoll
(?)
(?)
@ 2016-07-08 0:41 ` Jeremy McNicoll
2016-07-12 2:30 ` Jeremy McNicoll
-1 siblings, 1 reply; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-08 0:41 UTC (permalink / raw)
To: linux-arm-msm, linux-arm-kernel; +Cc: andy.gross, stephen.boyd, mail, jeremymc
From: Bastian Köcher <mail@kchr.de>
The clock definition was ported from the Google 3.10 kernel tree to
work with the latest kernel.
Signed-off-by: Bastian Köcher <mail@kchr.de>
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
---
.../devicetree/bindings/clock/qcom,gcc.txt | 2 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-msm8994.c | 2501 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8994.h | 145 ++
5 files changed, 2658 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-msm8994.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8994.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 9a60fde..a1dc2fe 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -14,6 +14,8 @@ Required properties :
"qcom,gcc-msm8974"
"qcom,gcc-msm8974pro"
"qcom,gcc-msm8974pro-ac"
+ "qcom,gcc-msm8994"
+ "qcom,gcc-msm8994v2"
"qcom,gcc-msm8996"
- reg : shall contain base register location and length
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 95e3b3e..6687c7f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -115,6 +115,15 @@ config MSM_MMCC_8974
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+config MSM_GCC_8994
+ tristate "MSM8994 Global Clock Controller"
+ select QCOM_GDSC
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the global clock controller on msm8994 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, SATA, PCIe, etc.
+
config MSM_GCC_8996
tristate "MSM8996 Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 2a25f4e..551a64d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
+obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
new file mode 100644
index 0000000..3897cfd
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -0,0 +1,2501 @@
+/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gcc-msm8994.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPLL4,
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 2 },
+};
+
+static const char * const gcc_xo_gpll0_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+};
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+static struct clk_fixed_factor xo = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "xo",
+ .parent_names = (const char *[]) { "xo_board" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll0_early = {
+ .offset = 0x00000,
+ .clkr = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll0_early",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x00000,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll0",
+ .parent_names = (const char *[]) { "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4_early = {
+ .offset = 0x1DC0,
+ .clkr = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll4_early",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x1DC0,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll4",
+ .parent_names = (const char *[]) { "gpll4_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+ F(50000000, P_GPLL0, 12, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(171430000, P_GPLL0, 3.5, 0, 0),
+ { }
+};
+
+static struct freq_tbl ftbl_ufs_axi_clk_src_v2[] = {
+ F(50000000, P_GPLL0, 12, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(171430000, P_GPLL0, 3.5, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+ .cmd_rcgr = 0x1D68,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_ufs_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "ufs_axi_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_usb30_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(125000000, P_GPLL0, 1, 5, 24),
+ { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+ .cmd_rcgr = 0x03D4,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_usb30_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "usb30_master_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0660,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blspqup_spi_apps_clk_src_v2[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x064C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x06E0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(46150000, P_GPLL0, 13, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x06CC,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0760,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp1_qup3_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x074C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp1_qup3_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x07E0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp1_qup4_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x07CC,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp1_qup4_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0860,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup5_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+ .cmd_rcgr = 0x084C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup5_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x08E0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup6_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(41380000, P_GPLL0, 14.5, 0, 0),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+ .cmd_rcgr = 0x08CC,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_qup6_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
+ F(3686400, P_GPLL0, 1, 96, 15625),
+ F(7372800, P_GPLL0, 1, 192, 15625),
+ F(14745600, P_GPLL0, 1, 384, 15625),
+ F(16000000, P_GPLL0, 5, 2, 15),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 5, 1, 5),
+ F(32000000, P_GPLL0, 1, 4, 75),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(46400000, P_GPLL0, 1, 29, 375),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(51200000, P_GPLL0, 1, 32, 375),
+ F(56000000, P_GPLL0, 1, 7, 75),
+ F(58982400, P_GPLL0, 1, 1536, 15625),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(63160000, P_GPLL0, 9.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x068C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x070C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
+ .cmd_rcgr = 0x078C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_uart3_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
+ .cmd_rcgr = 0x080C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_uart4_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
+ .cmd_rcgr = 0x088C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_uart5_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
+ .cmd_rcgr = 0x090C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp1_uart6_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x09A0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp2_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x098C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp2_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup1_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0A20,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp2_qup2_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x0A0C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp2_qup2_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup2_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0AA0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp2_qup3_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x0A8C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp2_qup3_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup3_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0B20,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp2_qup4_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x0B0C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp2_qup4_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup4_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0BA0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup5_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp2_qup5_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
+ .cmd_rcgr = 0x0B8C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp2_qup5_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup5_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0C20,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup6_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
+ .cmd_rcgr = 0x0C0C,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_qup6_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x09CC,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_uart1_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x0A4C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_uart2_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
+ .cmd_rcgr = 0x0ACC,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_uart3_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
+ .cmd_rcgr = 0x0B4C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_uart4_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
+ .cmd_rcgr = 0x0BCC,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_uart5_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
+ .cmd_rcgr = 0x0C4C,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "blsp2_uart6_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_gp1_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x1904,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gp1_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_gp2_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x1944,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_gp2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gp2_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_gp3_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x1984,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_gp3_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gp3_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
+ F(1011000, P_XO, 1, 1, 19),
+ { }
+};
+
+static struct clk_rcg2 pcie_0_aux_clk_src = {
+ .cmd_rcgr = 0x1B00,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .freq_tbl = ftbl_pcie_0_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "pcie_0_aux_clk_src",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
+ F(125000000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcie_0_pipe_clk_src = {
+ .cmd_rcgr = 0x1ADC,
+ .hid_width = 5,
+ .freq_tbl = ftbl_pcie_pipe_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "pcie_0_pipe_clk_src",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
+ F(1011000, P_XO, 1, 1, 19),
+ { }
+};
+
+static struct clk_rcg2 pcie_1_aux_clk_src = {
+ .cmd_rcgr = 0x1B80,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .freq_tbl = ftbl_pcie_1_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "pcie_1_aux_clk_src",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 pcie_1_pipe_clk_src = {
+ .cmd_rcgr = 0x1B5C,
+ .hid_width = 5,
+ .freq_tbl = ftbl_pcie_pipe_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "pcie_1_pipe_clk_src",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_pdm2_clk_src[] = {
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+ .cmd_rcgr = 0x0CD0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_pdm2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "pdm2_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0, 15, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 2, 0, 0),
+ F(384000000, P_GPLL4, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x04D0,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll4,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0, 15, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x0510,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 sdcc3_apps_clk_src = {
+ .cmd_rcgr = 0x0550,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "sdcc3_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 sdcc4_apps_clk_src = {
+ .cmd_rcgr = 0x0590,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "sdcc4_apps_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
+ F(105500, P_XO, 1, 1, 182),
+ { }
+};
+
+static struct clk_rcg2 tsif_ref_clk_src = {
+ .cmd_rcgr = 0x0D90,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .freq_tbl = ftbl_tsif_ref_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "tsif_ref_clk_src",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x03E8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "usb30_mock_utmi_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+ F(1200000, P_XO, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+ .cmd_rcgr = 0x1414,
+ .hid_width = 5,
+ .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "usb3_phy_aux_clk_src",
+ .parent_names = (const char *[]) { "xo" },
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
+ F(75000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb_hs_system_clk_src = {
+ .cmd_rcgr = 0x0490,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_usb_hs_system_clk_src,
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "usb_hs_system_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x05C4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1484,
+ .enable_mask = BIT(17),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x0648,
+ .clkr = {
+ .enable_reg = 0x0648,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x0644,
+ .clkr = {
+ .enable_reg = 0x0644,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x06C8,
+ .clkr = {
+ .enable_reg = 0x06C8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x06C4,
+ .clkr = {
+ .enable_reg = 0x06C4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x0748,
+ .clkr = {
+ .enable_reg = 0x0748,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x0744,
+ .clkr = {
+ .enable_reg = 0x0744,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x07C8,
+ .clkr = {
+ .enable_reg = 0x07C8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x07C4,
+ .clkr = {
+ .enable_reg = 0x07C4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+ .halt_reg = 0x0848,
+ .clkr = {
+ .enable_reg = 0x0848,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup5_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup5_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+ .halt_reg = 0x0844,
+ .clkr = {
+ .enable_reg = 0x0844,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup5_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup5_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+ .halt_reg = 0x08C8,
+ .clkr = {
+ .enable_reg = 0x08C8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup6_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup6_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+ .halt_reg = 0x08C4,
+ .clkr = {
+ .enable_reg = 0x08C4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_qup6_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_qup6_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x0684,
+ .clkr = {
+ .enable_reg = 0x0684,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x0704,
+ .clkr = {
+ .enable_reg = 0x0704,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+ .halt_reg = 0x0784,
+ .clkr = {
+ .enable_reg = 0x0784,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_uart3_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_uart3_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart4_apps_clk = {
+ .halt_reg = 0x0804,
+ .clkr = {
+ .enable_reg = 0x0804,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_uart4_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_uart4_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart5_apps_clk = {
+ .halt_reg = 0x0884,
+ .clkr = {
+ .enable_reg = 0x0884,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_uart5_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_uart5_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart6_apps_clk = {
+ .halt_reg = 0x0904,
+ .clkr = {
+ .enable_reg = 0x0904,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp1_uart6_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp1_uart6_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+ .halt_reg = 0x0944,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1484,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+ .halt_reg = 0x0988,
+ .clkr = {
+ .enable_reg = 0x0988,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+ .halt_reg = 0x0984,
+ .clkr = {
+ .enable_reg = 0x0984,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup1_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+ .halt_reg = 0x0A08,
+ .clkr = {
+ .enable_reg = 0x0A08,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+ .halt_reg = 0x0A04,
+ .clkr = {
+ .enable_reg = 0x0A04,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup2_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+ .halt_reg = 0x0A88,
+ .clkr = {
+ .enable_reg = 0x0A88,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+ .halt_reg = 0x0A84,
+ .clkr = {
+ .enable_reg = 0x0A84,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup3_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+ .halt_reg = 0x0B08,
+ .clkr = {
+ .enable_reg = 0x0B08,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+ .halt_reg = 0x0B04,
+ .clkr = {
+ .enable_reg = 0x0B04,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup4_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
+ .halt_reg = 0x0B88,
+ .clkr = {
+ .enable_reg = 0x0B88,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup5_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup5_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
+ .halt_reg = 0x0B84,
+ .clkr = {
+ .enable_reg = 0x0B84,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup5_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup5_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
+ .halt_reg = 0x0C08,
+ .clkr = {
+ .enable_reg = 0x0C08,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup6_i2c_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup6_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
+ .halt_reg = 0x0C04,
+ .clkr = {
+ .enable_reg = 0x0C04,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_qup6_spi_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_qup6_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+ .halt_reg = 0x09C4,
+ .clkr = {
+ .enable_reg = 0x09C4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_uart1_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+ .halt_reg = 0x0A44,
+ .clkr = {
+ .enable_reg = 0x0A44,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_uart2_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart3_apps_clk = {
+ .halt_reg = 0x0AC4,
+ .clkr = {
+ .enable_reg = 0x0AC4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_uart3_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_uart3_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart4_apps_clk = {
+ .halt_reg = 0x0B44,
+ .clkr = {
+ .enable_reg = 0x0B44,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_uart4_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_uart4_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart5_apps_clk = {
+ .halt_reg = 0x0BC4,
+ .clkr = {
+ .enable_reg = 0x0BC4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_uart5_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_uart5_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart6_apps_clk = {
+ .halt_reg = 0x0C44,
+ .clkr = {
+ .enable_reg = 0x0C44,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_blsp2_uart6_apps_clk",
+ .parent_names = (const char *[]) {
+ "blsp2_uart6_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x1900,
+ .clkr = {
+ .enable_reg = 0x1900,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]) {
+ "gp1_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x1940,
+ .clkr = {
+ .enable_reg = 0x1940,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]) {
+ "gp2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x1980,
+ .clkr = {
+ .enable_reg = 0x1980,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]) {
+ "gp3_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+ .halt_reg = 0x1AD4,
+ .clkr = {
+ .enable_reg = 0x1AD4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_pcie_0_aux_clk",
+ .parent_names = (const char *[]) {
+ "pcie_0_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+ .halt_reg = 0x1AD8,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1AD8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_pcie_0_pipe_clk",
+ .parent_names = (const char *[]) {
+ "pcie_0_pipe_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_1_aux_clk = {
+ .halt_reg = 0x1B54,
+ .clkr = {
+ .enable_reg = 0x1B54,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_pcie_1_aux_clk",
+ .parent_names = (const char *[]) {
+ "pcie_1_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_1_pipe_clk = {
+ .halt_reg = 0x1B58,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1B58,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_pcie_1_pipe_clk",
+ .parent_names = (const char *[]) {
+ "pcie_1_pipe_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x0CCC,
+ .clkr = {
+ .enable_reg = 0x0CCC,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_pdm2_clk",
+ .parent_names = (const char *[]) {
+ "pdm2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x04C4,
+ .clkr = {
+ .enable_reg = 0x04C4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]) {
+ "sdcc1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x0504,
+ .clkr = {
+ .enable_reg = 0x0504,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]) {
+ "sdcc2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc3_apps_clk = {
+ .halt_reg = 0x0544,
+ .clkr = {
+ .enable_reg = 0x0544,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_sdcc3_apps_clk",
+ .parent_names = (const char *[]) {
+ "sdcc3_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc4_apps_clk = {
+ .halt_reg = 0x0584,
+ .clkr = {
+ .enable_reg = 0x0584,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_sdcc4_apps_clk",
+ .parent_names = (const char *[]) {
+ "sdcc4_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
+ .halt_reg = 0x1D7C,
+ .clkr = {
+ .enable_reg = 0x1D7C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_sys_noc_ufs_axi_clk",
+ .parent_names = (const char *[]) {
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
+ .halt_reg = 0x03FC,
+ .clkr = {
+ .enable_reg = 0x03FC,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_sys_noc_usb3_axi_clk",
+ .parent_names = (const char *[]) {
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_tsif_ref_clk = {
+ .halt_reg = 0x0D88,
+ .clkr = {
+ .enable_reg = 0x0D88,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_tsif_ref_clk",
+ .parent_names = (const char *[]) {
+ "tsif_ref_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+ .halt_reg = 0x1D48,
+ .clkr = {
+ .enable_reg = 0x1D48,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_ufs_axi_clk",
+ .parent_names = (const char *[]) {
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_cfg_clk = {
+ .halt_reg = 0x1D54,
+ .clkr = {
+ .enable_reg = 0x1D54,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_ufs_rx_cfg_clk",
+ .parent_names = (const char *[]) {
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_tx_cfg_clk = {
+ .halt_reg = 0x1D50,
+ .clkr = {
+ .enable_reg = 0x1D50,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_ufs_tx_cfg_clk",
+ .parent_names = (const char *[]) {
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+ .halt_reg = 0x03C8,
+ .clkr = {
+ .enable_reg = 0x03C8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_usb30_master_clk",
+ .parent_names = (const char *[]) {
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+ .halt_reg = 0x03D0,
+ .clkr = {
+ .enable_reg = 0x03D0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_usb30_mock_utmi_clk",
+ .parent_names = (const char *[]) {
+ "usb30_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+ .halt_reg = 0x1408,
+ .clkr = {
+ .enable_reg = 0x1408,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_usb3_phy_aux_clk",
+ .parent_names = (const char *[]) {
+ "usb3_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb_hs_system_clk = {
+ .halt_reg = 0x0484,
+ .clkr = {
+ .enable_reg = 0x0484,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data)
+ {
+ .name = "gcc_usb_hs_system_clk",
+ .parent_names = (const char *[]) {
+ "usb_hs_system_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *gcc_msm8994_clocks[] = {
+ [GPLL0_EARLY] = &gpll0_early.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL4_EARLY] = &gpll4_early.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+ [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+ [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+ [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
+ [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
+ [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+ [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+ [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+ [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+ [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+ [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
+ [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
+ [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+ [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+ [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
+ [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
+ [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
+ [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
+ [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
+ [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
+ [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
+ [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
+ [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
+ [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+ [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+ [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+ [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
+ [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
+ [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
+ [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+ [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
+ [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+ [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+ [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
+ [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
+ [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
+ [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+ [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+ [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
+ [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
+ [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
+ [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
+ [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
+ [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
+ [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+ [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
+ [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
+ [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+ [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+ [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+ [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
+};
+
+static void msm_gcc_8994v2_fixup(void)
+{
+ ufs_axi_clk_src.freq_tbl = ftbl_ufs_axi_clk_src_v2;
+
+ blsp1_qup1_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp1_qup2_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp1_qup3_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp1_qup4_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp1_qup5_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp1_qup6_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp2_qup1_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp2_qup2_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp2_qup3_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp2_qup4_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp2_qup5_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+ blsp2_qup6_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
+}
+
+static const struct regmap_config gcc_msm8994_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x2000,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_msm8994_desc = {
+ .config = &gcc_msm8994_regmap_config,
+ .clks = gcc_msm8994_clocks,
+ .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
+ .resets = NULL,
+ .num_resets = 0,
+ .gdscs = NULL,
+ .num_gdscs = 0,
+};
+
+static const struct of_device_id gcc_msm8994_match_table[] = {
+ { .compatible = "qcom,gcc-8994" },
+ { .compatible = "qcom,gcc-8994v2" },
+ {}
+}
+
+MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
+
+static int gcc_msm8994_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct clk *clk;
+ const char *compat = NULL;
+ int compatlen = 0;
+ bool is_v2 = false;
+
+ clk = devm_clk_register(dev, &xo.hw);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
+ if (!compat || (compatlen <= 0))
+ return -EINVAL;
+
+ is_v2 = !strcmp(compat, "qcom,gcc-8994v2");
+ if (is_v2)
+ msm_gcc_8994v2_fixup();
+
+ return qcom_cc_probe(pdev, &gcc_msm8994_desc);
+}
+
+static struct platform_driver gcc_msm8994_driver = {
+ .probe = gcc_msm8994_probe,
+ .driver = {
+ .name = "gcc-msm8994",
+ .of_match_table = gcc_msm8994_match_table,
+ },
+};
+
+static int __init gcc_msm8994_init(void)
+{
+ return platform_driver_register(&gcc_msm8994_driver);
+}
+core_initcall(gcc_msm8994_init);
+
+static void __exit gcc_msm8994_exit(void)
+{
+ platform_driver_unregister(&gcc_msm8994_driver);
+}
+module_exit(gcc_msm8994_exit);
+
+MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-msm8994");
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
new file mode 100644
index 0000000..0ae494b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
+
+#define GPLL0_EARLY 0
+#define GPLL0 1
+#define GPLL4_EARLY 2
+#define GPLL4 3
+#define UFS_AXI_CLK_SRC 4
+#define USB30_MASTER_CLK_SRC 5
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
+#define BLSP1_UART1_APPS_CLK_SRC 18
+#define BLSP1_UART2_APPS_CLK_SRC 19
+#define BLSP1_UART3_APPS_CLK_SRC 20
+#define BLSP1_UART4_APPS_CLK_SRC 21
+#define BLSP1_UART5_APPS_CLK_SRC 22
+#define BLSP1_UART6_APPS_CLK_SRC 23
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
+#define BLSP2_UART1_APPS_CLK_SRC 36
+#define BLSP2_UART2_APPS_CLK_SRC 37
+#define BLSP2_UART3_APPS_CLK_SRC 38
+#define BLSP2_UART4_APPS_CLK_SRC 39
+#define BLSP2_UART5_APPS_CLK_SRC 40
+#define BLSP2_UART6_APPS_CLK_SRC 41
+#define GP1_CLK_SRC 42
+#define GP2_CLK_SRC 43
+#define GP3_CLK_SRC 44
+#define PCIE_0_AUX_CLK_SRC 45
+#define PCIE_0_PIPE_CLK_SRC 46
+#define PCIE_1_AUX_CLK_SRC 47
+#define PCIE_1_PIPE_CLK_SRC 48
+#define PDM2_CLK_SRC 49
+#define SDCC1_APPS_CLK_SRC 50
+#define SDCC2_APPS_CLK_SRC 51
+#define SDCC3_APPS_CLK_SRC 52
+#define SDCC4_APPS_CLK_SRC 53
+#define TSIF_REF_CLK_SRC 54
+#define USB30_MOCK_UTMI_CLK_SRC 55
+#define USB3_PHY_AUX_CLK_SRC 56
+#define USB_HS_SYSTEM_CLK_SRC 57
+#define GCC_BLSP1_AHB_CLK 58
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
+#define GCC_BLSP1_UART1_APPS_CLK 71
+#define GCC_BLSP1_UART2_APPS_CLK 72
+#define GCC_BLSP1_UART3_APPS_CLK 73
+#define GCC_BLSP1_UART4_APPS_CLK 74
+#define GCC_BLSP1_UART5_APPS_CLK 75
+#define GCC_BLSP1_UART6_APPS_CLK 76
+#define GCC_BLSP2_AHB_CLK 77
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
+#define GCC_BLSP2_UART1_APPS_CLK 90
+#define GCC_BLSP2_UART2_APPS_CLK 91
+#define GCC_BLSP2_UART3_APPS_CLK 92
+#define GCC_BLSP2_UART4_APPS_CLK 93
+#define GCC_BLSP2_UART5_APPS_CLK 94
+#define GCC_BLSP2_UART6_APPS_CLK 95
+#define GCC_GP1_CLK 96
+#define GCC_GP2_CLK 97
+#define GCC_GP3_CLK 98
+#define GCC_PCIE_0_AUX_CLK 99
+#define GCC_PCIE_0_PIPE_CLK 100
+#define GCC_PCIE_1_AUX_CLK 101
+#define GCC_PCIE_1_PIPE_CLK 102
+#define GCC_PDM2_CLK 103
+#define GCC_SDCC1_APPS_CLK 104
+#define GCC_SDCC2_APPS_CLK 105
+#define GCC_SDCC3_APPS_CLK 106
+#define GCC_SDCC4_APPS_CLK 107
+#define GCC_SYS_NOC_UFS_AXI_CLK 108
+#define GCC_SYS_NOC_USB3_AXI_CLK 109
+#define GCC_TSIF_REF_CLK 110
+#define GCC_UFS_AXI_CLK 111
+#define GCC_UFS_RX_CFG_CLK 112
+#define GCC_UFS_TX_CFG_CLK 113
+#define GCC_USB30_MASTER_CLK 114
+#define GCC_USB30_MOCK_UTMI_CLK 115
+#define GCC_USB3_PHY_AUX_CLK 116
+#define GCC_USB_HS_SYSTEM_CLK 117
+
+/* Indexes for GDSCs */
+#define BIMC_GDSC 0
+#define VENUS_GDSC 1
+#define MDSS_GDSC 2
+#define JPEG_GDSC 3
+#define VFE_GDSC 4
+#define OXILI_GDSC 5
+
+#endif
--
2.6.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
2016-07-08 0:41 ` Jeremy McNicoll
` (2 preceding siblings ...)
(?)
@ 2016-07-08 0:41 ` Jeremy McNicoll
2016-07-08 17:35 ` Andy Gross
2016-09-21 1:12 ` Andy Gross
-1 siblings, 2 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-08 0:41 UTC (permalink / raw)
To: linux-arm-msm, linux-arm-kernel; +Cc: andy.gross, stephen.boyd, mail, jeremymc
From: Bastian Köcher <mail@kchr.de>
Initial device tree support for Qualcomm MSM8994 SoC and
Huawei Angler / Google Nexus 6P support.
The device tree and the angler_defconfig are based on the
device tree from the Google 3.10 kernel tree.
The device can be booted into the initrd with only one CPU running.
Signed-off-by: Bastian Köcher <mail@kchr.de>
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
---
arch/arm64/Kconfig.platforms | 13 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/huawei/Makefile | 5 +
.../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
8 files changed, 1032 insertions(+)
create mode 100644 arch/arm64/boot/dts/huawei/Makefile
create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
create mode 100644 arch/arm64/configs/angler_defconfig
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 515e669..f253f60d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -98,6 +98,19 @@ config MACH_LGE
help
This enables support for the LGE Nexus 5X - BullHead MSM8992.
+config ARCH_MSM8994
+ bool "Qualcomm MSM8994"
+ depends on ARCH_QCOM
+ select ARCH_REQUIRE_GPIOLIB
+ help
+ This enables support for the Qualcomm MSM8994
+
+config MACH_HUAWEI
+ bool "Huawei Angler (MSM8994)"
+ depends on ARCH_QCOM
+ help
+ This enables support for the Huawei Nexus 6P - Angler MSM8994.
+
config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index bde90fb..d199f8b 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += hisilicon
+dts-dirs += huawei
dts-dirs += marvell
dts-dirs += mediatek
dts-dirs += nvidia
diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
new file mode 100644
index 0000000..4b31ff4
--- /dev/null
+++ b/arch/arm64/boot/dts/huawei/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
new file mode 100644
index 0000000..07a71d6
--- /dev/null
+++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
@@ -0,0 +1,41 @@
+/* Copyright (c) 2015, Huawei Inc. All rights reserved.
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "../qcom/msm8994-v2.0.dtsi"
+
+/ {
+ model = "HUAWEI MSM8994 ANGLER rev-1.01";
+ compatible = "qcom,msm8994";
+ qcom,board-id= <8026 0>;
+};
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ soc {
+ serial@f991e000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
new file mode 100644
index 0000000..0e4eea0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&msmgpio {
+ blsp1_uart2_default: blsp1_uart2_default {
+ pinmux {
+ function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ };
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart2_sleep: blsp1_uart2_sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ };
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
new file mode 100644
index 0000000..8fc4c41f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
@@ -0,0 +1,31 @@
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * As a general rule, only version-specific property overrides should be placed
+ * inside this file. Device definitions should be placed inside the msm8994.dtsi
+ * file.
+ */
+
+#include "msm8994.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
+ compatible = "qcom,msm8994";
+ qcom,msm-id = <207 0x20000>;
+
+};
+
+/* Clock driver overrides */
+&clock_gcc {
+ compatible = "qcom,gcc-8994v2";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
new file mode 100644
index 0000000..c95cb73
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -0,0 +1,237 @@
+/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/memreserve/ 0x00000000 0x00001000;
+/memreserve/ 0xac1c0000 0x00001000;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8994.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM 8994";
+ compatible = "qcom,msm8994";
+ qcom,msm-id = <207 0x0>;
+ qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ };
+ };
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ // The currents(uA) correspond to the frequencies in the
+ // frequency table.
+ current = < 24140 //384000 kHZ
+ 27200 //460800 kHZ
+ 32300 //600000 kHZ
+ 36940 //672000 kHz
+ 41570 //768000 kHZ
+ 49870 //864000 kHZ
+ 57840 //960000 kHZ
+ 79800 //1248000 kHZ
+ 88810 //1344000 kHZ
+ 102400 //1478400 kHZ
+ 110900>; //1555200 kHZ
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+ };
+
+ soc: soc { };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smem_mem: smem_region@0x6a00000 {
+ reg = <0x0 0x6a00000 0x0 0x200000>;
+ no-map;
+ };
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@f9000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xf9000000 0x1000>,
+ <0xf9002000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 2 0xff08>,
+ <1 3 0xff08>,
+ <1 4 0xff08>,
+ <1 1 0xff08>;
+ clock-frequency = <19200000>;
+ };
+
+ timer@f9020000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xf9020000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@f9021000 {
+ frame-number = <0>;
+ interrupts = <0 9 0x4>,
+ <0 8 0x4>;
+ reg = <0xf9021000 0x1000>,
+ <0xf9022000 0x1000>;
+ };
+
+ frame@f9023000 {
+ frame-number = <1>;
+ interrupts = <0 10 0x4>;
+ reg = <0xf9023000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9024000 {
+ frame-number = <2>;
+ interrupts = <0 11 0x4>;
+ reg = <0xf9024000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9025000 {
+ frame-number = <3>;
+ interrupts = <0 12 0x4>;
+ reg = <0xf9025000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9026000 {
+ frame-number = <4>;
+ interrupts = <0 13 0x4>;
+ reg = <0xf9026000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9027000 {
+ frame-number = <5>;
+ interrupts = <0 14 0x4>;
+ reg = <0xf9027000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9028000 {
+ frame-number = <6>;
+ interrupts = <0 15 0x4>;
+ reg = <0xf9028000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ restart@fc4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
+
+ msmgpio: pinctrl@fd510000 {
+ compatible = "qcom,msm8994-pinctrl", "qcom,msm8974-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ blsp1_uart2: serial@f991e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991e000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-names = "core", "iface";
+ clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ };
+
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ tcsr_mutex_regs: syscon@fd484000 {
+ compatible = "syscon";
+ reg = <0xfd484000 0x2000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x80>;
+ #hwlock-cells = <1>;
+ };
+
+ qcom,smem@6a00000 {
+ compatible = "qcom,smem";
+
+ memory-region = <&smem_mem>;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ clock_gcc: qcom,gcc@fc400000 {
+ compatible = "qcom,gcc-8994";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xfc400000 0x2000>;
+ };
+
+};
+
+#include "msm8994-pins.dtsi"
diff --git a/arch/arm64/configs/angler_defconfig b/arch/arm64/configs/angler_defconfig
new file mode 100644
index 0000000..00cf192
--- /dev/null
+++ b/arch/arm64/configs/angler_defconfig
@@ -0,0 +1,666 @@
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_SCHED_HMP=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_PCI_QUIRKS is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_PROFILING=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_MSM=y
+CONFIG_ARCH_MSM8994=y
+CONFIG_ARCH_MSM8994_V1_TLBI_WA=y
+CONFIG_PCI_MSM=y
+CONFIG_ARM64_A57_ERRATA_832075=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_ARCH_WANTS_CTXSW_LOGGING=y
+CONFIG_PREEMPT=y
+CONFIG_ARMV7_COMPAT=y
+CONFIG_BALANCE_ANON_FILE_RECLAIM=y
+CONFIG_ZSMALLOC=y
+CONFIG_SECCOMP=y
+CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
+# CONFIG_COREDUMP is not set
+CONFIG_COMPAT=y
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=0
+CONFIG_PM_RUNTIME=y
+CONFIG_SUSPEND_TIME=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+CONFIG_CPU_BOOST=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+# CONFIG_CPU_IDLE_GOV_MENU is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_REJECT_SKERR=y
+CONFIG_NF_NAT_IPV4=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_SECURITY=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_L2TP=y
+CONFIG_L2TP_DEBUGFS=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
+CONFIG_BRIDGE=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=y
+CONFIG_NET_EMATCH_NBYTE=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_EMATCH_META=y
+CONFIG_NET_EMATCH_TEXT=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_RMNET_DATA=y
+CONFIG_RMNET_DATA_FC=y
+CONFIG_RMNET_DATA_DEBUG_PKT=y
+CONFIG_SOCKEV_NLMCAST=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_MSM_BT_BLUESLEEP=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+CONFIG_RFKILL=y
+CONFIG_NFC=y
+CONFIG_NFC_PN548=y
+CONFIG_IPC_ROUTER=y
+CONFIG_IPC_ROUTER_SECURITY=y
+CONFIG_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_ARM_CCI=y
+CONFIG_ZRAM=y
+CONFIG_ZRAM_LZ4_COMPRESS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_UID_STAT=y
+CONFIG_QSEECOM=y
+CONFIG_TI_DRV2667=y
+CONFIG_UID_CPUTIME=y
+CONFIG_WIFI_SAR=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_REQ_CRYPT=y
+CONFIG_DM_VERITY=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+# CONFIG_ETHERNET is not set
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_CDC_NCM is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_CLD_LL_CORE=y
+CONFIG_BCMDHD=y
+CONFIG_BCMDHD_PCIE=y
+CONFIG_BCM4358=y
+CONFIG_BCMDHD_FW_PATH="/vendor/firmware/fw_bcmdhd.bin"
+CONFIG_DHD_USE_STATIC_BUF=y
+CONFIG_DHD_USE_SCHED_SCAN=y
+CONFIG_DHD_OF_SUPPORT=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_INPUT_TABLET=y
+CONFIG_TABLET_USB_ACECAD=y
+CONFIG_TABLET_USB_AIPTEK=y
+CONFIG_TABLET_USB_GTCO=y
+CONFIG_TABLET_USB_HANWANG=y
+CONFIG_TABLET_USB_KBTAB=y
+CONFIG_TABLET_USB_WACOM=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4=y
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICETREE_SUPPORT=y
+# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_PROXIMITY is not set
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_BINARY_FW_UPGRADE=y
+CONFIG_TOUCHSCREEN_HUAWEI_CYTTSP4_RECOVERY_FW_UPDATE=y
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_MANUAL_TTCONFIG_UPGRADE=y
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_USE_FW_BIN_FILE=y
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICE_ACCESS=y
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_LOADER=y
+CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEBUG_MODULE=y
+CONFIG_TOUCHSCREEN_GEN_VKEYS=y
+CONFIG_SECURE_TOUCH=y
+CONFIG_TOUCHSCREEN_HUAWEI_SYNAPTICS_DSX_v25=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_CORE=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_RMI_DEV=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_FW_UPDATE=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_KEYCHORD=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=y
+CONFIG_LASER_STMVL6180=y
+CONFIG_RF_DETECT=y
+# CONFIG_SERIO is not set
+CONFIG_FINGERPRINT_FPC=y
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_MSM_HS=y
+CONFIG_SERIAL_MSM_HSL=y
+CONFIG_SERIAL_MSM_HSL_CONSOLE=y
+CONFIG_SERIAL_MSM_SMD=y
+CONFIG_HW_RANDOM_MSM=y
+CONFIG_MSM_SMD_PKT=y
+CONFIG_MSM_ADSPRPC=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MSM_V2=y
+CONFIG_SLIMBUS_MSM_NGD=y
+CONFIG_SPI=y
+CONFIG_SPI_CONTEXTHUB=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_MSM_QPNP_INT=y
+CONFIG_USE_PINCTRL_IRQ=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_QPNP_PIN=y
+CONFIG_SMB349_DUAL_CHARGER=y
+CONFIG_SMB1351_USB_CHARGER=y
+CONFIG_QPNP_SMBCHARGER=y
+CONFIG_QPNP_FG=y
+CONFIG_BATTERY_BCL=y
+CONFIG_MSM_BCL_CTL=y
+CONFIG_MSM_BCL_PERIPHERAL_CTL=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_MSM_DLOAD_MODE=y
+CONFIG_MSM_PM=y
+CONFIG_APSS_CORE_EA=y
+CONFIG_SENSORS_EPM_ADC=y
+CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_TSENS8974=y
+CONFIG_LIMITS_MONITOR=y
+CONFIG_LIMITS_LITE_HW=y
+CONFIG_THERMAL_MONITOR=y
+CONFIG_THERMAL_QPNP=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
+CONFIG_WCD9330_CODEC=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PROXY_CONSUMER=y
+CONFIG_REGULATOR_MEM_ACC=y
+CONFIG_REGULATOR_TPS65132=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_REGULATOR_RPM_SMD=y
+CONFIG_REGULATOR_QPNP=y
+CONFIG_REGULATOR_QPNP_LABIBB=y
+CONFIG_REGULATOR_SPM=y
+CONFIG_REGULATOR_CPR=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEOBUF2_MSM_MEM=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF=y
+CONFIG_HI256=y
+CONFIG_MT9M114=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
+CONFIG_MSM_VIDC_V4L2=y
+CONFIG_TSPP=y
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_VGA_ARB is not set
+CONFIG_MSM_KGSL=y
+CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
+CONFIG_FB=y
+CONFIG_FB_MSM=y
+CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_WRITEBACK=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_MPU401=y
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_MSM8994=y
+CONFIG_SND_SOC_MAX98925=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_PRODIKEYS=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_HOLTEK=y
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_KEYTOUCH=y
+CONFIG_HID_KYE=y
+CONFIG_HID_UCLOGIC=y
+CONFIG_HID_WALTOP=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_ICADE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LCPOWER=y
+CONFIG_HID_LENOVO_TPKBD=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PRIMAX=y
+CONFIG_HID_PS3REMOTE=y
+CONFIG_HID_ROCCAT=y
+CONFIG_HID_SAITEK=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SPEEDLINK=y
+CONFIG_HID_STEELSERIES=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THINGM=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_WACOM=y
+CONFIG_HID_WIIMOTE=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_SENSOR_HUB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_EHSET=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_EMI62=y
+CONFIG_USB_EMI26=y
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_USB_PHY=y
+CONFIG_USB_MSM_SSPHY_QMP=y
+CONFIG_MSM_QUSB_PHY=y
+CONFIG_DUAL_ROLE_USB_INTF=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_DWC3_MSM=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_TYPEC=y
+CONFIG_TUSB320_TYPEC=y
+CONFIG_MMC=y
+CONFIG_MMC_PERF_PROFILING=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_PARANOID_SD_INIT=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=y
+CONFIG_MMC_BLOCK_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_LEDS_QPNP=y
+CONFIG_LEDS_QPNP_FLASH=y
+CONFIG_LEDS_QPNP_WLED=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_SWITCH=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_QPNP=y
+CONFIG_DMADEVICES=y
+CONFIG_QCOM_SPS_DMA=y
+CONFIG_UIO=y
+CONFIG_UIO_MSM_SHAREDMEM=y
+CONFIG_STAGING=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ASHMEM=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_ANDROID_INTF_ALARM_DEV=y
+CONFIG_ONESHOT_SYNC=y
+CONFIG_ION=y
+CONFIG_ION_MSM=y
+CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS=y
+# CONFIG_NET_VENDOR_SILICOM is not set
+CONFIG_SPS=y
+CONFIG_USB_BAM=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_QPNP_POWER_ON=y
+CONFIG_QPNP_REVID=y
+CONFIG_QPNP_COINCELL=y
+CONFIG_QPNP_USB_DETECT=y
+CONFIG_IPA=y
+CONFIG_RMNET_IPA=y
+CONFIG_MSM_AVTIMER=y
+CONFIG_PFT=y
+CONFIG_MSM_BUS_SCALING=y
+CONFIG_MSM_BUSPM_DEV=y
+CONFIG_BUS_TOPOLOGY_ADHOC=y
+CONFIG_DEBUG_BUS_VOTER=y
+CONFIG_QPNP_HAPTIC=y
+CONFIG_MSM_MDSS_PLL=y
+CONFIG_REMOTE_SPINLOCK_MSM=y
+CONFIG_MSM_IOMMU_V1=y
+CONFIG_MSM_IOMMU_VBIF_CHECK=y
+CONFIG_IOMMU_FORCE_4K_MAPPINGS=y
+CONFIG_DEVFREQ_SPDM=y
+CONFIG_PWM=y
+CONFIG_PWM_QPNP=y
+CONFIG_SENSORS_SSC=y
+CONFIG_GENERIC_PHY=y
+CONFIG_CP_ACCESS64=y
+CONFIG_MSM_EVENT_TIMER=y
+CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
+CONFIG_MSM_QMI_INTERFACE=y
+CONFIG_MSM_SMD_DEBUG=y
+CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
+CONFIG_MSM_RPM_LOG=y
+CONFIG_MSM_RPM_STATS_LOG=y
+CONFIG_MSM_RUN_QUEUE_STATS=y
+CONFIG_MSM_SMEM_LOGGING=y
+CONFIG_MSM_SMP2P=y
+CONFIG_MSM_SMP2P_TEST=y
+CONFIG_MSM_SPM=y
+CONFIG_MSM_L2_SPM=y
+CONFIG_MSM_ADSP_LOADER=y
+CONFIG_MSM_MEMORY_DUMP_V2=y
+CONFIG_MSM_DEBUG_LAR_UNLOCK=y
+CONFIG_MSM_DDR_HEALTH=y
+CONFIG_MSM_COMMON_LOG=y
+CONFIG_MSM_WATCHDOG_V2=y
+CONFIG_MSM_FORCE_WDOG_BITE_ON_PANIC=y
+CONFIG_MSM_HVC=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
+CONFIG_MSM_PIL=y
+CONFIG_MSM_PIL_SSR_GENERIC=y
+CONFIG_MSM_PIL_MSS_QDSP6V5=y
+CONFIG_MSM_OCMEM=y
+CONFIG_MSM_OCMEM_LOCAL_POWER_CTRL=y
+CONFIG_MSM_OCMEM_DEBUG=y
+CONFIG_MSM_BOOT_STATS=y
+CONFIG_MSM_SCM=y
+CONFIG_MSM_XPU_ERR_FATAL=y
+CONFIG_MSM_CPUSS_DUMP=y
+CONFIG_MSM_SHARED_HEAP_ACCESS=y
+CONFIG_MSM_SYSTEM_HEALTH_MONITOR=y
+CONFIG_QCOM_EARLY_RANDOM=y
+CONFIG_MSM_PERFORMANCE=y
+CONFIG_QCOM_NPA_DUMP=y
+CONFIG_MSM_TZ_LOG=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_FS_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PAGE_OWNER=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_RCU_CPU_STALL_INFO=y
+CONFIG_RCU_TRACE=y
+CONFIG_IPC_LOGGING=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_OOPS_LOG_BUFFER=y
+CONFIG_LOG_BUF_MAGIC=y
+CONFIG_OOPS_LOG_BUF_SHIFT=17
+CONFIG_PANIC_ON_DATA_CORRUPTION=y
+CONFIG_ARM64_PTDUMP=y
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_LSM_MMAP_MIN_ADDR=4096
+CONFIG_SECURITY_SELINUX=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEV_QCRYPTO=y
+CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DEV_QCEDEV=y
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_PUBLIC_KEY_ALGO_RSA=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_QMI_ENCDEC=y
+CONFIG_STRICT_MEMORY_RWX=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARCH_QCOM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMD=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_QCOM_PM=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_PINCTRL_MSM8X74=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_MSM_GCC_8994=y
+CONFIG_MACH_HUAWEI=y
+CONFIG_DEVTMPFS=y
+CONFIG_DMA_CMA=y
--
2.6.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [RFC 4/4] arm64: dts: msm8992 default serial config
2016-07-08 0:41 ` Jeremy McNicoll
` (3 preceding siblings ...)
(?)
@ 2016-07-08 0:41 ` Jeremy McNicoll
-1 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-08 0:41 UTC (permalink / raw)
To: linux-arm-msm, linux-arm-kernel; +Cc: andy.gross, stephen.boyd, mail, jeremymc
As per Documentation/devicetree/bindings/chosen.txt so that we
are not relying on implicit defaults.
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
---
arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
index 860cded..f2f525e 100644
--- a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
+++ b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
@@ -27,7 +27,7 @@
};
chosen {
- stdout-path = "serial0";
+ stdout-path = "serial0:115200n8";
};
soc {
--
2.6.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
2016-07-08 0:41 ` [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support Jeremy McNicoll
@ 2016-07-08 17:35 ` Andy Gross
2016-09-21 1:12 ` Andy Gross
1 sibling, 0 replies; 22+ messages in thread
From: Andy Gross @ 2016-07-08 17:35 UTC (permalink / raw)
To: Jeremy McNicoll
Cc: linux-arm-msm, linux-arm-kernel, stephen.boyd, mail, jeremymc
On Thu, Jul 07, 2016 at 05:41:06PM -0700, Jeremy McNicoll wrote:
> From: Bastian Köcher <mail@kchr.de>
>
> Initial device tree support for Qualcomm MSM8994 SoC and
> Huawei Angler / Google Nexus 6P support.
>
> The device tree and the angler_defconfig are based on the
> device tree from the Google 3.10 kernel tree.
>
> The device can be booted into the initrd with only one CPU running.
>
> Signed-off-by: Bastian Köcher <mail@kchr.de>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/Kconfig.platforms | 13 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/huawei/Makefile | 5 +
> .../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
> arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
> 8 files changed, 1032 insertions(+)
> create mode 100644 arch/arm64/boot/dts/huawei/Makefile
> create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
> create mode 100644 arch/arm64/configs/angler_defconfig
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 515e669..f253f60d 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -98,6 +98,19 @@ config MACH_LGE
> help
> This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> +config ARCH_MSM8994
> + bool "Qualcomm MSM8994"
> + depends on ARCH_QCOM
> + select ARCH_REQUIRE_GPIOLIB
> + help
> + This enables support for the Qualcomm MSM8994
> +
> +config MACH_HUAWEI
> + bool "Huawei Angler (MSM8994)"
> + depends on ARCH_QCOM
> + help
> + This enables support for the Huawei Nexus 6P - Angler MSM8994.
We don't add OEM/end user config options. We generally only add SoC vendors.
So whenever huawei makes their own processor and uses it in a product, then they
can get their own directory and config option.
> +
> config ARCH_ROCKCHIP
> bool "Rockchip Platforms"
> select ARCH_HAS_RESET_CONTROLLER
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index bde90fb..d199f8b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ dts-dirs += cavium
> dts-dirs += exynos
> dts-dirs += freescale
> dts-dirs += hisilicon
> +dts-dirs += huawei
> dts-dirs += marvell
> dts-dirs += mediatek
> dts-dirs += nvidia
> diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
> new file mode 100644
> index 0000000..4b31ff4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
Nope. This should be built if ARCH_QCOM is specified.
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> new file mode 100644
> index 0000000..07a71d6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
This needs to be in the qcom directory. And follow the QCOM filename
conventions
> @@ -0,0 +1,41 @@
> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "../qcom/msm8994-v2.0.dtsi"
> +
> +/ {
> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
> + compatible = "qcom,msm8994";
> + qcom,board-id= <8026 0>;
We never specify the qcom,board-id in the DT. We have a tool that adds this to
the dtb file after the fact. Please work with sboyd to get the 8994 board id
support in the current tool.
The dtbTool is part of the skales repo.
https://source.codeaurora.org/quic/kernel/skales/
> +};
> +
> +/ {
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc {
> + serial@f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
<snip>
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> new file mode 100644
> index 0000000..8fc4c41f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> @@ -0,0 +1,31 @@
> +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * As a general rule, only version-specific property overrides should be placed
> + * inside this file. Device definitions should be placed inside the msm8994.dtsi
> + * file.
> + */
> +
> +#include "msm8994.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x20000>;
See above comment concerning IDs.
> +
> +};
> +
> +/* Clock driver overrides */
> +&clock_gcc {
> + compatible = "qcom,gcc-8994v2";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> new file mode 100644
> index 0000000..c95cb73
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -0,0 +1,237 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/memreserve/ 0x00000000 0x00001000;
> +/memreserve/ 0xac1c0000 0x00001000;
This needs to be done in a reserved-memory { }; section.
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x0>;
> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
<snip>
> diff --git a/arch/arm64/configs/angler_defconfig b/arch/arm64/configs/angler_defconfig
> new file mode 100644
> index 0000000..00cf192
> --- /dev/null
> +++ b/arch/arm64/configs/angler_defconfigo
I believe the current modus operandi is that there will be one defconfig for
ARM64. Therefore, please identify specific options that you need to enable
using the ARM64 defconfig. And please split out the defconfig changes into a
separate patch.
> @@ -0,0 +1,666 @@
> +CONFIG_AUDIT=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> +CONFIG_RCU_FAST_NO_HZ=y
> +CONFIG_LOG_BUF_SHIFT=20
> +CONFIG_CGROUPS=y
> +CONFIG_CGROUP_DEBUG=y
<snip>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
@ 2016-07-08 17:35 ` Andy Gross
0 siblings, 0 replies; 22+ messages in thread
From: Andy Gross @ 2016-07-08 17:35 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 07, 2016 at 05:41:06PM -0700, Jeremy McNicoll wrote:
> From: Bastian K?cher <mail@kchr.de>
>
> Initial device tree support for Qualcomm MSM8994 SoC and
> Huawei Angler / Google Nexus 6P support.
>
> The device tree and the angler_defconfig are based on the
> device tree from the Google 3.10 kernel tree.
>
> The device can be booted into the initrd with only one CPU running.
>
> Signed-off-by: Bastian K?cher <mail@kchr.de>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/Kconfig.platforms | 13 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/huawei/Makefile | 5 +
> .../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
> arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
> 8 files changed, 1032 insertions(+)
> create mode 100644 arch/arm64/boot/dts/huawei/Makefile
> create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
> create mode 100644 arch/arm64/configs/angler_defconfig
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 515e669..f253f60d 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -98,6 +98,19 @@ config MACH_LGE
> help
> This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> +config ARCH_MSM8994
> + bool "Qualcomm MSM8994"
> + depends on ARCH_QCOM
> + select ARCH_REQUIRE_GPIOLIB
> + help
> + This enables support for the Qualcomm MSM8994
> +
> +config MACH_HUAWEI
> + bool "Huawei Angler (MSM8994)"
> + depends on ARCH_QCOM
> + help
> + This enables support for the Huawei Nexus 6P - Angler MSM8994.
We don't add OEM/end user config options. We generally only add SoC vendors.
So whenever huawei makes their own processor and uses it in a product, then they
can get their own directory and config option.
> +
> config ARCH_ROCKCHIP
> bool "Rockchip Platforms"
> select ARCH_HAS_RESET_CONTROLLER
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index bde90fb..d199f8b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ dts-dirs += cavium
> dts-dirs += exynos
> dts-dirs += freescale
> dts-dirs += hisilicon
> +dts-dirs += huawei
> dts-dirs += marvell
> dts-dirs += mediatek
> dts-dirs += nvidia
> diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
> new file mode 100644
> index 0000000..4b31ff4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
Nope. This should be built if ARCH_QCOM is specified.
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> new file mode 100644
> index 0000000..07a71d6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
This needs to be in the qcom directory. And follow the QCOM filename
conventions
> @@ -0,0 +1,41 @@
> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "../qcom/msm8994-v2.0.dtsi"
> +
> +/ {
> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
> + compatible = "qcom,msm8994";
> + qcom,board-id= <8026 0>;
We never specify the qcom,board-id in the DT. We have a tool that adds this to
the dtb file after the fact. Please work with sboyd to get the 8994 board id
support in the current tool.
The dtbTool is part of the skales repo.
https://source.codeaurora.org/quic/kernel/skales/
> +};
> +
> +/ {
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc {
> + serial at f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
<snip>
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> new file mode 100644
> index 0000000..8fc4c41f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> @@ -0,0 +1,31 @@
> +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * As a general rule, only version-specific property overrides should be placed
> + * inside this file. Device definitions should be placed inside the msm8994.dtsi
> + * file.
> + */
> +
> +#include "msm8994.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x20000>;
See above comment concerning IDs.
> +
> +};
> +
> +/* Clock driver overrides */
> +&clock_gcc {
> + compatible = "qcom,gcc-8994v2";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> new file mode 100644
> index 0000000..c95cb73
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -0,0 +1,237 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/memreserve/ 0x00000000 0x00001000;
> +/memreserve/ 0xac1c0000 0x00001000;
This needs to be done in a reserved-memory { }; section.
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x0>;
> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
<snip>
> diff --git a/arch/arm64/configs/angler_defconfig b/arch/arm64/configs/angler_defconfig
> new file mode 100644
> index 0000000..00cf192
> --- /dev/null
> +++ b/arch/arm64/configs/angler_defconfigo
I believe the current modus operandi is that there will be one defconfig for
ARM64. Therefore, please identify specific options that you need to enable
using the ARM64 defconfig. And please split out the defconfig changes into a
separate patch.
> @@ -0,0 +1,666 @@
> +CONFIG_AUDIT=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> +CONFIG_RCU_FAST_NO_HZ=y
> +CONFIG_LOG_BUF_SHIFT=20
> +CONFIG_CGROUPS=y
> +CONFIG_CGROUP_DEBUG=y
<snip>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
2016-07-08 0:41 ` [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support Jeremy McNicoll
@ 2016-07-08 17:41 ` Andy Gross
0 siblings, 0 replies; 22+ messages in thread
From: Andy Gross @ 2016-07-08 17:41 UTC (permalink / raw)
To: Jeremy McNicoll
Cc: linux-arm-msm, linux-arm-kernel, stephen.boyd, mail, jeremymc
On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
> Initial device tree support for Qualcomm MSM8992 SoC and
> LG Bullhead / Google Nexus 5X support.
>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/Kconfig.platforms | 12 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/lge/Makefile | 5 +
> .../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +++
> arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +++
> arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++++++++++++
> arch/arm64/configs/bullhead_defconfig | 377 +++++++++++++++++++++
> arch/arm64/configs/msm8992_defconfig | 5 +
> 8 files changed, 700 insertions(+)
> create mode 100644 arch/arm64/boot/dts/lge/Makefile
> create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
> create mode 100644 arch/arm64/configs/bullhead_defconfig
> create mode 100644 arch/arm64/configs/msm8992_defconfig
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 7ef1d05..515e669 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -86,6 +86,18 @@ config ARCH_QCOM
> help
> This enables support for the ARMv8 based Qualcomm chipsets.
>
> +config ARCH_MSM8992
> + bool "Qualcomm MSM8992"
> + depends on ARCH_QCOM
> + help
> + This enables support for the Qualcomm MSM8992 SoC.
> +
> +config MACH_LGE
> + bool "LGE BullHead (MSM8992)"
> + depends on ARCH_QCOM
> + help
> + This enables support for the LGE Nexus 5X - BullHead MSM8992.
We don't add config options for End users. Only for Soc Companies or people
actually producing the silicon.
> +
> config ARCH_ROCKCHIP
> bool "Rockchip Platforms"
> select ARCH_HAS_RESET_CONTROLLER
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 6e199c9..bde90fb 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ dts-dirs += marvell
> dts-dirs += mediatek
> dts-dirs += nvidia
> dts-dirs += qcom
> +dts-dirs += lge
No, please add the files to the qcom directory.
> dts-dirs += renesas
> dts-dirs += rockchip
> dts-dirs += socionext
> diff --git a/arch/arm64/boot/dts/lge/Makefile b/arch/arm64/boot/dts/lge/Makefile
> new file mode 100644
> index 0000000..f4e7860
> --- /dev/null
> +++ b/arch/arm64/boot/dts/lge/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_MACH_LGE) += msm8992-bullhead-rev-101.dtb
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
> new file mode 100644
> index 0000000..860cded
> --- /dev/null
> +++ b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
> @@ -0,0 +1,41 @@
> +/* Copyright (c) 2015, LGE Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "../qcom/msm8992.dtsi"
> +
> +/ {
> + model = "LGE MSM8992 BULLHEAD rev-1.01";
> + compatible = "qcom,msm8992";
> + qcom,board-id = <0xb64 0>;
Please work with sboyd to add the board-id to the dtbTool. We don't put
board-ids in the dts file. We post-process the dtb file and add them then.
> +};
> +
> +/ {
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc {
> + serial@f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
<snip>
> diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
> new file mode 100644
> index 0000000..fa92a1a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
> @@ -0,0 +1,221 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/memreserve/ 0x00000000 0x00001000;
Please use reserved-memory{}. And why are they setting aside 4k at the
beginning? Trying to cover up corruption issues?
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8992";
> + compatible = "qcom,msm8992";
> + qcom,msm-id = <251 0>, <252 0>;
> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
See above comment on ids.
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
<snip>
> +#include "msm8992-pins.dtsi"
> diff --git a/arch/arm64/configs/bullhead_defconfig b/arch/arm64/configs/bullhead_defconfig
Please add whatever config options you have to the default defconfig. we don't
define board specific configs for ARM64 platforms. Or I should say, they won't
be accepted into the kernel.
Also, please separate defconfig changes into separate patches.
<snip>
> diff --git a/arch/arm64/configs/msm8992_defconfig b/arch/arm64/configs/msm8992_defconfig
> new file mode 100644
> index 0000000..f673a27
> --- /dev/null
> +++ b/arch/arm64/configs/msm8992_defconfig
See above comment.
> @@ -0,0 +1,5 @@
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_SCHED_HMP=y
> +CONFIG_NAMESPACES=y
> +# CONFIG_CORESIGHT is not set
> --
> 2.6.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
@ 2016-07-08 17:41 ` Andy Gross
0 siblings, 0 replies; 22+ messages in thread
From: Andy Gross @ 2016-07-08 17:41 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
> Initial device tree support for Qualcomm MSM8992 SoC and
> LG Bullhead / Google Nexus 5X support.
>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/Kconfig.platforms | 12 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/lge/Makefile | 5 +
> .../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +++
> arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +++
> arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++++++++++++
> arch/arm64/configs/bullhead_defconfig | 377 +++++++++++++++++++++
> arch/arm64/configs/msm8992_defconfig | 5 +
> 8 files changed, 700 insertions(+)
> create mode 100644 arch/arm64/boot/dts/lge/Makefile
> create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
> create mode 100644 arch/arm64/configs/bullhead_defconfig
> create mode 100644 arch/arm64/configs/msm8992_defconfig
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 7ef1d05..515e669 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -86,6 +86,18 @@ config ARCH_QCOM
> help
> This enables support for the ARMv8 based Qualcomm chipsets.
>
> +config ARCH_MSM8992
> + bool "Qualcomm MSM8992"
> + depends on ARCH_QCOM
> + help
> + This enables support for the Qualcomm MSM8992 SoC.
> +
> +config MACH_LGE
> + bool "LGE BullHead (MSM8992)"
> + depends on ARCH_QCOM
> + help
> + This enables support for the LGE Nexus 5X - BullHead MSM8992.
We don't add config options for End users. Only for Soc Companies or people
actually producing the silicon.
> +
> config ARCH_ROCKCHIP
> bool "Rockchip Platforms"
> select ARCH_HAS_RESET_CONTROLLER
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 6e199c9..bde90fb 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ dts-dirs += marvell
> dts-dirs += mediatek
> dts-dirs += nvidia
> dts-dirs += qcom
> +dts-dirs += lge
No, please add the files to the qcom directory.
> dts-dirs += renesas
> dts-dirs += rockchip
> dts-dirs += socionext
> diff --git a/arch/arm64/boot/dts/lge/Makefile b/arch/arm64/boot/dts/lge/Makefile
> new file mode 100644
> index 0000000..f4e7860
> --- /dev/null
> +++ b/arch/arm64/boot/dts/lge/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_MACH_LGE) += msm8992-bullhead-rev-101.dtb
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
> new file mode 100644
> index 0000000..860cded
> --- /dev/null
> +++ b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
> @@ -0,0 +1,41 @@
> +/* Copyright (c) 2015, LGE Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "../qcom/msm8992.dtsi"
> +
> +/ {
> + model = "LGE MSM8992 BULLHEAD rev-1.01";
> + compatible = "qcom,msm8992";
> + qcom,board-id = <0xb64 0>;
Please work with sboyd to add the board-id to the dtbTool. We don't put
board-ids in the dts file. We post-process the dtb file and add them then.
> +};
> +
> +/ {
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc {
> + serial at f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
<snip>
> diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
> new file mode 100644
> index 0000000..fa92a1a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
> @@ -0,0 +1,221 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/memreserve/ 0x00000000 0x00001000;
Please use reserved-memory{}. And why are they setting aside 4k at the
beginning? Trying to cover up corruption issues?
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8992";
> + compatible = "qcom,msm8992";
> + qcom,msm-id = <251 0>, <252 0>;
> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
See above comment on ids.
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
<snip>
> +#include "msm8992-pins.dtsi"
> diff --git a/arch/arm64/configs/bullhead_defconfig b/arch/arm64/configs/bullhead_defconfig
Please add whatever config options you have to the default defconfig. we don't
define board specific configs for ARM64 platforms. Or I should say, they won't
be accepted into the kernel.
Also, please separate defconfig changes into separate patches.
<snip>
> diff --git a/arch/arm64/configs/msm8992_defconfig b/arch/arm64/configs/msm8992_defconfig
> new file mode 100644
> index 0000000..f673a27
> --- /dev/null
> +++ b/arch/arm64/configs/msm8992_defconfig
See above comment.
> @@ -0,0 +1,5 @@
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_SCHED_HMP=y
> +CONFIG_NAMESPACES=y
> +# CONFIG_CORESIGHT is not set
> --
> 2.6.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC 2/4] msm8994 clocks: global clock support Global clock support for the msm8994 SOC.
2016-07-08 0:41 ` [RFC 2/4] msm8994 clocks: global clock support Global clock support for the msm8994 SOC Jeremy McNicoll
@ 2016-07-12 2:30 ` Jeremy McNicoll
0 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-12 2:30 UTC (permalink / raw)
To: linux-arm-msm, linux-arm-kernel
Cc: andy.gross, stephen.boyd, Bastian Köcher, jeremymc, Stephen Boyd
On 2016-07-07 5:41 PM, Jeremy McNicoll wrote:
> From: Bastian Köcher <mail@kchr.de>
>
> The clock definition was ported from the Google 3.10 kernel tree to
> work with the latest kernel.
>
> Signed-off-by: Bastian Köcher <mail@kchr.de>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 2 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-msm8994.c | 2501 ++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-msm8994.h | 145 ++
> 5 files changed, 2658 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-msm8994.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8994.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> index 9a60fde..a1dc2fe 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> @@ -14,6 +14,8 @@ Required properties :
> "qcom,gcc-msm8974"
> "qcom,gcc-msm8974pro"
> "qcom,gcc-msm8974pro-ac"
> + "qcom,gcc-msm8994"
> + "qcom,gcc-msm8994v2"
> "qcom,gcc-msm8996"
>
> - reg : shall contain base register location and length
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 95e3b3e..6687c7f 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -115,6 +115,15 @@ config MSM_MMCC_8974
> Say Y if you want to support multimedia devices such as display,
> graphics, video encode/decode, camera, etc.
>
> +config MSM_GCC_8994
> + tristate "MSM8994 Global Clock Controller"
> + select QCOM_GDSC
> + depends on COMMON_CLK_QCOM
> + help
> + Support for the global clock controller on msm8994 devices.
> + Say Y if you want to use peripheral devices such as UART, SPI,
> + i2c, USB, SD/eMMC, SATA, PCIe, etc.
> +
> config MSM_GCC_8996
> tristate "MSM8996 Global Clock Controller"
> depends on COMMON_CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 2a25f4e..551a64d 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
> obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
> obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
> obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
> +obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
> obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
> obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
> obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
> diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
> new file mode 100644
> index 0000000..3897cfd
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-msm8994.c
> @@ -0,0 +1,2501 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/err.h>
> +#include <linux/ctype.h>
> +#include <linux/io.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "reset.h"
> +
> +enum {
> + P_XO,
> + P_GPLL0,
> + P_GPLL4,
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> +};
> +
> +static const char * const gcc_xo_gpll0[] = {
> + "xo",
> + "gpll0",
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL4, 2 },
sboyd on IRC today that P_GPLL4 needs to be 5.
gcc_xo_gpll0_gpll4_map[] -> 0, 1, 5
Hopefully he will have time to review and provide feedback on the rest
of the changes.
-jeremy
> +};
> +
> +static const char * const gcc_xo_gpll0_gpll4[] = {
> + "xo",
> + "gpll0",
> + "gpll4",
> +};
> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
> +
> +static struct clk_fixed_factor xo = {
> + .mult = 1,
> + .div = 1,
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "xo",
> + .parent_names = (const char *[]) { "xo_board" },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll0_early = {
> + .offset = 0x00000,
> + .clkr = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll0_early",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> + .offset = 0x00000,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll0",
> + .parent_names = (const char *[]) { "gpll0_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll4_early = {
> + .offset = 0x1DC0,
> + .clkr = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll4_early",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll4 = {
> + .offset = 0x1DC0,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll4",
> + .parent_names = (const char *[]) { "gpll4_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(171430000, P_GPLL0, 3.5, 0, 0),
> + { }
> +};
> +
> +static struct freq_tbl ftbl_ufs_axi_clk_src_v2[] = {
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(171430000, P_GPLL0, 3.5, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + F(240000000, P_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 ufs_axi_clk_src = {
> + .cmd_rcgr = 0x1D68,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_ufs_axi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "ufs_axi_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb30_master_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(125000000, P_GPLL0, 1, 5, 24),
> + { }
> +};
> +
> +static struct clk_rcg2 usb30_master_clk_src = {
> + .cmd_rcgr = 0x03D4,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_usb30_master_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb30_master_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0660,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup1_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blspqup_spi_apps_clk_src_v2[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x064C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup1_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x06E0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup2_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(46150000, P_GPLL0, 13, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x06CC,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup2_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0760,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup3_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup3_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x074C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup3_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup3_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x07E0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup4_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup4_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x07CC,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup4_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup4_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0860,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup5_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(40000000, P_GPLL0, 15, 0, 0),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> + .cmd_rcgr = 0x084C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup5_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x08E0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup6_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(41380000, P_GPLL0, 14.5, 0, 0),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> + .cmd_rcgr = 0x08CC,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup6_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
> + F(3686400, P_GPLL0, 1, 96, 15625),
> + F(7372800, P_GPLL0, 1, 192, 15625),
> + F(14745600, P_GPLL0, 1, 384, 15625),
> + F(16000000, P_GPLL0, 5, 2, 15),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 5, 1, 5),
> + F(32000000, P_GPLL0, 1, 4, 75),
> + F(40000000, P_GPLL0, 15, 0, 0),
> + F(46400000, P_GPLL0, 1, 29, 375),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(51200000, P_GPLL0, 1, 32, 375),
> + F(56000000, P_GPLL0, 1, 7, 75),
> + F(58982400, P_GPLL0, 1, 1536, 15625),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + F(63160000, P_GPLL0, 9.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x068C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart1_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x070C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart2_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> + .cmd_rcgr = 0x078C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart3_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> + .cmd_rcgr = 0x080C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart4_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> + .cmd_rcgr = 0x088C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart5_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> + .cmd_rcgr = 0x090C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart6_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x09A0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup1_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup1_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x098C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup1_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0A20,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup2_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup2_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0A0C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup2_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup2_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0AA0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup3_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup3_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0A8C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup3_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup3_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0B20,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup4_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup4_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0B0C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup4_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup4_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0BA0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup5_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup5_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0B8C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup5_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup5_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0C20,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup6_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0C0C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup6_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x09CC,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart1_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x0A4C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart2_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> + .cmd_rcgr = 0x0ACC,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart3_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> + .cmd_rcgr = 0x0B4C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart4_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> + .cmd_rcgr = 0x0BCC,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart5_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> + .cmd_rcgr = 0x0C4C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart6_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_gp1_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp1_clk_src = {
> + .cmd_rcgr = 0x1904,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gp1_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_gp2_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp2_clk_src = {
> + .cmd_rcgr = 0x1944,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_gp2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gp2_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_gp3_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp3_clk_src = {
> + .cmd_rcgr = 0x1984,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_gp3_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gp3_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
> + F(1011000, P_XO, 1, 1, 19),
> + { }
> +};
> +
> +static struct clk_rcg2 pcie_0_aux_clk_src = {
> + .cmd_rcgr = 0x1B00,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_0_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_0_aux_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
> + F(125000000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 pcie_0_pipe_clk_src = {
> + .cmd_rcgr = 0x1ADC,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_pipe_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_0_pipe_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
> + F(1011000, P_XO, 1, 1, 19),
> + { }
> +};
> +
> +static struct clk_rcg2 pcie_1_aux_clk_src = {
> + .cmd_rcgr = 0x1B80,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_1_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_1_aux_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 pcie_1_pipe_clk_src = {
> + .cmd_rcgr = 0x1B5C,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_pipe_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_1_pipe_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pdm2_clk_src[] = {
> + F(60000000, P_GPLL0, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 pdm2_clk_src = {
> + .cmd_rcgr = 0x0CD0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_pdm2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pdm2_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
> + F(144000, P_XO, 16, 3, 25),
> + F(400000, P_XO, 12, 1, 4),
> + F(20000000, P_GPLL0, 15, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(192000000, P_GPLL4, 2, 0, 0),
> + F(384000000, P_GPLL4, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc1_apps_clk_src = {
> + .cmd_rcgr = 0x04D0,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll4_map,
> + .freq_tbl = ftbl_sdcc1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc1_apps_clk_src",
> + .parent_names = gcc_xo_gpll0_gpll4,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
> + F(144000, P_XO, 16, 3, 25),
> + F(400000, P_XO, 12, 1, 4),
> + F(20000000, P_GPLL0, 15, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc2_apps_clk_src = {
> + .cmd_rcgr = 0x0510,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc2_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 sdcc3_apps_clk_src = {
> + .cmd_rcgr = 0x0550,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc3_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 sdcc4_apps_clk_src = {
> + .cmd_rcgr = 0x0590,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc4_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
> + F(105500, P_XO, 1, 1, 182),
> + { }
> +};
> +
> +static struct clk_rcg2 tsif_ref_clk_src = {
> + .cmd_rcgr = 0x0D90,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .freq_tbl = ftbl_tsif_ref_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "tsif_ref_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> + .cmd_rcgr = 0x03E8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb30_mock_utmi_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
> + F(1200000, P_XO, 16, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb3_phy_aux_clk_src = {
> + .cmd_rcgr = 0x1414,
> + .hid_width = 5,
> + .freq_tbl = ftbl_usb3_phy_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb3_phy_aux_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
> + F(75000000, P_GPLL0, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb_hs_system_clk_src = {
> + .cmd_rcgr = 0x0490,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_usb_hs_system_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb_hs_system_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_ahb_clk = {
> + .halt_reg = 0x05C4,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1484,
> + .enable_mask = BIT(17),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> + .halt_reg = 0x0648,
> + .clkr = {
> + .enable_reg = 0x0648,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup1_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup1_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> + .halt_reg = 0x0644,
> + .clkr = {
> + .enable_reg = 0x0644,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup1_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup1_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> + .halt_reg = 0x06C8,
> + .clkr = {
> + .enable_reg = 0x06C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup2_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup2_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> + .halt_reg = 0x06C4,
> + .clkr = {
> + .enable_reg = 0x06C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup2_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup2_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> + .halt_reg = 0x0748,
> + .clkr = {
> + .enable_reg = 0x0748,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup3_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup3_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> + .halt_reg = 0x0744,
> + .clkr = {
> + .enable_reg = 0x0744,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup3_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup3_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> + .halt_reg = 0x07C8,
> + .clkr = {
> + .enable_reg = 0x07C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup4_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup4_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> + .halt_reg = 0x07C4,
> + .clkr = {
> + .enable_reg = 0x07C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup4_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup4_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> + .halt_reg = 0x0848,
> + .clkr = {
> + .enable_reg = 0x0848,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup5_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup5_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> + .halt_reg = 0x0844,
> + .clkr = {
> + .enable_reg = 0x0844,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup5_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup5_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> + .halt_reg = 0x08C8,
> + .clkr = {
> + .enable_reg = 0x08C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup6_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup6_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> + .halt_reg = 0x08C4,
> + .clkr = {
> + .enable_reg = 0x08C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup6_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup6_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> + .halt_reg = 0x0684,
> + .clkr = {
> + .enable_reg = 0x0684,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart1_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> + .halt_reg = 0x0704,
> + .clkr = {
> + .enable_reg = 0x0704,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart2_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> + .halt_reg = 0x0784,
> + .clkr = {
> + .enable_reg = 0x0784,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart3_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart3_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart4_apps_clk = {
> + .halt_reg = 0x0804,
> + .clkr = {
> + .enable_reg = 0x0804,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart4_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart4_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart5_apps_clk = {
> + .halt_reg = 0x0884,
> + .clkr = {
> + .enable_reg = 0x0884,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart5_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart5_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart6_apps_clk = {
> + .halt_reg = 0x0904,
> + .clkr = {
> + .enable_reg = 0x0904,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart6_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart6_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_ahb_clk = {
> + .halt_reg = 0x0944,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1484,
> + .enable_mask = BIT(15),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> + .halt_reg = 0x0988,
> + .clkr = {
> + .enable_reg = 0x0988,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup1_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup1_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> + .halt_reg = 0x0984,
> + .clkr = {
> + .enable_reg = 0x0984,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup1_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup1_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> + .halt_reg = 0x0A08,
> + .clkr = {
> + .enable_reg = 0x0A08,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup2_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup2_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> + .halt_reg = 0x0A04,
> + .clkr = {
> + .enable_reg = 0x0A04,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup2_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup2_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> + .halt_reg = 0x0A88,
> + .clkr = {
> + .enable_reg = 0x0A88,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup3_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup3_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> + .halt_reg = 0x0A84,
> + .clkr = {
> + .enable_reg = 0x0A84,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup3_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup3_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> + .halt_reg = 0x0B08,
> + .clkr = {
> + .enable_reg = 0x0B08,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup4_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup4_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> + .halt_reg = 0x0B04,
> + .clkr = {
> + .enable_reg = 0x0B04,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup4_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup4_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
> + .halt_reg = 0x0B88,
> + .clkr = {
> + .enable_reg = 0x0B88,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup5_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup5_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
> + .halt_reg = 0x0B84,
> + .clkr = {
> + .enable_reg = 0x0B84,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup5_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup5_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
> + .halt_reg = 0x0C08,
> + .clkr = {
> + .enable_reg = 0x0C08,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup6_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup6_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
> + .halt_reg = 0x0C04,
> + .clkr = {
> + .enable_reg = 0x0C04,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup6_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup6_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> + .halt_reg = 0x09C4,
> + .clkr = {
> + .enable_reg = 0x09C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart1_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> + .halt_reg = 0x0A44,
> + .clkr = {
> + .enable_reg = 0x0A44,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart2_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart3_apps_clk = {
> + .halt_reg = 0x0AC4,
> + .clkr = {
> + .enable_reg = 0x0AC4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart3_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart3_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart4_apps_clk = {
> + .halt_reg = 0x0B44,
> + .clkr = {
> + .enable_reg = 0x0B44,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart4_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart4_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart5_apps_clk = {
> + .halt_reg = 0x0BC4,
> + .clkr = {
> + .enable_reg = 0x0BC4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart5_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart5_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart6_apps_clk = {
> + .halt_reg = 0x0C44,
> + .clkr = {
> + .enable_reg = 0x0C44,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart6_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart6_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp1_clk = {
> + .halt_reg = 0x1900,
> + .clkr = {
> + .enable_reg = 0x1900,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_gp1_clk",
> + .parent_names = (const char *[]) {
> + "gp1_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp2_clk = {
> + .halt_reg = 0x1940,
> + .clkr = {
> + .enable_reg = 0x1940,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_gp2_clk",
> + .parent_names = (const char *[]) {
> + "gp2_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp3_clk = {
> + .halt_reg = 0x1980,
> + .clkr = {
> + .enable_reg = 0x1980,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_gp3_clk",
> + .parent_names = (const char *[]) {
> + "gp3_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_aux_clk = {
> + .halt_reg = 0x1AD4,
> + .clkr = {
> + .enable_reg = 0x1AD4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_0_aux_clk",
> + .parent_names = (const char *[]) {
> + "pcie_0_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_pipe_clk = {
> + .halt_reg = 0x1AD8,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1AD8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_0_pipe_clk",
> + .parent_names = (const char *[]) {
> + "pcie_0_pipe_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_aux_clk = {
> + .halt_reg = 0x1B54,
> + .clkr = {
> + .enable_reg = 0x1B54,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_1_aux_clk",
> + .parent_names = (const char *[]) {
> + "pcie_1_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_pipe_clk = {
> + .halt_reg = 0x1B58,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1B58,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_1_pipe_clk",
> + .parent_names = (const char *[]) {
> + "pcie_1_pipe_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pdm2_clk = {
> + .halt_reg = 0x0CCC,
> + .clkr = {
> + .enable_reg = 0x0CCC,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pdm2_clk",
> + .parent_names = (const char *[]) {
> + "pdm2_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_apps_clk = {
> + .halt_reg = 0x04C4,
> + .clkr = {
> + .enable_reg = 0x04C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc1_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc2_apps_clk = {
> + .halt_reg = 0x0504,
> + .clkr = {
> + .enable_reg = 0x0504,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc2_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc3_apps_clk = {
> + .halt_reg = 0x0544,
> + .clkr = {
> + .enable_reg = 0x0544,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc3_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc3_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc4_apps_clk = {
> + .halt_reg = 0x0584,
> + .clkr = {
> + .enable_reg = 0x0584,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc4_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc4_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
> + .halt_reg = 0x1D7C,
> + .clkr = {
> + .enable_reg = 0x1D7C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sys_noc_ufs_axi_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
> + .halt_reg = 0x03FC,
> + .clkr = {
> + .enable_reg = 0x03FC,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sys_noc_usb3_axi_clk",
> + .parent_names = (const char *[]) {
> + "usb30_master_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_tsif_ref_clk = {
> + .halt_reg = 0x0D88,
> + .clkr = {
> + .enable_reg = 0x0D88,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_tsif_ref_clk",
> + .parent_names = (const char *[]) {
> + "tsif_ref_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_axi_clk = {
> + .halt_reg = 0x1D48,
> + .clkr = {
> + .enable_reg = 0x1D48,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_ufs_axi_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_rx_cfg_clk = {
> + .halt_reg = 0x1D54,
> + .clkr = {
> + .enable_reg = 0x1D54,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_ufs_rx_cfg_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_tx_cfg_clk = {
> + .halt_reg = 0x1D50,
> + .clkr = {
> + .enable_reg = 0x1D50,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_ufs_tx_cfg_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_master_clk = {
> + .halt_reg = 0x03C8,
> + .clkr = {
> + .enable_reg = 0x03C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb30_master_clk",
> + .parent_names = (const char *[]) {
> + "usb30_master_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_mock_utmi_clk = {
> + .halt_reg = 0x03D0,
> + .clkr = {
> + .enable_reg = 0x03D0,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb30_mock_utmi_clk",
> + .parent_names = (const char *[]) {
> + "usb30_mock_utmi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_phy_aux_clk = {
> + .halt_reg = 0x1408,
> + .clkr = {
> + .enable_reg = 0x1408,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb3_phy_aux_clk",
> + .parent_names = (const char *[]) {
> + "usb3_phy_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb_hs_system_clk = {
> + .halt_reg = 0x0484,
> + .clkr = {
> + .enable_reg = 0x0484,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb_hs_system_clk",
> + .parent_names = (const char *[]) {
> + "usb_hs_system_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap *gcc_msm8994_clocks[] = {
> + [GPLL0_EARLY] = &gpll0_early.clkr,
> + [GPLL0] = &gpll0.clkr,
> + [GPLL4_EARLY] = &gpll4_early.clkr,
> + [GPLL4] = &gpll4.clkr,
> + [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
> + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
> + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
> + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
> + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
> + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
> + [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
> + [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
> + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
> + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
> + [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
> + [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
> + [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
> + [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
> + [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
> + [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
> + [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
> + [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
> + [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
> + [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
> + [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
> + [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
> + [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
> + [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
> + [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
> + [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
> + [GP1_CLK_SRC] = &gp1_clk_src.clkr,
> + [GP2_CLK_SRC] = &gp2_clk_src.clkr,
> + [GP3_CLK_SRC] = &gp3_clk_src.clkr,
> + [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
> + [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
> + [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
> + [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
> + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
> + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
> + [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
> + [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
> + [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
> + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
> + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
> + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
> + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
> + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
> + [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
> + [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
> + [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
> + [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
> + [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
> + [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
> + [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
> + [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
> + [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
> + [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
> + [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
> + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
> + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
> + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
> + [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
> + [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
> + [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
> + [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
> + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
> + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
> + [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
> + [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
> + [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
> + [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
> + [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
> + [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
> + [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
> + [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
> + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
> + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
> + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
> + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
> +};
> +
> +static void msm_gcc_8994v2_fixup(void)
> +{
> + ufs_axi_clk_src.freq_tbl = ftbl_ufs_axi_clk_src_v2;
> +
> + blsp1_qup1_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup2_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup3_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup4_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup5_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup6_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup1_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup2_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup3_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup4_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup5_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup6_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> +}
> +
> +static const struct regmap_config gcc_msm8994_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x2000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gcc_msm8994_desc = {
> + .config = &gcc_msm8994_regmap_config,
> + .clks = gcc_msm8994_clocks,
> + .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
> + .resets = NULL,
> + .num_resets = 0,
> + .gdscs = NULL,
> + .num_gdscs = 0,
> +};
> +
> +static const struct of_device_id gcc_msm8994_match_table[] = {
> + { .compatible = "qcom,gcc-8994" },
> + { .compatible = "qcom,gcc-8994v2" },
> + {}
> +}
> +
> +MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
> +
> +static int gcc_msm8994_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct clk *clk;
> + const char *compat = NULL;
> + int compatlen = 0;
> + bool is_v2 = false;
> +
> + clk = devm_clk_register(dev, &xo.hw);
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
> + if (!compat || (compatlen <= 0))
> + return -EINVAL;
> +
> + is_v2 = !strcmp(compat, "qcom,gcc-8994v2");
> + if (is_v2)
> + msm_gcc_8994v2_fixup();
> +
> + return qcom_cc_probe(pdev, &gcc_msm8994_desc);
> +}
> +
> +static struct platform_driver gcc_msm8994_driver = {
> + .probe = gcc_msm8994_probe,
> + .driver = {
> + .name = "gcc-msm8994",
> + .of_match_table = gcc_msm8994_match_table,
> + },
> +};
> +
> +static int __init gcc_msm8994_init(void)
> +{
> + return platform_driver_register(&gcc_msm8994_driver);
> +}
> +core_initcall(gcc_msm8994_init);
> +
> +static void __exit gcc_msm8994_exit(void)
> +{
> + platform_driver_unregister(&gcc_msm8994_driver);
> +}
> +module_exit(gcc_msm8994_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:gcc-msm8994");
> diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
> new file mode 100644
> index 0000000..0ae494b
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
> +#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
> +
> +#define GPLL0_EARLY 0
> +#define GPLL0 1
> +#define GPLL4_EARLY 2
> +#define GPLL4 3
> +#define UFS_AXI_CLK_SRC 4
> +#define USB30_MASTER_CLK_SRC 5
> +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
> +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
> +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
> +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
> +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
> +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
> +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
> +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
> +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
> +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
> +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
> +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
> +#define BLSP1_UART1_APPS_CLK_SRC 18
> +#define BLSP1_UART2_APPS_CLK_SRC 19
> +#define BLSP1_UART3_APPS_CLK_SRC 20
> +#define BLSP1_UART4_APPS_CLK_SRC 21
> +#define BLSP1_UART5_APPS_CLK_SRC 22
> +#define BLSP1_UART6_APPS_CLK_SRC 23
> +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
> +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
> +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
> +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
> +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
> +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
> +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
> +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
> +#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
> +#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
> +#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
> +#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
> +#define BLSP2_UART1_APPS_CLK_SRC 36
> +#define BLSP2_UART2_APPS_CLK_SRC 37
> +#define BLSP2_UART3_APPS_CLK_SRC 38
> +#define BLSP2_UART4_APPS_CLK_SRC 39
> +#define BLSP2_UART5_APPS_CLK_SRC 40
> +#define BLSP2_UART6_APPS_CLK_SRC 41
> +#define GP1_CLK_SRC 42
> +#define GP2_CLK_SRC 43
> +#define GP3_CLK_SRC 44
> +#define PCIE_0_AUX_CLK_SRC 45
> +#define PCIE_0_PIPE_CLK_SRC 46
> +#define PCIE_1_AUX_CLK_SRC 47
> +#define PCIE_1_PIPE_CLK_SRC 48
> +#define PDM2_CLK_SRC 49
> +#define SDCC1_APPS_CLK_SRC 50
> +#define SDCC2_APPS_CLK_SRC 51
> +#define SDCC3_APPS_CLK_SRC 52
> +#define SDCC4_APPS_CLK_SRC 53
> +#define TSIF_REF_CLK_SRC 54
> +#define USB30_MOCK_UTMI_CLK_SRC 55
> +#define USB3_PHY_AUX_CLK_SRC 56
> +#define USB_HS_SYSTEM_CLK_SRC 57
> +#define GCC_BLSP1_AHB_CLK 58
> +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
> +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
> +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
> +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
> +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
> +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
> +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
> +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
> +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
> +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
> +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
> +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
> +#define GCC_BLSP1_UART1_APPS_CLK 71
> +#define GCC_BLSP1_UART2_APPS_CLK 72
> +#define GCC_BLSP1_UART3_APPS_CLK 73
> +#define GCC_BLSP1_UART4_APPS_CLK 74
> +#define GCC_BLSP1_UART5_APPS_CLK 75
> +#define GCC_BLSP1_UART6_APPS_CLK 76
> +#define GCC_BLSP2_AHB_CLK 77
> +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
> +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
> +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
> +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
> +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
> +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
> +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
> +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
> +#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
> +#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
> +#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
> +#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
> +#define GCC_BLSP2_UART1_APPS_CLK 90
> +#define GCC_BLSP2_UART2_APPS_CLK 91
> +#define GCC_BLSP2_UART3_APPS_CLK 92
> +#define GCC_BLSP2_UART4_APPS_CLK 93
> +#define GCC_BLSP2_UART5_APPS_CLK 94
> +#define GCC_BLSP2_UART6_APPS_CLK 95
> +#define GCC_GP1_CLK 96
> +#define GCC_GP2_CLK 97
> +#define GCC_GP3_CLK 98
> +#define GCC_PCIE_0_AUX_CLK 99
> +#define GCC_PCIE_0_PIPE_CLK 100
> +#define GCC_PCIE_1_AUX_CLK 101
> +#define GCC_PCIE_1_PIPE_CLK 102
> +#define GCC_PDM2_CLK 103
> +#define GCC_SDCC1_APPS_CLK 104
> +#define GCC_SDCC2_APPS_CLK 105
> +#define GCC_SDCC3_APPS_CLK 106
> +#define GCC_SDCC4_APPS_CLK 107
> +#define GCC_SYS_NOC_UFS_AXI_CLK 108
> +#define GCC_SYS_NOC_USB3_AXI_CLK 109
> +#define GCC_TSIF_REF_CLK 110
> +#define GCC_UFS_AXI_CLK 111
> +#define GCC_UFS_RX_CFG_CLK 112
> +#define GCC_UFS_TX_CFG_CLK 113
> +#define GCC_USB30_MASTER_CLK 114
> +#define GCC_USB30_MOCK_UTMI_CLK 115
> +#define GCC_USB3_PHY_AUX_CLK 116
> +#define GCC_USB_HS_SYSTEM_CLK 117
> +
> +/* Indexes for GDSCs */
> +#define BIMC_GDSC 0
> +#define VENUS_GDSC 1
> +#define MDSS_GDSC 2
> +#define JPEG_GDSC 3
> +#define VFE_GDSC 4
> +#define OXILI_GDSC 5
> +
> +#endif
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 2/4] msm8994 clocks: global clock support Global clock support for the msm8994 SOC.
@ 2016-07-12 2:30 ` Jeremy McNicoll
0 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-07-12 2:30 UTC (permalink / raw)
To: linux-arm-kernel
On 2016-07-07 5:41 PM, Jeremy McNicoll wrote:
> From: Bastian K?cher <mail@kchr.de>
>
> The clock definition was ported from the Google 3.10 kernel tree to
> work with the latest kernel.
>
> Signed-off-by: Bastian K?cher <mail@kchr.de>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 2 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-msm8994.c | 2501 ++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-msm8994.h | 145 ++
> 5 files changed, 2658 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-msm8994.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8994.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> index 9a60fde..a1dc2fe 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> @@ -14,6 +14,8 @@ Required properties :
> "qcom,gcc-msm8974"
> "qcom,gcc-msm8974pro"
> "qcom,gcc-msm8974pro-ac"
> + "qcom,gcc-msm8994"
> + "qcom,gcc-msm8994v2"
> "qcom,gcc-msm8996"
>
> - reg : shall contain base register location and length
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 95e3b3e..6687c7f 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -115,6 +115,15 @@ config MSM_MMCC_8974
> Say Y if you want to support multimedia devices such as display,
> graphics, video encode/decode, camera, etc.
>
> +config MSM_GCC_8994
> + tristate "MSM8994 Global Clock Controller"
> + select QCOM_GDSC
> + depends on COMMON_CLK_QCOM
> + help
> + Support for the global clock controller on msm8994 devices.
> + Say Y if you want to use peripheral devices such as UART, SPI,
> + i2c, USB, SD/eMMC, SATA, PCIe, etc.
> +
> config MSM_GCC_8996
> tristate "MSM8996 Global Clock Controller"
> depends on COMMON_CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 2a25f4e..551a64d 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
> obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
> obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
> obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
> +obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
> obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
> obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
> obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
> diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
> new file mode 100644
> index 0000000..3897cfd
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-msm8994.c
> @@ -0,0 +1,2501 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/err.h>
> +#include <linux/ctype.h>
> +#include <linux/io.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "reset.h"
> +
> +enum {
> + P_XO,
> + P_GPLL0,
> + P_GPLL4,
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> +};
> +
> +static const char * const gcc_xo_gpll0[] = {
> + "xo",
> + "gpll0",
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL4, 2 },
sboyd on IRC today that P_GPLL4 needs to be 5.
gcc_xo_gpll0_gpll4_map[] -> 0, 1, 5
Hopefully he will have time to review and provide feedback on the rest
of the changes.
-jeremy
> +};
> +
> +static const char * const gcc_xo_gpll0_gpll4[] = {
> + "xo",
> + "gpll0",
> + "gpll4",
> +};
> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
> +
> +static struct clk_fixed_factor xo = {
> + .mult = 1,
> + .div = 1,
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "xo",
> + .parent_names = (const char *[]) { "xo_board" },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll0_early = {
> + .offset = 0x00000,
> + .clkr = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll0_early",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> + .offset = 0x00000,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll0",
> + .parent_names = (const char *[]) { "gpll0_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll4_early = {
> + .offset = 0x1DC0,
> + .clkr = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll4_early",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll4 = {
> + .offset = 0x1DC0,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll4",
> + .parent_names = (const char *[]) { "gpll4_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(171430000, P_GPLL0, 3.5, 0, 0),
> + { }
> +};
> +
> +static struct freq_tbl ftbl_ufs_axi_clk_src_v2[] = {
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(171430000, P_GPLL0, 3.5, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + F(240000000, P_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 ufs_axi_clk_src = {
> + .cmd_rcgr = 0x1D68,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_ufs_axi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "ufs_axi_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb30_master_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(125000000, P_GPLL0, 1, 5, 24),
> + { }
> +};
> +
> +static struct clk_rcg2 usb30_master_clk_src = {
> + .cmd_rcgr = 0x03D4,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_usb30_master_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb30_master_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0660,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup1_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blspqup_spi_apps_clk_src_v2[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x064C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup1_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x06E0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup2_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(46150000, P_GPLL0, 13, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x06CC,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup2_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0760,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup3_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup3_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x074C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup3_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup3_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x07E0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup4_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup4_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x07CC,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup4_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup4_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0860,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup5_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(40000000, P_GPLL0, 15, 0, 0),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> + .cmd_rcgr = 0x084C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup5_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x08E0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup6_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(41380000, P_GPLL0, 14.5, 0, 0),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> + .cmd_rcgr = 0x08CC,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_qup6_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
> + F(3686400, P_GPLL0, 1, 96, 15625),
> + F(7372800, P_GPLL0, 1, 192, 15625),
> + F(14745600, P_GPLL0, 1, 384, 15625),
> + F(16000000, P_GPLL0, 5, 2, 15),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 5, 1, 5),
> + F(32000000, P_GPLL0, 1, 4, 75),
> + F(40000000, P_GPLL0, 15, 0, 0),
> + F(46400000, P_GPLL0, 1, 29, 375),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(51200000, P_GPLL0, 1, 32, 375),
> + F(56000000, P_GPLL0, 1, 7, 75),
> + F(58982400, P_GPLL0, 1, 1536, 15625),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + F(63160000, P_GPLL0, 9.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x068C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart1_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x070C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart2_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> + .cmd_rcgr = 0x078C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart3_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> + .cmd_rcgr = 0x080C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart4_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> + .cmd_rcgr = 0x088C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart5_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> + .cmd_rcgr = 0x090C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp1_uart6_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x09A0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup1_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup1_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x098C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup1_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0A20,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup2_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup2_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0A0C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup2_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup2_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0AA0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup3_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup3_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0A8C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup3_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup3_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0B20,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup4_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup4_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(42860000, P_GPLL0, 14, 0, 0),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0B0C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup4_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup4_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0BA0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup5_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup5_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0B8C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup5_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup5_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0C20,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup6_i2c_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 12.5, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(44440000, P_GPLL0, 13.5, 0, 0),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> + .cmd_rcgr = 0x0C0C,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_qup6_spi_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x09CC,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart1_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x0A4C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart2_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> + .cmd_rcgr = 0x0ACC,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart3_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> + .cmd_rcgr = 0x0B4C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart4_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> + .cmd_rcgr = 0x0BCC,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart5_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> + .cmd_rcgr = 0x0C4C,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "blsp2_uart6_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_gp1_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp1_clk_src = {
> + .cmd_rcgr = 0x1904,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gp1_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_gp2_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp2_clk_src = {
> + .cmd_rcgr = 0x1944,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_gp2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gp2_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_gp3_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp3_clk_src = {
> + .cmd_rcgr = 0x1984,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_gp3_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gp3_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
> + F(1011000, P_XO, 1, 1, 19),
> + { }
> +};
> +
> +static struct clk_rcg2 pcie_0_aux_clk_src = {
> + .cmd_rcgr = 0x1B00,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_0_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_0_aux_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
> + F(125000000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 pcie_0_pipe_clk_src = {
> + .cmd_rcgr = 0x1ADC,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_pipe_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_0_pipe_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
> + F(1011000, P_XO, 1, 1, 19),
> + { }
> +};
> +
> +static struct clk_rcg2 pcie_1_aux_clk_src = {
> + .cmd_rcgr = 0x1B80,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_1_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_1_aux_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 pcie_1_pipe_clk_src = {
> + .cmd_rcgr = 0x1B5C,
> + .hid_width = 5,
> + .freq_tbl = ftbl_pcie_pipe_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pcie_1_pipe_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_pdm2_clk_src[] = {
> + F(60000000, P_GPLL0, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 pdm2_clk_src = {
> + .cmd_rcgr = 0x0CD0,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_pdm2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "pdm2_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
> + F(144000, P_XO, 16, 3, 25),
> + F(400000, P_XO, 12, 1, 4),
> + F(20000000, P_GPLL0, 15, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(192000000, P_GPLL4, 2, 0, 0),
> + F(384000000, P_GPLL4, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc1_apps_clk_src = {
> + .cmd_rcgr = 0x04D0,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll4_map,
> + .freq_tbl = ftbl_sdcc1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc1_apps_clk_src",
> + .parent_names = gcc_xo_gpll0_gpll4,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
> + F(144000, P_XO, 16, 3, 25),
> + F(400000, P_XO, 12, 1, 4),
> + F(20000000, P_GPLL0, 15, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc2_apps_clk_src = {
> + .cmd_rcgr = 0x0510,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc2_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 sdcc3_apps_clk_src = {
> + .cmd_rcgr = 0x0550,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc3_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 sdcc4_apps_clk_src = {
> + .cmd_rcgr = 0x0590,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "sdcc4_apps_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
> + F(105500, P_XO, 1, 1, 182),
> + { }
> +};
> +
> +static struct clk_rcg2 tsif_ref_clk_src = {
> + .cmd_rcgr = 0x0D90,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .freq_tbl = ftbl_tsif_ref_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "tsif_ref_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> + .cmd_rcgr = 0x03E8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb30_mock_utmi_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
> + F(1200000, P_XO, 16, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb3_phy_aux_clk_src = {
> + .cmd_rcgr = 0x1414,
> + .hid_width = 5,
> + .freq_tbl = ftbl_usb3_phy_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb3_phy_aux_clk_src",
> + .parent_names = (const char *[]) { "xo" },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
> + F(75000000, P_GPLL0, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb_hs_system_clk_src = {
> + .cmd_rcgr = 0x0490,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_usb_hs_system_clk_src,
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "usb_hs_system_clk_src",
> + .parent_names = gcc_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_ahb_clk = {
> + .halt_reg = 0x05C4,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1484,
> + .enable_mask = BIT(17),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> + .halt_reg = 0x0648,
> + .clkr = {
> + .enable_reg = 0x0648,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup1_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup1_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> + .halt_reg = 0x0644,
> + .clkr = {
> + .enable_reg = 0x0644,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup1_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup1_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> + .halt_reg = 0x06C8,
> + .clkr = {
> + .enable_reg = 0x06C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup2_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup2_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> + .halt_reg = 0x06C4,
> + .clkr = {
> + .enable_reg = 0x06C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup2_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup2_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> + .halt_reg = 0x0748,
> + .clkr = {
> + .enable_reg = 0x0748,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup3_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup3_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> + .halt_reg = 0x0744,
> + .clkr = {
> + .enable_reg = 0x0744,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup3_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup3_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> + .halt_reg = 0x07C8,
> + .clkr = {
> + .enable_reg = 0x07C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup4_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup4_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> + .halt_reg = 0x07C4,
> + .clkr = {
> + .enable_reg = 0x07C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup4_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup4_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> + .halt_reg = 0x0848,
> + .clkr = {
> + .enable_reg = 0x0848,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup5_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup5_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> + .halt_reg = 0x0844,
> + .clkr = {
> + .enable_reg = 0x0844,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup5_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup5_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> + .halt_reg = 0x08C8,
> + .clkr = {
> + .enable_reg = 0x08C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup6_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup6_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> + .halt_reg = 0x08C4,
> + .clkr = {
> + .enable_reg = 0x08C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_qup6_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_qup6_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> + .halt_reg = 0x0684,
> + .clkr = {
> + .enable_reg = 0x0684,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart1_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> + .halt_reg = 0x0704,
> + .clkr = {
> + .enable_reg = 0x0704,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart2_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> + .halt_reg = 0x0784,
> + .clkr = {
> + .enable_reg = 0x0784,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart3_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart3_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart4_apps_clk = {
> + .halt_reg = 0x0804,
> + .clkr = {
> + .enable_reg = 0x0804,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart4_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart4_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart5_apps_clk = {
> + .halt_reg = 0x0884,
> + .clkr = {
> + .enable_reg = 0x0884,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart5_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart5_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart6_apps_clk = {
> + .halt_reg = 0x0904,
> + .clkr = {
> + .enable_reg = 0x0904,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp1_uart6_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp1_uart6_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_ahb_clk = {
> + .halt_reg = 0x0944,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1484,
> + .enable_mask = BIT(15),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> + .halt_reg = 0x0988,
> + .clkr = {
> + .enable_reg = 0x0988,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup1_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup1_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> + .halt_reg = 0x0984,
> + .clkr = {
> + .enable_reg = 0x0984,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup1_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup1_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> + .halt_reg = 0x0A08,
> + .clkr = {
> + .enable_reg = 0x0A08,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup2_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup2_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> + .halt_reg = 0x0A04,
> + .clkr = {
> + .enable_reg = 0x0A04,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup2_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup2_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> + .halt_reg = 0x0A88,
> + .clkr = {
> + .enable_reg = 0x0A88,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup3_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup3_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> + .halt_reg = 0x0A84,
> + .clkr = {
> + .enable_reg = 0x0A84,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup3_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup3_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> + .halt_reg = 0x0B08,
> + .clkr = {
> + .enable_reg = 0x0B08,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup4_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup4_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> + .halt_reg = 0x0B04,
> + .clkr = {
> + .enable_reg = 0x0B04,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup4_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup4_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
> + .halt_reg = 0x0B88,
> + .clkr = {
> + .enable_reg = 0x0B88,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup5_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup5_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
> + .halt_reg = 0x0B84,
> + .clkr = {
> + .enable_reg = 0x0B84,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup5_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup5_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
> + .halt_reg = 0x0C08,
> + .clkr = {
> + .enable_reg = 0x0C08,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup6_i2c_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup6_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
> + .halt_reg = 0x0C04,
> + .clkr = {
> + .enable_reg = 0x0C04,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_qup6_spi_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_qup6_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> + .halt_reg = 0x09C4,
> + .clkr = {
> + .enable_reg = 0x09C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart1_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> + .halt_reg = 0x0A44,
> + .clkr = {
> + .enable_reg = 0x0A44,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart2_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart3_apps_clk = {
> + .halt_reg = 0x0AC4,
> + .clkr = {
> + .enable_reg = 0x0AC4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart3_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart3_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart4_apps_clk = {
> + .halt_reg = 0x0B44,
> + .clkr = {
> + .enable_reg = 0x0B44,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart4_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart4_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart5_apps_clk = {
> + .halt_reg = 0x0BC4,
> + .clkr = {
> + .enable_reg = 0x0BC4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart5_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart5_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart6_apps_clk = {
> + .halt_reg = 0x0C44,
> + .clkr = {
> + .enable_reg = 0x0C44,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_blsp2_uart6_apps_clk",
> + .parent_names = (const char *[]) {
> + "blsp2_uart6_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp1_clk = {
> + .halt_reg = 0x1900,
> + .clkr = {
> + .enable_reg = 0x1900,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_gp1_clk",
> + .parent_names = (const char *[]) {
> + "gp1_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp2_clk = {
> + .halt_reg = 0x1940,
> + .clkr = {
> + .enable_reg = 0x1940,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_gp2_clk",
> + .parent_names = (const char *[]) {
> + "gp2_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp3_clk = {
> + .halt_reg = 0x1980,
> + .clkr = {
> + .enable_reg = 0x1980,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_gp3_clk",
> + .parent_names = (const char *[]) {
> + "gp3_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_aux_clk = {
> + .halt_reg = 0x1AD4,
> + .clkr = {
> + .enable_reg = 0x1AD4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_0_aux_clk",
> + .parent_names = (const char *[]) {
> + "pcie_0_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_pipe_clk = {
> + .halt_reg = 0x1AD8,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1AD8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_0_pipe_clk",
> + .parent_names = (const char *[]) {
> + "pcie_0_pipe_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_aux_clk = {
> + .halt_reg = 0x1B54,
> + .clkr = {
> + .enable_reg = 0x1B54,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_1_aux_clk",
> + .parent_names = (const char *[]) {
> + "pcie_1_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_pipe_clk = {
> + .halt_reg = 0x1B58,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1B58,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pcie_1_pipe_clk",
> + .parent_names = (const char *[]) {
> + "pcie_1_pipe_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pdm2_clk = {
> + .halt_reg = 0x0CCC,
> + .clkr = {
> + .enable_reg = 0x0CCC,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_pdm2_clk",
> + .parent_names = (const char *[]) {
> + "pdm2_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_apps_clk = {
> + .halt_reg = 0x04C4,
> + .clkr = {
> + .enable_reg = 0x04C4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc1_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc2_apps_clk = {
> + .halt_reg = 0x0504,
> + .clkr = {
> + .enable_reg = 0x0504,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc2_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc3_apps_clk = {
> + .halt_reg = 0x0544,
> + .clkr = {
> + .enable_reg = 0x0544,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc3_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc3_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc4_apps_clk = {
> + .halt_reg = 0x0584,
> + .clkr = {
> + .enable_reg = 0x0584,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sdcc4_apps_clk",
> + .parent_names = (const char *[]) {
> + "sdcc4_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
> + .halt_reg = 0x1D7C,
> + .clkr = {
> + .enable_reg = 0x1D7C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sys_noc_ufs_axi_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
> + .halt_reg = 0x03FC,
> + .clkr = {
> + .enable_reg = 0x03FC,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_sys_noc_usb3_axi_clk",
> + .parent_names = (const char *[]) {
> + "usb30_master_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_tsif_ref_clk = {
> + .halt_reg = 0x0D88,
> + .clkr = {
> + .enable_reg = 0x0D88,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_tsif_ref_clk",
> + .parent_names = (const char *[]) {
> + "tsif_ref_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_axi_clk = {
> + .halt_reg = 0x1D48,
> + .clkr = {
> + .enable_reg = 0x1D48,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_ufs_axi_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_rx_cfg_clk = {
> + .halt_reg = 0x1D54,
> + .clkr = {
> + .enable_reg = 0x1D54,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_ufs_rx_cfg_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_tx_cfg_clk = {
> + .halt_reg = 0x1D50,
> + .clkr = {
> + .enable_reg = 0x1D50,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_ufs_tx_cfg_clk",
> + .parent_names = (const char *[]) {
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_master_clk = {
> + .halt_reg = 0x03C8,
> + .clkr = {
> + .enable_reg = 0x03C8,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb30_master_clk",
> + .parent_names = (const char *[]) {
> + "usb30_master_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_mock_utmi_clk = {
> + .halt_reg = 0x03D0,
> + .clkr = {
> + .enable_reg = 0x03D0,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb30_mock_utmi_clk",
> + .parent_names = (const char *[]) {
> + "usb30_mock_utmi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_phy_aux_clk = {
> + .halt_reg = 0x1408,
> + .clkr = {
> + .enable_reg = 0x1408,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb3_phy_aux_clk",
> + .parent_names = (const char *[]) {
> + "usb3_phy_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb_hs_system_clk = {
> + .halt_reg = 0x0484,
> + .clkr = {
> + .enable_reg = 0x0484,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data)
> + {
> + .name = "gcc_usb_hs_system_clk",
> + .parent_names = (const char *[]) {
> + "usb_hs_system_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap *gcc_msm8994_clocks[] = {
> + [GPLL0_EARLY] = &gpll0_early.clkr,
> + [GPLL0] = &gpll0.clkr,
> + [GPLL4_EARLY] = &gpll4_early.clkr,
> + [GPLL4] = &gpll4.clkr,
> + [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
> + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
> + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
> + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
> + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
> + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
> + [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
> + [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
> + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
> + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
> + [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
> + [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
> + [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
> + [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
> + [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
> + [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
> + [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
> + [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
> + [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
> + [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
> + [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
> + [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
> + [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
> + [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
> + [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
> + [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
> + [GP1_CLK_SRC] = &gp1_clk_src.clkr,
> + [GP2_CLK_SRC] = &gp2_clk_src.clkr,
> + [GP3_CLK_SRC] = &gp3_clk_src.clkr,
> + [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
> + [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
> + [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
> + [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
> + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
> + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
> + [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
> + [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
> + [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
> + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
> + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
> + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
> + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
> + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
> + [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
> + [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
> + [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
> + [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
> + [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
> + [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
> + [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
> + [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
> + [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
> + [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
> + [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
> + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
> + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
> + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
> + [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
> + [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
> + [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
> + [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
> + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
> + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
> + [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
> + [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
> + [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
> + [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
> + [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
> + [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
> + [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
> + [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
> + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
> + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
> + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
> + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
> +};
> +
> +static void msm_gcc_8994v2_fixup(void)
> +{
> + ufs_axi_clk_src.freq_tbl = ftbl_ufs_axi_clk_src_v2;
> +
> + blsp1_qup1_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup2_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup3_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup4_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup5_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp1_qup6_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup1_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup2_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup3_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup4_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup5_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> + blsp2_qup6_spi_apps_clk_src.freq_tbl = ftbl_blspqup_spi_apps_clk_src_v2;
> +}
> +
> +static const struct regmap_config gcc_msm8994_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x2000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gcc_msm8994_desc = {
> + .config = &gcc_msm8994_regmap_config,
> + .clks = gcc_msm8994_clocks,
> + .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
> + .resets = NULL,
> + .num_resets = 0,
> + .gdscs = NULL,
> + .num_gdscs = 0,
> +};
> +
> +static const struct of_device_id gcc_msm8994_match_table[] = {
> + { .compatible = "qcom,gcc-8994" },
> + { .compatible = "qcom,gcc-8994v2" },
> + {}
> +}
> +
> +MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
> +
> +static int gcc_msm8994_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct clk *clk;
> + const char *compat = NULL;
> + int compatlen = 0;
> + bool is_v2 = false;
> +
> + clk = devm_clk_register(dev, &xo.hw);
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
> + if (!compat || (compatlen <= 0))
> + return -EINVAL;
> +
> + is_v2 = !strcmp(compat, "qcom,gcc-8994v2");
> + if (is_v2)
> + msm_gcc_8994v2_fixup();
> +
> + return qcom_cc_probe(pdev, &gcc_msm8994_desc);
> +}
> +
> +static struct platform_driver gcc_msm8994_driver = {
> + .probe = gcc_msm8994_probe,
> + .driver = {
> + .name = "gcc-msm8994",
> + .of_match_table = gcc_msm8994_match_table,
> + },
> +};
> +
> +static int __init gcc_msm8994_init(void)
> +{
> + return platform_driver_register(&gcc_msm8994_driver);
> +}
> +core_initcall(gcc_msm8994_init);
> +
> +static void __exit gcc_msm8994_exit(void)
> +{
> + platform_driver_unregister(&gcc_msm8994_driver);
> +}
> +module_exit(gcc_msm8994_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:gcc-msm8994");
> diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
> new file mode 100644
> index 0000000..0ae494b
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
> +#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
> +
> +#define GPLL0_EARLY 0
> +#define GPLL0 1
> +#define GPLL4_EARLY 2
> +#define GPLL4 3
> +#define UFS_AXI_CLK_SRC 4
> +#define USB30_MASTER_CLK_SRC 5
> +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
> +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
> +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
> +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
> +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
> +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
> +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
> +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
> +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
> +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
> +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
> +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
> +#define BLSP1_UART1_APPS_CLK_SRC 18
> +#define BLSP1_UART2_APPS_CLK_SRC 19
> +#define BLSP1_UART3_APPS_CLK_SRC 20
> +#define BLSP1_UART4_APPS_CLK_SRC 21
> +#define BLSP1_UART5_APPS_CLK_SRC 22
> +#define BLSP1_UART6_APPS_CLK_SRC 23
> +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
> +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
> +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
> +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
> +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
> +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
> +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
> +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
> +#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
> +#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
> +#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
> +#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
> +#define BLSP2_UART1_APPS_CLK_SRC 36
> +#define BLSP2_UART2_APPS_CLK_SRC 37
> +#define BLSP2_UART3_APPS_CLK_SRC 38
> +#define BLSP2_UART4_APPS_CLK_SRC 39
> +#define BLSP2_UART5_APPS_CLK_SRC 40
> +#define BLSP2_UART6_APPS_CLK_SRC 41
> +#define GP1_CLK_SRC 42
> +#define GP2_CLK_SRC 43
> +#define GP3_CLK_SRC 44
> +#define PCIE_0_AUX_CLK_SRC 45
> +#define PCIE_0_PIPE_CLK_SRC 46
> +#define PCIE_1_AUX_CLK_SRC 47
> +#define PCIE_1_PIPE_CLK_SRC 48
> +#define PDM2_CLK_SRC 49
> +#define SDCC1_APPS_CLK_SRC 50
> +#define SDCC2_APPS_CLK_SRC 51
> +#define SDCC3_APPS_CLK_SRC 52
> +#define SDCC4_APPS_CLK_SRC 53
> +#define TSIF_REF_CLK_SRC 54
> +#define USB30_MOCK_UTMI_CLK_SRC 55
> +#define USB3_PHY_AUX_CLK_SRC 56
> +#define USB_HS_SYSTEM_CLK_SRC 57
> +#define GCC_BLSP1_AHB_CLK 58
> +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
> +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
> +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
> +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
> +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
> +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
> +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
> +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
> +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
> +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
> +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
> +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
> +#define GCC_BLSP1_UART1_APPS_CLK 71
> +#define GCC_BLSP1_UART2_APPS_CLK 72
> +#define GCC_BLSP1_UART3_APPS_CLK 73
> +#define GCC_BLSP1_UART4_APPS_CLK 74
> +#define GCC_BLSP1_UART5_APPS_CLK 75
> +#define GCC_BLSP1_UART6_APPS_CLK 76
> +#define GCC_BLSP2_AHB_CLK 77
> +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
> +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
> +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
> +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
> +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
> +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
> +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
> +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
> +#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
> +#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
> +#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
> +#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
> +#define GCC_BLSP2_UART1_APPS_CLK 90
> +#define GCC_BLSP2_UART2_APPS_CLK 91
> +#define GCC_BLSP2_UART3_APPS_CLK 92
> +#define GCC_BLSP2_UART4_APPS_CLK 93
> +#define GCC_BLSP2_UART5_APPS_CLK 94
> +#define GCC_BLSP2_UART6_APPS_CLK 95
> +#define GCC_GP1_CLK 96
> +#define GCC_GP2_CLK 97
> +#define GCC_GP3_CLK 98
> +#define GCC_PCIE_0_AUX_CLK 99
> +#define GCC_PCIE_0_PIPE_CLK 100
> +#define GCC_PCIE_1_AUX_CLK 101
> +#define GCC_PCIE_1_PIPE_CLK 102
> +#define GCC_PDM2_CLK 103
> +#define GCC_SDCC1_APPS_CLK 104
> +#define GCC_SDCC2_APPS_CLK 105
> +#define GCC_SDCC3_APPS_CLK 106
> +#define GCC_SDCC4_APPS_CLK 107
> +#define GCC_SYS_NOC_UFS_AXI_CLK 108
> +#define GCC_SYS_NOC_USB3_AXI_CLK 109
> +#define GCC_TSIF_REF_CLK 110
> +#define GCC_UFS_AXI_CLK 111
> +#define GCC_UFS_RX_CFG_CLK 112
> +#define GCC_UFS_TX_CFG_CLK 113
> +#define GCC_USB30_MASTER_CLK 114
> +#define GCC_USB30_MOCK_UTMI_CLK 115
> +#define GCC_USB3_PHY_AUX_CLK 116
> +#define GCC_USB_HS_SYSTEM_CLK 117
> +
> +/* Indexes for GDSCs */
> +#define BIMC_GDSC 0
> +#define VENUS_GDSC 1
> +#define MDSS_GDSC 2
> +#define JPEG_GDSC 3
> +#define VFE_GDSC 4
> +#define OXILI_GDSC 5
> +
> +#endif
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
2016-07-08 17:41 ` Andy Gross
@ 2016-09-21 0:42 ` Jeremy McNicoll
-1 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-09-21 0:42 UTC (permalink / raw)
To: Andy Gross; +Cc: linux-arm-msm, linux-arm-kernel, stephen.boyd, mail, jeremymc
On 2016-07-08 10:41 AM, Andy Gross wrote:
> On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
>> Initial device tree support for Qualcomm MSM8992 SoC and
>> LG Bullhead / Google Nexus 5X support.
>>
Hopefully that was enough time for people to enjoy their summer
vacations and welcome new additions to the family.
>> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
>> ---
>> arch/arm64/Kconfig.platforms | 12 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/lge/Makefile | 5 +
>> .../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +++
>> arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +++
>> arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++++++++++++
>> arch/arm64/configs/bullhead_defconfig | 377 +++++++++++++++++++++
>> arch/arm64/configs/msm8992_defconfig | 5 +
>> 8 files changed, 700 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/lge/Makefile
>> create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
>> create mode 100644 arch/arm64/configs/bullhead_defconfig
>> create mode 100644 arch/arm64/configs/msm8992_defconfig
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 7ef1d05..515e669 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -86,6 +86,18 @@ config ARCH_QCOM
>> help
>> This enables support for the ARMv8 based Qualcomm chipsets.
>>
>> +config ARCH_MSM8992
>> + bool "Qualcomm MSM8992"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the Qualcomm MSM8992 SoC.
>> +
>> +config MACH_LGE
>> + bool "LGE BullHead (MSM8992)"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> We don't add config options for End users. Only for Soc Companies or people
> actually producing the silicon.
>
removed.
>> +
>> config ARCH_ROCKCHIP
>> bool "Rockchip Platforms"
>> select ARCH_HAS_RESET_CONTROLLER
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index 6e199c9..bde90fb 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -13,6 +13,7 @@ dts-dirs += marvell
>> dts-dirs += mediatek
>> dts-dirs += nvidia
>> dts-dirs += qcom
>> +dts-dirs += lge
>
> No, please add the files to the qcom directory.
>
ok, done
>> dts-dirs += renesas
>> dts-dirs += rockchip
>> dts-dirs += socionext
>> diff --git a/arch/arm64/boot/dts/lge/Makefile b/arch/arm64/boot/dts/lge/Makefile
>> new file mode 100644
>> index 0000000..f4e7860
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/lge/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_MACH_LGE) += msm8992-bullhead-rev-101.dtb
>> +
>> +always := $(dtb-y)
>> +subdir-y := $(dts-dirs)
>> +clean-files := *.dtb
>> diff --git a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> new file mode 100644
>> index 0000000..860cded
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> @@ -0,0 +1,41 @@
>> +/* Copyright (c) 2015, LGE Inc. All rights reserved.
>> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "../qcom/msm8992.dtsi"
>> +
>> +/ {
>> + model = "LGE MSM8992 BULLHEAD rev-1.01";
>> + compatible = "qcom,msm8992";
>> + qcom,board-id = <0xb64 0>;
>
> Please work with sboyd to add the board-id to the dtbTool. We don't put
> board-ids in the dts file. We post-process the dtb file and add them then.
>
sboyd has all the info he needs for this, I believe its just with legal
now. Will remove for V2.
It would be nice if we could get this dtbTool to automagically run as
part of the build system.
>
>> +};
>> +
>> +/ {
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> + };
>> +
>> + soc {
>> + serial@f991e000 {
>> + status = "okay";
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&blsp1_uart2_default>;
>> + pinctrl-1 = <&blsp1_uart2_sleep>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
>
> <snip>
>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
>> new file mode 100644
>> index 0000000..fa92a1a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
>> @@ -0,0 +1,221 @@
>> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/memreserve/ 0x00000000 0x00001000;
>
> Please use reserved-memory{}. And why are they setting aside 4k at the
> beginning? Trying to cover up corruption issues?
>
I only have the existing kernel (3.10) and no insight as to why this is
needed. Something very interesting and/or unexpected was that I needed
memreserve when using earlycon combined with
CONFIG_DEBUG_DRIVER && CONFIG_DEBUG_DEVRES
in order for the target / phone to boot. It have very well booted its
just I cant tell given the serial debug is the way I currently have to
gain visibility into the status of the phone.
But when I turned off the a fore mentioned config options and continued
to use earlycon it booted fine.
Removing memreserve.
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8992";
>> + compatible = "qcom,msm8992";
>> + qcom,msm-id = <251 0>, <252 0>;
This is needed or else the LK provides the following error
[5380] qcom,msm-id entry not found
and refuses to boot.
>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>
> See above comment on ids.
removal of this (pmic-id) seems to be ok.
>
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>
> <snip>
>
>> +#include "msm8992-pins.dtsi"
>> diff --git a/arch/arm64/configs/bullhead_defconfig b/arch/arm64/configs/bullhead_defconfig
>
> Please add whatever config options you have to the default defconfig. we don't
> define board specific configs for ARM64 platforms. Or I should say, they won't
> be accepted into the kernel.
>
> Also, please separate defconfig changes into separate patches.
>
Will keep the changes to the absolute minimum.
Looks like I am going to need these 3
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
as this unit doent have all the bits'N pieces working currently and is
_ONLY_ able to boot a ramdisk.
-jeremy
> <snip>
>
>> diff --git a/arch/arm64/configs/msm8992_defconfig b/arch/arm64/configs/msm8992_defconfig
>> new file mode 100644
>> index 0000000..f673a27
>> --- /dev/null
>> +++ b/arch/arm64/configs/msm8992_defconfig
>
> See above comment.
>> @@ -0,0 +1,5 @@
>> +CONFIG_NO_HZ=y
>> +CONFIG_HIGH_RES_TIMERS=y
>> +CONFIG_SCHED_HMP=y
>> +CONFIG_NAMESPACES=y
>> +# CONFIG_CORESIGHT is not set
>> --
>> 2.6.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
@ 2016-09-21 0:42 ` Jeremy McNicoll
0 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-09-21 0:42 UTC (permalink / raw)
To: linux-arm-kernel
On 2016-07-08 10:41 AM, Andy Gross wrote:
> On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
>> Initial device tree support for Qualcomm MSM8992 SoC and
>> LG Bullhead / Google Nexus 5X support.
>>
Hopefully that was enough time for people to enjoy their summer
vacations and welcome new additions to the family.
>> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
>> ---
>> arch/arm64/Kconfig.platforms | 12 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/lge/Makefile | 5 +
>> .../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +++
>> arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +++
>> arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++++++++++++
>> arch/arm64/configs/bullhead_defconfig | 377 +++++++++++++++++++++
>> arch/arm64/configs/msm8992_defconfig | 5 +
>> 8 files changed, 700 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/lge/Makefile
>> create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
>> create mode 100644 arch/arm64/configs/bullhead_defconfig
>> create mode 100644 arch/arm64/configs/msm8992_defconfig
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 7ef1d05..515e669 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -86,6 +86,18 @@ config ARCH_QCOM
>> help
>> This enables support for the ARMv8 based Qualcomm chipsets.
>>
>> +config ARCH_MSM8992
>> + bool "Qualcomm MSM8992"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the Qualcomm MSM8992 SoC.
>> +
>> +config MACH_LGE
>> + bool "LGE BullHead (MSM8992)"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> We don't add config options for End users. Only for Soc Companies or people
> actually producing the silicon.
>
removed.
>> +
>> config ARCH_ROCKCHIP
>> bool "Rockchip Platforms"
>> select ARCH_HAS_RESET_CONTROLLER
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index 6e199c9..bde90fb 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -13,6 +13,7 @@ dts-dirs += marvell
>> dts-dirs += mediatek
>> dts-dirs += nvidia
>> dts-dirs += qcom
>> +dts-dirs += lge
>
> No, please add the files to the qcom directory.
>
ok, done
>> dts-dirs += renesas
>> dts-dirs += rockchip
>> dts-dirs += socionext
>> diff --git a/arch/arm64/boot/dts/lge/Makefile b/arch/arm64/boot/dts/lge/Makefile
>> new file mode 100644
>> index 0000000..f4e7860
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/lge/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_MACH_LGE) += msm8992-bullhead-rev-101.dtb
>> +
>> +always := $(dtb-y)
>> +subdir-y := $(dts-dirs)
>> +clean-files := *.dtb
>> diff --git a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> new file mode 100644
>> index 0000000..860cded
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> @@ -0,0 +1,41 @@
>> +/* Copyright (c) 2015, LGE Inc. All rights reserved.
>> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "../qcom/msm8992.dtsi"
>> +
>> +/ {
>> + model = "LGE MSM8992 BULLHEAD rev-1.01";
>> + compatible = "qcom,msm8992";
>> + qcom,board-id = <0xb64 0>;
>
> Please work with sboyd to add the board-id to the dtbTool. We don't put
> board-ids in the dts file. We post-process the dtb file and add them then.
>
sboyd has all the info he needs for this, I believe its just with legal
now. Will remove for V2.
It would be nice if we could get this dtbTool to automagically run as
part of the build system.
>
>> +};
>> +
>> +/ {
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> + };
>> +
>> + soc {
>> + serial at f991e000 {
>> + status = "okay";
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&blsp1_uart2_default>;
>> + pinctrl-1 = <&blsp1_uart2_sleep>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
>
> <snip>
>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
>> new file mode 100644
>> index 0000000..fa92a1a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
>> @@ -0,0 +1,221 @@
>> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/memreserve/ 0x00000000 0x00001000;
>
> Please use reserved-memory{}. And why are they setting aside 4k at the
> beginning? Trying to cover up corruption issues?
>
I only have the existing kernel (3.10) and no insight as to why this is
needed. Something very interesting and/or unexpected was that I needed
memreserve when using earlycon combined with
CONFIG_DEBUG_DRIVER && CONFIG_DEBUG_DEVRES
in order for the target / phone to boot. It have very well booted its
just I cant tell given the serial debug is the way I currently have to
gain visibility into the status of the phone.
But when I turned off the a fore mentioned config options and continued
to use earlycon it booted fine.
Removing memreserve.
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8992";
>> + compatible = "qcom,msm8992";
>> + qcom,msm-id = <251 0>, <252 0>;
This is needed or else the LK provides the following error
[5380] qcom,msm-id entry not found
and refuses to boot.
>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>
> See above comment on ids.
removal of this (pmic-id) seems to be ok.
>
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>
> <snip>
>
>> +#include "msm8992-pins.dtsi"
>> diff --git a/arch/arm64/configs/bullhead_defconfig b/arch/arm64/configs/bullhead_defconfig
>
> Please add whatever config options you have to the default defconfig. we don't
> define board specific configs for ARM64 platforms. Or I should say, they won't
> be accepted into the kernel.
>
> Also, please separate defconfig changes into separate patches.
>
Will keep the changes to the absolute minimum.
Looks like I am going to need these 3
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
as this unit doent have all the bits'N pieces working currently and is
_ONLY_ able to boot a ramdisk.
-jeremy
> <snip>
>
>> diff --git a/arch/arm64/configs/msm8992_defconfig b/arch/arm64/configs/msm8992_defconfig
>> new file mode 100644
>> index 0000000..f673a27
>> --- /dev/null
>> +++ b/arch/arm64/configs/msm8992_defconfig
>
> See above comment.
>> @@ -0,0 +1,5 @@
>> +CONFIG_NO_HZ=y
>> +CONFIG_HIGH_RES_TIMERS=y
>> +CONFIG_SCHED_HMP=y
>> +CONFIG_NAMESPACES=y
>> +# CONFIG_CORESIGHT is not set
>> --
>> 2.6.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
2016-07-08 0:41 ` [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support Jeremy McNicoll
@ 2016-09-21 1:12 ` Andy Gross
2016-09-21 1:12 ` Andy Gross
1 sibling, 0 replies; 22+ messages in thread
From: Andy Gross @ 2016-09-21 1:12 UTC (permalink / raw)
To: Jeremy McNicoll
Cc: linux-arm-msm, linux-arm-kernel, stephen.boyd, mail, jeremymc
On Thu, Jul 07, 2016 at 05:41:06PM -0700, Jeremy McNicoll wrote:
> From: Bastian Köcher <mail@kchr.de>
>
> Initial device tree support for Qualcomm MSM8994 SoC and
> Huawei Angler / Google Nexus 6P support.
>
> The device tree and the angler_defconfig are based on the
> device tree from the Google 3.10 kernel tree.
>
> The device can be booted into the initrd with only one CPU running.
>
> Signed-off-by: Bastian Köcher <mail@kchr.de>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/Kconfig.platforms | 13 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/huawei/Makefile | 5 +
> .../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
There is nothing to warrant having huawei have their own directory unless they
are making their own SOC.
> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
> arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
We don't need to add defconfigs. We just need to turn on the options in the
main defconfig.
Also, when you do have defconfigs, please separate those changes into a separate
patch.
> 8 files changed, 1032 insertions(+)
> create mode 100644 arch/arm64/boot/dts/huawei/Makefile
> create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
> create mode 100644 arch/arm64/configs/angler_defconfig
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 515e669..f253f60d 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -98,6 +98,19 @@ config MACH_LGE
> help
> This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> +config ARCH_MSM8994
> + bool "Qualcomm MSM8994"
> + depends on ARCH_QCOM
> + select ARCH_REQUIRE_GPIOLIB
> + help
> + This enables support for the Qualcomm MSM8994
> +
> +config MACH_HUAWEI
> + bool "Huawei Angler (MSM8994)"
> + depends on ARCH_QCOM
> + help
> + This enables support for the Huawei Nexus 6P - Angler MSM8994.
Remove both of these. We aren't adding more ARCHs or machs.
> +
> config ARCH_ROCKCHIP
> bool "Rockchip Platforms"
> select ARCH_HAS_RESET_CONTROLLER
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index bde90fb..d199f8b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ dts-dirs += cavium
> dts-dirs += exynos
> dts-dirs += freescale
> dts-dirs += hisilicon
> +dts-dirs += huawei
> dts-dirs += marvell
> dts-dirs += mediatek
> dts-dirs += nvidia
> diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
> new file mode 100644
> index 0000000..4b31ff4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> new file mode 100644
> index 0000000..07a71d6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> @@ -0,0 +1,41 @@
> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "../qcom/msm8994-v2.0.dtsi"
> +
> +/ {
> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
> + compatible = "qcom,msm8994";
> + qcom,board-id= <8026 0>;
> +};
> +
> +/ {
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc {
> + serial@f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> new file mode 100644
> index 0000000..0e4eea0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +&msmgpio {
> + blsp1_uart2_default: blsp1_uart2_default {
> + pinmux {
> + function = "blsp_uart2";
> + pins = "gpio4", "gpio5";
> + };
> + pinconf {
> + pins = "gpio4", "gpio5";
> + drive-strength = <16>;
> + bias-disable;
> + };
> + };
> +
> + blsp1_uart2_sleep: blsp1_uart2_sleep {
> + pinmux {
> + function = "gpio";
> + pins = "gpio4", "gpio5";
> + };
> + pinconf {
> + pins = "gpio4", "gpio5";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> new file mode 100644
> index 0000000..8fc4c41f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> @@ -0,0 +1,31 @@
> +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * As a general rule, only version-specific property overrides should be placed
> + * inside this file. Device definitions should be placed inside the msm8994.dtsi
> + * file.
> + */
> +
> +#include "msm8994.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x20000>;
Drop the msm-id
> +
> +};
> +
> +/* Clock driver overrides */
> +&clock_gcc {
> + compatible = "qcom,gcc-8994v2";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> new file mode 100644
> index 0000000..c95cb73
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -0,0 +1,237 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/memreserve/ 0x00000000 0x00001000;
> +/memreserve/ 0xac1c0000 0x00001000;
So the 0x00000000 is totally bogus. And the 0xac1c0000 needs to move to a
reserved area lower in the dts.
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x0>;
> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
kill the ids
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> + };
> + };
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0>;
> + next-level-cache = <&L2_0>;
> + // The currents(uA) correspond to the frequencies in the
> + // frequency table.
> + current = < 24140 //384000 kHZ
> + 27200 //460800 kHZ
> + 32300 //600000 kHZ
> + 36940 //672000 kHz
> + 41570 //768000 kHZ
> + 49870 //864000 kHZ
> + 57840 //960000 kHZ
> + 79800 //1248000 kHZ
> + 88810 //1344000 kHZ
> + 102400 //1478400 kHZ
> + 110900>; //1555200 kHZ
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> + };
> +
> + soc: soc { };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the reg */
> + reg = <0 0 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Move that reserve down here and make it no-map.
> +
> + smem_mem: smem_region@0x6a00000 {
> + reg = <0x0 0x6a00000 0x0 0x200000>;
> + no-map;
> + };
> + };
> +};
> +
> +&soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + compatible = "simple-bus";
> +
> + intc: interrupt-controller@f9000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0xf9000000 0x1000>,
> + <0xf9002000 0x1000>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <1 2 0xff08>,
> + <1 3 0xff08>,
> + <1 4 0xff08>,
> + <1 1 0xff08>;
> + clock-frequency = <19200000>;
> + };
> +
> + timer@f9020000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0xf9020000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@f9021000 {
> + frame-number = <0>;
> + interrupts = <0 9 0x4>,
> + <0 8 0x4>;
> + reg = <0xf9021000 0x1000>,
> + <0xf9022000 0x1000>;
> + };
> +
> + frame@f9023000 {
> + frame-number = <1>;
> + interrupts = <0 10 0x4>;
> + reg = <0xf9023000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9024000 {
> + frame-number = <2>;
> + interrupts = <0 11 0x4>;
> + reg = <0xf9024000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9025000 {
> + frame-number = <3>;
> + interrupts = <0 12 0x4>;
> + reg = <0xf9025000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9026000 {
> + frame-number = <4>;
> + interrupts = <0 13 0x4>;
> + reg = <0xf9026000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9027000 {
> + frame-number = <5>;
> + interrupts = <0 14 0x4>;
> + reg = <0xf9027000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9028000 {
> + frame-number = <6>;
> + interrupts = <0 15 0x4>;
> + reg = <0xf9028000 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + restart@fc4ab000 {
> + compatible = "qcom,pshold";
> + reg = <0xfc4ab000 0x4>;
> + };
> +
> + msmgpio: pinctrl@fd510000 {
> + compatible = "qcom,msm8994-pinctrl", "qcom,msm8974-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + blsp1_uart2: serial@f991e000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0xf991e000 0x1000>;
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + clock-names = "core", "iface";
> + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
> + <&clock_gcc GCC_BLSP1_AHB_CLK>;
> + };
> +
> + clocks {
> + xo_board: xo_board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + };
> +
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + };
> +
> + tcsr_mutex_regs: syscon@fd484000 {
> + compatible = "syscon";
> + reg = <0xfd484000 0x2000>;
> + };
> +
> + tcsr_mutex: hwlock {
> + compatible = "qcom,tcsr-mutex";
> + syscon = <&tcsr_mutex_regs 0 0x80>;
> + #hwlock-cells = <1>;
> + };
> +
> + qcom,smem@6a00000 {
> + compatible = "qcom,smem";
> +
> + memory-region = <&smem_mem>;
> +
> + hwlocks = <&tcsr_mutex 3>;
> + };
> +
> + clock_gcc: qcom,gcc@fc400000 {
> + compatible = "qcom,gcc-8994";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0xfc400000 0x2000>;
> + };
> +
> +};
> +
> +#include "msm8994-pins.dtsi"
> diff --git a/arch/arm64/configs/angler_defconfig b/arch/arm64/configs/angler_defconfig
> new file mode 100644
> index 0000000..00cf192
> --- /dev/null
> +++ b/arch/arm64/configs/angler_defconfig
> @@ -0,0 +1,666 @@
> +CONFIG_AUDIT=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> +CONFIG_RCU_FAST_NO_HZ=y
> +CONFIG_LOG_BUF_SHIFT=20
> +CONFIG_CGROUPS=y
> +CONFIG_CGROUP_DEBUG=y
> +CONFIG_CGROUP_FREEZER=y
> +CONFIG_CPUSETS=y
> +CONFIG_CGROUP_CPUACCT=y
> +CONFIG_RESOURCE_COUNTERS=y
> +CONFIG_CGROUP_SCHED=y
> +CONFIG_CFS_BANDWIDTH=y
> +CONFIG_RT_GROUP_SCHED=y
> +CONFIG_SCHED_HMP=y
> +CONFIG_NAMESPACES=y
> +# CONFIG_UTS_NS is not set
> +# CONFIG_PID_NS is not set
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> +CONFIG_PANIC_TIMEOUT=5
> +CONFIG_KALLSYMS_ALL=y
> +# CONFIG_PCI_QUIRKS is not set
> +CONFIG_EMBEDDED=y
> +# CONFIG_SLUB_DEBUG is not set
> +CONFIG_PROFILING=y
> +CONFIG_PARTITION_ADVANCED=y
> +CONFIG_ARCH_MSM=y
> +CONFIG_ARCH_MSM8994=y
> +CONFIG_ARCH_MSM8994_V1_TLBI_WA=y
> +CONFIG_PCI_MSM=y
> +CONFIG_ARM64_A57_ERRATA_832075=y
> +CONFIG_SMP=y
> +CONFIG_SCHED_MC=y
> +CONFIG_ARCH_WANTS_CTXSW_LOGGING=y
> +CONFIG_PREEMPT=y
> +CONFIG_ARMV7_COMPAT=y
> +CONFIG_BALANCE_ANON_FILE_RECLAIM=y
> +CONFIG_ZSMALLOC=y
> +CONFIG_SECCOMP=y
> +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
> +# CONFIG_COREDUMP is not set
> +CONFIG_COMPAT=y
> +CONFIG_PM_AUTOSLEEP=y
> +CONFIG_PM_WAKELOCKS=y
> +CONFIG_PM_WAKELOCKS_LIMIT=0
> +CONFIG_PM_RUNTIME=y
> +CONFIG_SUSPEND_TIME=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> +CONFIG_CPU_FREQ_GOV_USERSPACE=y
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
> +CONFIG_CPU_BOOST=y
> +CONFIG_CPU_IDLE=y
> +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
> +# CONFIG_CPU_IDLE_GOV_LADDER is not set
> +# CONFIG_CPU_IDLE_GOV_MENU is not set
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_XFRM_USER=y
> +CONFIG_XFRM_STATISTICS=y
> +CONFIG_NET_KEY=y
> +CONFIG_INET=y
> +CONFIG_IP_ADVANCED_ROUTER=y
> +CONFIG_IP_MULTIPLE_TABLES=y
> +CONFIG_IP_ROUTE_VERBOSE=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_INET_AH=y
> +CONFIG_INET_ESP=y
> +CONFIG_INET_IPCOMP=y
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_LRO is not set
> +CONFIG_IPV6_PRIVACY=y
> +CONFIG_IPV6_ROUTER_PREF=y
> +CONFIG_IPV6_ROUTE_INFO=y
> +CONFIG_IPV6_OPTIMISTIC_DAD=y
> +CONFIG_INET6_AH=y
> +CONFIG_INET6_ESP=y
> +CONFIG_INET6_IPCOMP=y
> +CONFIG_IPV6_MIP6=y
> +CONFIG_IPV6_MULTIPLE_TABLES=y
> +CONFIG_IPV6_SUBTREES=y
> +CONFIG_NETFILTER=y
> +CONFIG_NF_CONNTRACK=y
> +CONFIG_NF_CONNTRACK_EVENTS=y
> +CONFIG_NF_CT_PROTO_DCCP=y
> +CONFIG_NF_CT_PROTO_SCTP=y
> +CONFIG_NF_CT_PROTO_UDPLITE=y
> +CONFIG_NF_CONNTRACK_AMANDA=y
> +CONFIG_NF_CONNTRACK_FTP=y
> +CONFIG_NF_CONNTRACK_H323=y
> +CONFIG_NF_CONNTRACK_IRC=y
> +CONFIG_NF_CONNTRACK_NETBIOS_NS=y
> +CONFIG_NF_CONNTRACK_PPTP=y
> +CONFIG_NF_CONNTRACK_SANE=y
> +CONFIG_NF_CONNTRACK_SIP=y
> +CONFIG_NF_CONNTRACK_TFTP=y
> +CONFIG_NF_CT_NETLINK=y
> +CONFIG_NETFILTER_TPROXY=y
> +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
> +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
> +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
> +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
> +CONFIG_NETFILTER_XT_TARGET_LOG=y
> +CONFIG_NETFILTER_XT_TARGET_MARK=y
> +CONFIG_NETFILTER_XT_TARGET_NFLOG=y
> +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
> +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
> +CONFIG_NETFILTER_XT_TARGET_TEE=y
> +CONFIG_NETFILTER_XT_TARGET_TPROXY=y
> +CONFIG_NETFILTER_XT_TARGET_TRACE=y
> +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
> +CONFIG_NETFILTER_XT_MATCH_COMMENT=y
> +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
> +CONFIG_NETFILTER_XT_MATCH_DSCP=y
> +CONFIG_NETFILTER_XT_MATCH_ESP=y
> +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_HELPER=y
> +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
> +CONFIG_NETFILTER_XT_MATCH_LENGTH=y
> +CONFIG_NETFILTER_XT_MATCH_LIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_MAC=y
> +CONFIG_NETFILTER_XT_MATCH_MARK=y
> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
> +CONFIG_NETFILTER_XT_MATCH_POLICY=y
> +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
> +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
> +CONFIG_NETFILTER_XT_MATCH_SOCKET=y
> +CONFIG_NETFILTER_XT_MATCH_STATE=y
> +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
> +CONFIG_NETFILTER_XT_MATCH_STRING=y
> +CONFIG_NETFILTER_XT_MATCH_TIME=y
> +CONFIG_NETFILTER_XT_MATCH_U32=y
> +CONFIG_NF_CONNTRACK_IPV4=y
> +CONFIG_IP_NF_IPTABLES=y
> +CONFIG_IP_NF_MATCH_AH=y
> +CONFIG_IP_NF_MATCH_ECN=y
> +CONFIG_IP_NF_MATCH_TTL=y
> +CONFIG_IP_NF_FILTER=y
> +CONFIG_IP_NF_TARGET_REJECT=y
> +CONFIG_IP_NF_TARGET_REJECT_SKERR=y
> +CONFIG_NF_NAT_IPV4=y
> +CONFIG_IP_NF_TARGET_MASQUERADE=y
> +CONFIG_IP_NF_TARGET_NETMAP=y
> +CONFIG_IP_NF_TARGET_REDIRECT=y
> +CONFIG_IP_NF_MANGLE=y
> +CONFIG_IP_NF_RAW=y
> +CONFIG_IP_NF_SECURITY=y
> +CONFIG_IP_NF_ARPTABLES=y
> +CONFIG_IP_NF_ARPFILTER=y
> +CONFIG_IP_NF_ARP_MANGLE=y
> +CONFIG_NF_CONNTRACK_IPV6=y
> +CONFIG_IP6_NF_IPTABLES=y
> +CONFIG_IP6_NF_FILTER=y
> +CONFIG_IP6_NF_TARGET_REJECT=y
> +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
> +CONFIG_IP6_NF_MANGLE=y
> +CONFIG_IP6_NF_RAW=y
> +CONFIG_BRIDGE_NF_EBTABLES=y
> +CONFIG_BRIDGE_EBT_BROUTE=y
> +CONFIG_L2TP=y
> +CONFIG_L2TP_DEBUGFS=y
> +CONFIG_L2TP_V3=y
> +CONFIG_L2TP_IP=y
> +CONFIG_L2TP_ETH=y
> +CONFIG_BRIDGE=y
> +CONFIG_NET_SCHED=y
> +CONFIG_NET_SCH_HTB=y
> +CONFIG_NET_SCH_PRIO=y
> +CONFIG_NET_CLS_FW=y
> +CONFIG_NET_CLS_U32=y
> +CONFIG_CLS_U32_MARK=y
> +CONFIG_NET_CLS_FLOW=y
> +CONFIG_NET_EMATCH=y
> +CONFIG_NET_EMATCH_CMP=y
> +CONFIG_NET_EMATCH_NBYTE=y
> +CONFIG_NET_EMATCH_U32=y
> +CONFIG_NET_EMATCH_META=y
> +CONFIG_NET_EMATCH_TEXT=y
> +CONFIG_NET_CLS_ACT=y
> +CONFIG_RMNET_DATA=y
> +CONFIG_RMNET_DATA_FC=y
> +CONFIG_RMNET_DATA_DEBUG_PKT=y
> +CONFIG_SOCKEV_NLMCAST=y
> +CONFIG_BT=y
> +CONFIG_BT_RFCOMM=y
> +CONFIG_BT_RFCOMM_TTY=y
> +CONFIG_BT_BNEP=y
> +CONFIG_BT_BNEP_MC_FILTER=y
> +CONFIG_BT_BNEP_PROTO_FILTER=y
> +CONFIG_BT_HIDP=y
> +CONFIG_MSM_BT_BLUESLEEP=y
> +CONFIG_CFG80211=y
> +CONFIG_CFG80211_INTERNAL_REGDB=y
> +CONFIG_RFKILL=y
> +CONFIG_NFC=y
> +CONFIG_NFC_PN548=y
> +CONFIG_IPC_ROUTER=y
> +CONFIG_IPC_ROUTER_SECURITY=y
> +CONFIG_CMA=y
> +CONFIG_CMA_SIZE_MBYTES=32
> +CONFIG_ARM_CCI=y
> +CONFIG_ZRAM=y
> +CONFIG_ZRAM_LZ4_COMPRESS=y
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_BLK_DEV_RAM=y
> +CONFIG_UID_STAT=y
> +CONFIG_QSEECOM=y
> +CONFIG_TI_DRV2667=y
> +CONFIG_UID_CPUTIME=y
> +CONFIG_WIFI_SAR=y
> +CONFIG_SCSI=y
> +CONFIG_SCSI_TGT=y
> +CONFIG_BLK_DEV_SD=y
> +CONFIG_CHR_DEV_SG=y
> +CONFIG_SCSI_MULTI_LUN=y
> +CONFIG_SCSI_CONSTANTS=y
> +CONFIG_SCSI_LOGGING=y
> +CONFIG_SCSI_SCAN_ASYNC=y
> +# CONFIG_SCSI_LOWLEVEL is not set
> +CONFIG_MD=y
> +CONFIG_BLK_DEV_DM=y
> +CONFIG_DM_CRYPT=y
> +CONFIG_DM_REQ_CRYPT=y
> +CONFIG_DM_VERITY=y
> +CONFIG_NETDEVICES=y
> +CONFIG_DUMMY=y
> +CONFIG_TUN=y
> +# CONFIG_ETHERNET is not set
> +CONFIG_PPP=y
> +CONFIG_PPP_BSDCOMP=y
> +CONFIG_PPP_DEFLATE=y
> +CONFIG_PPP_FILTER=y
> +CONFIG_PPP_MPPE=y
> +CONFIG_PPP_MULTILINK=y
> +CONFIG_PPPOE=y
> +CONFIG_PPPOL2TP=y
> +CONFIG_PPPOLAC=y
> +CONFIG_PPPOPNS=y
> +CONFIG_PPP_ASYNC=y
> +CONFIG_PPP_SYNC_TTY=y
> +CONFIG_USB_KAWETH=y
> +CONFIG_USB_PEGASUS=y
> +CONFIG_USB_RTL8150=y
> +CONFIG_USB_RTL8152=y
> +CONFIG_USB_USBNET=y
> +# CONFIG_USB_NET_CDC_NCM is not set
> +# CONFIG_USB_NET_NET1080 is not set
> +# CONFIG_USB_NET_CDC_SUBSET is not set
> +# CONFIG_USB_NET_ZAURUS is not set
> +CONFIG_CLD_LL_CORE=y
> +CONFIG_BCMDHD=y
> +CONFIG_BCMDHD_PCIE=y
> +CONFIG_BCM4358=y
> +CONFIG_BCMDHD_FW_PATH="/vendor/firmware/fw_bcmdhd.bin"
> +CONFIG_DHD_USE_STATIC_BUF=y
> +CONFIG_DHD_USE_SCHED_SCAN=y
> +CONFIG_DHD_OF_SUPPORT=y
> +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> +CONFIG_INPUT_EVDEV=y
> +# CONFIG_KEYBOARD_ATKBD is not set
> +CONFIG_KEYBOARD_GPIO=y
> +# CONFIG_INPUT_MOUSE is not set
> +CONFIG_INPUT_JOYSTICK=y
> +CONFIG_JOYSTICK_XPAD=y
> +CONFIG_JOYSTICK_XPAD_FF=y
> +CONFIG_JOYSTICK_XPAD_LEDS=y
> +CONFIG_INPUT_TABLET=y
> +CONFIG_TABLET_USB_ACECAD=y
> +CONFIG_TABLET_USB_AIPTEK=y
> +CONFIG_TABLET_USB_GTCO=y
> +CONFIG_TABLET_USB_HANWANG=y
> +CONFIG_TABLET_USB_KBTAB=y
> +CONFIG_TABLET_USB_WACOM=y
> +CONFIG_INPUT_TOUCHSCREEN=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICETREE_SUPPORT=y
> +# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_PROXIMITY is not set
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_BINARY_FW_UPGRADE=y
> +CONFIG_TOUCHSCREEN_HUAWEI_CYTTSP4_RECOVERY_FW_UPDATE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_MANUAL_TTCONFIG_UPGRADE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_USE_FW_BIN_FILE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICE_ACCESS=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_LOADER=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEBUG_MODULE=y
> +CONFIG_TOUCHSCREEN_GEN_VKEYS=y
> +CONFIG_SECURE_TOUCH=y
> +CONFIG_TOUCHSCREEN_HUAWEI_SYNAPTICS_DSX_v25=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_CORE=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_RMI_DEV=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_FW_UPDATE=y
> +CONFIG_INPUT_MISC=y
> +CONFIG_INPUT_KEYCHORD=y
> +CONFIG_INPUT_UINPUT=y
> +CONFIG_INPUT_GPIO=y
> +CONFIG_LASER_STMVL6180=y
> +CONFIG_RF_DETECT=y
> +# CONFIG_SERIO is not set
> +CONFIG_FINGERPRINT_FPC=y
> +# CONFIG_VT is not set
> +# CONFIG_LEGACY_PTYS is not set
> +# CONFIG_DEVMEM is not set
> +# CONFIG_DEVKMEM is not set
> +CONFIG_SERIAL_MSM_HS=y
> +CONFIG_SERIAL_MSM_HSL=y
> +CONFIG_SERIAL_MSM_HSL_CONSOLE=y
> +CONFIG_SERIAL_MSM_SMD=y
> +CONFIG_HW_RANDOM_MSM=y
> +CONFIG_MSM_SMD_PKT=y
> +CONFIG_MSM_ADSPRPC=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_MSM_V2=y
> +CONFIG_SLIMBUS_MSM_NGD=y
> +CONFIG_SPI=y
> +CONFIG_SPI_CONTEXTHUB=y
> +CONFIG_SPI_QUP=y
> +CONFIG_SPMI=y
> +CONFIG_SPMI_MSM_PMIC_ARB=y
> +CONFIG_MSM_QPNP_INT=y
> +CONFIG_USE_PINCTRL_IRQ=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_GPIO_QPNP_PIN=y
> +CONFIG_SMB349_DUAL_CHARGER=y
> +CONFIG_SMB1351_USB_CHARGER=y
> +CONFIG_QPNP_SMBCHARGER=y
> +CONFIG_QPNP_FG=y
> +CONFIG_BATTERY_BCL=y
> +CONFIG_MSM_BCL_CTL=y
> +CONFIG_MSM_BCL_PERIPHERAL_CTL=y
> +CONFIG_POWER_RESET_MSM=y
> +CONFIG_MSM_DLOAD_MODE=y
> +CONFIG_MSM_PM=y
> +CONFIG_APSS_CORE_EA=y
> +CONFIG_SENSORS_EPM_ADC=y
> +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
> +CONFIG_THERMAL=y
> +CONFIG_THERMAL_TSENS8974=y
> +CONFIG_LIMITS_MONITOR=y
> +CONFIG_LIMITS_LITE_HW=y
> +CONFIG_THERMAL_MONITOR=y
> +CONFIG_THERMAL_QPNP=y
> +CONFIG_THERMAL_QPNP_ADC_TM=y
> +CONFIG_WCD9330_CODEC=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_REGULATOR_PROXY_CONSUMER=y
> +CONFIG_REGULATOR_MEM_ACC=y
> +CONFIG_REGULATOR_TPS65132=y
> +CONFIG_REGULATOR_STUB=y
> +CONFIG_REGULATOR_RPM_SMD=y
> +CONFIG_REGULATOR_QPNP=y
> +CONFIG_REGULATOR_QPNP_LABIBB=y
> +CONFIG_REGULATOR_SPM=y
> +CONFIG_REGULATOR_CPR=y
> +CONFIG_MEDIA_SUPPORT=y
> +CONFIG_MEDIA_CAMERA_SUPPORT=y
> +CONFIG_MEDIA_RADIO_SUPPORT=y
> +CONFIG_MEDIA_CONTROLLER=y
> +CONFIG_VIDEO_V4L2_SUBDEV_API=y
> +CONFIG_VIDEOBUF2_MSM_MEM=y
> +CONFIG_MEDIA_USB_SUPPORT=y
> +CONFIG_USB_VIDEO_CLASS=y
> +# CONFIG_USB_GSPCA is not set
> +CONFIG_V4L_PLATFORM_DRIVERS=y
> +CONFIG_MSMB_CAMERA=y
> +CONFIG_MSM_CAMERA_SENSOR=y
> +CONFIG_MSM_CPP=y
> +CONFIG_MSM_CCI=y
> +CONFIG_MSM_CSI30_HEADER=y
> +CONFIG_MSM_CSIPHY=y
> +CONFIG_MSM_CSID=y
> +CONFIG_MSM_EEPROM=y
> +CONFIG_MSM_ISPIF=y
> +CONFIG_HI256=y
> +CONFIG_MT9M114=y
> +CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
> +CONFIG_MSMB_JPEG=y
> +CONFIG_MSM_FD=y
> +CONFIG_MSM_VIDC_V4L2=y
> +CONFIG_TSPP=y
> +# CONFIG_RADIO_ADAPTERS is not set
> +# CONFIG_VGA_ARB is not set
> +CONFIG_MSM_KGSL=y
> +CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
> +CONFIG_FB=y
> +CONFIG_FB_MSM=y
> +CONFIG_FB_MSM_MDSS=y
> +CONFIG_FB_MSM_MDSS_WRITEBACK=y
> +CONFIG_SOUND=y
> +CONFIG_SND=y
> +CONFIG_SND_MPU401=y
> +# CONFIG_SND_PCI is not set
> +# CONFIG_SND_SPI is not set
> +CONFIG_SND_USB_AUDIO=y
> +CONFIG_SND_SOC=y
> +CONFIG_SND_SOC_MSM8994=y
> +CONFIG_SND_SOC_MAX98925=y
> +CONFIG_HID_BATTERY_STRENGTH=y
> +CONFIG_HIDRAW=y
> +CONFIG_UHID=y
> +CONFIG_HID_A4TECH=y
> +CONFIG_HID_APPLE=y
> +CONFIG_HID_BELKIN=y
> +CONFIG_HID_CHERRY=y
> +CONFIG_HID_CHICONY=y
> +CONFIG_HID_PRODIKEYS=y
> +CONFIG_HID_CYPRESS=y
> +CONFIG_HID_ELECOM=y
> +CONFIG_HID_EZKEY=y
> +CONFIG_HID_HOLTEK=y
> +CONFIG_HOLTEK_FF=y
> +CONFIG_HID_KEYTOUCH=y
> +CONFIG_HID_KYE=y
> +CONFIG_HID_UCLOGIC=y
> +CONFIG_HID_WALTOP=y
> +CONFIG_HID_GYRATION=y
> +CONFIG_HID_ICADE=y
> +CONFIG_HID_KENSINGTON=y
> +CONFIG_HID_LCPOWER=y
> +CONFIG_HID_LENOVO_TPKBD=y
> +CONFIG_HID_LOGITECH=y
> +CONFIG_HID_LOGITECH_DJ=y
> +CONFIG_LOGITECH_FF=y
> +CONFIG_LOGIRUMBLEPAD2_FF=y
> +CONFIG_LOGIG940_FF=y
> +CONFIG_HID_MAGICMOUSE=y
> +CONFIG_HID_MICROSOFT=y
> +CONFIG_HID_MONTEREY=y
> +CONFIG_HID_MULTITOUCH=y
> +CONFIG_HID_NTRIG=y
> +CONFIG_HID_ORTEK=y
> +CONFIG_HID_PANTHERLORD=y
> +CONFIG_PANTHERLORD_FF=y
> +CONFIG_HID_PRIMAX=y
> +CONFIG_HID_PS3REMOTE=y
> +CONFIG_HID_ROCCAT=y
> +CONFIG_HID_SAITEK=y
> +CONFIG_HID_SAMSUNG=y
> +CONFIG_HID_SONY=y
> +CONFIG_HID_SPEEDLINK=y
> +CONFIG_HID_STEELSERIES=y
> +CONFIG_HID_SUNPLUS=y
> +CONFIG_HID_SMARTJOYPLUS=y
> +CONFIG_SMARTJOYPLUS_FF=y
> +CONFIG_HID_TOPSEED=y
> +CONFIG_HID_THINGM=y
> +CONFIG_HID_THRUSTMASTER=y
> +CONFIG_THRUSTMASTER_FF=y
> +CONFIG_HID_WACOM=y
> +CONFIG_HID_WIIMOTE=y
> +CONFIG_HID_ZEROPLUS=y
> +CONFIG_ZEROPLUS_FF=y
> +CONFIG_HID_SENSOR_HUB=y
> +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_EHSET=y
> +CONFIG_USB_EHCI_MSM=y
> +CONFIG_USB_ACM=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_SERIAL=y
> +CONFIG_USB_SERIAL_GENERIC=y
> +CONFIG_USB_SERIAL_FTDI_SIO=y
> +CONFIG_USB_SERIAL_PL2303=y
> +CONFIG_USB_EMI62=y
> +CONFIG_USB_EMI26=y
> +CONFIG_USB_EHSET_TEST_FIXTURE=y
> +CONFIG_USB_PHY=y
> +CONFIG_USB_MSM_SSPHY_QMP=y
> +CONFIG_MSM_QUSB_PHY=y
> +CONFIG_DUAL_ROLE_USB_INTF=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DEBUG_FILES=y
> +CONFIG_USB_GADGET_DEBUG_FS=y
> +CONFIG_USB_CI13XXX_MSM=y
> +CONFIG_USB_DWC3_MSM=y
> +CONFIG_USB_G_ANDROID=y
> +CONFIG_TYPEC=y
> +CONFIG_TUSB320_TYPEC=y
> +CONFIG_MMC=y
> +CONFIG_MMC_PERF_PROFILING=y
> +CONFIG_MMC_UNSAFE_RESUME=y
> +CONFIG_MMC_CLKGATE=y
> +CONFIG_MMC_PARANOID_SD_INIT=y
> +CONFIG_MMC_BLOCK_MINORS=32
> +CONFIG_MMC_TEST=y
> +CONFIG_MMC_BLOCK_TEST=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_MSM=y
> +CONFIG_LEDS_QPNP=y
> +CONFIG_LEDS_QPNP_FLASH=y
> +CONFIG_LEDS_QPNP_WLED=y
> +CONFIG_LEDS_TRIGGERS=y
> +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> +CONFIG_SWITCH=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_QPNP=y
> +CONFIG_DMADEVICES=y
> +CONFIG_QCOM_SPS_DMA=y
> +CONFIG_UIO=y
> +CONFIG_UIO_MSM_SHAREDMEM=y
> +CONFIG_STAGING=y
> +CONFIG_ANDROID=y
> +CONFIG_ANDROID_BINDER_IPC=y
> +CONFIG_ASHMEM=y
> +CONFIG_ANDROID_LOGGER=y
> +CONFIG_ANDROID_LOW_MEMORY_KILLER=y
> +CONFIG_ANDROID_INTF_ALARM_DEV=y
> +CONFIG_ONESHOT_SYNC=y
> +CONFIG_ION=y
> +CONFIG_ION_MSM=y
> +CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS=y
> +# CONFIG_NET_VENDOR_SILICOM is not set
> +CONFIG_SPS=y
> +CONFIG_USB_BAM=y
> +CONFIG_SPS_SUPPORT_NDP_BAM=y
> +CONFIG_QPNP_POWER_ON=y
> +CONFIG_QPNP_REVID=y
> +CONFIG_QPNP_COINCELL=y
> +CONFIG_QPNP_USB_DETECT=y
> +CONFIG_IPA=y
> +CONFIG_RMNET_IPA=y
> +CONFIG_MSM_AVTIMER=y
> +CONFIG_PFT=y
> +CONFIG_MSM_BUS_SCALING=y
> +CONFIG_MSM_BUSPM_DEV=y
> +CONFIG_BUS_TOPOLOGY_ADHOC=y
> +CONFIG_DEBUG_BUS_VOTER=y
> +CONFIG_QPNP_HAPTIC=y
> +CONFIG_MSM_MDSS_PLL=y
> +CONFIG_REMOTE_SPINLOCK_MSM=y
> +CONFIG_MSM_IOMMU_V1=y
> +CONFIG_MSM_IOMMU_VBIF_CHECK=y
> +CONFIG_IOMMU_FORCE_4K_MAPPINGS=y
> +CONFIG_DEVFREQ_SPDM=y
> +CONFIG_PWM=y
> +CONFIG_PWM_QPNP=y
> +CONFIG_SENSORS_SSC=y
> +CONFIG_GENERIC_PHY=y
> +CONFIG_CP_ACCESS64=y
> +CONFIG_MSM_EVENT_TIMER=y
> +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
> +CONFIG_MSM_QMI_INTERFACE=y
> +CONFIG_MSM_SMD_DEBUG=y
> +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
> +CONFIG_MSM_RPM_LOG=y
> +CONFIG_MSM_RPM_STATS_LOG=y
> +CONFIG_MSM_RUN_QUEUE_STATS=y
> +CONFIG_MSM_SMEM_LOGGING=y
> +CONFIG_MSM_SMP2P=y
> +CONFIG_MSM_SMP2P_TEST=y
> +CONFIG_MSM_SPM=y
> +CONFIG_MSM_L2_SPM=y
> +CONFIG_MSM_ADSP_LOADER=y
> +CONFIG_MSM_MEMORY_DUMP_V2=y
> +CONFIG_MSM_DEBUG_LAR_UNLOCK=y
> +CONFIG_MSM_DDR_HEALTH=y
> +CONFIG_MSM_COMMON_LOG=y
> +CONFIG_MSM_WATCHDOG_V2=y
> +CONFIG_MSM_FORCE_WDOG_BITE_ON_PANIC=y
> +CONFIG_MSM_HVC=y
> +CONFIG_MSM_SUBSYSTEM_RESTART=y
> +CONFIG_MSM_SYSMON_COMM=y
> +CONFIG_MSM_PIL=y
> +CONFIG_MSM_PIL_SSR_GENERIC=y
> +CONFIG_MSM_PIL_MSS_QDSP6V5=y
> +CONFIG_MSM_OCMEM=y
> +CONFIG_MSM_OCMEM_LOCAL_POWER_CTRL=y
> +CONFIG_MSM_OCMEM_DEBUG=y
> +CONFIG_MSM_BOOT_STATS=y
> +CONFIG_MSM_SCM=y
> +CONFIG_MSM_XPU_ERR_FATAL=y
> +CONFIG_MSM_CPUSS_DUMP=y
> +CONFIG_MSM_SHARED_HEAP_ACCESS=y
> +CONFIG_MSM_SYSTEM_HEALTH_MONITOR=y
> +CONFIG_QCOM_EARLY_RANDOM=y
> +CONFIG_MSM_PERFORMANCE=y
> +CONFIG_QCOM_NPA_DUMP=y
> +CONFIG_MSM_TZ_LOG=y
> +CONFIG_EXT4_FS=y
> +CONFIG_EXT4_FS_SECURITY=y
> +CONFIG_EXT4_FS_ENCRYPTION=y
> +CONFIG_FUSE_FS=y
> +CONFIG_VFAT_FS=y
> +CONFIG_TMPFS=y
> +CONFIG_TMPFS_POSIX_ACL=y
> +CONFIG_PSTORE=y
> +CONFIG_PSTORE_CONSOLE=y
> +CONFIG_PSTORE_PMSG=y
> +CONFIG_PSTORE_RAM=y
> +# CONFIG_NETWORK_FILESYSTEMS is not set
> +CONFIG_NLS_CODEPAGE_437=y
> +CONFIG_NLS_ASCII=y
> +CONFIG_NLS_ISO8859_1=y
> +CONFIG_NLS_UTF8=y
> +CONFIG_PRINTK_TIME=y
> +CONFIG_MAGIC_SYSRQ=y
> +CONFIG_PAGE_OWNER=y
> +# CONFIG_SYSRQ_SCHED_DEBUG is not set
> +CONFIG_SCHEDSTATS=y
> +CONFIG_TIMER_STATS=y
> +CONFIG_DEBUG_INFO=y
> +CONFIG_RCU_CPU_STALL_INFO=y
> +CONFIG_RCU_TRACE=y
> +CONFIG_IPC_LOGGING=y
> +CONFIG_BLK_DEV_IO_TRACE=y
> +CONFIG_DYNAMIC_DEBUG=y
> +CONFIG_OOPS_LOG_BUFFER=y
> +CONFIG_LOG_BUF_MAGIC=y
> +CONFIG_OOPS_LOG_BUF_SHIFT=17
> +CONFIG_PANIC_ON_DATA_CORRUPTION=y
> +CONFIG_ARM64_PTDUMP=y
> +CONFIG_PID_IN_CONTEXTIDR=y
> +CONFIG_SECURITY=y
> +CONFIG_SECURITY_NETWORK=y
> +CONFIG_LSM_MMAP_MIN_ADDR=4096
> +CONFIG_SECURITY_SELINUX=y
> +CONFIG_CRYPTO_NULL=y
> +CONFIG_CRYPTO_XCBC=y
> +CONFIG_CRYPTO_MD4=y
> +CONFIG_CRYPTO_TWOFISH=y
> +CONFIG_CRYPTO_DEV_QCRYPTO=y
> +CONFIG_CRYPTO_DEV_QCE=y
> +CONFIG_CRYPTO_DEV_QCEDEV=y
> +CONFIG_CRYPTO_DEV_QCOM_ICE=y
> +CONFIG_ASYMMETRIC_KEY_TYPE=y
> +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
> +CONFIG_PUBLIC_KEY_ALGO_RSA=y
> +CONFIG_X509_CERTIFICATE_PARSER=y
> +CONFIG_ARM64_CRYPTO=y
> +CONFIG_CRYPTO_SHA1_ARM64_CE=y
> +CONFIG_CRYPTO_SHA2_ARM64_CE=y
> +CONFIG_CRYPTO_GHASH_ARM64_CE=y
> +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
> +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
> +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
> +CONFIG_QMI_ENCDEC=y
> +CONFIG_STRICT_MEMORY_RWX=y
> +CONFIG_ARM_APPENDED_DTB=y
> +CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_ARCH_QCOM=y
> +CONFIG_QCOM_SMD_RPM=y
> +CONFIG_QCOM_SMEM=y
> +CONFIG_QCOM_SMD=y
> +CONFIG_HWSPINLOCK_QCOM=y
> +CONFIG_QCOM_PM=y
> +CONFIG_SERIAL_MSM=y
> +CONFIG_SERIAL_MSM_CONSOLE=y
> +CONFIG_PINCTRL_MSM8X74=y
> +CONFIG_COMMON_CLK_QCOM=y
> +CONFIG_MSM_GCC_8994=y
> +CONFIG_MACH_HUAWEI=y
> +CONFIG_DEVTMPFS=y
> +CONFIG_DMA_CMA=y
> --
> 2.6.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
@ 2016-09-21 1:12 ` Andy Gross
0 siblings, 0 replies; 22+ messages in thread
From: Andy Gross @ 2016-09-21 1:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 07, 2016 at 05:41:06PM -0700, Jeremy McNicoll wrote:
> From: Bastian K?cher <mail@kchr.de>
>
> Initial device tree support for Qualcomm MSM8994 SoC and
> Huawei Angler / Google Nexus 6P support.
>
> The device tree and the angler_defconfig are based on the
> device tree from the Google 3.10 kernel tree.
>
> The device can be booted into the initrd with only one CPU running.
>
> Signed-off-by: Bastian K?cher <mail@kchr.de>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/Kconfig.platforms | 13 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/huawei/Makefile | 5 +
> .../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
There is nothing to warrant having huawei have their own directory unless they
are making their own SOC.
> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
> arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
We don't need to add defconfigs. We just need to turn on the options in the
main defconfig.
Also, when you do have defconfigs, please separate those changes into a separate
patch.
> 8 files changed, 1032 insertions(+)
> create mode 100644 arch/arm64/boot/dts/huawei/Makefile
> create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
> create mode 100644 arch/arm64/configs/angler_defconfig
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 515e669..f253f60d 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -98,6 +98,19 @@ config MACH_LGE
> help
> This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> +config ARCH_MSM8994
> + bool "Qualcomm MSM8994"
> + depends on ARCH_QCOM
> + select ARCH_REQUIRE_GPIOLIB
> + help
> + This enables support for the Qualcomm MSM8994
> +
> +config MACH_HUAWEI
> + bool "Huawei Angler (MSM8994)"
> + depends on ARCH_QCOM
> + help
> + This enables support for the Huawei Nexus 6P - Angler MSM8994.
Remove both of these. We aren't adding more ARCHs or machs.
> +
> config ARCH_ROCKCHIP
> bool "Rockchip Platforms"
> select ARCH_HAS_RESET_CONTROLLER
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index bde90fb..d199f8b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ dts-dirs += cavium
> dts-dirs += exynos
> dts-dirs += freescale
> dts-dirs += hisilicon
> +dts-dirs += huawei
> dts-dirs += marvell
> dts-dirs += mediatek
> dts-dirs += nvidia
> diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
> new file mode 100644
> index 0000000..4b31ff4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> new file mode 100644
> index 0000000..07a71d6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> @@ -0,0 +1,41 @@
> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "../qcom/msm8994-v2.0.dtsi"
> +
> +/ {
> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
> + compatible = "qcom,msm8994";
> + qcom,board-id= <8026 0>;
> +};
> +
> +/ {
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc {
> + serial at f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> new file mode 100644
> index 0000000..0e4eea0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +&msmgpio {
> + blsp1_uart2_default: blsp1_uart2_default {
> + pinmux {
> + function = "blsp_uart2";
> + pins = "gpio4", "gpio5";
> + };
> + pinconf {
> + pins = "gpio4", "gpio5";
> + drive-strength = <16>;
> + bias-disable;
> + };
> + };
> +
> + blsp1_uart2_sleep: blsp1_uart2_sleep {
> + pinmux {
> + function = "gpio";
> + pins = "gpio4", "gpio5";
> + };
> + pinconf {
> + pins = "gpio4", "gpio5";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> new file mode 100644
> index 0000000..8fc4c41f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> @@ -0,0 +1,31 @@
> +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * As a general rule, only version-specific property overrides should be placed
> + * inside this file. Device definitions should be placed inside the msm8994.dtsi
> + * file.
> + */
> +
> +#include "msm8994.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x20000>;
Drop the msm-id
> +
> +};
> +
> +/* Clock driver overrides */
> +&clock_gcc {
> + compatible = "qcom,gcc-8994v2";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> new file mode 100644
> index 0000000..c95cb73
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -0,0 +1,237 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/memreserve/ 0x00000000 0x00001000;
> +/memreserve/ 0xac1c0000 0x00001000;
So the 0x00000000 is totally bogus. And the 0xac1c0000 needs to move to a
reserved area lower in the dts.
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x0>;
> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
kill the ids
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> + };
> + };
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0>;
> + next-level-cache = <&L2_0>;
> + // The currents(uA) correspond to the frequencies in the
> + // frequency table.
> + current = < 24140 //384000 kHZ
> + 27200 //460800 kHZ
> + 32300 //600000 kHZ
> + 36940 //672000 kHz
> + 41570 //768000 kHZ
> + 49870 //864000 kHZ
> + 57840 //960000 kHZ
> + 79800 //1248000 kHZ
> + 88810 //1344000 kHZ
> + 102400 //1478400 kHZ
> + 110900>; //1555200 kHZ
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> + };
> +
> + soc: soc { };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the reg */
> + reg = <0 0 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Move that reserve down here and make it no-map.
> +
> + smem_mem: smem_region at 0x6a00000 {
> + reg = <0x0 0x6a00000 0x0 0x200000>;
> + no-map;
> + };
> + };
> +};
> +
> +&soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + compatible = "simple-bus";
> +
> + intc: interrupt-controller at f9000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0xf9000000 0x1000>,
> + <0xf9002000 0x1000>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <1 2 0xff08>,
> + <1 3 0xff08>,
> + <1 4 0xff08>,
> + <1 1 0xff08>;
> + clock-frequency = <19200000>;
> + };
> +
> + timer at f9020000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0xf9020000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame at f9021000 {
> + frame-number = <0>;
> + interrupts = <0 9 0x4>,
> + <0 8 0x4>;
> + reg = <0xf9021000 0x1000>,
> + <0xf9022000 0x1000>;
> + };
> +
> + frame at f9023000 {
> + frame-number = <1>;
> + interrupts = <0 10 0x4>;
> + reg = <0xf9023000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9024000 {
> + frame-number = <2>;
> + interrupts = <0 11 0x4>;
> + reg = <0xf9024000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9025000 {
> + frame-number = <3>;
> + interrupts = <0 12 0x4>;
> + reg = <0xf9025000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9026000 {
> + frame-number = <4>;
> + interrupts = <0 13 0x4>;
> + reg = <0xf9026000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9027000 {
> + frame-number = <5>;
> + interrupts = <0 14 0x4>;
> + reg = <0xf9027000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9028000 {
> + frame-number = <6>;
> + interrupts = <0 15 0x4>;
> + reg = <0xf9028000 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + restart at fc4ab000 {
> + compatible = "qcom,pshold";
> + reg = <0xfc4ab000 0x4>;
> + };
> +
> + msmgpio: pinctrl at fd510000 {
> + compatible = "qcom,msm8994-pinctrl", "qcom,msm8974-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + blsp1_uart2: serial at f991e000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0xf991e000 0x1000>;
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + clock-names = "core", "iface";
> + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
> + <&clock_gcc GCC_BLSP1_AHB_CLK>;
> + };
> +
> + clocks {
> + xo_board: xo_board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + };
> +
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + };
> +
> + tcsr_mutex_regs: syscon at fd484000 {
> + compatible = "syscon";
> + reg = <0xfd484000 0x2000>;
> + };
> +
> + tcsr_mutex: hwlock {
> + compatible = "qcom,tcsr-mutex";
> + syscon = <&tcsr_mutex_regs 0 0x80>;
> + #hwlock-cells = <1>;
> + };
> +
> + qcom,smem at 6a00000 {
> + compatible = "qcom,smem";
> +
> + memory-region = <&smem_mem>;
> +
> + hwlocks = <&tcsr_mutex 3>;
> + };
> +
> + clock_gcc: qcom,gcc at fc400000 {
> + compatible = "qcom,gcc-8994";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0xfc400000 0x2000>;
> + };
> +
> +};
> +
> +#include "msm8994-pins.dtsi"
> diff --git a/arch/arm64/configs/angler_defconfig b/arch/arm64/configs/angler_defconfig
> new file mode 100644
> index 0000000..00cf192
> --- /dev/null
> +++ b/arch/arm64/configs/angler_defconfig
> @@ -0,0 +1,666 @@
> +CONFIG_AUDIT=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> +CONFIG_RCU_FAST_NO_HZ=y
> +CONFIG_LOG_BUF_SHIFT=20
> +CONFIG_CGROUPS=y
> +CONFIG_CGROUP_DEBUG=y
> +CONFIG_CGROUP_FREEZER=y
> +CONFIG_CPUSETS=y
> +CONFIG_CGROUP_CPUACCT=y
> +CONFIG_RESOURCE_COUNTERS=y
> +CONFIG_CGROUP_SCHED=y
> +CONFIG_CFS_BANDWIDTH=y
> +CONFIG_RT_GROUP_SCHED=y
> +CONFIG_SCHED_HMP=y
> +CONFIG_NAMESPACES=y
> +# CONFIG_UTS_NS is not set
> +# CONFIG_PID_NS is not set
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> +CONFIG_PANIC_TIMEOUT=5
> +CONFIG_KALLSYMS_ALL=y
> +# CONFIG_PCI_QUIRKS is not set
> +CONFIG_EMBEDDED=y
> +# CONFIG_SLUB_DEBUG is not set
> +CONFIG_PROFILING=y
> +CONFIG_PARTITION_ADVANCED=y
> +CONFIG_ARCH_MSM=y
> +CONFIG_ARCH_MSM8994=y
> +CONFIG_ARCH_MSM8994_V1_TLBI_WA=y
> +CONFIG_PCI_MSM=y
> +CONFIG_ARM64_A57_ERRATA_832075=y
> +CONFIG_SMP=y
> +CONFIG_SCHED_MC=y
> +CONFIG_ARCH_WANTS_CTXSW_LOGGING=y
> +CONFIG_PREEMPT=y
> +CONFIG_ARMV7_COMPAT=y
> +CONFIG_BALANCE_ANON_FILE_RECLAIM=y
> +CONFIG_ZSMALLOC=y
> +CONFIG_SECCOMP=y
> +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
> +# CONFIG_COREDUMP is not set
> +CONFIG_COMPAT=y
> +CONFIG_PM_AUTOSLEEP=y
> +CONFIG_PM_WAKELOCKS=y
> +CONFIG_PM_WAKELOCKS_LIMIT=0
> +CONFIG_PM_RUNTIME=y
> +CONFIG_SUSPEND_TIME=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> +CONFIG_CPU_FREQ_GOV_USERSPACE=y
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
> +CONFIG_CPU_BOOST=y
> +CONFIG_CPU_IDLE=y
> +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
> +# CONFIG_CPU_IDLE_GOV_LADDER is not set
> +# CONFIG_CPU_IDLE_GOV_MENU is not set
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_XFRM_USER=y
> +CONFIG_XFRM_STATISTICS=y
> +CONFIG_NET_KEY=y
> +CONFIG_INET=y
> +CONFIG_IP_ADVANCED_ROUTER=y
> +CONFIG_IP_MULTIPLE_TABLES=y
> +CONFIG_IP_ROUTE_VERBOSE=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_INET_AH=y
> +CONFIG_INET_ESP=y
> +CONFIG_INET_IPCOMP=y
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_LRO is not set
> +CONFIG_IPV6_PRIVACY=y
> +CONFIG_IPV6_ROUTER_PREF=y
> +CONFIG_IPV6_ROUTE_INFO=y
> +CONFIG_IPV6_OPTIMISTIC_DAD=y
> +CONFIG_INET6_AH=y
> +CONFIG_INET6_ESP=y
> +CONFIG_INET6_IPCOMP=y
> +CONFIG_IPV6_MIP6=y
> +CONFIG_IPV6_MULTIPLE_TABLES=y
> +CONFIG_IPV6_SUBTREES=y
> +CONFIG_NETFILTER=y
> +CONFIG_NF_CONNTRACK=y
> +CONFIG_NF_CONNTRACK_EVENTS=y
> +CONFIG_NF_CT_PROTO_DCCP=y
> +CONFIG_NF_CT_PROTO_SCTP=y
> +CONFIG_NF_CT_PROTO_UDPLITE=y
> +CONFIG_NF_CONNTRACK_AMANDA=y
> +CONFIG_NF_CONNTRACK_FTP=y
> +CONFIG_NF_CONNTRACK_H323=y
> +CONFIG_NF_CONNTRACK_IRC=y
> +CONFIG_NF_CONNTRACK_NETBIOS_NS=y
> +CONFIG_NF_CONNTRACK_PPTP=y
> +CONFIG_NF_CONNTRACK_SANE=y
> +CONFIG_NF_CONNTRACK_SIP=y
> +CONFIG_NF_CONNTRACK_TFTP=y
> +CONFIG_NF_CT_NETLINK=y
> +CONFIG_NETFILTER_TPROXY=y
> +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
> +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
> +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
> +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
> +CONFIG_NETFILTER_XT_TARGET_LOG=y
> +CONFIG_NETFILTER_XT_TARGET_MARK=y
> +CONFIG_NETFILTER_XT_TARGET_NFLOG=y
> +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
> +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
> +CONFIG_NETFILTER_XT_TARGET_TEE=y
> +CONFIG_NETFILTER_XT_TARGET_TPROXY=y
> +CONFIG_NETFILTER_XT_TARGET_TRACE=y
> +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
> +CONFIG_NETFILTER_XT_MATCH_COMMENT=y
> +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
> +CONFIG_NETFILTER_XT_MATCH_DSCP=y
> +CONFIG_NETFILTER_XT_MATCH_ESP=y
> +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_HELPER=y
> +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
> +CONFIG_NETFILTER_XT_MATCH_LENGTH=y
> +CONFIG_NETFILTER_XT_MATCH_LIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_MAC=y
> +CONFIG_NETFILTER_XT_MATCH_MARK=y
> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
> +CONFIG_NETFILTER_XT_MATCH_POLICY=y
> +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
> +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
> +CONFIG_NETFILTER_XT_MATCH_SOCKET=y
> +CONFIG_NETFILTER_XT_MATCH_STATE=y
> +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
> +CONFIG_NETFILTER_XT_MATCH_STRING=y
> +CONFIG_NETFILTER_XT_MATCH_TIME=y
> +CONFIG_NETFILTER_XT_MATCH_U32=y
> +CONFIG_NF_CONNTRACK_IPV4=y
> +CONFIG_IP_NF_IPTABLES=y
> +CONFIG_IP_NF_MATCH_AH=y
> +CONFIG_IP_NF_MATCH_ECN=y
> +CONFIG_IP_NF_MATCH_TTL=y
> +CONFIG_IP_NF_FILTER=y
> +CONFIG_IP_NF_TARGET_REJECT=y
> +CONFIG_IP_NF_TARGET_REJECT_SKERR=y
> +CONFIG_NF_NAT_IPV4=y
> +CONFIG_IP_NF_TARGET_MASQUERADE=y
> +CONFIG_IP_NF_TARGET_NETMAP=y
> +CONFIG_IP_NF_TARGET_REDIRECT=y
> +CONFIG_IP_NF_MANGLE=y
> +CONFIG_IP_NF_RAW=y
> +CONFIG_IP_NF_SECURITY=y
> +CONFIG_IP_NF_ARPTABLES=y
> +CONFIG_IP_NF_ARPFILTER=y
> +CONFIG_IP_NF_ARP_MANGLE=y
> +CONFIG_NF_CONNTRACK_IPV6=y
> +CONFIG_IP6_NF_IPTABLES=y
> +CONFIG_IP6_NF_FILTER=y
> +CONFIG_IP6_NF_TARGET_REJECT=y
> +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
> +CONFIG_IP6_NF_MANGLE=y
> +CONFIG_IP6_NF_RAW=y
> +CONFIG_BRIDGE_NF_EBTABLES=y
> +CONFIG_BRIDGE_EBT_BROUTE=y
> +CONFIG_L2TP=y
> +CONFIG_L2TP_DEBUGFS=y
> +CONFIG_L2TP_V3=y
> +CONFIG_L2TP_IP=y
> +CONFIG_L2TP_ETH=y
> +CONFIG_BRIDGE=y
> +CONFIG_NET_SCHED=y
> +CONFIG_NET_SCH_HTB=y
> +CONFIG_NET_SCH_PRIO=y
> +CONFIG_NET_CLS_FW=y
> +CONFIG_NET_CLS_U32=y
> +CONFIG_CLS_U32_MARK=y
> +CONFIG_NET_CLS_FLOW=y
> +CONFIG_NET_EMATCH=y
> +CONFIG_NET_EMATCH_CMP=y
> +CONFIG_NET_EMATCH_NBYTE=y
> +CONFIG_NET_EMATCH_U32=y
> +CONFIG_NET_EMATCH_META=y
> +CONFIG_NET_EMATCH_TEXT=y
> +CONFIG_NET_CLS_ACT=y
> +CONFIG_RMNET_DATA=y
> +CONFIG_RMNET_DATA_FC=y
> +CONFIG_RMNET_DATA_DEBUG_PKT=y
> +CONFIG_SOCKEV_NLMCAST=y
> +CONFIG_BT=y
> +CONFIG_BT_RFCOMM=y
> +CONFIG_BT_RFCOMM_TTY=y
> +CONFIG_BT_BNEP=y
> +CONFIG_BT_BNEP_MC_FILTER=y
> +CONFIG_BT_BNEP_PROTO_FILTER=y
> +CONFIG_BT_HIDP=y
> +CONFIG_MSM_BT_BLUESLEEP=y
> +CONFIG_CFG80211=y
> +CONFIG_CFG80211_INTERNAL_REGDB=y
> +CONFIG_RFKILL=y
> +CONFIG_NFC=y
> +CONFIG_NFC_PN548=y
> +CONFIG_IPC_ROUTER=y
> +CONFIG_IPC_ROUTER_SECURITY=y
> +CONFIG_CMA=y
> +CONFIG_CMA_SIZE_MBYTES=32
> +CONFIG_ARM_CCI=y
> +CONFIG_ZRAM=y
> +CONFIG_ZRAM_LZ4_COMPRESS=y
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_BLK_DEV_RAM=y
> +CONFIG_UID_STAT=y
> +CONFIG_QSEECOM=y
> +CONFIG_TI_DRV2667=y
> +CONFIG_UID_CPUTIME=y
> +CONFIG_WIFI_SAR=y
> +CONFIG_SCSI=y
> +CONFIG_SCSI_TGT=y
> +CONFIG_BLK_DEV_SD=y
> +CONFIG_CHR_DEV_SG=y
> +CONFIG_SCSI_MULTI_LUN=y
> +CONFIG_SCSI_CONSTANTS=y
> +CONFIG_SCSI_LOGGING=y
> +CONFIG_SCSI_SCAN_ASYNC=y
> +# CONFIG_SCSI_LOWLEVEL is not set
> +CONFIG_MD=y
> +CONFIG_BLK_DEV_DM=y
> +CONFIG_DM_CRYPT=y
> +CONFIG_DM_REQ_CRYPT=y
> +CONFIG_DM_VERITY=y
> +CONFIG_NETDEVICES=y
> +CONFIG_DUMMY=y
> +CONFIG_TUN=y
> +# CONFIG_ETHERNET is not set
> +CONFIG_PPP=y
> +CONFIG_PPP_BSDCOMP=y
> +CONFIG_PPP_DEFLATE=y
> +CONFIG_PPP_FILTER=y
> +CONFIG_PPP_MPPE=y
> +CONFIG_PPP_MULTILINK=y
> +CONFIG_PPPOE=y
> +CONFIG_PPPOL2TP=y
> +CONFIG_PPPOLAC=y
> +CONFIG_PPPOPNS=y
> +CONFIG_PPP_ASYNC=y
> +CONFIG_PPP_SYNC_TTY=y
> +CONFIG_USB_KAWETH=y
> +CONFIG_USB_PEGASUS=y
> +CONFIG_USB_RTL8150=y
> +CONFIG_USB_RTL8152=y
> +CONFIG_USB_USBNET=y
> +# CONFIG_USB_NET_CDC_NCM is not set
> +# CONFIG_USB_NET_NET1080 is not set
> +# CONFIG_USB_NET_CDC_SUBSET is not set
> +# CONFIG_USB_NET_ZAURUS is not set
> +CONFIG_CLD_LL_CORE=y
> +CONFIG_BCMDHD=y
> +CONFIG_BCMDHD_PCIE=y
> +CONFIG_BCM4358=y
> +CONFIG_BCMDHD_FW_PATH="/vendor/firmware/fw_bcmdhd.bin"
> +CONFIG_DHD_USE_STATIC_BUF=y
> +CONFIG_DHD_USE_SCHED_SCAN=y
> +CONFIG_DHD_OF_SUPPORT=y
> +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> +CONFIG_INPUT_EVDEV=y
> +# CONFIG_KEYBOARD_ATKBD is not set
> +CONFIG_KEYBOARD_GPIO=y
> +# CONFIG_INPUT_MOUSE is not set
> +CONFIG_INPUT_JOYSTICK=y
> +CONFIG_JOYSTICK_XPAD=y
> +CONFIG_JOYSTICK_XPAD_FF=y
> +CONFIG_JOYSTICK_XPAD_LEDS=y
> +CONFIG_INPUT_TABLET=y
> +CONFIG_TABLET_USB_ACECAD=y
> +CONFIG_TABLET_USB_AIPTEK=y
> +CONFIG_TABLET_USB_GTCO=y
> +CONFIG_TABLET_USB_HANWANG=y
> +CONFIG_TABLET_USB_KBTAB=y
> +CONFIG_TABLET_USB_WACOM=y
> +CONFIG_INPUT_TOUCHSCREEN=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICETREE_SUPPORT=y
> +# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_PROXIMITY is not set
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_BINARY_FW_UPGRADE=y
> +CONFIG_TOUCHSCREEN_HUAWEI_CYTTSP4_RECOVERY_FW_UPDATE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_MANUAL_TTCONFIG_UPGRADE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_USE_FW_BIN_FILE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICE_ACCESS=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_LOADER=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEBUG_MODULE=y
> +CONFIG_TOUCHSCREEN_GEN_VKEYS=y
> +CONFIG_SECURE_TOUCH=y
> +CONFIG_TOUCHSCREEN_HUAWEI_SYNAPTICS_DSX_v25=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_CORE=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_RMI_DEV=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_FW_UPDATE=y
> +CONFIG_INPUT_MISC=y
> +CONFIG_INPUT_KEYCHORD=y
> +CONFIG_INPUT_UINPUT=y
> +CONFIG_INPUT_GPIO=y
> +CONFIG_LASER_STMVL6180=y
> +CONFIG_RF_DETECT=y
> +# CONFIG_SERIO is not set
> +CONFIG_FINGERPRINT_FPC=y
> +# CONFIG_VT is not set
> +# CONFIG_LEGACY_PTYS is not set
> +# CONFIG_DEVMEM is not set
> +# CONFIG_DEVKMEM is not set
> +CONFIG_SERIAL_MSM_HS=y
> +CONFIG_SERIAL_MSM_HSL=y
> +CONFIG_SERIAL_MSM_HSL_CONSOLE=y
> +CONFIG_SERIAL_MSM_SMD=y
> +CONFIG_HW_RANDOM_MSM=y
> +CONFIG_MSM_SMD_PKT=y
> +CONFIG_MSM_ADSPRPC=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_MSM_V2=y
> +CONFIG_SLIMBUS_MSM_NGD=y
> +CONFIG_SPI=y
> +CONFIG_SPI_CONTEXTHUB=y
> +CONFIG_SPI_QUP=y
> +CONFIG_SPMI=y
> +CONFIG_SPMI_MSM_PMIC_ARB=y
> +CONFIG_MSM_QPNP_INT=y
> +CONFIG_USE_PINCTRL_IRQ=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_GPIO_QPNP_PIN=y
> +CONFIG_SMB349_DUAL_CHARGER=y
> +CONFIG_SMB1351_USB_CHARGER=y
> +CONFIG_QPNP_SMBCHARGER=y
> +CONFIG_QPNP_FG=y
> +CONFIG_BATTERY_BCL=y
> +CONFIG_MSM_BCL_CTL=y
> +CONFIG_MSM_BCL_PERIPHERAL_CTL=y
> +CONFIG_POWER_RESET_MSM=y
> +CONFIG_MSM_DLOAD_MODE=y
> +CONFIG_MSM_PM=y
> +CONFIG_APSS_CORE_EA=y
> +CONFIG_SENSORS_EPM_ADC=y
> +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
> +CONFIG_THERMAL=y
> +CONFIG_THERMAL_TSENS8974=y
> +CONFIG_LIMITS_MONITOR=y
> +CONFIG_LIMITS_LITE_HW=y
> +CONFIG_THERMAL_MONITOR=y
> +CONFIG_THERMAL_QPNP=y
> +CONFIG_THERMAL_QPNP_ADC_TM=y
> +CONFIG_WCD9330_CODEC=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_REGULATOR_PROXY_CONSUMER=y
> +CONFIG_REGULATOR_MEM_ACC=y
> +CONFIG_REGULATOR_TPS65132=y
> +CONFIG_REGULATOR_STUB=y
> +CONFIG_REGULATOR_RPM_SMD=y
> +CONFIG_REGULATOR_QPNP=y
> +CONFIG_REGULATOR_QPNP_LABIBB=y
> +CONFIG_REGULATOR_SPM=y
> +CONFIG_REGULATOR_CPR=y
> +CONFIG_MEDIA_SUPPORT=y
> +CONFIG_MEDIA_CAMERA_SUPPORT=y
> +CONFIG_MEDIA_RADIO_SUPPORT=y
> +CONFIG_MEDIA_CONTROLLER=y
> +CONFIG_VIDEO_V4L2_SUBDEV_API=y
> +CONFIG_VIDEOBUF2_MSM_MEM=y
> +CONFIG_MEDIA_USB_SUPPORT=y
> +CONFIG_USB_VIDEO_CLASS=y
> +# CONFIG_USB_GSPCA is not set
> +CONFIG_V4L_PLATFORM_DRIVERS=y
> +CONFIG_MSMB_CAMERA=y
> +CONFIG_MSM_CAMERA_SENSOR=y
> +CONFIG_MSM_CPP=y
> +CONFIG_MSM_CCI=y
> +CONFIG_MSM_CSI30_HEADER=y
> +CONFIG_MSM_CSIPHY=y
> +CONFIG_MSM_CSID=y
> +CONFIG_MSM_EEPROM=y
> +CONFIG_MSM_ISPIF=y
> +CONFIG_HI256=y
> +CONFIG_MT9M114=y
> +CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
> +CONFIG_MSMB_JPEG=y
> +CONFIG_MSM_FD=y
> +CONFIG_MSM_VIDC_V4L2=y
> +CONFIG_TSPP=y
> +# CONFIG_RADIO_ADAPTERS is not set
> +# CONFIG_VGA_ARB is not set
> +CONFIG_MSM_KGSL=y
> +CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
> +CONFIG_FB=y
> +CONFIG_FB_MSM=y
> +CONFIG_FB_MSM_MDSS=y
> +CONFIG_FB_MSM_MDSS_WRITEBACK=y
> +CONFIG_SOUND=y
> +CONFIG_SND=y
> +CONFIG_SND_MPU401=y
> +# CONFIG_SND_PCI is not set
> +# CONFIG_SND_SPI is not set
> +CONFIG_SND_USB_AUDIO=y
> +CONFIG_SND_SOC=y
> +CONFIG_SND_SOC_MSM8994=y
> +CONFIG_SND_SOC_MAX98925=y
> +CONFIG_HID_BATTERY_STRENGTH=y
> +CONFIG_HIDRAW=y
> +CONFIG_UHID=y
> +CONFIG_HID_A4TECH=y
> +CONFIG_HID_APPLE=y
> +CONFIG_HID_BELKIN=y
> +CONFIG_HID_CHERRY=y
> +CONFIG_HID_CHICONY=y
> +CONFIG_HID_PRODIKEYS=y
> +CONFIG_HID_CYPRESS=y
> +CONFIG_HID_ELECOM=y
> +CONFIG_HID_EZKEY=y
> +CONFIG_HID_HOLTEK=y
> +CONFIG_HOLTEK_FF=y
> +CONFIG_HID_KEYTOUCH=y
> +CONFIG_HID_KYE=y
> +CONFIG_HID_UCLOGIC=y
> +CONFIG_HID_WALTOP=y
> +CONFIG_HID_GYRATION=y
> +CONFIG_HID_ICADE=y
> +CONFIG_HID_KENSINGTON=y
> +CONFIG_HID_LCPOWER=y
> +CONFIG_HID_LENOVO_TPKBD=y
> +CONFIG_HID_LOGITECH=y
> +CONFIG_HID_LOGITECH_DJ=y
> +CONFIG_LOGITECH_FF=y
> +CONFIG_LOGIRUMBLEPAD2_FF=y
> +CONFIG_LOGIG940_FF=y
> +CONFIG_HID_MAGICMOUSE=y
> +CONFIG_HID_MICROSOFT=y
> +CONFIG_HID_MONTEREY=y
> +CONFIG_HID_MULTITOUCH=y
> +CONFIG_HID_NTRIG=y
> +CONFIG_HID_ORTEK=y
> +CONFIG_HID_PANTHERLORD=y
> +CONFIG_PANTHERLORD_FF=y
> +CONFIG_HID_PRIMAX=y
> +CONFIG_HID_PS3REMOTE=y
> +CONFIG_HID_ROCCAT=y
> +CONFIG_HID_SAITEK=y
> +CONFIG_HID_SAMSUNG=y
> +CONFIG_HID_SONY=y
> +CONFIG_HID_SPEEDLINK=y
> +CONFIG_HID_STEELSERIES=y
> +CONFIG_HID_SUNPLUS=y
> +CONFIG_HID_SMARTJOYPLUS=y
> +CONFIG_SMARTJOYPLUS_FF=y
> +CONFIG_HID_TOPSEED=y
> +CONFIG_HID_THINGM=y
> +CONFIG_HID_THRUSTMASTER=y
> +CONFIG_THRUSTMASTER_FF=y
> +CONFIG_HID_WACOM=y
> +CONFIG_HID_WIIMOTE=y
> +CONFIG_HID_ZEROPLUS=y
> +CONFIG_ZEROPLUS_FF=y
> +CONFIG_HID_SENSOR_HUB=y
> +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_EHSET=y
> +CONFIG_USB_EHCI_MSM=y
> +CONFIG_USB_ACM=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_SERIAL=y
> +CONFIG_USB_SERIAL_GENERIC=y
> +CONFIG_USB_SERIAL_FTDI_SIO=y
> +CONFIG_USB_SERIAL_PL2303=y
> +CONFIG_USB_EMI62=y
> +CONFIG_USB_EMI26=y
> +CONFIG_USB_EHSET_TEST_FIXTURE=y
> +CONFIG_USB_PHY=y
> +CONFIG_USB_MSM_SSPHY_QMP=y
> +CONFIG_MSM_QUSB_PHY=y
> +CONFIG_DUAL_ROLE_USB_INTF=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DEBUG_FILES=y
> +CONFIG_USB_GADGET_DEBUG_FS=y
> +CONFIG_USB_CI13XXX_MSM=y
> +CONFIG_USB_DWC3_MSM=y
> +CONFIG_USB_G_ANDROID=y
> +CONFIG_TYPEC=y
> +CONFIG_TUSB320_TYPEC=y
> +CONFIG_MMC=y
> +CONFIG_MMC_PERF_PROFILING=y
> +CONFIG_MMC_UNSAFE_RESUME=y
> +CONFIG_MMC_CLKGATE=y
> +CONFIG_MMC_PARANOID_SD_INIT=y
> +CONFIG_MMC_BLOCK_MINORS=32
> +CONFIG_MMC_TEST=y
> +CONFIG_MMC_BLOCK_TEST=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_MSM=y
> +CONFIG_LEDS_QPNP=y
> +CONFIG_LEDS_QPNP_FLASH=y
> +CONFIG_LEDS_QPNP_WLED=y
> +CONFIG_LEDS_TRIGGERS=y
> +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> +CONFIG_SWITCH=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_QPNP=y
> +CONFIG_DMADEVICES=y
> +CONFIG_QCOM_SPS_DMA=y
> +CONFIG_UIO=y
> +CONFIG_UIO_MSM_SHAREDMEM=y
> +CONFIG_STAGING=y
> +CONFIG_ANDROID=y
> +CONFIG_ANDROID_BINDER_IPC=y
> +CONFIG_ASHMEM=y
> +CONFIG_ANDROID_LOGGER=y
> +CONFIG_ANDROID_LOW_MEMORY_KILLER=y
> +CONFIG_ANDROID_INTF_ALARM_DEV=y
> +CONFIG_ONESHOT_SYNC=y
> +CONFIG_ION=y
> +CONFIG_ION_MSM=y
> +CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS=y
> +# CONFIG_NET_VENDOR_SILICOM is not set
> +CONFIG_SPS=y
> +CONFIG_USB_BAM=y
> +CONFIG_SPS_SUPPORT_NDP_BAM=y
> +CONFIG_QPNP_POWER_ON=y
> +CONFIG_QPNP_REVID=y
> +CONFIG_QPNP_COINCELL=y
> +CONFIG_QPNP_USB_DETECT=y
> +CONFIG_IPA=y
> +CONFIG_RMNET_IPA=y
> +CONFIG_MSM_AVTIMER=y
> +CONFIG_PFT=y
> +CONFIG_MSM_BUS_SCALING=y
> +CONFIG_MSM_BUSPM_DEV=y
> +CONFIG_BUS_TOPOLOGY_ADHOC=y
> +CONFIG_DEBUG_BUS_VOTER=y
> +CONFIG_QPNP_HAPTIC=y
> +CONFIG_MSM_MDSS_PLL=y
> +CONFIG_REMOTE_SPINLOCK_MSM=y
> +CONFIG_MSM_IOMMU_V1=y
> +CONFIG_MSM_IOMMU_VBIF_CHECK=y
> +CONFIG_IOMMU_FORCE_4K_MAPPINGS=y
> +CONFIG_DEVFREQ_SPDM=y
> +CONFIG_PWM=y
> +CONFIG_PWM_QPNP=y
> +CONFIG_SENSORS_SSC=y
> +CONFIG_GENERIC_PHY=y
> +CONFIG_CP_ACCESS64=y
> +CONFIG_MSM_EVENT_TIMER=y
> +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
> +CONFIG_MSM_QMI_INTERFACE=y
> +CONFIG_MSM_SMD_DEBUG=y
> +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
> +CONFIG_MSM_RPM_LOG=y
> +CONFIG_MSM_RPM_STATS_LOG=y
> +CONFIG_MSM_RUN_QUEUE_STATS=y
> +CONFIG_MSM_SMEM_LOGGING=y
> +CONFIG_MSM_SMP2P=y
> +CONFIG_MSM_SMP2P_TEST=y
> +CONFIG_MSM_SPM=y
> +CONFIG_MSM_L2_SPM=y
> +CONFIG_MSM_ADSP_LOADER=y
> +CONFIG_MSM_MEMORY_DUMP_V2=y
> +CONFIG_MSM_DEBUG_LAR_UNLOCK=y
> +CONFIG_MSM_DDR_HEALTH=y
> +CONFIG_MSM_COMMON_LOG=y
> +CONFIG_MSM_WATCHDOG_V2=y
> +CONFIG_MSM_FORCE_WDOG_BITE_ON_PANIC=y
> +CONFIG_MSM_HVC=y
> +CONFIG_MSM_SUBSYSTEM_RESTART=y
> +CONFIG_MSM_SYSMON_COMM=y
> +CONFIG_MSM_PIL=y
> +CONFIG_MSM_PIL_SSR_GENERIC=y
> +CONFIG_MSM_PIL_MSS_QDSP6V5=y
> +CONFIG_MSM_OCMEM=y
> +CONFIG_MSM_OCMEM_LOCAL_POWER_CTRL=y
> +CONFIG_MSM_OCMEM_DEBUG=y
> +CONFIG_MSM_BOOT_STATS=y
> +CONFIG_MSM_SCM=y
> +CONFIG_MSM_XPU_ERR_FATAL=y
> +CONFIG_MSM_CPUSS_DUMP=y
> +CONFIG_MSM_SHARED_HEAP_ACCESS=y
> +CONFIG_MSM_SYSTEM_HEALTH_MONITOR=y
> +CONFIG_QCOM_EARLY_RANDOM=y
> +CONFIG_MSM_PERFORMANCE=y
> +CONFIG_QCOM_NPA_DUMP=y
> +CONFIG_MSM_TZ_LOG=y
> +CONFIG_EXT4_FS=y
> +CONFIG_EXT4_FS_SECURITY=y
> +CONFIG_EXT4_FS_ENCRYPTION=y
> +CONFIG_FUSE_FS=y
> +CONFIG_VFAT_FS=y
> +CONFIG_TMPFS=y
> +CONFIG_TMPFS_POSIX_ACL=y
> +CONFIG_PSTORE=y
> +CONFIG_PSTORE_CONSOLE=y
> +CONFIG_PSTORE_PMSG=y
> +CONFIG_PSTORE_RAM=y
> +# CONFIG_NETWORK_FILESYSTEMS is not set
> +CONFIG_NLS_CODEPAGE_437=y
> +CONFIG_NLS_ASCII=y
> +CONFIG_NLS_ISO8859_1=y
> +CONFIG_NLS_UTF8=y
> +CONFIG_PRINTK_TIME=y
> +CONFIG_MAGIC_SYSRQ=y
> +CONFIG_PAGE_OWNER=y
> +# CONFIG_SYSRQ_SCHED_DEBUG is not set
> +CONFIG_SCHEDSTATS=y
> +CONFIG_TIMER_STATS=y
> +CONFIG_DEBUG_INFO=y
> +CONFIG_RCU_CPU_STALL_INFO=y
> +CONFIG_RCU_TRACE=y
> +CONFIG_IPC_LOGGING=y
> +CONFIG_BLK_DEV_IO_TRACE=y
> +CONFIG_DYNAMIC_DEBUG=y
> +CONFIG_OOPS_LOG_BUFFER=y
> +CONFIG_LOG_BUF_MAGIC=y
> +CONFIG_OOPS_LOG_BUF_SHIFT=17
> +CONFIG_PANIC_ON_DATA_CORRUPTION=y
> +CONFIG_ARM64_PTDUMP=y
> +CONFIG_PID_IN_CONTEXTIDR=y
> +CONFIG_SECURITY=y
> +CONFIG_SECURITY_NETWORK=y
> +CONFIG_LSM_MMAP_MIN_ADDR=4096
> +CONFIG_SECURITY_SELINUX=y
> +CONFIG_CRYPTO_NULL=y
> +CONFIG_CRYPTO_XCBC=y
> +CONFIG_CRYPTO_MD4=y
> +CONFIG_CRYPTO_TWOFISH=y
> +CONFIG_CRYPTO_DEV_QCRYPTO=y
> +CONFIG_CRYPTO_DEV_QCE=y
> +CONFIG_CRYPTO_DEV_QCEDEV=y
> +CONFIG_CRYPTO_DEV_QCOM_ICE=y
> +CONFIG_ASYMMETRIC_KEY_TYPE=y
> +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
> +CONFIG_PUBLIC_KEY_ALGO_RSA=y
> +CONFIG_X509_CERTIFICATE_PARSER=y
> +CONFIG_ARM64_CRYPTO=y
> +CONFIG_CRYPTO_SHA1_ARM64_CE=y
> +CONFIG_CRYPTO_SHA2_ARM64_CE=y
> +CONFIG_CRYPTO_GHASH_ARM64_CE=y
> +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
> +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
> +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
> +CONFIG_QMI_ENCDEC=y
> +CONFIG_STRICT_MEMORY_RWX=y
> +CONFIG_ARM_APPENDED_DTB=y
> +CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_ARCH_QCOM=y
> +CONFIG_QCOM_SMD_RPM=y
> +CONFIG_QCOM_SMEM=y
> +CONFIG_QCOM_SMD=y
> +CONFIG_HWSPINLOCK_QCOM=y
> +CONFIG_QCOM_PM=y
> +CONFIG_SERIAL_MSM=y
> +CONFIG_SERIAL_MSM_CONSOLE=y
> +CONFIG_PINCTRL_MSM8X74=y
> +CONFIG_COMMON_CLK_QCOM=y
> +CONFIG_MSM_GCC_8994=y
> +CONFIG_MACH_HUAWEI=y
> +CONFIG_DEVTMPFS=y
> +CONFIG_DMA_CMA=y
> --
> 2.6.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
2016-09-21 0:42 ` Jeremy McNicoll
@ 2016-09-22 18:39 ` Stephen Boyd
-1 siblings, 0 replies; 22+ messages in thread
From: Stephen Boyd @ 2016-09-22 18:39 UTC (permalink / raw)
To: Jeremy McNicoll, Andy Gross
Cc: linux-arm-msm, linux-arm-kernel, mail, jeremymc
Quoting Jeremy McNicoll (2016-09-20 17:42:02)
> On 2016-07-08 10:41 AM, Andy Gross wrote:
> > On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
> >> +
> >> +#include "../qcom/msm8992.dtsi"
> >> +
> >> +/ {
> >> + model = "LGE MSM8992 BULLHEAD rev-1.01";
> >> + compatible = "qcom,msm8992";
> >> + qcom,board-id = <0xb64 0>;
> >
> > Please work with sboyd to add the board-id to the dtbTool. We don't put
> > board-ids in the dts file. We post-process the dtb file and add them then.
> >
>
> sboyd has all the info he needs for this, I believe its just with legal
> now. Will remove for V2.
I've pushed out an update for dtbtool to have these msm ids.
>
> >> +
> >> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> >> +
> >> +/ {
> >> + model = "Qualcomm Technologies, Inc. MSM 8992";
> >> + compatible = "qcom,msm8992";
> >> + qcom,msm-id = <251 0>, <252 0>;
>
> This is needed or else the LK provides the following error
>
> [5380] qcom,msm-id entry not found
>
> and refuses to boot.
>
>
> >> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
> >
> > See above comment on ids.
>
> removal of this (pmic-id) seems to be ok.
>
Having the msm ids (and the pmic ids) in dtbtool isn't going to help
here though. I believe the bootloader on these devices uses a design of
appended dtbs where each dtb has the qcom,{msm-id,board-id,pmic-id}
properties in them. The QCDT "header" that dtbtool generates is not
used.
To fix that problem we'll need to update dtbtool to inject these
properties into the dtbs based on the compatible strings. Or get
maintainers to accept that these ids are now necessary for proper
functionality.
Furthermore, the value of board-id (0xb64) is concerning. qcom only
supports a certain set of values there for their boards, but vendors are
free to do whatever they want with that value. This means they can reuse
existing values that would map to qcom's concept of the "mtp" or "cdp"
boards, or they can numbers that would alias with other vendors.
Thankfully, msm-id and pmic-id are values that are under qcom's control,
so those are always going to be unique and sane. Really all that could
alias is board-id.
What does this all mean? We can't support non-qcom boards in the same
boot.img because of the possibility for the board-id property to alias
between different dtbs. Or at least dtbtool will have to do some alias
analysis and eject one aliasing dtbs from the blob. It also means that
we have a lot of work to do in dtbtool to inject these properties based
on strings, and to have custom parsers for different vendor prefixes so
that we know what values to inject (the nightmare is growing).
I've asked the bootloader folks to fix this in future platforms so that
we match based on the compatible string, instead of having to do any
post processing. Basically, put dtbtool logic into the bootloader. The
discussion is still on-going, but I'm hopeful that we don't need to keep
doing things here with post-processing and the headache will be reduced.
That could totally backfire though if vendors decide to leave the
bootloader unchanged and boot the "qcom,msm8992-mtp" dtb that's been
slightly tweaked for their design. Let's hope that doesn't happen.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
@ 2016-09-22 18:39 ` Stephen Boyd
0 siblings, 0 replies; 22+ messages in thread
From: Stephen Boyd @ 2016-09-22 18:39 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Jeremy McNicoll (2016-09-20 17:42:02)
> On 2016-07-08 10:41 AM, Andy Gross wrote:
> > On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
> >> +
> >> +#include "../qcom/msm8992.dtsi"
> >> +
> >> +/ {
> >> + model = "LGE MSM8992 BULLHEAD rev-1.01";
> >> + compatible = "qcom,msm8992";
> >> + qcom,board-id = <0xb64 0>;
> >
> > Please work with sboyd to add the board-id to the dtbTool. We don't put
> > board-ids in the dts file. We post-process the dtb file and add them then.
> >
>
> sboyd has all the info he needs for this, I believe its just with legal
> now. Will remove for V2.
I've pushed out an update for dtbtool to have these msm ids.
>
> >> +
> >> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> >> +
> >> +/ {
> >> + model = "Qualcomm Technologies, Inc. MSM 8992";
> >> + compatible = "qcom,msm8992";
> >> + qcom,msm-id = <251 0>, <252 0>;
>
> This is needed or else the LK provides the following error
>
> [5380] qcom,msm-id entry not found
>
> and refuses to boot.
>
>
> >> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
> >
> > See above comment on ids.
>
> removal of this (pmic-id) seems to be ok.
>
Having the msm ids (and the pmic ids) in dtbtool isn't going to help
here though. I believe the bootloader on these devices uses a design of
appended dtbs where each dtb has the qcom,{msm-id,board-id,pmic-id}
properties in them. The QCDT "header" that dtbtool generates is not
used.
To fix that problem we'll need to update dtbtool to inject these
properties into the dtbs based on the compatible strings. Or get
maintainers to accept that these ids are now necessary for proper
functionality.
Furthermore, the value of board-id (0xb64) is concerning. qcom only
supports a certain set of values there for their boards, but vendors are
free to do whatever they want with that value. This means they can reuse
existing values that would map to qcom's concept of the "mtp" or "cdp"
boards, or they can numbers that would alias with other vendors.
Thankfully, msm-id and pmic-id are values that are under qcom's control,
so those are always going to be unique and sane. Really all that could
alias is board-id.
What does this all mean? We can't support non-qcom boards in the same
boot.img because of the possibility for the board-id property to alias
between different dtbs. Or at least dtbtool will have to do some alias
analysis and eject one aliasing dtbs from the blob. It also means that
we have a lot of work to do in dtbtool to inject these properties based
on strings, and to have custom parsers for different vendor prefixes so
that we know what values to inject (the nightmare is growing).
I've asked the bootloader folks to fix this in future platforms so that
we match based on the compatible string, instead of having to do any
post processing. Basically, put dtbtool logic into the bootloader. The
discussion is still on-going, but I'm hopeful that we don't need to keep
doing things here with post-processing and the headache will be reduced.
That could totally backfire though if vendors decide to leave the
bootloader unchanged and boot the "qcom,msm8992-mtp" dtb that's been
slightly tweaked for their design. Let's hope that doesn't happen.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
2016-09-22 18:39 ` Stephen Boyd
@ 2016-09-23 23:27 ` Jeremy McNicoll
-1 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-09-23 23:27 UTC (permalink / raw)
To: Stephen Boyd, Andy Gross; +Cc: linux-arm-msm, linux-arm-kernel, mail, jeremymc
On 2016-09-22 11:39 AM, Stephen Boyd wrote:
> Quoting Jeremy McNicoll (2016-09-20 17:42:02)
>> On 2016-07-08 10:41 AM, Andy Gross wrote:
>>> On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
>>>> +
>>>> +#include "../qcom/msm8992.dtsi"
>>>> +
>>>> +/ {
>>>> + model = "LGE MSM8992 BULLHEAD rev-1.01";
>>>> + compatible = "qcom,msm8992";
>>>> + qcom,board-id = <0xb64 0>;
>>>
>>> Please work with sboyd to add the board-id to the dtbTool. We don't put
>>> board-ids in the dts file. We post-process the dtb file and add them then.
>>>
>>
>> sboyd has all the info he needs for this, I believe its just with legal
>> now. Will remove for V2.
>
> I've pushed out an update for dtbtool to have these msm ids.
>
>>
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>>>> +
>>>> +/ {
>>>> + model = "Qualcomm Technologies, Inc. MSM 8992";
>>>> + compatible = "qcom,msm8992";
>>>> + qcom,msm-id = <251 0>, <252 0>;
>>
>> This is needed or else the LK provides the following error
>>
>> [5380] qcom,msm-id entry not found
>>
>> and refuses to boot.
>>
>>
>>>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>>>
>>> See above comment on ids.
>>
>> removal of this (pmic-id) seems to be ok.
>>
>
> Having the msm ids (and the pmic ids) in dtbtool isn't going to help
> here though. I believe the bootloader on these devices uses a design of
> appended dtbs where each dtb has the qcom,{msm-id,board-id,pmic-id}
> properties in them. The QCDT "header" that dtbtool generates is not
> used.
>
> To fix that problem we'll need to update dtbtool to inject these
> properties into the dtbs based on the compatible strings. Or get
> maintainers to accept that these ids are now necessary for proper
> functionality.
I will try modifying the tool to inject these values to understand
how easy and/or complicated it will be. This topic will be raised
during plumbers as most people will be there.
>
> Furthermore, the value of board-id (0xb64) is concerning. qcom only
> supports a certain set of values there for their boards, but vendors are
> free to do whatever they want with that value. This means they can reuse
> existing values that would map to qcom's concept of the "mtp" or "cdp"
> boards, or they can numbers that would alias with other vendors.
> Thankfully, msm-id and pmic-id are values that are under qcom's control,
> so those are always going to be unique and sane. Really all that could
> alias is board-id.
>
> What does this all mean? We can't support non-qcom boards in the same
> boot.img because of the possibility for the board-id property to alias
> between different dtbs. Or at least dtbtool will have to do some alias
> analysis and eject one aliasing dtbs from the blob. It also means that
> we have a lot of work to do in dtbtool to inject these properties based
> on strings, and to have custom parsers for different vendor prefixes so
> that we know what values to inject (the nightmare is growing).
>
This provides a reasonably compelling argument that can be discussed
with the device tree maintainers during Plumbers.
> I've asked the bootloader folks to fix this in future platforms so that
> we match based on the compatible string, instead of having to do any
> post processing. Basically, put dtbtool logic into the bootloader. The
> discussion is still on-going, but I'm hopeful that we don't need to keep
> doing things here with post-processing and the headache will be reduced.
> That could totally backfire though if vendors decide to leave the
> bootloader unchanged and boot the "qcom,msm8992-mtp" dtb that's been
> slightly tweaked for their design. Let's hope that doesn't happen.
>
Thank you for pushing this internally as it will definitely aid in the
mainline support going forward.
-jeremy
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
@ 2016-09-23 23:27 ` Jeremy McNicoll
0 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-09-23 23:27 UTC (permalink / raw)
To: linux-arm-kernel
On 2016-09-22 11:39 AM, Stephen Boyd wrote:
> Quoting Jeremy McNicoll (2016-09-20 17:42:02)
>> On 2016-07-08 10:41 AM, Andy Gross wrote:
>>> On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
>>>> +
>>>> +#include "../qcom/msm8992.dtsi"
>>>> +
>>>> +/ {
>>>> + model = "LGE MSM8992 BULLHEAD rev-1.01";
>>>> + compatible = "qcom,msm8992";
>>>> + qcom,board-id = <0xb64 0>;
>>>
>>> Please work with sboyd to add the board-id to the dtbTool. We don't put
>>> board-ids in the dts file. We post-process the dtb file and add them then.
>>>
>>
>> sboyd has all the info he needs for this, I believe its just with legal
>> now. Will remove for V2.
>
> I've pushed out an update for dtbtool to have these msm ids.
>
>>
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>>>> +
>>>> +/ {
>>>> + model = "Qualcomm Technologies, Inc. MSM 8992";
>>>> + compatible = "qcom,msm8992";
>>>> + qcom,msm-id = <251 0>, <252 0>;
>>
>> This is needed or else the LK provides the following error
>>
>> [5380] qcom,msm-id entry not found
>>
>> and refuses to boot.
>>
>>
>>>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>>>
>>> See above comment on ids.
>>
>> removal of this (pmic-id) seems to be ok.
>>
>
> Having the msm ids (and the pmic ids) in dtbtool isn't going to help
> here though. I believe the bootloader on these devices uses a design of
> appended dtbs where each dtb has the qcom,{msm-id,board-id,pmic-id}
> properties in them. The QCDT "header" that dtbtool generates is not
> used.
>
> To fix that problem we'll need to update dtbtool to inject these
> properties into the dtbs based on the compatible strings. Or get
> maintainers to accept that these ids are now necessary for proper
> functionality.
I will try modifying the tool to inject these values to understand
how easy and/or complicated it will be. This topic will be raised
during plumbers as most people will be there.
>
> Furthermore, the value of board-id (0xb64) is concerning. qcom only
> supports a certain set of values there for their boards, but vendors are
> free to do whatever they want with that value. This means they can reuse
> existing values that would map to qcom's concept of the "mtp" or "cdp"
> boards, or they can numbers that would alias with other vendors.
> Thankfully, msm-id and pmic-id are values that are under qcom's control,
> so those are always going to be unique and sane. Really all that could
> alias is board-id.
>
> What does this all mean? We can't support non-qcom boards in the same
> boot.img because of the possibility for the board-id property to alias
> between different dtbs. Or at least dtbtool will have to do some alias
> analysis and eject one aliasing dtbs from the blob. It also means that
> we have a lot of work to do in dtbtool to inject these properties based
> on strings, and to have custom parsers for different vendor prefixes so
> that we know what values to inject (the nightmare is growing).
>
This provides a reasonably compelling argument that can be discussed
with the device tree maintainers during Plumbers.
> I've asked the bootloader folks to fix this in future platforms so that
> we match based on the compatible string, instead of having to do any
> post processing. Basically, put dtbtool logic into the bootloader. The
> discussion is still on-going, but I'm hopeful that we don't need to keep
> doing things here with post-processing and the headache will be reduced.
> That could totally backfire though if vendors decide to leave the
> bootloader unchanged and boot the "qcom,msm8992-mtp" dtb that's been
> slightly tweaked for their design. Let's hope that doesn't happen.
>
Thank you for pushing this internally as it will definitely aid in the
mainline support going forward.
-jeremy
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
2016-09-21 1:12 ` Andy Gross
@ 2016-10-01 0:36 ` Jeremy McNicoll
-1 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-10-01 0:36 UTC (permalink / raw)
To: Andy Gross; +Cc: linux-arm-msm, linux-arm-kernel, stephen.boyd, mail, jeremymc
On 2016-09-20 6:12 PM, Andy Gross wrote:
> On Thu, Jul 07, 2016 at 05:41:06PM -0700, Jeremy McNicoll wrote:
>> From: Bastian Köcher <mail@kchr.de>
>>
>> Initial device tree support for Qualcomm MSM8994 SoC and
>> Huawei Angler / Google Nexus 6P support.
>>
>> The device tree and the angler_defconfig are based on the
>> device tree from the Google 3.10 kernel tree.
>>
>> The device can be booted into the initrd with only one CPU running.
>>
>> Signed-off-by: Bastian Köcher <mail@kchr.de>
>> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
>> ---
>> arch/arm64/Kconfig.platforms | 13 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/huawei/Makefile | 5 +
>> .../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
>
> There is nothing to warrant having huawei have their own directory unless they
> are making their own SOC.
>
done
>> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
>> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
>> arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
>> arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
>
> We don't need to add defconfigs. We just need to turn on the options in the
> main defconfig.
>
ok, removed
> Also, when you do have defconfigs, please separate those changes into a separate
> patch.
>
will do.
>> 8 files changed, 1032 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/huawei/Makefile
>> create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
>> create mode 100644 arch/arm64/configs/angler_defconfig
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 515e669..f253f60d 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -98,6 +98,19 @@ config MACH_LGE
>> help
>> This enables support for the LGE Nexus 5X - BullHead MSM8992.
>>
>> +config ARCH_MSM8994
>> + bool "Qualcomm MSM8994"
>> + depends on ARCH_QCOM
>> + select ARCH_REQUIRE_GPIOLIB
>> + help
>> + This enables support for the Qualcomm MSM8994
>> +
>> +config MACH_HUAWEI
>> + bool "Huawei Angler (MSM8994)"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the Huawei Nexus 6P - Angler MSM8994.
>
> Remove both of these. We aren't adding more ARCHs or machs.
>
done
>
>> +
>> config ARCH_ROCKCHIP
>> bool "Rockchip Platforms"
>> select ARCH_HAS_RESET_CONTROLLER
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index bde90fb..d199f8b 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -9,6 +9,7 @@ dts-dirs += cavium
>> dts-dirs += exynos
>> dts-dirs += freescale
>> dts-dirs += hisilicon
>> +dts-dirs += huawei
>> dts-dirs += marvell
>> dts-dirs += mediatek
>> dts-dirs += nvidia
>> diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
>> new file mode 100644
>> index 0000000..4b31ff4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/huawei/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
>> +
>> +always := $(dtb-y)
>> +subdir-y := $(dts-dirs)
>> +clean-files := *.dtb
>> diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
>> new file mode 100644
>> index 0000000..07a71d6
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
>> @@ -0,0 +1,41 @@
>> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
>> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "../qcom/msm8994-v2.0.dtsi"
>> +
>> +/ {
>> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
>> + compatible = "qcom,msm8994";
>> + qcom,board-id= <8026 0>;
>> +};
>> +
>> +/ {
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> + };
>> +
>> + soc {
>> + serial@f991e000 {
>> + status = "okay";
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&blsp1_uart2_default>;
>> + pinctrl-1 = <&blsp1_uart2_sleep>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
>> new file mode 100644
>> index 0000000..0e4eea0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
>> @@ -0,0 +1,38 @@
>> +/*
>> + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +&msmgpio {
>> + blsp1_uart2_default: blsp1_uart2_default {
>> + pinmux {
>> + function = "blsp_uart2";
>> + pins = "gpio4", "gpio5";
>> + };
>> + pinconf {
>> + pins = "gpio4", "gpio5";
>> + drive-strength = <16>;
>> + bias-disable;
>> + };
>> + };
>> +
>> + blsp1_uart2_sleep: blsp1_uart2_sleep {
>> + pinmux {
>> + function = "gpio";
>> + pins = "gpio4", "gpio5";
>> + };
>> + pinconf {
>> + pins = "gpio4", "gpio5";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
>> new file mode 100644
>> index 0000000..8fc4c41f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
>> @@ -0,0 +1,31 @@
>> +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/*
>> + * As a general rule, only version-specific property overrides should be placed
>> + * inside this file. Device definitions should be placed inside the msm8994.dtsi
>> + * file.
>> + */
>> +
>> +#include "msm8994.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
>> + compatible = "qcom,msm8994";
>> + qcom,msm-id = <207 0x20000>;
>
> Drop the msm-id
>
Dealt with over IRC.
>> +
>> +};
>> +
>> +/* Clock driver overrides */
>> +&clock_gcc {
>> + compatible = "qcom,gcc-8994v2";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
>> new file mode 100644
>> index 0000000..c95cb73
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
>> @@ -0,0 +1,237 @@
>> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/memreserve/ 0x00000000 0x00001000;
>> +/memreserve/ 0xac1c0000 0x00001000;
>
> So the 0x00000000 is totally bogus. And the 0xac1c0000 needs to move to a
> reserved area lower in the dts.
>
I am going to leave this in until we get a chance to test the various
permutations etc... ideally we will be able to remove both completely.
This is explicitly mentioned in the leadin for v2.
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8994";
>> + compatible = "qcom,msm8994";
>> + qcom,msm-id = <207 0x0>;
>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>
> kill the ids
>
done
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&CPU0>;
>> + };
>> + };
>> + };
>> +
>> + CPU0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + reg = <0x0>;
>> + next-level-cache = <&L2_0>;
>> + // The currents(uA) correspond to the frequencies in the
>> + // frequency table.
>> + current = < 24140 //384000 kHZ
>> + 27200 //460800 kHZ
>> + 32300 //600000 kHZ
>> + 36940 //672000 kHz
>> + 41570 //768000 kHZ
>> + 49870 //864000 kHZ
>> + 57840 //960000 kHZ
>> + 79800 //1248000 kHZ
>> + 88810 //1344000 kHZ
>> + 102400 //1478400 kHZ
>> + 110900>; //1555200 kHZ
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + };
>> + };
>> + };
>> +
>> + soc: soc { };
>> +
>> + memory {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the reg */
>> + reg = <0 0 0 0>;
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>
> Move that reserve down here and make it no-map.
>
See comment above on reserved memory.
<....snip>
-jeremy
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
@ 2016-10-01 0:36 ` Jeremy McNicoll
0 siblings, 0 replies; 22+ messages in thread
From: Jeremy McNicoll @ 2016-10-01 0:36 UTC (permalink / raw)
To: linux-arm-kernel
On 2016-09-20 6:12 PM, Andy Gross wrote:
> On Thu, Jul 07, 2016 at 05:41:06PM -0700, Jeremy McNicoll wrote:
>> From: Bastian K?cher <mail@kchr.de>
>>
>> Initial device tree support for Qualcomm MSM8994 SoC and
>> Huawei Angler / Google Nexus 6P support.
>>
>> The device tree and the angler_defconfig are based on the
>> device tree from the Google 3.10 kernel tree.
>>
>> The device can be booted into the initrd with only one CPU running.
>>
>> Signed-off-by: Bastian K?cher <mail@kchr.de>
>> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
>> ---
>> arch/arm64/Kconfig.platforms | 13 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/huawei/Makefile | 5 +
>> .../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
>
> There is nothing to warrant having huawei have their own directory unless they
> are making their own SOC.
>
done
>> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
>> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
>> arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
>> arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
>
> We don't need to add defconfigs. We just need to turn on the options in the
> main defconfig.
>
ok, removed
> Also, when you do have defconfigs, please separate those changes into a separate
> patch.
>
will do.
>> 8 files changed, 1032 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/huawei/Makefile
>> create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
>> create mode 100644 arch/arm64/configs/angler_defconfig
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 515e669..f253f60d 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -98,6 +98,19 @@ config MACH_LGE
>> help
>> This enables support for the LGE Nexus 5X - BullHead MSM8992.
>>
>> +config ARCH_MSM8994
>> + bool "Qualcomm MSM8994"
>> + depends on ARCH_QCOM
>> + select ARCH_REQUIRE_GPIOLIB
>> + help
>> + This enables support for the Qualcomm MSM8994
>> +
>> +config MACH_HUAWEI
>> + bool "Huawei Angler (MSM8994)"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the Huawei Nexus 6P - Angler MSM8994.
>
> Remove both of these. We aren't adding more ARCHs or machs.
>
done
>
>> +
>> config ARCH_ROCKCHIP
>> bool "Rockchip Platforms"
>> select ARCH_HAS_RESET_CONTROLLER
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index bde90fb..d199f8b 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -9,6 +9,7 @@ dts-dirs += cavium
>> dts-dirs += exynos
>> dts-dirs += freescale
>> dts-dirs += hisilicon
>> +dts-dirs += huawei
>> dts-dirs += marvell
>> dts-dirs += mediatek
>> dts-dirs += nvidia
>> diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
>> new file mode 100644
>> index 0000000..4b31ff4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/huawei/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
>> +
>> +always := $(dtb-y)
>> +subdir-y := $(dts-dirs)
>> +clean-files := *.dtb
>> diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
>> new file mode 100644
>> index 0000000..07a71d6
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
>> @@ -0,0 +1,41 @@
>> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
>> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "../qcom/msm8994-v2.0.dtsi"
>> +
>> +/ {
>> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
>> + compatible = "qcom,msm8994";
>> + qcom,board-id= <8026 0>;
>> +};
>> +
>> +/ {
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> + };
>> +
>> + soc {
>> + serial at f991e000 {
>> + status = "okay";
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&blsp1_uart2_default>;
>> + pinctrl-1 = <&blsp1_uart2_sleep>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
>> new file mode 100644
>> index 0000000..0e4eea0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
>> @@ -0,0 +1,38 @@
>> +/*
>> + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +&msmgpio {
>> + blsp1_uart2_default: blsp1_uart2_default {
>> + pinmux {
>> + function = "blsp_uart2";
>> + pins = "gpio4", "gpio5";
>> + };
>> + pinconf {
>> + pins = "gpio4", "gpio5";
>> + drive-strength = <16>;
>> + bias-disable;
>> + };
>> + };
>> +
>> + blsp1_uart2_sleep: blsp1_uart2_sleep {
>> + pinmux {
>> + function = "gpio";
>> + pins = "gpio4", "gpio5";
>> + };
>> + pinconf {
>> + pins = "gpio4", "gpio5";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
>> new file mode 100644
>> index 0000000..8fc4c41f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
>> @@ -0,0 +1,31 @@
>> +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/*
>> + * As a general rule, only version-specific property overrides should be placed
>> + * inside this file. Device definitions should be placed inside the msm8994.dtsi
>> + * file.
>> + */
>> +
>> +#include "msm8994.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
>> + compatible = "qcom,msm8994";
>> + qcom,msm-id = <207 0x20000>;
>
> Drop the msm-id
>
Dealt with over IRC.
>> +
>> +};
>> +
>> +/* Clock driver overrides */
>> +&clock_gcc {
>> + compatible = "qcom,gcc-8994v2";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
>> new file mode 100644
>> index 0000000..c95cb73
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
>> @@ -0,0 +1,237 @@
>> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/memreserve/ 0x00000000 0x00001000;
>> +/memreserve/ 0xac1c0000 0x00001000;
>
> So the 0x00000000 is totally bogus. And the 0xac1c0000 needs to move to a
> reserved area lower in the dts.
>
I am going to leave this in until we get a chance to test the various
permutations etc... ideally we will be able to remove both completely.
This is explicitly mentioned in the leadin for v2.
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8994";
>> + compatible = "qcom,msm8994";
>> + qcom,msm-id = <207 0x0>;
>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>
> kill the ids
>
done
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&CPU0>;
>> + };
>> + };
>> + };
>> +
>> + CPU0: cpu at 0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + reg = <0x0>;
>> + next-level-cache = <&L2_0>;
>> + // The currents(uA) correspond to the frequencies in the
>> + // frequency table.
>> + current = < 24140 //384000 kHZ
>> + 27200 //460800 kHZ
>> + 32300 //600000 kHZ
>> + 36940 //672000 kHz
>> + 41570 //768000 kHZ
>> + 49870 //864000 kHZ
>> + 57840 //960000 kHZ
>> + 79800 //1248000 kHZ
>> + 88810 //1344000 kHZ
>> + 102400 //1478400 kHZ
>> + 110900>; //1555200 kHZ
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + };
>> + };
>> + };
>> +
>> + soc: soc { };
>> +
>> + memory {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the reg */
>> + reg = <0 0 0 0>;
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>
> Move that reserve down here and make it no-map.
>
See comment above on reserved memory.
<....snip>
-jeremy
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2016-10-01 0:36 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-08 0:41 [RFC] msm8992/msm8994: Google Nexus 5X/6P initial board support Jeremy McNicoll
2016-07-08 0:41 ` Jeremy McNicoll
2016-07-08 0:41 ` [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support Jeremy McNicoll
2016-07-08 17:41 ` Andy Gross
2016-07-08 17:41 ` Andy Gross
2016-09-21 0:42 ` Jeremy McNicoll
2016-09-21 0:42 ` Jeremy McNicoll
2016-09-22 18:39 ` Stephen Boyd
2016-09-22 18:39 ` Stephen Boyd
2016-09-23 23:27 ` Jeremy McNicoll
2016-09-23 23:27 ` Jeremy McNicoll
2016-07-08 0:41 ` [RFC 2/4] msm8994 clocks: global clock support Global clock support for the msm8994 SOC Jeremy McNicoll
2016-07-12 2:30 ` Jeremy McNicoll
2016-07-12 2:30 ` Jeremy McNicoll
2016-07-08 0:41 ` [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support Jeremy McNicoll
2016-07-08 17:35 ` Andy Gross
2016-07-08 17:35 ` Andy Gross
2016-09-21 1:12 ` Andy Gross
2016-09-21 1:12 ` Andy Gross
2016-10-01 0:36 ` Jeremy McNicoll
2016-10-01 0:36 ` Jeremy McNicoll
2016-07-08 0:41 ` [RFC 4/4] arm64: dts: msm8992 default serial config Jeremy McNicoll
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