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From: Chris Zhong <zyw@rock-chips.com>
To: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de,
	yzq@rock-chips.com
Cc: linux-rockchip@lists.infradead.org,
	Chris Zhong <zyw@rock-chips.com>,
	Mark Yao <mark.yao@rock-chips.com>,
	David Airlie <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 6/7] drm/rockchip: dw-mipi: fix phy clk lane stop state timeout
Date: Fri,  8 Jul 2016 17:05:00 +0800	[thread overview]
Message-ID: <1467968701-15620-7-git-send-email-zyw@rock-chips.com> (raw)
In-Reply-To: <1467968701-15620-1-git-send-email-zyw@rock-chips.com>

Before phy init, the detection of phy state should be controlled
manually. After that, we can switch the detection to hardward,
it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end
of phy init.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 72d7f48..8401185 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -477,6 +477,8 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 		dev_err(dsi->dev,
 			"failed to wait for phy clk lane stop state\n");
 
+	dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+
 phy_init_end:
 	if (!IS_ERR(dsi->phy_cfg_clk))
 		clk_disable_unprepare(dsi->phy_cfg_clk);
@@ -714,7 +716,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 		  | PHY_RSTZ | PHY_SHUTDOWNZ);
 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 		  TX_ESC_CLK_DIVIDSION(7));
-	dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 }
 
 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
-- 
2.6.3

WARNING: multiple messages have this Message-ID (diff)
From: Chris Zhong <zyw@rock-chips.com>
To: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de,
	yzq@rock-chips.com
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-rockchip@lists.infradead.org,
	Chris Zhong <zyw@rock-chips.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/7] drm/rockchip: dw-mipi: fix phy clk lane stop state timeout
Date: Fri,  8 Jul 2016 17:05:00 +0800	[thread overview]
Message-ID: <1467968701-15620-7-git-send-email-zyw@rock-chips.com> (raw)
In-Reply-To: <1467968701-15620-1-git-send-email-zyw@rock-chips.com>

Before phy init, the detection of phy state should be controlled
manually. After that, we can switch the detection to hardward,
it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end
of phy init.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 72d7f48..8401185 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -477,6 +477,8 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 		dev_err(dsi->dev,
 			"failed to wait for phy clk lane stop state\n");
 
+	dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+
 phy_init_end:
 	if (!IS_ERR(dsi->phy_cfg_clk))
 		clk_disable_unprepare(dsi->phy_cfg_clk);
@@ -714,7 +716,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 		  | PHY_RSTZ | PHY_SHUTDOWNZ);
 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 		  TX_ESC_CLK_DIVIDSION(7));
-	dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 }
 
 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
-- 
2.6.3

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WARNING: multiple messages have this Message-ID (diff)
From: zyw@rock-chips.com (Chris Zhong)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/7] drm/rockchip: dw-mipi: fix phy clk lane stop state timeout
Date: Fri,  8 Jul 2016 17:05:00 +0800	[thread overview]
Message-ID: <1467968701-15620-7-git-send-email-zyw@rock-chips.com> (raw)
In-Reply-To: <1467968701-15620-1-git-send-email-zyw@rock-chips.com>

Before phy init, the detection of phy state should be controlled
manually. After that, we can switch the detection to hardward,
it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end
of phy init.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 72d7f48..8401185 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -477,6 +477,8 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 		dev_err(dsi->dev,
 			"failed to wait for phy clk lane stop state\n");
 
+	dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+
 phy_init_end:
 	if (!IS_ERR(dsi->phy_cfg_clk))
 		clk_disable_unprepare(dsi->phy_cfg_clk);
@@ -714,7 +716,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 		  | PHY_RSTZ | PHY_SHUTDOWNZ);
 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 		  TX_ESC_CLK_DIVIDSION(7));
-	dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 }
 
 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
-- 
2.6.3

  parent reply	other threads:[~2016-07-08  9:06 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-08  9:04 [PATCH 0/7] Rockchip dw-mipi-dsi driver Chris Zhong
2016-07-08  9:04 ` Chris Zhong
2016-07-08  9:04 ` Chris Zhong
2016-07-08  9:04 ` [PATCH 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-13 13:49   ` Rob Herring
2016-07-13 13:49     ` Rob Herring
2016-07-13 13:49     ` Rob Herring
2016-07-08  9:04 ` [PATCH 2/7] DRM: mipi: support rk3399 mipi dsi Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08  9:04 ` [PATCH 3/7] dt-bindings: add power domain node for dw-mipi-rockchip Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-13 13:50   ` Rob Herring
2016-07-13 13:50     ` Rob Herring
2016-07-13 13:50     ` Rob Herring
2016-07-08  9:04 ` [PATCH 4/7] drm/rockchip: dw-mipi: add dw-mipi power domain support Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08  9:04 ` [PATCH 5/7] drm/rockchip: dw-mipi: support HPD poll Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08  9:04   ` Chris Zhong
2016-07-08 13:52   ` John Keeping
2016-07-08 13:52     ` John Keeping
2016-07-08 13:52     ` John Keeping
2016-07-11  0:46     ` Mark yao
2016-07-11  0:46       ` Mark yao
2016-07-11  0:46       ` Mark yao
2016-07-11  9:20       ` John Keeping
2016-07-11  9:20         ` John Keeping
2016-07-11  9:20         ` John Keeping
2016-07-08  9:05 ` Chris Zhong [this message]
2016-07-08  9:05   ` [PATCH 6/7] drm/rockchip: dw-mipi: fix phy clk lane stop state timeout Chris Zhong
2016-07-08  9:05   ` Chris Zhong
2016-07-08  9:05 ` [PATCH 7/7] drm/rockchip: dw-mipi: fix insufficient bandwidth of some panel Chris Zhong
2016-07-08  9:05   ` Chris Zhong
2016-07-08  9:05   ` Chris Zhong

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