[Qemu-devel] [PATCH 3/7] hw/mips: fix PCI bus initialization

From: Marcel Apfelbaum <marcel@redhat.com>
To: qemu-devel@nongnu.org
Cc: marcel@redhat.com, qemu-ppc@nongnu.org, qemu-arm@nongnu.org,
	rth@twiddle.net, aurelien@aurel32.net, leon.alrae@imgtec.com,
	agraf@suse.de, peter.maydell@linaro.org,
	mark.cave-ayland@ilande.co.uk, mst@redhat.com, thuth@redhat.com
Subject: [Qemu-devel]  [PATCH 3/7] hw/mips: fix PCI bus initialization
Date: Thu, 14 Jul 2016 16:43:42 +0300	[thread overview]
Message-ID: <1468503826-10617-4-git-send-email-marcel@redhat.com> (raw)
In-Reply-To: <1468503826-10617-1-git-send-email-marcel@redhat.com>

Delay the host-bridge 'realization' until the
PCI root bus is attached.

Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
 hw/mips/gt64xxx_pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 3f4523d..4811843 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1167,7 +1167,6 @@ PCIBus *gt64120_register(qemu_irq *pic)
     DeviceState *dev;
 
     dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
-    qdev_init_nofail(dev);
     d = GT64120_PCI_HOST_BRIDGE(dev);
     phb = PCI_HOST_BRIDGE(dev);
     memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);
@@ -1178,6 +1177,7 @@ PCIBus *gt64120_register(qemu_irq *pic)
                                 &d->pci0_mem,
                                 get_system_io(),
                                 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
+    qdev_init_nofail(dev);
     memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
 
     pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
-- 
2.4.3
