From: Sinan Kaya <okaya@codeaurora.org> To: dmaengine@vger.kernel.org, timur@codeaurora.org, devicetree@vger.kernel.org, cov@codeaurora.org, vinod.koul@intel.com, jcm@redhat.com Cc: eric.auger@linaro.org, agross@codeaurora.org, arnd@arndb.de, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya <okaya@codeaurora.org>, Dan Williams <dan.j.williams@intel.com>, Andy Shevchenko <andy.shevchenko@gmail.com>, linux-kernel@vger.kernel.org Subject: [PATCH 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Date: Mon, 18 Jul 2016 14:39:32 -0400 [thread overview] Message-ID: <1468867177-15007-6-git-send-email-okaya@codeaurora.org> (raw) In-Reply-To: <1468867177-15007-1-git-send-email-okaya@codeaurora.org> Getting ready for the MSI interrupts. The pending_tre_count is used in the interrupt handler to make sure all outstanding requests are serviced. Making it atomic so that it can be updated from multiple contexts. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> --- drivers/dma/qcom/hidma.h | 2 +- drivers/dma/qcom/hidma_dbg.c | 3 ++- drivers/dma/qcom/hidma_ll.c | 13 ++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/dma/qcom/hidma.h b/drivers/dma/qcom/hidma.h index db413a5..158bf1f 100644 --- a/drivers/dma/qcom/hidma.h +++ b/drivers/dma/qcom/hidma.h @@ -58,7 +58,7 @@ struct hidma_lldev { void __iomem *evca; /* Event Channel address */ struct hidma_tre **pending_tre_list; /* Pointers to pending TREs */ - s32 pending_tre_count; /* Number of TREs pending */ + atomic_t pending_tre_count; /* Number of TREs pending */ void *tre_ring; /* TRE ring */ dma_addr_t tre_dma; /* TRE ring to be shared with HW */ diff --git a/drivers/dma/qcom/hidma_dbg.c b/drivers/dma/qcom/hidma_dbg.c index fa827e5..87db285 100644 --- a/drivers/dma/qcom/hidma_dbg.c +++ b/drivers/dma/qcom/hidma_dbg.c @@ -74,7 +74,8 @@ static void hidma_ll_devstats(struct seq_file *s, void *llhndl) seq_printf(s, "tre_ring_handle=%pap\n", &lldev->tre_dma); seq_printf(s, "tre_ring_size = 0x%x\n", lldev->tre_ring_size); seq_printf(s, "tre_processed_off = 0x%x\n", lldev->tre_processed_off); - seq_printf(s, "pending_tre_count=%d\n", lldev->pending_tre_count); + seq_printf(s, "pending_tre_count=%d\n", + atomic_read(&lldev->pending_tre_count)); seq_printf(s, "evca=%p\n", lldev->evca); seq_printf(s, "evre_ring=%p\n", lldev->evre_ring); seq_printf(s, "evre_ring_handle=%pap\n", &lldev->evre_dma); diff --git a/drivers/dma/qcom/hidma_ll.c b/drivers/dma/qcom/hidma_ll.c index f392900..f564c92 100644 --- a/drivers/dma/qcom/hidma_ll.c +++ b/drivers/dma/qcom/hidma_ll.c @@ -218,10 +218,9 @@ static int hidma_post_completed(struct hidma_lldev *lldev, int tre_iterator, * Keep track of pending TREs that SW is expecting to receive * from HW. We got one now. Decrement our counter. */ - lldev->pending_tre_count--; - if (lldev->pending_tre_count < 0) { + if (atomic_dec_return(&lldev->pending_tre_count) < 0) { dev_warn(lldev->dev, "tre count mismatch on completion"); - lldev->pending_tre_count = 0; + atomic_set(&lldev->pending_tre_count, 0); } spin_unlock_irqrestore(&lldev->lock, flags); @@ -321,7 +320,7 @@ void hidma_cleanup_pending_tre(struct hidma_lldev *lldev, u8 err_info, u32 tre_read_off; tre_iterator = lldev->tre_processed_off; - while (lldev->pending_tre_count) { + while (atomic_read(&lldev->pending_tre_count)) { if (hidma_post_completed(lldev, tre_iterator, err_info, err_code)) break; @@ -564,7 +563,7 @@ void hidma_ll_queue_request(struct hidma_lldev *lldev, u32 tre_ch) tre->err_code = 0; tre->err_info = 0; tre->queued = 1; - lldev->pending_tre_count++; + atomic_inc(&lldev->pending_tre_count); lldev->tre_write_offset = (lldev->tre_write_offset + HIDMA_TRE_SIZE) % lldev->tre_ring_size; spin_unlock_irqrestore(&lldev->lock, flags); @@ -670,7 +669,7 @@ int hidma_ll_setup(struct hidma_lldev *lldev) u32 val; u32 nr_tres = lldev->nr_tres; - lldev->pending_tre_count = 0; + atomic_set(&lldev->pending_tre_count, 0); lldev->tre_processed_off = 0; lldev->evre_processed_off = 0; lldev->tre_write_offset = 0; @@ -833,7 +832,7 @@ int hidma_ll_uninit(struct hidma_lldev *lldev) tasklet_kill(&lldev->task); memset(lldev->trepool, 0, required_bytes); lldev->trepool = NULL; - lldev->pending_tre_count = 0; + atomic_set(&lldev->pending_tre_count, 0); lldev->tre_write_offset = 0; rc = hidma_ll_reset(lldev); -- 1.8.2.1
WARNING: multiple messages have this Message-ID (diff)
From: okaya@codeaurora.org (Sinan Kaya) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Date: Mon, 18 Jul 2016 14:39:32 -0400 [thread overview] Message-ID: <1468867177-15007-6-git-send-email-okaya@codeaurora.org> (raw) In-Reply-To: <1468867177-15007-1-git-send-email-okaya@codeaurora.org> Getting ready for the MSI interrupts. The pending_tre_count is used in the interrupt handler to make sure all outstanding requests are serviced. Making it atomic so that it can be updated from multiple contexts. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> --- drivers/dma/qcom/hidma.h | 2 +- drivers/dma/qcom/hidma_dbg.c | 3 ++- drivers/dma/qcom/hidma_ll.c | 13 ++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/dma/qcom/hidma.h b/drivers/dma/qcom/hidma.h index db413a5..158bf1f 100644 --- a/drivers/dma/qcom/hidma.h +++ b/drivers/dma/qcom/hidma.h @@ -58,7 +58,7 @@ struct hidma_lldev { void __iomem *evca; /* Event Channel address */ struct hidma_tre **pending_tre_list; /* Pointers to pending TREs */ - s32 pending_tre_count; /* Number of TREs pending */ + atomic_t pending_tre_count; /* Number of TREs pending */ void *tre_ring; /* TRE ring */ dma_addr_t tre_dma; /* TRE ring to be shared with HW */ diff --git a/drivers/dma/qcom/hidma_dbg.c b/drivers/dma/qcom/hidma_dbg.c index fa827e5..87db285 100644 --- a/drivers/dma/qcom/hidma_dbg.c +++ b/drivers/dma/qcom/hidma_dbg.c @@ -74,7 +74,8 @@ static void hidma_ll_devstats(struct seq_file *s, void *llhndl) seq_printf(s, "tre_ring_handle=%pap\n", &lldev->tre_dma); seq_printf(s, "tre_ring_size = 0x%x\n", lldev->tre_ring_size); seq_printf(s, "tre_processed_off = 0x%x\n", lldev->tre_processed_off); - seq_printf(s, "pending_tre_count=%d\n", lldev->pending_tre_count); + seq_printf(s, "pending_tre_count=%d\n", + atomic_read(&lldev->pending_tre_count)); seq_printf(s, "evca=%p\n", lldev->evca); seq_printf(s, "evre_ring=%p\n", lldev->evre_ring); seq_printf(s, "evre_ring_handle=%pap\n", &lldev->evre_dma); diff --git a/drivers/dma/qcom/hidma_ll.c b/drivers/dma/qcom/hidma_ll.c index f392900..f564c92 100644 --- a/drivers/dma/qcom/hidma_ll.c +++ b/drivers/dma/qcom/hidma_ll.c @@ -218,10 +218,9 @@ static int hidma_post_completed(struct hidma_lldev *lldev, int tre_iterator, * Keep track of pending TREs that SW is expecting to receive * from HW. We got one now. Decrement our counter. */ - lldev->pending_tre_count--; - if (lldev->pending_tre_count < 0) { + if (atomic_dec_return(&lldev->pending_tre_count) < 0) { dev_warn(lldev->dev, "tre count mismatch on completion"); - lldev->pending_tre_count = 0; + atomic_set(&lldev->pending_tre_count, 0); } spin_unlock_irqrestore(&lldev->lock, flags); @@ -321,7 +320,7 @@ void hidma_cleanup_pending_tre(struct hidma_lldev *lldev, u8 err_info, u32 tre_read_off; tre_iterator = lldev->tre_processed_off; - while (lldev->pending_tre_count) { + while (atomic_read(&lldev->pending_tre_count)) { if (hidma_post_completed(lldev, tre_iterator, err_info, err_code)) break; @@ -564,7 +563,7 @@ void hidma_ll_queue_request(struct hidma_lldev *lldev, u32 tre_ch) tre->err_code = 0; tre->err_info = 0; tre->queued = 1; - lldev->pending_tre_count++; + atomic_inc(&lldev->pending_tre_count); lldev->tre_write_offset = (lldev->tre_write_offset + HIDMA_TRE_SIZE) % lldev->tre_ring_size; spin_unlock_irqrestore(&lldev->lock, flags); @@ -670,7 +669,7 @@ int hidma_ll_setup(struct hidma_lldev *lldev) u32 val; u32 nr_tres = lldev->nr_tres; - lldev->pending_tre_count = 0; + atomic_set(&lldev->pending_tre_count, 0); lldev->tre_processed_off = 0; lldev->evre_processed_off = 0; lldev->tre_write_offset = 0; @@ -833,7 +832,7 @@ int hidma_ll_uninit(struct hidma_lldev *lldev) tasklet_kill(&lldev->task); memset(lldev->trepool, 0, required_bytes); lldev->trepool = NULL; - lldev->pending_tre_count = 0; + atomic_set(&lldev->pending_tre_count, 0); lldev->tre_write_offset = 0; rc = hidma_ll_reset(lldev); -- 1.8.2.1
next prev parent reply other threads:[~2016-07-18 18:39 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-07-18 18:39 [PATCH 00/10] dmaengine: qcom_hidma: add MSI interrupt support Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-18 18:39 ` [PATCH 02/10] Documentation: DT: qcom_hidma: correct spelling mistakes Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-20 1:16 ` Rob Herring 2016-07-20 1:16 ` Rob Herring 2016-07-18 18:39 ` [PATCH 03/10] of: irq: make of_msi_configure accessible from modules Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya [not found] ` <1468867177-15007-4-git-send-email-okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-07-18 21:24 ` Rob Herring 2016-07-18 21:24 ` Rob Herring 2016-07-18 21:24 ` Rob Herring 2016-07-19 21:40 ` Sinan Kaya 2016-07-19 21:40 ` Sinan Kaya 2016-07-19 21:40 ` Sinan Kaya 2016-07-18 18:39 ` [PATCH 04/10] dmaending: qcom_hidma: configure DMA and MSI for OF Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-24 6:33 ` Vinod Koul 2016-07-24 6:33 ` Vinod Koul 2016-07-24 6:33 ` Vinod Koul 2016-07-24 14:40 ` Sinan Kaya 2016-07-24 14:40 ` Sinan Kaya 2016-07-24 14:40 ` Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya [this message] 2016-07-18 18:39 ` [PATCH 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Sinan Kaya 2016-07-18 18:39 ` [PATCH 06/10] dmaengine: qcom_hidma: make error and success path common Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-18 18:39 ` [PATCH 07/10] dmaengine: qcom_hidma: eliminate processed variables Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-18 18:39 ` [PATCH 08/10] dmaengine: qcom_hidma: bring out interrupt cause Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-18 18:39 ` [PATCH 09/10] dmaengine: qcom_hidma: add a common API to setup the interrupt Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya [not found] ` <1468867177-15007-1-git-send-email-okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-07-18 18:39 ` [PATCH 01/10] Documentation: DT: qcom_hidma: update binding for MSI Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-19 10:37 ` Mark Rutland 2016-07-19 10:37 ` Mark Rutland 2016-07-19 12:42 ` Sinan Kaya 2016-07-19 12:42 ` Sinan Kaya 2016-07-18 18:39 ` [PATCH 10/10] dmaengine: qcom_hidma: add MSI support for interrupts Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-18 18:39 ` Sinan Kaya 2016-07-24 6:42 ` Vinod Koul 2016-07-24 6:42 ` Vinod Koul 2016-07-24 6:42 ` Vinod Koul 2016-07-24 14:38 ` Sinan Kaya 2016-07-24 14:38 ` Sinan Kaya 2016-07-24 14:38 ` Sinan Kaya 2016-08-04 12:46 ` Vinod Koul 2016-08-04 12:46 ` Vinod Koul 2016-08-04 12:46 ` Vinod Koul 2016-08-04 13:59 ` Sinan Kaya 2016-08-04 13:59 ` Sinan Kaya 2016-08-04 13:59 ` Sinan Kaya [not found] ` <497ddb6c-0233-657f-72c6-b844b798ff11-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-08-08 8:14 ` Vinod Koul 2016-08-08 8:14 ` Vinod Koul 2016-08-08 8:14 ` Vinod Koul 2016-08-08 11:48 ` okaya 2016-08-08 11:48 ` okaya at codeaurora.org
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