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From: Andrew Jeffery <andrew@aj.id.au>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	devicetree@vger.kernel.org, Andrew Jeffery <andrew@aj.id.au>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Russell King <linux@armlinux.org.uk>,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
	linux-arm-kernel@lists.infradead.org, Jeremy Kerr <jk@ozlabs.org>
Subject: [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers
Date: Wed, 20 Jul 2016 15:28:22 +0930	[thread overview]
Message-ID: <1468994313-13538-2-git-send-email-andrew@aj.id.au> (raw)
In-Reply-To: <1468994313-13538-1-git-send-email-andrew@aj.id.au>

Outline expectations on the pin controller's relationship with the
System Control Unit (SCU) IP through syscon, and document the compatible
strings for 4th and 5th generation Aspeed SoC pin controllers.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 45 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
new file mode 100644
index 000000000000..5aac6a0a2e89
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -0,0 +1,45 @@
+Aspeed Pin Controllers
+----------------------
+
+The Aspeed SoCs vary in functionality inside a generation but have a common mux
+device register layout.
+
+Required properties:
+- compatible: should be one of the following:
+	"aspeed,g4-pinctrl";
+	"aspeed,g5-pinctrl"
+
+The pin controller node should be a child of a syscon node with the required
+property:
+- compatible: "syscon", "simple-mfd"
+
+Refer to the the bindings described in
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Subnode format:
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The required properties of child nodes are (as defined in pinctrl-bindings):
+- function
+- groups
+
+Each function has only one associated pin group. Each group is named by its
+function.
+
+Examples:
+
+syscon: scu@1e6e2000 {
+	compatible = "syscon", "simple-mfd";
+	reg = <0x1e6e2000 0x1a8>;
+
+	pinctrl: pinctrl@1e6e2000 {
+		compatible = "aspeed,g4-pinctrl";
+
+		pinctrl_i2c3_default: i2c3_default {
+			function = "I2C3";
+			groups = "I2C3";
+		};
+	};
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 1209323b7e43..b5f2d3576d3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1003,6 +1003,7 @@ S:	Maintained
 F:	arch/arm/mach-aspeed/
 F:	arch/arm/boot/dts/aspeed-*
 F:	drivers/*/*aspeed*
+F:	Documentation/devicetree/bindings/*/*aspeed*
 
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M:	Nicolas Ferre <nicolas.ferre@atmel.com>
-- 
2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jeffery <andrew@aj.id.au>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>,
	Joel Stanley <joel@jms.id.au>,
	Mark Rutland <mark.rutland@arm.com>,
	Rob Herring <robh+dt@kernel.org>,
	Russell King <linux@armlinux.org.uk>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Jeremy Kerr <jk@ozlabs.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
	Andrew Jeffery <andrew@aj.id.au>
Subject: [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers
Date: Wed, 20 Jul 2016 15:28:22 +0930	[thread overview]
Message-ID: <1468994313-13538-2-git-send-email-andrew@aj.id.au> (raw)
In-Reply-To: <1468994313-13538-1-git-send-email-andrew@aj.id.au>

Outline expectations on the pin controller's relationship with the
System Control Unit (SCU) IP through syscon, and document the compatible
strings for 4th and 5th generation Aspeed SoC pin controllers.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 45 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
new file mode 100644
index 000000000000..5aac6a0a2e89
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -0,0 +1,45 @@
+Aspeed Pin Controllers
+----------------------
+
+The Aspeed SoCs vary in functionality inside a generation but have a common mux
+device register layout.
+
+Required properties:
+- compatible: should be one of the following:
+	"aspeed,g4-pinctrl";
+	"aspeed,g5-pinctrl"
+
+The pin controller node should be a child of a syscon node with the required
+property:
+- compatible: "syscon", "simple-mfd"
+
+Refer to the the bindings described in
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Subnode format:
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The required properties of child nodes are (as defined in pinctrl-bindings):
+- function
+- groups
+
+Each function has only one associated pin group. Each group is named by its
+function.
+
+Examples:
+
+syscon: scu@1e6e2000 {
+	compatible = "syscon", "simple-mfd";
+	reg = <0x1e6e2000 0x1a8>;
+
+	pinctrl: pinctrl@1e6e2000 {
+		compatible = "aspeed,g4-pinctrl";
+
+		pinctrl_i2c3_default: i2c3_default {
+			function = "I2C3";
+			groups = "I2C3";
+		};
+	};
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 1209323b7e43..b5f2d3576d3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1003,6 +1003,7 @@ S:	Maintained
 F:	arch/arm/mach-aspeed/
 F:	arch/arm/boot/dts/aspeed-*
 F:	drivers/*/*aspeed*
+F:	Documentation/devicetree/bindings/*/*aspeed*
 
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M:	Nicolas Ferre <nicolas.ferre@atmel.com>
-- 
2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: andrew@aj.id.au (Andrew Jeffery)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers
Date: Wed, 20 Jul 2016 15:28:22 +0930	[thread overview]
Message-ID: <1468994313-13538-2-git-send-email-andrew@aj.id.au> (raw)
In-Reply-To: <1468994313-13538-1-git-send-email-andrew@aj.id.au>

Outline expectations on the pin controller's relationship with the
System Control Unit (SCU) IP through syscon, and document the compatible
strings for 4th and 5th generation Aspeed SoC pin controllers.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 45 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
new file mode 100644
index 000000000000..5aac6a0a2e89
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -0,0 +1,45 @@
+Aspeed Pin Controllers
+----------------------
+
+The Aspeed SoCs vary in functionality inside a generation but have a common mux
+device register layout.
+
+Required properties:
+- compatible: should be one of the following:
+	"aspeed,g4-pinctrl";
+	"aspeed,g5-pinctrl"
+
+The pin controller node should be a child of a syscon node with the required
+property:
+- compatible: "syscon", "simple-mfd"
+
+Refer to the the bindings described in
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Subnode format:
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The required properties of child nodes are (as defined in pinctrl-bindings):
+- function
+- groups
+
+Each function has only one associated pin group. Each group is named by its
+function.
+
+Examples:
+
+syscon: scu at 1e6e2000 {
+	compatible = "syscon", "simple-mfd";
+	reg = <0x1e6e2000 0x1a8>;
+
+	pinctrl: pinctrl at 1e6e2000 {
+		compatible = "aspeed,g4-pinctrl";
+
+		pinctrl_i2c3_default: i2c3_default {
+			function = "I2C3";
+			groups = "I2C3";
+		};
+	};
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 1209323b7e43..b5f2d3576d3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1003,6 +1003,7 @@ S:	Maintained
 F:	arch/arm/mach-aspeed/
 F:	arch/arm/boot/dts/aspeed-*
 F:	drivers/*/*aspeed*
+F:	Documentation/devicetree/bindings/*/*aspeed*
 
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M:	Nicolas Ferre <nicolas.ferre@atmel.com>
-- 
2.7.4

  reply	other threads:[~2016-07-20  5:58 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-20  5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
2016-07-20  5:58 ` Andrew Jeffery
2016-07-20  5:58 ` Andrew Jeffery
2016-07-20  5:58 ` Andrew Jeffery [this message]
2016-07-20  5:58   ` [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20 19:05   ` Rob Herring
2016-07-20 19:05     ` Rob Herring
2016-07-20 23:13     ` Andrew Jeffery
2016-07-20 23:13       ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-22  6:29   ` Joel Stanley
2016-07-22  6:29     ` Joel Stanley
2016-08-11  8:41   ` Linus Walleij
2016-08-11  8:41     ` Linus Walleij
2016-08-11  8:41     ` Linus Walleij
2016-08-12  0:33     ` Andrew Jeffery
2016-08-12  0:33       ` Andrew Jeffery
2016-08-12  0:33       ` Andrew Jeffery
2016-08-12 13:18       ` Linus Walleij
2016-08-12 13:18         ` Linus Walleij
2016-08-12 13:18         ` Linus Walleij
2016-08-13  0:58         ` Benjamin Herrenschmidt
2016-08-13  0:58           ` Benjamin Herrenschmidt
2016-08-13  0:58           ` Benjamin Herrenschmidt
     [not found]           ` <1471049894.12231.41.camel-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
2016-08-15  0:36             ` Andrew Jeffery
2016-08-15  0:36               ` Andrew Jeffery
2016-08-15  0:36               ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 03/12] pinctrl: Add pinctrl-aspeed-g4 driver Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 04/12] pinctrl: Add pinctrl-aspeed-g5 driver Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
     [not found]   ` <1468994313-13538-6-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-07-20 19:06     ` Rob Herring
2016-07-20 19:06       ` Rob Herring
2016-07-20 19:06       ` Rob Herring
2016-07-20  5:58 ` [PATCH 06/12] gpio: Add Aspeed driver Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-21 20:12   ` Paul Gortmaker
2016-07-21 20:12     ` Paul Gortmaker
2016-07-21 20:12     ` Paul Gortmaker
2016-07-22  0:49     ` Andrew Jeffery
2016-07-22  0:49       ` Andrew Jeffery
2016-07-22  0:49       ` Andrew Jeffery
     [not found]   ` <1468994313-13538-7-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-08-11  9:20     ` Linus Walleij
2016-08-11  9:20       ` Linus Walleij
2016-08-11  9:20       ` Linus Walleij
     [not found]       ` <CACRpkdYvZdTa7dpSs5=vnK77wpRGFT2W3e3=AS3GJGY7CXdwRA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-08-12  0:54         ` Andrew Jeffery
2016-08-12  0:54           ` Andrew Jeffery
2016-08-12  0:54           ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20 19:09   ` Rob Herring
2016-07-20 19:09     ` Rob Herring
2016-07-21  1:04     ` Andrew Jeffery
2016-07-21  1:04       ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 08/12] aspeed-g4: Add syscon and pin controller nodes Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 09/12] palmetto: Request relevant mux functions in devicetree Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 10/12] aspeed-g4: Add gpio controller to devicetree Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 11/12] aspeed-g5: Add syscon and pin controller nodes Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58 ` [PATCH 12/12] aspeed-g5: Add gpio controller to devicetree Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery
2016-07-20  5:58   ` Andrew Jeffery

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