* Fix the vma leak
@ 2016-07-25 17:31 Chris Wilson
2016-07-25 17:31 ` [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Chris Wilson
` (56 more replies)
0 siblings, 57 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Long, long ago vma were found to exist after the parent ppgtt had ceased.
They still do. This series fixes the leak by introducing vma activity
tracking, with this a vma for one client does not stall another client
and we can track when each client's vm are idle independently.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
2016-07-25 17:31 Fix the vma leak Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-26 5:07 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 02/55] drm/i915: Prefer list_first_entry_or_null Chris Wilson
` (55 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Since intel_engine_enable_signaling() is now only called via
fence_enable_sw_signaling(), we can rely on it to provide serialisation
and run-once for us and so make ourselves slightly simpler.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-2-git-send-email-chris@chris-wilson.co.uk
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index d893ccdd62ac..90867446f1a5 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -480,19 +480,15 @@ void intel_engine_enable_signaling(struct drm_i915_gem_request *request)
struct rb_node *parent, **p;
bool first, wakeup;
- if (unlikely(READ_ONCE(request->signaling.wait.tsk)))
- return;
-
- spin_lock(&b->lock);
- if (unlikely(request->signaling.wait.tsk)) {
- wakeup = false;
- goto unlock;
- }
+ /* locked by fence_enable_sw_signaling() */
+ assert_spin_locked(&request->lock);
request->signaling.wait.tsk = b->signaler;
request->signaling.wait.seqno = request->fence.seqno;
i915_gem_request_get(request);
+ spin_lock(&b->lock);
+
/* First add ourselves into the list of waiters, but register our
* bottom-half as the signaller thread. As per usual, only the oldest
* waiter (not just signaller) is tasked as the bottom-half waking
@@ -525,7 +521,6 @@ void intel_engine_enable_signaling(struct drm_i915_gem_request *request)
if (first)
smp_store_mb(b->first_signal, request);
-unlock:
spin_unlock(&b->lock);
if (wakeup)
--
2.8.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 02/55] drm/i915: Prefer list_first_entry_or_null
2016-07-25 17:31 Fix the vma leak Chris Wilson
2016-07-25 17:31 ` [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 03/55] drm/i915: Only clear the client pointer when tearing down the file Chris Wilson
` (54 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
list_first_entry_or_null() can generate better code than using
if (!list_empty()) {ptr = list_first_entry()) ..., so put it to use.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-3-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +++++-------
drivers/gpu/drm/i915/i915_gem_request.c | 8 +++-----
drivers/gpu/drm/i915/i915_gem_shrinker.c | 9 +++++----
3 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 30da543e1bdf..38e7d992a20d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2736,13 +2736,11 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node,
if (node->color != color)
*start += 4096;
- if (!list_empty(&node->node_list)) {
- node = list_entry(node->node_list.next,
- struct drm_mm_node,
- node_list);
- if (node->allocated && node->color != color)
- *end -= 4096;
- }
+ node = list_first_entry_or_null(&node->node_list,
+ struct drm_mm_node,
+ node_list);
+ if (node && node->allocated && node->color != color)
+ *end -= 4096;
}
static int i915_gem_setup_global_gtt(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 60a3a343b3a8..49396b895a36 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -317,12 +317,10 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
return ret;
/* Move the oldest request to the slab-cache (if not in use!) */
- if (!list_empty(&engine->request_list)) {
- req = list_first_entry(&engine->request_list,
+ req = list_first_entry_or_null(&engine->request_list,
typeof(*req), list);
- if (i915_gem_request_completed(req))
- i915_gem_request_retire(req);
- }
+ if (req && i915_gem_request_completed(req))
+ i915_gem_request_retire(req);
req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
if (!req)
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index afaa2597e35e..5d4772c146b1 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -163,17 +163,18 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
*/
for (phase = phases; phase->list; phase++) {
struct list_head still_in_list;
+ struct drm_i915_gem_object *obj;
if ((flags & phase->bit) == 0)
continue;
INIT_LIST_HEAD(&still_in_list);
- while (count < target && !list_empty(phase->list)) {
- struct drm_i915_gem_object *obj;
+ while (count < target &&
+ (obj = list_first_entry_or_null(phase->list,
+ typeof(*obj),
+ global_list))) {
struct i915_vma *vma, *v;
- obj = list_first_entry(phase->list,
- typeof(*obj), global_list);
list_move_tail(&obj->global_list, &still_in_list);
if (flags & I915_SHRINK_PURGEABLE &&
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 03/55] drm/i915: Only clear the client pointer when tearing down the file
2016-07-25 17:31 Fix the vma leak Chris Wilson
2016-07-25 17:31 ` [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Chris Wilson
2016-07-25 17:31 ` [PATCH 02/55] drm/i915: Prefer list_first_entry_or_null Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 04/55] drm/i915: Only drop the batch-pool's object reference Chris Wilson
` (53 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Upon release of the file (i.e. the user calls close(fd)), we decouple
all objects from the client list so that we don't chase the dangling
file_priv. As we always inspect file_priv first, we only need to nullify
that pointer and can safely ignore the list_head.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-4-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c8436639b3ed..3730aecc1eae 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4745,21 +4745,15 @@ int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
void i915_gem_release(struct drm_device *dev, struct drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
+ struct drm_i915_gem_request *request;
/* Clean up our request list when the client is going away, so that
* later retire_requests won't dereference our soon-to-be-gone
* file_priv.
*/
spin_lock(&file_priv->mm.lock);
- while (!list_empty(&file_priv->mm.request_list)) {
- struct drm_i915_gem_request *request;
-
- request = list_first_entry(&file_priv->mm.request_list,
- struct drm_i915_gem_request,
- client_list);
- list_del(&request->client_list);
+ list_for_each_entry(request, &file_priv->mm.request_list, client_list)
request->file_priv = NULL;
- }
spin_unlock(&file_priv->mm.lock);
if (!list_empty(&file_priv->rps.link)) {
--
2.8.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 04/55] drm/i915: Only drop the batch-pool's object reference
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (2 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 03/55] drm/i915: Only clear the client pointer when tearing down the file Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 05/55] drm/i915/cmdparser: Remove stray intel_engine_cs *ring Chris Wilson
` (52 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
The obj->batch_pool_link is only inspected when traversing the batch
pool list and when on the batch pool list the object is referenced. Thus
when freeing the batch pool list, we only need to unreference the object
and do not have to worry about the obj->batch_pool_link.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-5-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
index 3507b2753fd3..825981b5aa40 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
@@ -68,15 +68,14 @@ void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool)
WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex));
for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) {
- while (!list_empty(&pool->cache_list[n])) {
- struct drm_i915_gem_object *obj =
- list_first_entry(&pool->cache_list[n],
- struct drm_i915_gem_object,
- batch_pool_link);
+ struct drm_i915_gem_object *obj, *next;
- list_del(&obj->batch_pool_link);
+ list_for_each_entry_safe(obj, next,
+ &pool->cache_list[n],
+ batch_pool_link)
i915_gem_object_put(obj);
- }
+
+ INIT_LIST_HEAD(&pool->cache_list[n]);
}
}
--
2.8.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 05/55] drm/i915/cmdparser: Remove stray intel_engine_cs *ring
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (3 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 04/55] drm/i915: Only drop the batch-pool's object reference Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 06/55] drm/i915: Use engine to refer to the user's BSD intel_engine_cs Chris Wilson
` (51 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
When we refer to intel_engine_cs, we want to use engine so as not to
confuse ourselves about ringbuffers.
v2: Rename all the functions as well, as well as a few more stray comments.
v3: Split the really long error message strings
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-6-git-send-email-chris@chris-wilson.co.uk
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 74 ++++++++++++++++--------------
drivers/gpu/drm/i915/i915_drv.h | 23 +++++-----
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 +++---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++--
7 files changed, 66 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index b0fd6a7b0603..1db829c8b912 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -62,23 +62,23 @@
* The parser always rejects such commands.
*
* The majority of the problematic commands fall in the MI_* range, with only a
- * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
+ * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
*
* Implementation:
- * Each ring maintains tables of commands and registers which the parser uses in
- * scanning batch buffers submitted to that ring.
+ * Each engine maintains tables of commands and registers which the parser
+ * uses in scanning batch buffers submitted to that engine.
*
* Since the set of commands that the parser must check for is significantly
* smaller than the number of commands supported, the parser tables contain only
* those commands required by the parser. This generally works because command
* opcode ranges have standard command length encodings. So for commands that
* the parser does not need to check, it can easily skip them. This is
- * implemented via a per-ring length decoding vfunc.
+ * implemented via a per-engine length decoding vfunc.
*
* Unfortunately, there are a number of commands that do not follow the standard
* length encoding for their opcode range, primarily amongst the MI_* commands.
* To handle this, the parser provides a way to define explicit "skip" entries
- * in the per-ring command tables.
+ * in the per-engine command tables.
*
* Other command table entries map fairly directly to high level categories
* mentioned above: rejected, master-only, register whitelist. The parser
@@ -603,7 +603,7 @@ static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
return 0;
}
-static bool validate_cmds_sorted(struct intel_engine_cs *engine,
+static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
const struct drm_i915_cmd_table *cmd_tables,
int cmd_table_count)
{
@@ -624,8 +624,10 @@ static bool validate_cmds_sorted(struct intel_engine_cs *engine,
u32 curr = desc->cmd.value & desc->cmd.mask;
if (curr < previous) {
- DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
- engine->id, i, j, curr, previous);
+ DRM_ERROR("CMD: %s [%d] command table not sorted: "
+ "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
+ engine->name, engine->id,
+ i, j, curr, previous);
ret = false;
}
@@ -636,7 +638,7 @@ static bool validate_cmds_sorted(struct intel_engine_cs *engine,
return ret;
}
-static bool check_sorted(int ring_id,
+static bool check_sorted(const struct intel_engine_cs *engine,
const struct drm_i915_reg_descriptor *reg_table,
int reg_count)
{
@@ -648,8 +650,10 @@ static bool check_sorted(int ring_id,
u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
if (curr < previous) {
- DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
- ring_id, i, curr, previous);
+ DRM_ERROR("CMD: %s [%d] register table not sorted: "
+ "entry=%d reg=0x%08X prev=0x%08X\n",
+ engine->name, engine->id,
+ i, curr, previous);
ret = false;
}
@@ -666,7 +670,7 @@ static bool validate_regs_sorted(struct intel_engine_cs *engine)
for (i = 0; i < engine->reg_table_count; i++) {
table = &engine->reg_tables[i];
- if (!check_sorted(engine->id, table->regs, table->num_regs))
+ if (!check_sorted(engine, table->regs, table->num_regs))
return false;
}
@@ -736,7 +740,7 @@ static void fini_hash_table(struct intel_engine_cs *engine)
}
/**
- * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
+ * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
* @engine: the engine to initialize
*
* Optionally initializes fields related to batch buffer command parsing in the
@@ -745,7 +749,7 @@ static void fini_hash_table(struct intel_engine_cs *engine)
*
* Return: non-zero if initialization fails
*/
-int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
+int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
{
const struct drm_i915_cmd_table *cmd_tables;
int cmd_table_count;
@@ -806,8 +810,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
break;
default:
- DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
- engine->id);
+ MISSING_CASE(engine->id);
BUG();
}
@@ -829,13 +832,13 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
}
/**
- * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
+ * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
* @engine: the engine to clean up
*
* Releases any resources related to command parsing that may have been
- * initialized for the specified ring.
+ * initialized for the specified engine.
*/
-void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine)
+void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
{
if (!engine->needs_cmd_parser)
return;
@@ -866,9 +869,9 @@ find_cmd_in_table(struct intel_engine_cs *engine,
* Returns a pointer to a descriptor for the command specified by cmd_header.
*
* The caller must supply space for a default descriptor via the default_desc
- * parameter. If no descriptor for the specified command exists in the ring's
+ * parameter. If no descriptor for the specified command exists in the engine's
* command parser tables, this function fills in default_desc based on the
- * ring's default length encoding and returns default_desc.
+ * engine's default length encoding and returns default_desc.
*/
static const struct drm_i915_cmd_descriptor*
find_cmd(struct intel_engine_cs *engine,
@@ -1023,15 +1026,16 @@ unpin_src:
}
/**
- * i915_needs_cmd_parser() - should a given ring use software command parsing?
+ * intel_engine_needs_cmd_parser() - should a given engine use software
+ * command parsing?
* @engine: the engine in question
*
* Only certain platforms require software batch buffer command parsing, and
* only when enabled via module parameter.
*
- * Return: true if the ring requires software command parsing
+ * Return: true if the engine requires software command parsing
*/
-bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
+bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine)
{
if (!engine->needs_cmd_parser)
return false;
@@ -1078,8 +1082,8 @@ static bool check_cmd(const struct intel_engine_cs *engine,
reg_addr);
if (!reg) {
- DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
- reg_addr, *cmd, engine->id);
+ DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (exec_id=%d)\n",
+ reg_addr, *cmd, engine->exec_id);
return false;
}
@@ -1159,11 +1163,11 @@ static bool check_cmd(const struct intel_engine_cs *engine,
desc->bits[i].mask;
if (dword != desc->bits[i].expected) {
- DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
+ DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (exec_id=%d)\n",
*cmd,
desc->bits[i].mask,
desc->bits[i].expected,
- dword, engine->id);
+ dword, engine->exec_id);
return false;
}
}
@@ -1189,12 +1193,12 @@ static bool check_cmd(const struct intel_engine_cs *engine,
* Return: non-zero if the parser finds violations or otherwise fails; -EACCES
* if the batch appears legal but should use hardware parsing
*/
-int i915_parse_cmds(struct intel_engine_cs *engine,
- struct drm_i915_gem_object *batch_obj,
- struct drm_i915_gem_object *shadow_batch_obj,
- u32 batch_start_offset,
- u32 batch_len,
- bool is_master)
+int intel_engine_cmd_parser(struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *batch_obj,
+ struct drm_i915_gem_object *shadow_batch_obj,
+ u32 batch_start_offset,
+ u32 batch_len,
+ bool is_master)
{
u32 *cmd, *batch_base, *batch_end;
struct drm_i915_cmd_descriptor default_desc = { 0 };
@@ -1295,7 +1299,7 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
/* If the command parser is not enabled, report 0 - unsupported */
for_each_engine(engine, dev_priv) {
- if (i915_needs_cmd_parser(engine)) {
+ if (intel_engine_needs_cmd_parser(engine)) {
active = true;
break;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9f655e2add66..ea9b95335a67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2500,8 +2500,9 @@ struct drm_i915_cmd_descriptor {
/*
* A table of commands requiring special handling by the command parser.
*
- * Each ring has an array of tables. Each table consists of an array of command
- * descriptors, which must be sorted with command opcodes in ascending order.
+ * Each engine has an array of tables. Each table consists of an array of
+ * command descriptors, which must be sorted with command opcodes in
+ * ascending order.
*/
struct drm_i915_cmd_table {
const struct drm_i915_cmd_descriptor *table;
@@ -3529,15 +3530,15 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
/* i915_cmd_parser.c */
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
-int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
-void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
-bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
-int i915_parse_cmds(struct intel_engine_cs *engine,
- struct drm_i915_gem_object *batch_obj,
- struct drm_i915_gem_object *shadow_batch_obj,
- u32 batch_start_offset,
- u32 batch_len,
- bool is_master);
+int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
+void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
+bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
+int intel_engine_cmd_parser(struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *batch_obj,
+ struct drm_i915_gem_object *shadow_batch_obj,
+ u32 batch_start_offset,
+ u32 batch_len,
+ bool is_master);
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f8d8ae39fc2f..cd3f87345757 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1216,12 +1216,12 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
if (IS_ERR(shadow_batch_obj))
return shadow_batch_obj;
- ret = i915_parse_cmds(engine,
- batch_obj,
- shadow_batch_obj,
- batch_start_offset,
- batch_len,
- is_master);
+ ret = intel_engine_cmd_parser(engine,
+ batch_obj,
+ shadow_batch_obj,
+ batch_start_offset,
+ batch_len,
+ is_master);
if (ret)
goto err;
@@ -1563,7 +1563,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
}
params->args_batch_start_offset = args->batch_start_offset;
- if (i915_needs_cmd_parser(engine) && args->batch_len) {
+ if (intel_engine_needs_cmd_parser(engine) && args->batch_len) {
struct drm_i915_gem_object *parsed_batch_obj;
parsed_batch_obj = i915_gem_execbuffer_parse(engine,
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index f4a35ec78481..e28873cb0672 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -207,5 +207,5 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
if (ret)
return ret;
- return i915_cmd_parser_init_ring(engine);
+ return intel_engine_init_cmd_parser(engine);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index daf1279a317d..dd3f490556dc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1925,7 +1925,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
if (engine->cleanup)
engine->cleanup(engine);
- i915_cmd_parser_fini_ring(engine);
+ intel_engine_cleanup_cmd_parser(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
intel_engine_fini_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0b5d1de8a7fb..15acaf617303 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2267,7 +2267,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
cleanup_phys_status_page(engine);
}
- i915_cmd_parser_fini_ring(engine);
+ intel_engine_cleanup_cmd_parser(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
intel_engine_fini_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 0f8019488d33..9a0a02653039 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -340,7 +340,7 @@ struct intel_engine_cs {
/*
* Table of commands the command parser needs to know about
- * for this ring.
+ * for this engine.
*/
DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
@@ -354,11 +354,11 @@ struct intel_engine_cs {
* Returns the bitmask for the length field of the specified command.
* Return 0 for an unrecognized/invalid command.
*
- * If the command parser finds an entry for a command in the ring's
+ * If the command parser finds an entry for a command in the engine's
* cmd_tables, it gets the command's length based on the table entry.
- * If not, it calls this function to determine the per-ring length field
- * encoding for the command (i.e. certain opcode ranges use certain bits
- * to encode the command length in the header).
+ * If not, it calls this function to determine the per-engine length
+ * field encoding for the command (i.e. different opcode ranges use
+ * certain bits to encode the command length in the header).
*/
u32 (*get_cmd_length_mask)(u32 cmd_header);
};
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 06/55] drm/i915: Use engine to refer to the user's BSD intel_engine_cs
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (4 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 05/55] drm/i915/cmdparser: Remove stray intel_engine_cs *ring Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture Chris Wilson
` (50 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
This patch transitions the execbuf engine selection away from using the
ring nomenclature - though we still refer to the user's incoming
selector as their user_ring_id.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-7-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 ++++++++-------
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea9b95335a67..97f827979a66 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -402,7 +402,7 @@ struct drm_i915_file_private {
unsigned boosts;
} rps;
- unsigned int bsd_ring;
+ unsigned int bsd_engine;
};
/* Used by dp and fdi links */
@@ -1331,7 +1331,7 @@ struct i915_gem_mm {
bool interruptible;
/* the indicator for dispatch video commands on two BSD rings */
- unsigned int bsd_ring_dispatch_index;
+ unsigned int bsd_engine_dispatch_index;
/** Bit 6 swizzling required for X tiling */
uint32_t bit_6_swizzle_x;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3730aecc1eae..e155e8dd28ed 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4782,7 +4782,7 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file)
spin_lock_init(&file_priv->mm.lock);
INIT_LIST_HEAD(&file_priv->mm.request_list);
- file_priv->bsd_ring = -1;
+ file_priv->bsd_engine = -1;
ret = i915_gem_context_open(dev, file);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index cd3f87345757..aa35867f3032 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1351,23 +1351,24 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
/**
* Find one BSD ring to dispatch the corresponding BSD command.
- * The ring index is returned.
+ * The engine index is returned.
*/
static unsigned int
-gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file *file)
+gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
+ struct drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
/* Check whether the file_priv has already selected one ring. */
- if ((int)file_priv->bsd_ring < 0) {
+ if ((int)file_priv->bsd_engine < 0) {
/* If not, use the ping-pong mechanism to select one. */
mutex_lock(&dev_priv->drm.struct_mutex);
- file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index;
- dev_priv->mm.bsd_ring_dispatch_index ^= 1;
+ file_priv->bsd_engine = dev_priv->mm.bsd_engine_dispatch_index;
+ dev_priv->mm.bsd_engine_dispatch_index ^= 1;
mutex_unlock(&dev_priv->drm.struct_mutex);
}
- return file_priv->bsd_ring;
+ return file_priv->bsd_engine;
}
#define I915_USER_RINGS (4)
@@ -1404,7 +1405,7 @@ eb_select_engine(struct drm_i915_private *dev_priv,
unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
- bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file);
+ bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
bsd_idx <= I915_EXEC_BSD_RING2) {
bsd_idx >>= I915_EXEC_BSD_SHIFT;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (5 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 06/55] drm/i915: Use engine to refer to the user's BSD intel_engine_cs Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-26 4:59 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c Chris Wilson
` (49 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Inside the error capture itself, we refer to not only the hardware
engine, its ringbuffer but also the capture state. Finding clear names
for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
compromise we keep using ering for the error capture.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 255 +++++++++++++++++-----------------
2 files changed, 134 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97f827979a66..11c0204aac23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -512,7 +512,7 @@ struct drm_i915_error_state {
struct intel_display_error_state *display;
struct drm_i915_error_object *semaphore_obj;
- struct drm_i915_error_ring {
+ struct drm_i915_error_engine {
bool valid;
/* Software tracked state */
bool waiting;
@@ -578,7 +578,7 @@ struct drm_i915_error_state {
pid_t pid;
char comm[TASK_COMM_LEN];
- } ring[I915_NUM_ENGINES];
+ } engine[I915_NUM_ENGINES];
struct drm_i915_error_buffer {
u32 size;
@@ -593,7 +593,7 @@ struct drm_i915_error_state {
u32 dirty:1;
u32 purgeable:1;
u32 userptr:1;
- s32 ring:4;
+ s32 engine:4;
u32 cache_level:3;
} **active_bo, **pinned_bo;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4d39c7284605..0ec917fa115d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -30,9 +30,9 @@
#include <generated/utsrelease.h>
#include "i915_drv.h"
-static const char *ring_str(int ring)
+static const char *engine_str(int engine)
{
- switch (ring) {
+ switch (engine) {
case RCS: return "render";
case VCS: return "bsd";
case BCS: return "blt";
@@ -207,8 +207,8 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
err_puts(m, dirty_flag(err->dirty));
err_puts(m, purgeable_flag(err->purgeable));
err_puts(m, err->userptr ? " userptr" : "");
- err_puts(m, err->ring != -1 ? " " : "");
- err_puts(m, ring_str(err->ring));
+ err_puts(m, err->engine != -1 ? " " : "");
+ err_puts(m, engine_str(err->engine));
err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
if (err->name)
@@ -240,69 +240,71 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
}
static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
- struct drm_device *dev,
- struct drm_i915_error_state *error,
- int ring_idx)
+ struct drm_device *dev,
+ struct drm_i915_error_state *error,
+ int engine_idx)
{
- struct drm_i915_error_ring *ring = &error->ring[ring_idx];
+ struct drm_i915_error_engine *ering = &error->engine[engine_idx];
- if (!ring->valid)
+ if (!ering->valid)
return;
- err_printf(m, "%s command stream:\n", ring_str(ring_idx));
- err_printf(m, " START: 0x%08x\n", ring->start);
- err_printf(m, " HEAD: 0x%08x\n", ring->head);
- err_printf(m, " TAIL: 0x%08x\n", ring->tail);
- err_printf(m, " CTL: 0x%08x\n", ring->ctl);
- err_printf(m, " HWS: 0x%08x\n", ring->hws);
- err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
- err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
- err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
- err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
+ err_printf(m, "%s command stream:\n", engine_str(engine_idx));
+ err_printf(m, " START: 0x%08x\n", ering->start);
+ err_printf(m, " HEAD: 0x%08x\n", ering->head);
+ err_printf(m, " TAIL: 0x%08x\n", ering->tail);
+ err_printf(m, " CTL: 0x%08x\n", ering->ctl);
+ err_printf(m, " HWS: 0x%08x\n", ering->hws);
+ err_printf(m, " ACTHD: 0x%08x %08x\n",
+ (u32)(ering->acthd>>32), (u32)ering->acthd);
+ err_printf(m, " IPEIR: 0x%08x\n", ering->ipeir);
+ err_printf(m, " IPEHR: 0x%08x\n", ering->ipehr);
+ err_printf(m, " INSTDONE: 0x%08x\n", ering->instdone);
if (INTEL_INFO(dev)->gen >= 4) {
- err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
- err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
- err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
+ err_printf(m, " BBADDR: 0x%08x %08x\n",
+ (u32)(ering->bbaddr>>32), (u32)ering->bbaddr);
+ err_printf(m, " BB_STATE: 0x%08x\n", ering->bbstate);
+ err_printf(m, " INSTPS: 0x%08x\n", ering->instps);
}
- err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
- err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
- lower_32_bits(ring->faddr));
+ err_printf(m, " INSTPM: 0x%08x\n", ering->instpm);
+ err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ering->faddr),
+ lower_32_bits(ering->faddr));
if (INTEL_INFO(dev)->gen >= 6) {
- err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
- err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
+ err_printf(m, " RC PSMI: 0x%08x\n", ering->rc_psmi);
+ err_printf(m, " FAULT_REG: 0x%08x\n", ering->fault_reg);
err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
- ring->semaphore_mboxes[0],
- ring->semaphore_seqno[0]);
+ ering->semaphore_mboxes[0],
+ ering->semaphore_seqno[0]);
err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
- ring->semaphore_mboxes[1],
- ring->semaphore_seqno[1]);
+ ering->semaphore_mboxes[1],
+ ering->semaphore_seqno[1]);
if (HAS_VEBOX(dev)) {
err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
- ring->semaphore_mboxes[2],
- ring->semaphore_seqno[2]);
+ ering->semaphore_mboxes[2],
+ ering->semaphore_seqno[2]);
}
}
if (USES_PPGTT(dev)) {
- err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
+ err_printf(m, " GFX_MODE: 0x%08x\n", ering->vm_info.gfx_mode);
if (INTEL_INFO(dev)->gen >= 8) {
int i;
for (i = 0; i < 4; i++)
err_printf(m, " PDP%d: 0x%016llx\n",
- i, ring->vm_info.pdp[i]);
+ i, ering->vm_info.pdp[i]);
} else {
err_printf(m, " PP_DIR_BASE: 0x%08x\n",
- ring->vm_info.pp_dir_base);
+ ering->vm_info.pp_dir_base);
}
}
- err_printf(m, " seqno: 0x%08x\n", ring->seqno);
- err_printf(m, " last_seqno: 0x%08x\n", ring->last_seqno);
- err_printf(m, " waiting: %s\n", yesno(ring->waiting));
- err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
- err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
+ err_printf(m, " seqno: 0x%08x\n", ering->seqno);
+ err_printf(m, " last_seqno: 0x%08x\n", ering->last_seqno);
+ err_printf(m, " waiting: %s\n", yesno(ering->waiting));
+ err_printf(m, " ring->head: 0x%08x\n", ering->cpu_ring_head);
+ err_printf(m, " ring->tail: 0x%08x\n", ering->cpu_ring_tail);
err_printf(m, " hangcheck: %s [%d]\n",
- hangcheck_action_to_str(ring->hangcheck_action),
- ring->hangcheck_score);
+ hangcheck_action_to_str(ering->hangcheck_action),
+ ering->hangcheck_score);
}
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
@@ -348,17 +350,17 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
error->time.tv_usec);
err_printf(m, "Kernel: " UTS_RELEASE "\n");
max_hangcheck_score = 0;
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- if (error->ring[i].hangcheck_score > max_hangcheck_score)
- max_hangcheck_score = error->ring[i].hangcheck_score;
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ if (error->engine[i].hangcheck_score > max_hangcheck_score)
+ max_hangcheck_score = error->engine[i].hangcheck_score;
}
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- if (error->ring[i].hangcheck_score == max_hangcheck_score &&
- error->ring[i].pid != -1) {
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ if (error->engine[i].hangcheck_score == max_hangcheck_score &&
+ error->engine[i].pid != -1) {
err_printf(m, "Active process (on ring %s): %s [%d]\n",
- ring_str(i),
- error->ring[i].comm,
- error->ring[i].pid);
+ engine_str(i),
+ error->engine[i].comm,
+ error->engine[i].pid);
}
}
err_printf(m, "Reset count: %u\n", error->reset_count);
@@ -414,7 +416,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
if (IS_GEN7(dev))
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
- for (i = 0; i < ARRAY_SIZE(error->ring); i++)
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++)
i915_ring_error_state(m, dev, error, i);
for (i = 0; i < error->vm_count; i++) {
@@ -429,21 +431,23 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
error->pinned_bo_count[i]);
}
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- obj = error->ring[i].batchbuffer;
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ struct drm_i915_error_engine *ering = &error->engine[i];
+
+ obj = ering->batchbuffer;
if (obj) {
err_puts(m, dev_priv->engine[i].name);
- if (error->ring[i].pid != -1)
+ if (ering->pid != -1)
err_printf(m, " (submitted by %s [%d])",
- error->ring[i].comm,
- error->ring[i].pid);
+ ering->comm,
+ ering->pid);
err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
upper_32_bits(obj->gtt_offset),
lower_32_bits(obj->gtt_offset));
print_error_obj(m, obj);
}
- obj = error->ring[i].wa_batchbuffer;
+ obj = ering->wa_batchbuffer;
if (obj) {
err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
dev_priv->engine[i].name,
@@ -451,38 +455,38 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
print_error_obj(m, obj);
}
- if (error->ring[i].num_requests) {
+ if (ering->num_requests) {
err_printf(m, "%s --- %d requests\n",
dev_priv->engine[i].name,
- error->ring[i].num_requests);
- for (j = 0; j < error->ring[i].num_requests; j++) {
+ ering->num_requests);
+ for (j = 0; j < ering->num_requests; j++) {
err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
- error->ring[i].requests[j].seqno,
- error->ring[i].requests[j].jiffies,
- error->ring[i].requests[j].tail);
+ ering->requests[j].seqno,
+ ering->requests[j].jiffies,
+ ering->requests[j].tail);
}
}
- if (error->ring[i].num_waiters) {
+ if (ering->num_waiters) {
err_printf(m, "%s --- %d waiters\n",
dev_priv->engine[i].name,
- error->ring[i].num_waiters);
- for (j = 0; j < error->ring[i].num_waiters; j++) {
+ ering->num_waiters);
+ for (j = 0; j < ering->num_waiters; j++) {
err_printf(m, " seqno 0x%08x for %s [%d]\n",
- error->ring[i].waiters[j].seqno,
- error->ring[i].waiters[j].comm,
- error->ring[i].waiters[j].pid);
+ ering->waiters[j].seqno,
+ ering->waiters[j].comm,
+ ering->waiters[j].pid);
}
}
- if ((obj = error->ring[i].ringbuffer)) {
+ if ((obj = ering->ringbuffer)) {
err_printf(m, "%s --- ringbuffer = 0x%08x\n",
dev_priv->engine[i].name,
lower_32_bits(obj->gtt_offset));
print_error_obj(m, obj);
}
- if ((obj = error->ring[i].hws_page)) {
+ if ((obj = ering->hws_page)) {
u64 hws_offset = obj->gtt_offset;
u32 *hws_page = &obj->pages[0][0];
@@ -504,7 +508,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
}
}
- obj = error->ring[i].wa_ctx;
+ obj = ering->wa_ctx;
if (obj) {
u64 wa_ctx_offset = obj->gtt_offset;
u32 *wa_ctx_page = &obj->pages[0][0];
@@ -526,7 +530,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
}
}
- if ((obj = error->ring[i].ctx)) {
+ if ((obj = ering->ctx)) {
err_printf(m, "%s --- HW Context = 0x%08x\n",
dev_priv->engine[i].name,
lower_32_bits(obj->gtt_offset));
@@ -611,15 +615,18 @@ static void i915_error_state_free(struct kref *error_ref)
typeof(*error), ref);
int i;
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- i915_error_object_free(error->ring[i].batchbuffer);
- i915_error_object_free(error->ring[i].wa_batchbuffer);
- i915_error_object_free(error->ring[i].ringbuffer);
- i915_error_object_free(error->ring[i].hws_page);
- i915_error_object_free(error->ring[i].ctx);
- i915_error_object_free(error->ring[i].wa_ctx);
- kfree(error->ring[i].requests);
- kfree(error->ring[i].waiters);
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ struct drm_i915_error_engine *ering = &error->engine[i];
+
+ i915_error_object_free(ering->batchbuffer);
+ i915_error_object_free(ering->wa_batchbuffer);
+ i915_error_object_free(ering->ringbuffer);
+ i915_error_object_free(ering->hws_page);
+ i915_error_object_free(ering->ctx);
+ i915_error_object_free(ering->wa_ctx);
+
+ kfree(ering->requests);
+ kfree(ering->waiters);
}
i915_error_object_free(error->semaphore_obj);
@@ -762,8 +769,8 @@ static void capture_bo(struct drm_i915_error_buffer *err,
err->dirty = obj->dirty;
err->purgeable = obj->madv != I915_MADV_WILLNEED;
err->userptr = obj->userptr.mm != NULL;
- err->ring = obj->last_write_req ?
- i915_gem_request_get_engine(obj->last_write_req)->id : -1;
+ err->engine = obj->last_write_req ?
+ i915_gem_request_get_engine(obj->last_write_req)->id : -1;
err->cache_level = obj->cache_level;
}
@@ -815,7 +822,7 @@ static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
*/
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
- int *ring_id)
+ int *engine_id)
{
uint32_t error_code = 0;
int i;
@@ -826,11 +833,11 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
* strictly a client bug. Use instdone to differentiate those some.
*/
for (i = 0; i < I915_NUM_ENGINES; i++) {
- if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
- if (ring_id)
- *ring_id = i;
+ if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
+ if (engine_id)
+ *engine_id = i;
- return error->ring[i].ipehr ^ error->ring[i].instdone;
+ return error->engine[i].ipehr ^ error->engine[i].instdone;
}
}
@@ -858,7 +865,7 @@ static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+ struct drm_i915_error_engine *ering)
{
struct intel_engine_cs *to;
enum intel_engine_id id;
@@ -891,7 +898,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+ struct drm_i915_error_engine *ering)
{
ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
@@ -906,7 +913,7 @@ static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
}
static void engine_record_waiters(struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+ struct drm_i915_error_engine *ering)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
struct drm_i915_error_waiter *waiter;
@@ -950,7 +957,7 @@ static void engine_record_waiters(struct intel_engine_cs *engine,
static void i915_record_ring_state(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+ struct drm_i915_error_engine *ering)
{
if (INTEL_GEN(dev_priv) >= 6) {
ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
@@ -1048,7 +1055,7 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
static void i915_gem_record_active_context(struct intel_engine_cs *engine,
struct drm_i915_error_state *error,
- struct drm_i915_error_ring *ering)
+ struct drm_i915_error_engine *ering)
{
struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_gem_object *obj;
@@ -1077,16 +1084,17 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct intel_engine_cs *engine = &dev_priv->engine[i];
+ struct drm_i915_error_engine *ering = &error->engine[i];
- error->ring[i].pid = -1;
+ ering->pid = -1;
if (!intel_engine_initialized(engine))
continue;
- error->ring[i].valid = true;
+ ering->valid = true;
- i915_record_ring_state(dev_priv, error, engine, &error->ring[i]);
- engine_record_waiters(engine, &error->ring[i]);
+ i915_record_ring_state(dev_priv, error, engine, ering);
+ engine_record_waiters(engine, ering);
request = i915_gem_find_active_request(engine);
if (request) {
@@ -1100,13 +1108,13 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
* as the simplest method to avoid being overwritten
* by userspace.
*/
- error->ring[i].batchbuffer =
+ ering->batchbuffer =
i915_error_object_create(dev_priv,
request->batch_obj,
vm);
if (HAS_BROKEN_CS_TLB(dev_priv))
- error->ring[i].wa_batchbuffer =
+ ering->wa_batchbuffer =
i915_error_ggtt_object_create(dev_priv,
engine->scratch.obj);
@@ -1116,8 +1124,8 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
rcu_read_lock();
task = pid_task(request->pid, PIDTYPE_PID);
if (task) {
- strcpy(error->ring[i].comm, task->comm);
- error->ring[i].pid = task->pid;
+ strcpy(ering->comm, task->comm);
+ ering->pid = task->pid;
}
rcu_read_unlock();
}
@@ -1126,35 +1134,34 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
rb = request->ringbuf;
- error->ring[i].cpu_ring_head = rb->head;
- error->ring[i].cpu_ring_tail = rb->tail;
- error->ring[i].ringbuffer =
+ ering->cpu_ring_head = rb->head;
+ ering->cpu_ring_tail = rb->tail;
+ ering->ringbuffer =
i915_error_ggtt_object_create(dev_priv,
rb->obj);
}
- error->ring[i].hws_page =
+ ering->hws_page =
i915_error_ggtt_object_create(dev_priv,
engine->status_page.obj);
if (engine->wa_ctx.obj) {
- error->ring[i].wa_ctx =
+ ering->wa_ctx =
i915_error_ggtt_object_create(dev_priv,
engine->wa_ctx.obj);
}
- i915_gem_record_active_context(engine, error, &error->ring[i]);
+ i915_gem_record_active_context(engine, error, ering);
count = 0;
list_for_each_entry(request, &engine->request_list, list)
count++;
- error->ring[i].num_requests = count;
- error->ring[i].requests =
- kcalloc(count, sizeof(*error->ring[i].requests),
- GFP_ATOMIC);
- if (error->ring[i].requests == NULL) {
- error->ring[i].num_requests = 0;
+ ering->num_requests = count;
+ ering->requests =
+ kcalloc(count, sizeof(*ering->requests), GFP_ATOMIC);
+ if (!ering->requests) {
+ ering->num_requests = 0;
continue;
}
@@ -1162,7 +1169,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
list_for_each_entry(request, &engine->request_list, list) {
struct drm_i915_error_request *erq;
- if (count >= error->ring[i].num_requests) {
+ if (count >= ering->num_requests) {
/*
* If the ring request list was changed in
* between the point where the error request
@@ -1181,7 +1188,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
break;
}
- erq = &error->ring[i].requests[count++];
+ erq = &ering->requests[count++];
erq->seqno = request->fence.seqno;
erq->jiffies = request->emitted_jiffies;
erq->tail = request->postfix;
@@ -1352,20 +1359,20 @@ static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
const char *error_msg)
{
u32 ecode;
- int ring_id = -1, len;
+ int engine_id = -1, len;
- ecode = i915_error_generate_code(dev_priv, error, &ring_id);
+ ecode = i915_error_generate_code(dev_priv, error, &engine_id);
len = scnprintf(error->error_msg, sizeof(error->error_msg),
"GPU HANG: ecode %d:%d:0x%08x",
- INTEL_GEN(dev_priv), ring_id, ecode);
+ INTEL_GEN(dev_priv), engine_id, ecode);
- if (ring_id != -1 && error->ring[ring_id].pid != -1)
+ if (engine_id != -1 && error->engine[engine_id].pid != -1)
len += scnprintf(error->error_msg + len,
sizeof(error->error_msg) - len,
", in %s [%d]",
- error->ring[ring_id].comm,
- error->ring[ring_id].pid);
+ error->engine[engine_id].comm,
+ error->engine[engine_id].pid);
scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
", reason: %s, action: %s",
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (6 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-26 5:02 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 09/55] drm/i915: Update a couple of hangcheck comments to talk about engines Chris Wilson
` (48 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
A few places we use ring when referring to the struct intel_engine_cs. An
anachronism we are pruning out.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-9-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e155e8dd28ed..7bfce1d5c61b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -46,7 +46,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
static void
i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
static void
-i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
+i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
static bool cpu_cache_is_coherent(struct drm_device *dev,
enum i915_cache_level level)
@@ -1385,10 +1385,10 @@ static void
i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *req)
{
- int ring = req->engine->id;
+ int idx = req->engine->id;
- if (obj->last_read_req[ring] == req)
- i915_gem_object_retire__read(obj, ring);
+ if (obj->last_read_req[idx] == req)
+ i915_gem_object_retire__read(obj, idx);
else if (obj->last_write_req == req)
i915_gem_object_retire__write(obj);
@@ -2381,20 +2381,20 @@ i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
}
static void
-i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
+i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
{
struct i915_vma *vma;
- GEM_BUG_ON(obj->last_read_req[ring] == NULL);
- GEM_BUG_ON(!(obj->active & (1 << ring)));
+ GEM_BUG_ON(obj->last_read_req[idx] == NULL);
+ GEM_BUG_ON(!(obj->active & (1 << idx)));
- list_del_init(&obj->engine_list[ring]);
- i915_gem_request_assign(&obj->last_read_req[ring], NULL);
+ list_del_init(&obj->engine_list[idx]);
+ i915_gem_request_assign(&obj->last_read_req[idx], NULL);
- if (obj->last_write_req && obj->last_write_req->engine->id == ring)
+ if (obj->last_write_req && obj->last_write_req->engine->id == idx)
i915_gem_object_retire__write(obj);
- obj->active &= ~(1 << ring);
+ obj->active &= ~(1 << idx);
if (obj->active)
return;
@@ -4599,7 +4599,7 @@ int i915_gem_init(struct drm_device *dev)
ret = i915_gem_init_hw(dev);
if (ret == -EIO) {
- /* Allow ring initialisation to fail by marking the GPU as
+ /* Allow engine initialisation to fail by marking the GPU as
* wedged. But we only want to do this where the GPU is angry,
* for all other failure, such as an allocation failure, bail.
*/
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 09/55] drm/i915: Update a couple of hangcheck comments to talk about engines
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (7 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 10/55] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit Chris Wilson
` (47 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
We still have lots of comments that refer to the old ring when we mean
struct intel_engine_cs and its hardware correspondence. This patch fixes
an instance inside hangcheck to talk about engines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-10-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7104dc1463eb..f5bf4f913a91 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3140,13 +3140,13 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
}
} else {
/* We always increment the hangcheck score
- * if the ring is busy and still processing
+ * if the engine is busy and still processing
* the same request, so that no single request
* can run indefinitely (such as a chain of
* batches). The only time we do not increment
* the hangcheck score on this ring, if this
- * ring is in a legitimate wait for another
- * ring. In that case the waiting ring is a
+ * engine is in a legitimate wait for another
+ * engine. In that case the waiting engine is a
* victim and we want to be sure we catch the
* right culprit. Then every time we do kick
* the ring, add a small increment to the
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 10/55] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (8 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 09/55] drm/i915: Update a couple of hangcheck comments to talk about engines Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 11/55] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
` (46 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Both perform the same actions with more or less indirection, so just
unify the code.
v2: Add back a few intel_engine_cs locals
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-11-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_context.c | 47 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 53 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 48 ++--
drivers/gpu/drm/i915/intel_display.c | 80 +++---
drivers/gpu/drm/i915/intel_lrc.c | 183 +++++++-------
drivers/gpu/drm/i915/intel_lrc.h | 26 --
drivers/gpu/drm/i915/intel_mocs.c | 38 ++-
drivers/gpu/drm/i915/intel_overlay.c | 50 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 382 +++++++++++++++--------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 25 +-
10 files changed, 450 insertions(+), 482 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index bd13d084e19c..a0e24eb5e167 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -552,6 +552,7 @@ static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
struct drm_i915_private *dev_priv = req->i915;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_engine_cs *engine = req->engine;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
@@ -589,64 +590,64 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
if (INTEL_GEN(dev_priv) >= 7) {
- intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
+ intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
if (num_rings) {
struct intel_engine_cs *signaller;
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_LOAD_REGISTER_IMM(num_rings));
for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
- intel_ring_emit_reg(engine,
+ intel_ring_emit_reg(ring,
RING_PSMI_CTL(signaller->mmio_base));
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
_MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
}
}
}
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_emit(engine, MI_SET_CONTEXT);
- intel_ring_emit(engine,
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_SET_CONTEXT);
+ intel_ring_emit(ring,
i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) |
flags);
/*
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
* WaMiSetContext_Hang:snb,ivb,vlv
*/
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
if (INTEL_GEN(dev_priv) >= 7) {
if (num_rings) {
struct intel_engine_cs *signaller;
i915_reg_t last_reg = {}; /* keep gcc quiet */
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_LOAD_REGISTER_IMM(num_rings));
for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
last_reg = RING_PSMI_CTL(signaller->mmio_base);
- intel_ring_emit_reg(engine, last_reg);
- intel_ring_emit(engine,
+ intel_ring_emit_reg(ring, last_reg);
+ intel_ring_emit(ring,
_MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
}
/* Insert a delay before the next switch! */
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_STORE_REGISTER_MEM |
MI_SRM_LRM_GLOBAL_GTT);
- intel_ring_emit_reg(engine, last_reg);
- intel_ring_emit(engine, engine->scratch.gtt_offset);
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit_reg(ring, last_reg);
+ intel_ring_emit(ring, engine->scratch.gtt_offset);
+ intel_ring_emit(ring, MI_NOOP);
}
- intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+ intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
}
- intel_ring_advance(engine);
+ intel_ring_advance(ring);
return ret;
}
@@ -654,7 +655,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
static int remap_l3(struct drm_i915_gem_request *req, int slice)
{
u32 *remap_info = req->i915->l3_parity.remap_info[slice];
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int i, ret;
if (!remap_info)
@@ -669,13 +670,13 @@ static int remap_l3(struct drm_i915_gem_request *req, int slice)
* here because no other code should access these registers other than
* at initialization time.
*/
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
- intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));
- intel_ring_emit(engine, remap_info[i]);
+ intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));
+ intel_ring_emit(ring, remap_info[i]);
}
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index aa35867f3032..2f9f0daa1bc2 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1171,14 +1171,12 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
}
static int
-i915_reset_gen7_sol_offsets(struct drm_device *dev,
- struct drm_i915_gem_request *req)
+i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret, i;
- if (!IS_GEN7(dev) || engine != &dev_priv->engine[RCS]) {
+ if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
DRM_DEBUG("sol reset is gen7/rcs only\n");
return -EINVAL;
}
@@ -1188,12 +1186,12 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev,
return ret;
for (i = 0; i < 4; i++) {
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(engine, GEN7_SO_WRITE_OFFSET(i));
- intel_ring_emit(engine, 0);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
+ intel_ring_emit(ring, 0);
}
- intel_ring_advance(engine);
+ intel_ring_advance(ring);
return 0;
}
@@ -1256,9 +1254,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas)
{
- struct drm_device *dev = params->dev;
- struct intel_engine_cs *engine = params->engine;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = params->request->i915;
u64 exec_start, exec_len;
int instp_mode;
u32 instp_mask;
@@ -1272,34 +1268,31 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
if (ret)
return ret;
- WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<engine->id),
- "%s didn't clear reload\n", engine->name);
-
instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
instp_mask = I915_EXEC_CONSTANTS_MASK;
switch (instp_mode) {
case I915_EXEC_CONSTANTS_REL_GENERAL:
case I915_EXEC_CONSTANTS_ABSOLUTE:
case I915_EXEC_CONSTANTS_REL_SURFACE:
- if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
+ if (instp_mode != 0 && params->engine->id != RCS) {
DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
return -EINVAL;
}
if (instp_mode != dev_priv->relative_constants_mode) {
- if (INTEL_INFO(dev)->gen < 4) {
+ if (INTEL_INFO(dev_priv)->gen < 4) {
DRM_DEBUG("no rel constants on pre-gen4\n");
return -EINVAL;
}
- if (INTEL_INFO(dev)->gen > 5 &&
+ if (INTEL_INFO(dev_priv)->gen > 5 &&
instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
return -EINVAL;
}
/* The HW changed the meaning on this bit on gen6 */
- if (INTEL_INFO(dev)->gen >= 6)
+ if (INTEL_INFO(dev_priv)->gen >= 6)
instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
}
break;
@@ -1308,23 +1301,25 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
return -EINVAL;
}
- if (engine == &dev_priv->engine[RCS] &&
+ if (params->engine->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
+ struct intel_ringbuffer *ring = params->request->ringbuf;
+
ret = intel_ring_begin(params->request, 4);
if (ret)
return ret;
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(engine, INSTPM);
- intel_ring_emit(engine, instp_mask << 16 | instp_mode);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ring, INSTPM);
+ intel_ring_emit(ring, instp_mask << 16 | instp_mode);
+ intel_ring_advance(ring);
dev_priv->relative_constants_mode = instp_mode;
}
if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
- ret = i915_reset_gen7_sol_offsets(dev, params->request);
+ ret = i915_reset_gen7_sol_offsets(params->request);
if (ret)
return ret;
}
@@ -1336,9 +1331,9 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
if (exec_len == 0)
exec_len = params->batch_obj->base.size;
- ret = engine->dispatch_execbuffer(params->request,
- exec_start, exec_len,
- params->dispatch_flags);
+ ret = params->engine->dispatch_execbuffer(params->request,
+ exec_start, exec_len,
+ params->dispatch_flags);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 38e7d992a20d..b38a5311f996 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -669,6 +669,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
unsigned entry,
dma_addr_t addr)
{
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -678,13 +679,13 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry));
- intel_ring_emit(engine, upper_32_bits(addr));
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry));
- intel_ring_emit(engine, lower_32_bits(addr));
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry));
+ intel_ring_emit(ring, upper_32_bits(addr));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry));
+ intel_ring_emit(ring, lower_32_bits(addr));
+ intel_ring_advance(ring);
return 0;
}
@@ -1660,6 +1661,7 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1672,13 +1674,13 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
if (ret)
return ret;
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
- intel_ring_emit(engine, PP_DIR_DCLV_2G);
- intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
- intel_ring_emit(engine, get_pd_offset(ppgtt));
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
+ intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));
+ intel_ring_emit(ring, PP_DIR_DCLV_2G);
+ intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));
+ intel_ring_emit(ring, get_pd_offset(ppgtt));
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -1686,6 +1688,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1698,17 +1701,18 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
if (ret)
return ret;
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
- intel_ring_emit(engine, PP_DIR_DCLV_2G);
- intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
- intel_ring_emit(engine, get_pd_offset(ppgtt));
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
+ intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));
+ intel_ring_emit(ring, PP_DIR_DCLV_2G);
+ intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));
+ intel_ring_emit(ring, get_pd_offset(ppgtt));
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
/* XXX: RCS is the only one to auto invalidate the TLBs? */
if (engine->id != RCS) {
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = engine->flush(req,
+ I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 78beb7e9d384..d18ed32e6a31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11123,7 +11123,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -11139,13 +11139,13 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
else
flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
- intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_emit(engine, MI_DISPLAY_FLIP |
+ intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_DISPLAY_FLIP |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
- intel_ring_emit(engine, fb->pitches[0]);
- intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
- intel_ring_emit(engine, 0); /* aux display base address, unused */
+ intel_ring_emit(ring, fb->pitches[0]);
+ intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
+ intel_ring_emit(ring, 0); /* aux display base address, unused */
return 0;
}
@@ -11157,7 +11157,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -11170,13 +11170,13 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
else
flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
- intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
+ intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
- intel_ring_emit(engine, fb->pitches[0]);
- intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, fb->pitches[0]);
+ intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
+ intel_ring_emit(ring, MI_NOOP);
return 0;
}
@@ -11188,7 +11188,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -11202,10 +11202,10 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
* Display Registers (which do not change across a page-flip)
* so we need only reprogram the base address.
*/
- intel_ring_emit(engine, MI_DISPLAY_FLIP |
+ intel_ring_emit(ring, MI_DISPLAY_FLIP |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
- intel_ring_emit(engine, fb->pitches[0]);
- intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
+ intel_ring_emit(ring, fb->pitches[0]);
+ intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
obj->tiling_mode);
/* XXX Enabling the panel-fitter across page-flip is so far
@@ -11214,7 +11214,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
*/
pf = 0;
pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
- intel_ring_emit(engine, pf | pipesrc);
+ intel_ring_emit(ring, pf | pipesrc);
return 0;
}
@@ -11226,7 +11226,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -11236,10 +11236,10 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
if (ret)
return ret;
- intel_ring_emit(engine, MI_DISPLAY_FLIP |
+ intel_ring_emit(ring, MI_DISPLAY_FLIP |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
- intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
- intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
+ intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
+ intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
/* Contrary to the suggestions in the documentation,
* "Enable Panel Fitter" does not seem to be required when page
@@ -11249,7 +11249,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
*/
pf = 0;
pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
- intel_ring_emit(engine, pf | pipesrc);
+ intel_ring_emit(ring, pf | pipesrc);
return 0;
}
@@ -11261,7 +11261,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t plane_bit = 0;
int len, ret;
@@ -11282,7 +11282,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
}
len = 4;
- if (engine->id == RCS) {
+ if (req->engine->id == RCS) {
len += 6;
/*
* On Gen 8, SRM is now taking an extra dword to accommodate
@@ -11320,30 +11320,30 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
* for the RCS also doesn't appear to drop events. Setting the DERRMR
* to zero does lead to lockups within MI_DISPLAY_FLIP.
*/
- if (engine->id == RCS) {
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(engine, DERRMR);
- intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
+ if (req->engine->id == RCS) {
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ring, DERRMR);
+ intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
DERRMR_PIPEB_PRI_FLIP_DONE |
DERRMR_PIPEC_PRI_FLIP_DONE));
if (IS_GEN8(dev))
- intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
+ intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
MI_SRM_LRM_GLOBAL_GTT);
else
- intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
+ intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
MI_SRM_LRM_GLOBAL_GTT);
- intel_ring_emit_reg(engine, DERRMR);
- intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
+ intel_ring_emit_reg(ring, DERRMR);
+ intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);
if (IS_GEN8(dev)) {
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
}
}
- intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
- intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
- intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
- intel_ring_emit(engine, (MI_NOOP));
+ intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
+ intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
+ intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
+ intel_ring_emit(ring, (MI_NOOP));
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dd3f490556dc..d851b4eef139 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -773,7 +773,7 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
struct intel_ringbuffer *ringbuf = request->ringbuf;
struct intel_engine_cs *engine = request->engine;
- intel_logical_ring_advance(ringbuf);
+ intel_ring_advance(ringbuf);
request->tail = ringbuf->tail;
/*
@@ -782,9 +782,9 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
*
* Caller must reserve WA_TAIL_DWORDS for us!
*/
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
/* We keep the previous context alive until we retire the following
* request. This ensures that any the context object is still pinned
@@ -868,11 +868,11 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
- intel_logical_ring_emit_reg(ringbuf, INSTPM);
- intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ringbuf, INSTPM);
+ intel_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
+ intel_ring_advance(ringbuf);
dev_priv->relative_constants_mode = instp_mode;
}
@@ -1045,14 +1045,14 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
+ intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
for (i = 0; i < w->count; i++) {
- intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
- intel_logical_ring_emit(ringbuf, w->reg[i].value);
+ intel_ring_emit_reg(ringbuf, w->reg[i].addr);
+ intel_ring_emit(ringbuf, w->reg[i].value);
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_advance(ringbuf);
engine->gpu_caches_dirty = true;
ret = logical_ring_flush_all_caches(req);
@@ -1553,8 +1553,8 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ringbuf = req->ringbuf;
const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
int i, ret;
@@ -1562,20 +1562,18 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
- intel_logical_ring_emit_reg(ringbuf,
- GEN8_RING_PDP_UDW(engine, i));
- intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
- intel_logical_ring_emit_reg(ringbuf,
- GEN8_RING_PDP_LDW(engine, i));
- intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
+ intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i));
+ intel_ring_emit(ring, upper_32_bits(pd_daddr));
+ intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i));
+ intel_ring_emit(ring, lower_32_bits(pd_daddr));
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -1583,7 +1581,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
u64 offset, unsigned dispatch_flags)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ringbuf;
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -1610,14 +1608,14 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
return ret;
/* FIXME(BDW): Address space and security selectors. */
- intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
- (ppgtt<<8) |
- (dispatch_flags & I915_DISPATCH_RS ?
- MI_BATCH_RESOURCE_STREAMER : 0));
- intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
- intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
+ (ppgtt<<8) |
+ (dispatch_flags & I915_DISPATCH_RS ?
+ MI_BATCH_RESOURCE_STREAMER : 0));
+ intel_ring_emit(ring, lower_32_bits(offset));
+ intel_ring_emit(ring, upper_32_bits(offset));
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -1640,9 +1638,8 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 unused)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
- struct intel_engine_cs *engine = ringbuf->engine;
- struct drm_i915_private *dev_priv = request->i915;
+ struct intel_ringbuffer *ring = request->ringbuf;
+ struct intel_engine_cs *engine = ring->engine;
uint32_t cmd;
int ret;
@@ -1661,17 +1658,17 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
cmd |= MI_INVALIDATE_TLB;
- if (engine == &dev_priv->engine[VCS])
+ if (engine->id == VCS)
cmd |= MI_INVALIDATE_BSD;
}
- intel_logical_ring_emit(ringbuf, cmd);
- intel_logical_ring_emit(ringbuf,
- I915_GEM_HWS_SCRATCH_ADDR |
- MI_FLUSH_DW_USE_GTT);
- intel_logical_ring_emit(ringbuf, 0); /* upper addr */
- intel_logical_ring_emit(ringbuf, 0); /* value */
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring,
+ I915_GEM_HWS_SCRATCH_ADDR |
+ MI_FLUSH_DW_USE_GTT);
+ intel_ring_emit(ring, 0); /* upper addr */
+ intel_ring_emit(ring, 0); /* value */
+ intel_ring_advance(ring);
return 0;
}
@@ -1680,8 +1677,8 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
- struct intel_engine_cs *engine = ringbuf->engine;
+ struct intel_ringbuffer *ring = request->ringbuf;
+ struct intel_engine_cs *engine = request->engine;
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
bool vf_flush_wa = false, dc_flush_wa = false;
u32 flags = 0;
@@ -1732,40 +1729,40 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
return ret;
if (vf_flush_wa) {
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
}
if (dc_flush_wa) {
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
}
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_logical_ring_emit(ringbuf, flags);
- intel_logical_ring_emit(ringbuf, scratch_addr);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
if (dc_flush_wa) {
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, PIPE_CONTROL_CS_STALL);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
}
- intel_logical_ring_advance(ringbuf);
+ intel_ring_advance(ring);
return 0;
}
@@ -1794,7 +1791,7 @@ static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
static int gen8_emit_request(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
+ struct intel_ringbuffer *ring = request->ringbuf;
int ret;
ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
@@ -1804,21 +1801,20 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
- intel_logical_ring_emit(ringbuf,
- (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
- intel_logical_ring_emit(ringbuf,
- intel_hws_seqno_address(request->engine) |
- MI_FLUSH_DW_USE_GTT);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, request->fence.seqno);
- intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
- intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ring, (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
+ intel_ring_emit(ring,
+ intel_hws_seqno_address(request->engine) |
+ MI_FLUSH_DW_USE_GTT);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, request->fence.seqno);
+ intel_ring_emit(ring, MI_USER_INTERRUPT);
+ intel_ring_emit(ring, MI_NOOP);
return intel_logical_ring_advance_and_submit(request);
}
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
+ struct intel_ringbuffer *ring = request->ringbuf;
int ret;
ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
@@ -1832,19 +1828,18 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
* need a prior CS_STALL, which is emitted by the flush
* following the batch.
*/
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_logical_ring_emit(ringbuf,
- (PIPE_CONTROL_GLOBAL_GTT_IVB |
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_QW_WRITE));
- intel_logical_ring_emit(ringbuf,
- intel_hws_seqno_address(request->engine));
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring,
+ (PIPE_CONTROL_GLOBAL_GTT_IVB |
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_QW_WRITE));
+ intel_ring_emit(ring, intel_hws_seqno_address(request->engine));
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, i915_gem_request_get_seqno(request));
/* We're thrashing one dword of HWS. */
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
- intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_USER_INTERRUPT);
+ intel_ring_emit(ring, MI_NOOP);
return intel_logical_ring_advance_and_submit(request);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 38287302c5ba..d26fb44549e5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -73,32 +73,6 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine);
int intel_engines_init(struct drm_device *dev);
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
-/**
- * intel_logical_ring_advance() - advance the ringbuffer tail
- * @ringbuf: Ringbuffer to advance.
- *
- * The tail is only updated in our logical ringbuffer struct.
- */
-static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
-{
- __intel_ringbuffer_advance(ringbuf);
-}
-
-/**
- * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
- * @ringbuf: Ringbuffer to write to.
- * @data: DWORD to write.
- */
-static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
- u32 data)
-{
- __intel_ringbuffer_emit(ringbuf, data);
-}
-static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
- i915_reg_t reg)
-{
- intel_logical_ring_emit(ringbuf, i915_mmio_reg_offset(reg));
-}
/* Logical Ring Contexts */
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index bd46968d8a07..3059c52030b4 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -288,14 +288,11 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf,
- MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
+ intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
for (index = 0; index < table->size; index++) {
- intel_logical_ring_emit_reg(ringbuf,
- mocs_register(engine, index));
- intel_logical_ring_emit(ringbuf,
- table->table[index].control_value);
+ intel_ring_emit_reg(ringbuf, mocs_register(engine, index));
+ intel_ring_emit(ringbuf, table->table[index].control_value);
}
/*
@@ -307,14 +304,12 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
* that value to all the used entries.
*/
for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
- intel_logical_ring_emit_reg(ringbuf,
- mocs_register(engine, index));
- intel_logical_ring_emit(ringbuf,
- table->table[0].control_value);
+ intel_ring_emit_reg(ringbuf, mocs_register(engine, index));
+ intel_ring_emit(ringbuf, table->table[0].control_value);
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
return 0;
}
@@ -352,19 +347,18 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf,
+ intel_ring_emit(ringbuf,
MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
for (i = 0; i < table->size/2; i++) {
- intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
- intel_logical_ring_emit(ringbuf,
- l3cc_combine(table, 2*i, 2*i+1));
+ intel_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
+ intel_ring_emit(ringbuf, l3cc_combine(table, 2*i, 2*i+1));
}
if (table->size & 0x01) {
/* Odd table size - 1 left over */
- intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
- intel_logical_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0));
+ intel_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
+ intel_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0));
i++;
}
@@ -374,12 +368,12 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
* they are reserved by the hardware.
*/
for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
- intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
- intel_logical_ring_emit(ringbuf, l3cc_combine(table, 0, 0));
+ intel_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
+ intel_ring_emit(ringbuf, l3cc_combine(table, 0, 0));
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index c10ce368787e..ec63b64fb202 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -235,6 +235,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
struct drm_i915_private *dev_priv = overlay->i915;
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
+ struct intel_ringbuffer *ring;
int ret;
WARN_ON(overlay->active);
@@ -252,11 +253,12 @@ static int intel_overlay_on(struct intel_overlay *overlay)
overlay->active = true;
- intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
- intel_ring_emit(engine, overlay->flip_addr | OFC_UPDATE);
- intel_ring_emit(engine, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ ring = req->ringbuf;
+ intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
+ intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
+ intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return intel_overlay_do_wait_request(overlay, req, NULL);
}
@@ -268,6 +270,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
struct drm_i915_private *dev_priv = overlay->i915;
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
+ struct intel_ringbuffer *ring;
u32 flip_addr = overlay->flip_addr;
u32 tmp;
int ret;
@@ -292,9 +295,10 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
return ret;
}
- intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
- intel_ring_emit(engine, flip_addr);
- intel_ring_advance(engine);
+ ring = req->ringbuf;
+ intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
+ intel_ring_emit(ring, flip_addr);
+ intel_ring_advance(ring);
WARN_ON(overlay->last_flip_req);
i915_gem_request_assign(&overlay->last_flip_req, req);
@@ -336,6 +340,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
struct drm_i915_private *dev_priv = overlay->i915;
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
+ struct intel_ringbuffer *ring;
u32 flip_addr = overlay->flip_addr;
int ret;
@@ -357,24 +362,25 @@ static int intel_overlay_off(struct intel_overlay *overlay)
return ret;
}
+ ring = req->ringbuf;
/* wait for overlay to go idle */
- intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
- intel_ring_emit(engine, flip_addr);
- intel_ring_emit(engine, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
+ intel_ring_emit(ring, flip_addr);
+ intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
/* turn overlay off */
if (IS_I830(dev_priv)) {
/* Workaround: Don't disable the overlay fully, since otherwise
* it dies on the next OVERLAY_ON cmd. */
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
} else {
- intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
- intel_ring_emit(engine, flip_addr);
- intel_ring_emit(engine,
+ intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
+ intel_ring_emit(ring, flip_addr);
+ intel_ring_emit(ring,
MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
}
- intel_ring_advance(engine);
+ intel_ring_advance(ring);
return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
}
@@ -420,6 +426,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
/* synchronous slowpath */
struct drm_i915_gem_request *req;
+ struct intel_ringbuffer *ring;
req = i915_gem_request_alloc(engine, NULL);
if (IS_ERR(req))
@@ -431,10 +438,11 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
return ret;
}
- intel_ring_emit(engine,
+ ring = req->ringbuf;
+ intel_ring_emit(ring,
MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
ret = intel_overlay_do_wait_request(overlay, req,
intel_overlay_release_old_vid_tail);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 15acaf617303..12670068f081 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -58,7 +58,7 @@ void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
ringbuf->tail, ringbuf->size);
}
-static void __intel_ring_advance(struct intel_engine_cs *engine)
+static void __intel_engine_submit(struct intel_engine_cs *engine)
{
struct intel_ringbuffer *ringbuf = engine->buffer;
ringbuf->tail &= ringbuf->size - 1;
@@ -70,7 +70,7 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
u32 cmd;
int ret;
@@ -85,9 +85,9 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(engine, cmd);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -97,7 +97,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
u32 cmd;
int ret;
@@ -129,23 +129,20 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
* are flushed at any MI_FLUSH.
*/
- cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
- if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
- cmd &= ~MI_NO_WRITE_FLUSH;
- if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
+ cmd = MI_FLUSH;
+ if (invalidate_domains) {
cmd |= MI_EXE_FLUSH;
-
- if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
- (IS_G4X(req->i915) || IS_GEN5(req->i915)))
- cmd |= MI_INVALIDATE_ISP;
+ if (IS_G4X(req->i915) || IS_GEN5(req->i915))
+ cmd |= MI_INVALIDATE_ISP;
+ }
ret = intel_ring_begin(req, 2);
if (ret)
return ret;
- intel_ring_emit(engine, cmd);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -190,34 +187,35 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
static int
intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
- u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ u32 scratch_addr =
+ req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
ret = intel_ring_begin(req, 6);
if (ret)
return ret;
- intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
- intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
+ intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
- intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
- intel_ring_emit(engine, 0); /* low dword */
- intel_ring_emit(engine, 0); /* high dword */
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, 0); /* low dword */
+ intel_ring_emit(ring, 0); /* high dword */
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
ret = intel_ring_begin(req, 6);
if (ret)
return ret;
- intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
- intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
- intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
+ intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
+ intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -226,9 +224,10 @@ static int
gen6_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ u32 scratch_addr =
+ req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
u32 flags = 0;
- u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/* Force SNB workarounds for PIPE_CONTROL flushes */
@@ -266,11 +265,11 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
- intel_ring_emit(engine, flags);
- intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
- intel_ring_emit(engine, 0);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, 0);
+ intel_ring_advance(ring);
return 0;
}
@@ -278,19 +277,20 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
static int
gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 4);
if (ret)
return ret;
- intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
- intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_STALL_AT_SCOREBOARD);
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, 0);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
+ intel_ring_emit(ring,
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_advance(ring);
return 0;
}
@@ -299,9 +299,10 @@ static int
gen7_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ u32 scratch_addr =
+ req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
u32 flags = 0;
- u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/*
@@ -350,11 +351,11 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
- intel_ring_emit(engine, flags);
- intel_ring_emit(engine, scratch_addr);
- intel_ring_emit(engine, 0);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr);
+ intel_ring_emit(ring, 0);
+ intel_ring_advance(ring);
return 0;
}
@@ -363,20 +364,20 @@ static int
gen8_emit_pipe_control(struct drm_i915_gem_request *req,
u32 flags, u32 scratch_addr)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 6);
if (ret)
return ret;
- intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(engine, flags);
- intel_ring_emit(engine, scratch_addr);
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, 0);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_advance(ring);
return 0;
}
@@ -385,8 +386,8 @@ static int
gen8_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- u32 flags = 0;
u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 flags = 0;
int ret;
flags |= PIPE_CONTROL_CS_STALL;
@@ -679,14 +680,14 @@ err:
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct i915_workarounds *w = &req->i915->workarounds;
int ret, i;
if (w->count == 0)
return 0;
- engine->gpu_caches_dirty = true;
+ req->engine->gpu_caches_dirty = true;
ret = intel_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -695,16 +696,16 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
for (i = 0; i < w->count; i++) {
- intel_ring_emit_reg(engine, w->reg[i].addr);
- intel_ring_emit(engine, w->reg[i].value);
+ intel_ring_emit_reg(ring, w->reg[i].addr);
+ intel_ring_emit(ring, w->reg[i].value);
}
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_advance(ring);
- engine->gpu_caches_dirty = true;
+ req->engine->gpu_caches_dirty = true;
ret = intel_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -1337,7 +1338,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 8
- struct intel_engine_cs *signaller = signaller_req->engine;
+ struct intel_ringbuffer *signaller = signaller_req->ringbuf;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
@@ -1352,20 +1353,23 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
+ u64 gtt_offset =
+ signaller_req->engine->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
- PIPE_CONTROL_QW_WRITE |
- PIPE_CONTROL_CS_STALL);
+ intel_ring_emit(signaller,
+ PIPE_CONTROL_GLOBAL_GTT_IVB |
+ PIPE_CONTROL_QW_WRITE |
+ PIPE_CONTROL_CS_STALL);
intel_ring_emit(signaller, lower_32_bits(gtt_offset));
intel_ring_emit(signaller, upper_32_bits(gtt_offset));
intel_ring_emit(signaller, signaller_req->fence.seqno);
intel_ring_emit(signaller, 0);
- intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
- MI_SEMAPHORE_TARGET(waiter->hw_id));
+ intel_ring_emit(signaller,
+ MI_SEMAPHORE_SIGNAL |
+ MI_SEMAPHORE_TARGET(waiter->hw_id));
intel_ring_emit(signaller, 0);
}
@@ -1376,7 +1380,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 6
- struct intel_engine_cs *signaller = signaller_req->engine;
+ struct intel_ringbuffer *signaller = signaller_req->ringbuf;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
@@ -1391,18 +1395,21 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
+ u64 gtt_offset =
+ signaller_req->engine->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
- MI_FLUSH_DW_OP_STOREDW);
- intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
- MI_FLUSH_DW_USE_GTT);
+ intel_ring_emit(signaller,
+ (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
+ intel_ring_emit(signaller,
+ lower_32_bits(gtt_offset) |
+ MI_FLUSH_DW_USE_GTT);
intel_ring_emit(signaller, upper_32_bits(gtt_offset));
intel_ring_emit(signaller, signaller_req->fence.seqno);
- intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
- MI_SEMAPHORE_TARGET(waiter->hw_id));
+ intel_ring_emit(signaller,
+ MI_SEMAPHORE_SIGNAL |
+ MI_SEMAPHORE_TARGET(waiter->hw_id));
intel_ring_emit(signaller, 0);
}
@@ -1412,7 +1419,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
- struct intel_engine_cs *signaller = signaller_req->engine;
+ struct intel_ringbuffer *signaller = signaller_req->ringbuf;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
enum intel_engine_id id;
@@ -1428,7 +1435,8 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
return ret;
for_each_engine_id(useless, dev_priv, id) {
- i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
+ i915_reg_t mbox_reg =
+ signaller_req->engine->semaphore.mbox.signal[id];
if (i915_mmio_reg_valid(mbox_reg)) {
intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
@@ -1456,6 +1464,7 @@ static int
gen6_add_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
if (engine->semaphore.signal)
@@ -1466,12 +1475,11 @@ gen6_add_request(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
- intel_ring_emit(engine,
- I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- intel_ring_emit(engine, req->fence.seqno);
- intel_ring_emit(engine, MI_USER_INTERRUPT);
- __intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
+ intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+ intel_ring_emit(ring, req->fence.seqno);
+ intel_ring_emit(ring, MI_USER_INTERRUPT);
+ __intel_engine_submit(engine);
return 0;
}
@@ -1480,6 +1488,7 @@ static int
gen8_render_add_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
if (engine->semaphore.signal)
@@ -1489,18 +1498,18 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_QW_WRITE));
- intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, i915_gem_request_get_seqno(req));
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB |
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_QW_WRITE));
+ intel_ring_emit(ring, intel_hws_seqno_address(engine));
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, i915_gem_request_get_seqno(req));
/* We're thrashing one dword of HWS. */
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, MI_USER_INTERRUPT);
- intel_ring_emit(engine, MI_NOOP);
- __intel_ring_advance(engine);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_USER_INTERRUPT);
+ intel_ring_emit(ring, MI_NOOP);
+ __intel_engine_submit(engine);
return 0;
}
@@ -1524,9 +1533,9 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_engine_cs *waiter = waiter_req->engine;
+ struct intel_ringbuffer *waiter = waiter_req->ringbuf;
struct drm_i915_private *dev_priv = waiter_req->i915;
- u64 offset = GEN8_WAIT_OFFSET(waiter, signaller->id);
+ u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id);
struct i915_hw_ppgtt *ppgtt;
int ret;
@@ -1558,11 +1567,11 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_engine_cs *waiter = waiter_req->engine;
+ struct intel_ringbuffer *waiter = waiter_req->ringbuf;
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
- u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
+ u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->engine->id];
int ret;
/* Throughout all of the GEM code, seqno passed implies our current
@@ -1692,35 +1701,34 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
if (ret)
return ret;
- intel_ring_emit(engine, MI_FLUSH);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_FLUSH);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
static int
i9xx_add_request(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 4);
if (ret)
return ret;
- intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
- intel_ring_emit(engine,
- I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- intel_ring_emit(engine, req->fence.seqno);
- intel_ring_emit(engine, MI_USER_INTERRUPT);
- __intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
+ intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+ intel_ring_emit(ring, req->fence.seqno);
+ intel_ring_emit(ring, MI_USER_INTERRUPT);
+ __intel_engine_submit(req->engine);
return 0;
}
@@ -1787,20 +1795,20 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
if (ret)
return ret;
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_BATCH_BUFFER_START |
MI_BATCH_GTT |
(dispatch_flags & I915_DISPATCH_SECURE ?
0 : MI_BATCH_NON_SECURE_I965));
- intel_ring_emit(engine, offset);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, offset);
+ intel_ring_advance(ring);
return 0;
}
@@ -1814,8 +1822,8 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *engine = req->engine;
- u32 cs_offset = engine->scratch.gtt_offset;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ u32 cs_offset = req->engine->scratch.gtt_offset;
int ret;
ret = intel_ring_begin(req, 6);
@@ -1823,13 +1831,13 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
return ret;
/* Evict the invalid PTE TLBs */
- intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
- intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
- intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
- intel_ring_emit(engine, cs_offset);
- intel_ring_emit(engine, 0xdeadbeef);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
+ intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
+ intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
+ intel_ring_emit(ring, cs_offset);
+ intel_ring_emit(ring, 0xdeadbeef);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
if (len > I830_BATCH_LIMIT)
@@ -1843,17 +1851,17 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
* stable batch scratch bo area (so that the CS never
* stumbles over its tlb invalidation bug) ...
*/
- intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
- intel_ring_emit(engine,
+ intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
+ intel_ring_emit(ring,
BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
- intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
- intel_ring_emit(engine, cs_offset);
- intel_ring_emit(engine, 4096);
- intel_ring_emit(engine, offset);
+ intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
+ intel_ring_emit(ring, cs_offset);
+ intel_ring_emit(ring, 4096);
+ intel_ring_emit(ring, offset);
- intel_ring_emit(engine, MI_FLUSH);
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_FLUSH);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
/* ... and execute it. */
offset = cs_offset;
@@ -1863,10 +1871,10 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
- intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
- 0 : MI_BATCH_NON_SECURE));
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
+ intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
+ 0 : MI_BATCH_NON_SECURE));
+ intel_ring_advance(ring);
return 0;
}
@@ -1876,17 +1884,17 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
if (ret)
return ret;
- intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
- intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
- 0 : MI_BATCH_NON_SECURE));
- intel_ring_advance(engine);
+ intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
+ intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
+ 0 : MI_BATCH_NON_SECURE));
+ intel_ring_advance(ring);
return 0;
}
@@ -2418,8 +2426,9 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
/* Align the ring tail to a cacheline boundary */
int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
- int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
+ struct intel_ringbuffer *ring = req->ringbuf;
+ int num_dwords =
+ (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
int ret;
if (num_dwords == 0)
@@ -2431,9 +2440,9 @@ int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
return ret;
while (num_dwords--)
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_advance(ring);
return 0;
}
@@ -2524,7 +2533,7 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
uint32_t cmd;
int ret;
@@ -2552,17 +2561,16 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
if (invalidate & I915_GEM_GPU_DOMAINS)
cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
- intel_ring_emit(engine, cmd);
- intel_ring_emit(engine,
- I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
if (INTEL_GEN(req->i915) >= 8) {
- intel_ring_emit(engine, 0); /* upper addr */
- intel_ring_emit(engine, 0); /* value */
+ intel_ring_emit(ring, 0); /* upper addr */
+ intel_ring_emit(ring, 0); /* value */
} else {
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
}
- intel_ring_advance(engine);
+ intel_ring_advance(ring);
return 0;
}
@@ -2571,8 +2579,8 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *engine = req->engine;
- bool ppgtt = USES_PPGTT(engine->dev) &&
+ struct intel_ringbuffer *ring = req->ringbuf;
+ bool ppgtt = USES_PPGTT(req->i915) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -2581,13 +2589,13 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
return ret;
/* FIXME(BDW): Address space and security selectors. */
- intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
+ intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
(dispatch_flags & I915_DISPATCH_RS ?
MI_BATCH_RESOURCE_STREAMER : 0));
- intel_ring_emit(engine, lower_32_bits(offset));
- intel_ring_emit(engine, upper_32_bits(offset));
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, lower_32_bits(offset));
+ intel_ring_emit(ring, upper_32_bits(offset));
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -2597,22 +2605,22 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
if (ret)
return ret;
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_BATCH_BUFFER_START |
(dispatch_flags & I915_DISPATCH_SECURE ?
0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
(dispatch_flags & I915_DISPATCH_RS ?
MI_BATCH_RESOURCE_STREAMER : 0));
/* bit0-7 is the length on GEN6+ */
- intel_ring_emit(engine, offset);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, offset);
+ intel_ring_advance(ring);
return 0;
}
@@ -2622,20 +2630,20 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
if (ret)
return ret;
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_BATCH_BUFFER_START |
(dispatch_flags & I915_DISPATCH_SECURE ?
0 : MI_BATCH_NON_SECURE_I965));
/* bit0-7 is the length on GEN6+ */
- intel_ring_emit(engine, offset);
- intel_ring_advance(engine);
+ intel_ring_emit(ring, offset);
+ intel_ring_advance(ring);
return 0;
}
@@ -2645,7 +2653,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_engine_cs *engine = req->engine;
+ struct intel_ringbuffer *ring = req->ringbuf;
uint32_t cmd;
int ret;
@@ -2672,17 +2680,17 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
*/
if (invalidate & I915_GEM_DOMAIN_RENDER)
cmd |= MI_INVALIDATE_TLB;
- intel_ring_emit(engine, cmd);
- intel_ring_emit(engine,
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring,
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
if (INTEL_GEN(req->i915) >= 8) {
- intel_ring_emit(engine, 0); /* upper addr */
- intel_ring_emit(engine, 0); /* value */
+ intel_ring_emit(ring, 0); /* upper addr */
+ intel_ring_emit(ring, 0); /* value */
} else {
- intel_ring_emit(engine, 0);
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
}
- intel_ring_advance(engine);
+ intel_ring_advance(ring);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 9a0a02653039..4f4b8ea4df82 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -454,32 +454,21 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
-static inline void __intel_ringbuffer_emit(struct intel_ringbuffer *rb,
- u32 data)
+static inline void intel_ring_emit(struct intel_ringbuffer *ring, u32 data)
{
- *(uint32_t *)(rb->vaddr + rb->tail) = data;
- rb->tail += 4;
+ *(uint32_t *)(ring->vaddr + ring->tail) = data;
+ ring->tail += 4;
}
-static inline void __intel_ringbuffer_advance(struct intel_ringbuffer *rb)
-{
- rb->tail &= rb->size - 1;
-}
-
-static inline void intel_ring_emit(struct intel_engine_cs *engine, u32 data)
-{
- __intel_ringbuffer_emit(engine->buffer, data);
-}
-
-static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
+static inline void intel_ring_emit_reg(struct intel_ringbuffer *ring,
i915_reg_t reg)
{
- intel_ring_emit(engine, i915_mmio_reg_offset(reg));
+ intel_ring_emit(ring, i915_mmio_reg_offset(reg));
}
-static inline void intel_ring_advance(struct intel_engine_cs *engine)
+static inline void intel_ring_advance(struct intel_ringbuffer *ring)
{
- __intel_ringbuffer_advance(engine->buffer);
+ ring->tail &= ring->size - 1;
}
int __intel_ring_space(int head, int tail, int size);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 11/55] drm/i915: Rename request->ringbuf to request->ring
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (9 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 10/55] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 12/55] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
` (45 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Now that we have disambuigated ring and engine, we can use the clearer
and more consistent name for the intel_ringbuffer pointer in the
request.
@@
struct drm_i915_gem_request *r;
@@
- r->ringbuf
+ r->ring
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-12-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
drivers/gpu/drm/i915/i915_gem_request.c | 16 +++---
drivers/gpu/drm/i915/i915_gem_request.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 20 +++----
drivers/gpu/drm/i915/intel_display.c | 10 ++--
drivers/gpu/drm/i915/intel_lrc.c | 57 +++++++++---------
drivers/gpu/drm/i915/intel_mocs.c | 36 ++++++------
drivers/gpu/drm/i915/intel_overlay.c | 8 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 92 +++++++++++++++---------------
11 files changed, 126 insertions(+), 129 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index a0e24eb5e167..f7f4a8c40afe 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -552,7 +552,7 @@ static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
struct drm_i915_private *dev_priv = req->i915;
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
@@ -655,7 +655,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
static int remap_l3(struct drm_i915_gem_request *req, int slice)
{
u32 *remap_info = req->i915->l3_parity.remap_info[slice];
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int i, ret;
if (!remap_info)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2f9f0daa1bc2..42389de4752a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1173,7 +1173,7 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
static int
i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret, i;
if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
@@ -1303,7 +1303,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
if (params->engine->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
- struct intel_ringbuffer *ring = params->request->ringbuf;
+ struct intel_ringbuffer *ring = params->request->ring;
ret = intel_ring_begin(params->request, 4);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b38a5311f996..46cae2a92bda 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -669,7 +669,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
unsigned entry,
dma_addr_t addr)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1661,7 +1661,7 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1688,7 +1688,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 49396b895a36..d2133c41be13 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -170,7 +170,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
* Note this requires that we are always called in request
* completion order.
*/
- request->ringbuf->last_retired_head = request->postfix;
+ request->ring->last_retired_head = request->postfix;
i915_gem_request_remove_from_client(request);
@@ -423,7 +423,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
bool flush_caches)
{
struct intel_engine_cs *engine;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
u32 request_start;
u32 reserved_tail;
int ret;
@@ -432,14 +432,14 @@ void __i915_add_request(struct drm_i915_gem_request *request,
return;
engine = request->engine;
- ringbuf = request->ringbuf;
+ ring = request->ring;
/*
* To ensure that this call will not fail, space for its emissions
* should already have been reserved in the ring buffer. Let the ring
* know that it is time to use that space up.
*/
- request_start = intel_ring_get_tail(ringbuf);
+ request_start = intel_ring_get_tail(ring);
reserved_tail = request->reserved_space;
request->reserved_space = 0;
@@ -486,21 +486,21 @@ void __i915_add_request(struct drm_i915_gem_request *request,
* GPU processing the request, we never over-estimate the
* position of the head.
*/
- request->postfix = intel_ring_get_tail(ringbuf);
+ request->postfix = intel_ring_get_tail(ring);
if (i915.enable_execlists) {
ret = engine->emit_request(request);
} else {
ret = engine->add_request(request);
- request->tail = intel_ring_get_tail(ringbuf);
+ request->tail = intel_ring_get_tail(ring);
}
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
/* Sanity check that the reserved size was large enough. */
- ret = intel_ring_get_tail(ringbuf) - request_start;
+ ret = intel_ring_get_tail(ring) - request_start;
if (ret < 0)
- ret += ringbuf->size;
+ ret += ring->size;
WARN_ONCE(ret > reserved_tail,
"Not enough space reserved (%d bytes) "
"for adding the request (%d bytes)\n",
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index e06e81f459df..68868d825d9d 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -61,7 +61,7 @@ struct drm_i915_gem_request {
*/
struct i915_gem_context *ctx;
struct intel_engine_cs *engine;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
struct intel_signal_node signaling;
/** GEM sequence number associated with the previous request,
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0ec917fa115d..491523c2deda 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1099,7 +1099,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
request = i915_gem_find_active_request(engine);
if (request) {
struct i915_address_space *vm;
- struct intel_ringbuffer *rb;
+ struct intel_ringbuffer *ring;
vm = request->ctx->ppgtt ?
&request->ctx->ppgtt->base : &ggtt->base;
@@ -1116,7 +1116,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
if (HAS_BROKEN_CS_TLB(dev_priv))
ering->wa_batchbuffer =
i915_error_ggtt_object_create(dev_priv,
- engine->scratch.obj);
+ engine->scratch.obj);
if (request->pid) {
struct task_struct *task;
@@ -1133,23 +1133,21 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
error->simulated |=
request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
- rb = request->ringbuf;
- ering->cpu_ring_head = rb->head;
- ering->cpu_ring_tail = rb->tail;
+ ring = request->ring;
+ ering->cpu_ring_head = ring->head;
+ ering->cpu_ring_tail = ring->tail;
ering->ringbuffer =
i915_error_ggtt_object_create(dev_priv,
- rb->obj);
+ ring->obj);
}
ering->hws_page =
i915_error_ggtt_object_create(dev_priv,
engine->status_page.obj);
- if (engine->wa_ctx.obj) {
- ering->wa_ctx =
- i915_error_ggtt_object_create(dev_priv,
- engine->wa_ctx.obj);
- }
+ ering->wa_ctx =
+ i915_error_ggtt_object_create(dev_priv,
+ engine->wa_ctx.obj);
i915_gem_record_active_context(engine, error, ering);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d18ed32e6a31..d1932840a268 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11123,7 +11123,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -11157,7 +11157,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -11188,7 +11188,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -11226,7 +11226,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -11261,7 +11261,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t plane_bit = 0;
int len, ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d851b4eef139..041868c1ee9e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -714,7 +714,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
return ret;
}
- request->ringbuf = ce->ringbuf;
+ request->ring = ce->ringbuf;
if (i915.enable_guc_submission) {
/*
@@ -770,11 +770,11 @@ err_unpin:
static int
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
+ struct intel_ringbuffer *ring = request->ring;
struct intel_engine_cs *engine = request->engine;
- intel_ring_advance(ringbuf);
- request->tail = ringbuf->tail;
+ intel_ring_advance(ring);
+ request->tail = ring->tail;
/*
* Here we add two extra NOOPs as padding to avoid
@@ -782,9 +782,9 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
*
* Caller must reserve WA_TAIL_DWORDS for us!
*/
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
/* We keep the previous context alive until we retire the following
* request. This ensures that any the context object is still pinned
@@ -821,7 +821,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
struct drm_device *dev = params->dev;
struct intel_engine_cs *engine = params->engine;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf;
+ struct intel_ringbuffer *ring = params->request->ring;
u64 exec_start;
int instp_mode;
u32 instp_mask;
@@ -833,7 +833,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
case I915_EXEC_CONSTANTS_REL_GENERAL:
case I915_EXEC_CONSTANTS_ABSOLUTE:
case I915_EXEC_CONSTANTS_REL_SURFACE:
- if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
+ if (instp_mode != 0 && engine->id != RCS) {
DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
return -EINVAL;
}
@@ -862,17 +862,17 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
if (ret)
return ret;
- if (engine == &dev_priv->engine[RCS] &&
+ if (engine->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
ret = intel_ring_begin(params->request, 4);
if (ret)
return ret;
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(ringbuf, INSTPM);
- intel_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ring, INSTPM);
+ intel_ring_emit(ring, instp_mask << 16 | instp_mode);
+ intel_ring_advance(ring);
dev_priv->relative_constants_mode = instp_mode;
}
@@ -1030,7 +1030,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
int ret, i;
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct i915_workarounds *w = &req->i915->workarounds;
if (w->count == 0)
@@ -1045,14 +1045,14 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
for (i = 0; i < w->count; i++) {
- intel_ring_emit_reg(ringbuf, w->reg[i].addr);
- intel_ring_emit(ringbuf, w->reg[i].value);
+ intel_ring_emit_reg(ring, w->reg[i].addr);
+ intel_ring_emit(ring, w->reg[i].value);
}
- intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_advance(ring);
engine->gpu_caches_dirty = true;
ret = logical_ring_flush_all_caches(req);
@@ -1553,7 +1553,7 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
int i, ret;
@@ -1581,7 +1581,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
u64 offset, unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -1638,8 +1638,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 unused)
{
- struct intel_ringbuffer *ring = request->ringbuf;
- struct intel_engine_cs *engine = ring->engine;
+ struct intel_ringbuffer *ring = request->ring;
uint32_t cmd;
int ret;
@@ -1658,7 +1657,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
cmd |= MI_INVALIDATE_TLB;
- if (engine->id == VCS)
+ if (request->engine->id == VCS)
cmd |= MI_INVALIDATE_BSD;
}
@@ -1677,7 +1676,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = request->ringbuf;
+ struct intel_ringbuffer *ring = request->ring;
struct intel_engine_cs *engine = request->engine;
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
bool vf_flush_wa = false, dc_flush_wa = false;
@@ -1791,7 +1790,7 @@ static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
static int gen8_emit_request(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ring = request->ringbuf;
+ struct intel_ringbuffer *ring = request->ring;
int ret;
ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
@@ -1814,7 +1813,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ring = request->ringbuf;
+ struct intel_ringbuffer *ring = request->ring;
int ret;
ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 3059c52030b4..8534ec3648bd 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -276,7 +276,7 @@ int intel_mocs_init_engine(struct intel_engine_cs *engine)
static int emit_mocs_control_table(struct drm_i915_gem_request *req,
const struct drm_i915_mocs_table *table)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
enum intel_engine_id engine = req->engine->id;
unsigned int index;
int ret;
@@ -288,11 +288,11 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
for (index = 0; index < table->size; index++) {
- intel_ring_emit_reg(ringbuf, mocs_register(engine, index));
- intel_ring_emit(ringbuf, table->table[index].control_value);
+ intel_ring_emit_reg(ring, mocs_register(engine, index));
+ intel_ring_emit(ring, table->table[index].control_value);
}
/*
@@ -304,12 +304,12 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
* that value to all the used entries.
*/
for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
- intel_ring_emit_reg(ringbuf, mocs_register(engine, index));
- intel_ring_emit(ringbuf, table->table[0].control_value);
+ intel_ring_emit_reg(ring, mocs_register(engine, index));
+ intel_ring_emit(ring, table->table[0].control_value);
}
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -336,7 +336,7 @@ static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
const struct drm_i915_mocs_table *table)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
unsigned int i;
int ret;
@@ -347,18 +347,18 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(ringbuf,
+ intel_ring_emit(ring,
MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
for (i = 0; i < table->size/2; i++) {
- intel_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
- intel_ring_emit(ringbuf, l3cc_combine(table, 2*i, 2*i+1));
+ intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
+ intel_ring_emit(ring, l3cc_combine(table, 2*i, 2*i+1));
}
if (table->size & 0x01) {
/* Odd table size - 1 left over */
- intel_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
- intel_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0));
+ intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
+ intel_ring_emit(ring, l3cc_combine(table, 2*i, 0));
i++;
}
@@ -368,12 +368,12 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
* they are reserved by the hardware.
*/
for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
- intel_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
- intel_ring_emit(ringbuf, l3cc_combine(table, 0, 0));
+ intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
+ intel_ring_emit(ring, l3cc_combine(table, 0, 0));
}
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index ec63b64fb202..e750c0e3a267 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -253,7 +253,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
overlay->active = true;
- ring = req->ringbuf;
+ ring = req->ring;
intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -295,7 +295,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
return ret;
}
- ring = req->ringbuf;
+ ring = req->ring;
intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
intel_ring_emit(ring, flip_addr);
intel_ring_advance(ring);
@@ -362,7 +362,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
return ret;
}
- ring = req->ringbuf;
+ ring = req->ring;
/* wait for overlay to go idle */
intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
intel_ring_emit(ring, flip_addr);
@@ -438,7 +438,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
return ret;
}
- ring = req->ringbuf;
+ ring = req->ring;
intel_ring_emit(ring,
MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
intel_ring_emit(ring, MI_NOOP);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 12670068f081..9d70d2f92de7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -70,7 +70,7 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 cmd;
int ret;
@@ -97,7 +97,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 cmd;
int ret;
@@ -187,7 +187,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
static int
intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 scratch_addr =
req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
@@ -224,7 +224,7 @@ static int
gen6_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 scratch_addr =
req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
u32 flags = 0;
@@ -277,7 +277,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
static int
gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 4);
@@ -299,7 +299,7 @@ static int
gen7_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 scratch_addr =
req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
u32 flags = 0;
@@ -364,7 +364,7 @@ static int
gen8_emit_pipe_control(struct drm_i915_gem_request *req,
u32 flags, u32 scratch_addr)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 6);
@@ -680,7 +680,7 @@ err:
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct i915_workarounds *w = &req->i915->workarounds;
int ret, i;
@@ -1338,7 +1338,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 8
- struct intel_ringbuffer *signaller = signaller_req->ringbuf;
+ struct intel_ringbuffer *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
@@ -1380,7 +1380,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 6
- struct intel_ringbuffer *signaller = signaller_req->ringbuf;
+ struct intel_ringbuffer *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
@@ -1419,7 +1419,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
- struct intel_ringbuffer *signaller = signaller_req->ringbuf;
+ struct intel_ringbuffer *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
enum intel_engine_id id;
@@ -1464,7 +1464,7 @@ static int
gen6_add_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
if (engine->semaphore.signal)
@@ -1488,7 +1488,7 @@ static int
gen8_render_add_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
if (engine->semaphore.signal)
@@ -1533,7 +1533,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_ringbuffer *waiter = waiter_req->ringbuf;
+ struct intel_ringbuffer *waiter = waiter_req->ring;
struct drm_i915_private *dev_priv = waiter_req->i915;
u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id);
struct i915_hw_ppgtt *ppgtt;
@@ -1567,7 +1567,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_ringbuffer *waiter = waiter_req->ringbuf;
+ struct intel_ringbuffer *waiter = waiter_req->ring;
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
@@ -1701,7 +1701,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1717,7 +1717,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
static int
i9xx_add_request(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 4);
@@ -1795,7 +1795,7 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1822,7 +1822,7 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 cs_offset = req->engine->scratch.gtt_offset;
int ret;
@@ -1884,7 +1884,7 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2312,7 +2312,7 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
*/
request->reserved_space += LEGACY_REQUEST_SIZE;
- request->ringbuf = request->engine->buffer;
+ request->ring = request->engine->buffer;
ret = intel_ring_begin(request, 0);
if (ret)
@@ -2324,12 +2324,12 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *target;
- intel_ring_update_space(ringbuf);
- if (ringbuf->space >= bytes)
+ intel_ring_update_space(ring);
+ if (ring->space >= bytes)
return 0;
/*
@@ -2351,12 +2351,12 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
* from multiple ringbuffers. Here, we must ignore any that
* aren't from the ringbuffer we're considering.
*/
- if (target->ringbuf != ringbuf)
+ if (target->ring != ring)
continue;
/* Would completion of this request free enough space? */
- space = __intel_ring_space(target->postfix, ringbuf->tail,
- ringbuf->size);
+ space = __intel_ring_space(target->postfix, ring->tail,
+ ring->size);
if (space >= bytes)
break;
}
@@ -2369,9 +2369,9 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
- int remain_actual = ringbuf->size - ringbuf->tail;
- int remain_usable = ringbuf->effective_size - ringbuf->tail;
+ struct intel_ringbuffer *ring = req->ring;
+ int remain_actual = ring->size - ring->tail;
+ int remain_usable = ring->effective_size - ring->tail;
int bytes = num_dwords * sizeof(u32);
int total_bytes, wait_bytes;
bool need_wrap = false;
@@ -2398,35 +2398,35 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
wait_bytes = total_bytes;
}
- if (wait_bytes > ringbuf->space) {
+ if (wait_bytes > ring->space) {
int ret = wait_for_space(req, wait_bytes);
if (unlikely(ret))
return ret;
- intel_ring_update_space(ringbuf);
- if (unlikely(ringbuf->space < wait_bytes))
+ intel_ring_update_space(ring);
+ if (unlikely(ring->space < wait_bytes))
return -EAGAIN;
}
if (unlikely(need_wrap)) {
- GEM_BUG_ON(remain_actual > ringbuf->space);
- GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
+ GEM_BUG_ON(remain_actual > ring->space);
+ GEM_BUG_ON(ring->tail + remain_actual > ring->size);
/* Fill the tail with MI_NOOP */
- memset(ringbuf->vaddr + ringbuf->tail, 0, remain_actual);
- ringbuf->tail = 0;
- ringbuf->space -= remain_actual;
+ memset(ring->vaddr + ring->tail, 0, remain_actual);
+ ring->tail = 0;
+ ring->space -= remain_actual;
}
- ringbuf->space -= bytes;
- GEM_BUG_ON(ringbuf->space < 0);
+ ring->space -= bytes;
+ GEM_BUG_ON(ring->space < 0);
return 0;
}
/* Align the ring tail to a cacheline boundary */
int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int num_dwords =
(ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
int ret;
@@ -2533,7 +2533,7 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
uint32_t cmd;
int ret;
@@ -2579,7 +2579,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
bool ppgtt = USES_PPGTT(req->i915) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -2605,7 +2605,7 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2630,7 +2630,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2653,7 +2653,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
uint32_t cmd;
int ret;
--
2.8.1
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* [PATCH 12/55] drm/i915: Rename intel_context[engine].ringbuf
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (10 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 11/55] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 13/55] drm/i915: Rename struct intel_ringbuffer to struct intel_ring Chris Wilson
` (44 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Perform s/ringbuf/ring/ on the context struct for consistency with the
ring/engine split.
v2: Kill an outdated error_ringbuf label
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-14-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++----
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 37 ++++++++++++++----------------
5 files changed, 25 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9aa62c5b5f65..bde68741809b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -425,8 +425,8 @@ static int per_file_ctx_stats(int id, void *ptr, void *data)
for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
if (ctx->engine[n].state)
per_file_stats(0, ctx->engine[n].state, data);
- if (ctx->engine[n].ringbuf)
- per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
+ if (ctx->engine[n].ring)
+ per_file_stats(0, ctx->engine[n].ring->obj, data);
}
return 0;
@@ -2066,8 +2066,8 @@ static int i915_context_status(struct seq_file *m, void *unused)
seq_putc(m, ce->initialised ? 'I' : 'i');
if (ce->state)
describe_obj(m, ce->state);
- if (ce->ringbuf)
- describe_ctx_ringbuf(m, ce->ringbuf);
+ if (ce->ring)
+ describe_ctx_ringbuf(m, ce->ring);
seq_putc(m, '\n');
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11c0204aac23..e2067e195c16 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -894,7 +894,7 @@ struct i915_gem_context {
struct intel_context {
struct drm_i915_gem_object *state;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
struct i915_vma *lrc_vma;
uint32_t *lrc_reg_state;
u64 lrc_desc;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f7f4a8c40afe..f825b1e4aadf 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -173,8 +173,8 @@ void i915_gem_context_free(struct kref *ctx_ref)
continue;
WARN_ON(ce->pin_count);
- if (ce->ringbuf)
- intel_ringbuffer_free(ce->ringbuf);
+ if (ce->ring)
+ intel_ringbuffer_free(ce->ring);
i915_gem_object_put(ce->state);
}
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 01c1c1671811..eccd34832fe6 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -363,7 +363,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
(engine->guc_id << GUC_ELC_ENGINE_OFFSET);
- obj = ce->ringbuf->obj;
+ obj = ce->ring->obj;
gfx_addr = i915_gem_obj_ggtt_offset(obj);
lrc->ring_begin = gfx_addr;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 041868c1ee9e..5dce6fa5179a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -482,11 +482,8 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
* resubmit the request. See gen8_emit_request() for where we
* prepare the padding after the end of the request.
*/
- struct intel_ringbuffer *ringbuf;
-
- ringbuf = req0->ctx->engine[engine->id].ringbuf;
req0->tail += 8;
- req0->tail &= ringbuf->size - 1;
+ req0->tail &= req0->ring->size - 1;
}
execlists_submit_requests(req0, req1);
@@ -714,7 +711,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
return ret;
}
- request->ring = ce->ringbuf;
+ request->ring = ce->ring;
if (i915.enable_guc_submission) {
/*
@@ -976,14 +973,14 @@ static int intel_lr_context_pin(struct i915_gem_context *ctx,
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ce->ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ce->ring);
if (ret)
goto unpin_map;
ce->lrc_vma = i915_gem_obj_to_ggtt(ce->state);
intel_lr_context_descriptor_update(ctx, engine);
- lrc_reg_state[CTX_RING_BUFFER_START+1] = ce->ringbuf->vma->node.start;
+ lrc_reg_state[CTX_RING_BUFFER_START+1] = ce->ring->vma->node.start;
ce->lrc_reg_state = lrc_reg_state;
ce->state->dirty = true;
@@ -1014,7 +1011,7 @@ void intel_lr_context_unpin(struct i915_gem_context *ctx,
if (--ce->pin_count)
return;
- intel_unpin_ringbuffer_obj(ce->ringbuf);
+ intel_unpin_ringbuffer_obj(ce->ring);
i915_gem_object_unpin_map(ce->state);
i915_gem_object_ggtt_unpin(ce->state);
@@ -2346,7 +2343,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct drm_i915_gem_object *ctx_obj;
struct intel_context *ce = &ctx->engine[engine->id];
uint32_t context_size;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
int ret;
WARN_ON(ce->state);
@@ -2362,29 +2359,29 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
return PTR_ERR(ctx_obj);
}
- ringbuf = intel_engine_create_ringbuffer(engine, ctx->ring_size);
- if (IS_ERR(ringbuf)) {
- ret = PTR_ERR(ringbuf);
+ ring = intel_engine_create_ringbuffer(engine, ctx->ring_size);
+ if (IS_ERR(ring)) {
+ ret = PTR_ERR(ring);
goto error_deref_obj;
}
- ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
+ ret = populate_lr_context(ctx, ctx_obj, engine, ring);
if (ret) {
DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
- goto error_ringbuf;
+ goto error_ring_free;
}
- ce->ringbuf = ringbuf;
+ ce->ring = ring;
ce->state = ctx_obj;
ce->initialised = engine->init_context == NULL;
return 0;
-error_ringbuf:
- intel_ringbuffer_free(ringbuf);
+error_ring_free:
+ intel_ringbuffer_free(ring);
error_deref_obj:
i915_gem_object_put(ctx_obj);
- ce->ringbuf = NULL;
+ ce->ring = NULL;
ce->state = NULL;
return ret;
}
@@ -2415,7 +2412,7 @@ void intel_lr_context_reset(struct drm_i915_private *dev_priv,
i915_gem_object_unpin_map(ctx_obj);
- ce->ringbuf->head = 0;
- ce->ringbuf->tail = 0;
+ ce->ring->head = 0;
+ ce->ring->tail = 0;
}
}
--
2.8.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 13/55] drm/i915: Rename struct intel_ringbuffer to struct intel_ring
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (11 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 12/55] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 14/55] drm/i915: Rename residual ringbuf parameters Chris Wilson
` (43 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
The state stored in this struct is not only the information about the
buffer object, but the ring used to communicate with the hardware. Using
buffer here is overly specific and, for me at least, conflates with the
notion of buffer objects themselves.
s/struct intel_ringbuffer/struct intel_ring/
s/enum intel_ring_hangcheck/enum intel_engine_hangcheck/
s/describe_ctx_ringbuf()/describe_ctx_ring()/
s/intel_ring_get_active_head()/intel_engine_get_active_head()/
s/intel_ring_sync_index()/intel_engine_sync_index()/
s/intel_ring_init_seqno()/intel_engine_init_seqno()/
s/ring_stuck()/engine_stuck()/
s/intel_cleanup_engine()/intel_engine_cleanup()/
s/intel_stop_engine()/intel_engine_stop()/
s/intel_pin_and_map_ringbuffer_obj()/intel_pin_and_map_ring()/
s/intel_unpin_ringbuffer()/intel_unpin_ring()/
s/intel_engine_create_ringbuffer()/intel_engine_create_ring()/
s/intel_ring_flush_all_caches()/intel_engine_flush_all_caches()/
s/intel_ring_invalidate_all_caches()/intel_engine_invalidate_all_caches()/
s/intel_ringbuffer_free()/intel_ring_free()/
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-15-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 ++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 16 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
drivers/gpu/drm/i915/i915_gem_request.c | 6 +-
drivers/gpu/drm/i915/i915_gem_request.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +-
drivers/gpu/drm/i915/i915_irq.c | 14 ++--
drivers/gpu/drm/i915/intel_display.c | 10 +--
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 34 ++++----
drivers/gpu/drm/i915/intel_mocs.c | 4 +-
drivers/gpu/drm/i915/intel_overlay.c | 8 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 128 ++++++++++++++---------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 51 ++++++------
17 files changed, 157 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bde68741809b..dccc72d63dd0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1419,7 +1419,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
intel_runtime_pm_get(dev_priv);
for_each_engine_id(engine, dev_priv, id) {
- acthd[id] = intel_ring_get_active_head(engine);
+ acthd[id] = intel_engine_get_active_head(engine);
seqno[id] = intel_engine_get_seqno(engine);
}
@@ -2017,12 +2017,11 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
return 0;
}
-static void describe_ctx_ringbuf(struct seq_file *m,
- struct intel_ringbuffer *ringbuf)
+static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
{
seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
- ringbuf->space, ringbuf->head, ringbuf->tail,
- ringbuf->last_retired_head);
+ ring->space, ring->head, ring->tail,
+ ring->last_retired_head);
}
static int i915_context_status(struct seq_file *m, void *unused)
@@ -2067,7 +2066,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
if (ce->state)
describe_obj(m, ce->state);
if (ce->ring)
- describe_ctx_ringbuf(m, ce->ring);
+ describe_ctx_ring(m, ce->ring);
seq_putc(m, '\n');
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e2067e195c16..b7e298b4253e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -518,7 +518,7 @@ struct drm_i915_error_state {
bool waiting;
int num_waiters;
int hangcheck_score;
- enum intel_ring_hangcheck_action hangcheck_action;
+ enum intel_engine_hangcheck_action hangcheck_action;
int num_requests;
/* our own tracking of ring head and tail */
@@ -894,7 +894,7 @@ struct i915_gem_context {
struct intel_context {
struct drm_i915_gem_object *state;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
struct i915_vma *lrc_vma;
uint32_t *lrc_reg_state;
u64 lrc_desc;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7bfce1d5c61b..59890f523c5f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2486,7 +2486,7 @@ static void i915_gem_reset_engine_status(struct intel_engine_cs *engine)
static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
{
- struct intel_ringbuffer *buffer;
+ struct intel_ring *ring;
while (!list_empty(&engine->active_list)) {
struct drm_i915_gem_object *obj;
@@ -2502,7 +2502,7 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
* (lockless) lookup doesn't try and wait upon the request as we
* reset it.
*/
- intel_ring_init_seqno(engine, engine->last_submitted_seqno);
+ intel_engine_init_seqno(engine, engine->last_submitted_seqno);
/*
* Clear the execlists queue up before freeing the requests, as those
@@ -2541,9 +2541,9 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
* upon reset is less than when we start. Do one more pass over
* all the ringbuffers to reset last_retired_head.
*/
- list_for_each_entry(buffer, &engine->buffers, link) {
- buffer->last_retired_head = buffer->tail;
- intel_ring_update_space(buffer);
+ list_for_each_entry(ring, &engine->buffers, link) {
+ ring->last_retired_head = ring->tail;
+ intel_ring_update_space(ring);
}
engine->i915->gt.active_engines &= ~intel_engine_flag(engine);
@@ -2870,7 +2870,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
i915_gem_object_retire_request(obj, from_req);
} else {
- int idx = intel_ring_sync_index(from, to);
+ int idx = intel_engine_sync_index(from, to);
u32 seqno = i915_gem_request_get_seqno(from_req);
WARN_ON(!to_req);
@@ -4570,8 +4570,8 @@ int i915_gem_init(struct drm_device *dev)
if (!i915.enable_execlists) {
dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
- dev_priv->gt.cleanup_engine = intel_cleanup_engine;
- dev_priv->gt.stop_engine = intel_stop_engine;
+ dev_priv->gt.cleanup_engine = intel_engine_cleanup;
+ dev_priv->gt.stop_engine = intel_engine_stop;
} else {
dev_priv->gt.execbuf_submit = intel_execlists_submission;
dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f825b1e4aadf..3336a5fcd029 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -174,7 +174,7 @@ void i915_gem_context_free(struct kref *ctx_ref)
WARN_ON(ce->pin_count);
if (ce->ring)
- intel_ringbuffer_free(ce->ring);
+ intel_ring_free(ce->ring);
i915_gem_object_put(ce->state);
}
@@ -552,7 +552,7 @@ static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
struct drm_i915_private *dev_priv = req->i915;
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
@@ -655,7 +655,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
static int remap_l3(struct drm_i915_gem_request *req, int slice)
{
u32 *remap_info = req->i915->l3_parity.remap_info[slice];
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int i, ret;
if (!remap_info)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 42389de4752a..d0ef675fb169 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1001,7 +1001,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
/* Unconditionally invalidate gpu caches and ensure that we do flush
* any residual writes from the previous batch.
*/
- return intel_ring_invalidate_all_caches(req);
+ return intel_engine_invalidate_all_caches(req);
}
static bool
@@ -1173,7 +1173,7 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
static int
i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret, i;
if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
@@ -1303,7 +1303,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
if (params->engine->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
- struct intel_ringbuffer *ring = params->request->ring;
+ struct intel_ring *ring = params->request->ring;
ret = intel_ring_begin(params->request, 4);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 46cae2a92bda..ebfa0406a6a1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -669,7 +669,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
unsigned entry,
dma_addr_t addr)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1661,7 +1661,7 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1688,7 +1688,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index d2133c41be13..942b5b1f1602 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -244,7 +244,7 @@ static int i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
/* Finally reset hw state */
for_each_engine(engine, dev_priv)
- intel_ring_init_seqno(engine, seqno);
+ intel_engine_init_seqno(engine, seqno);
return 0;
}
@@ -423,7 +423,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
bool flush_caches)
{
struct intel_engine_cs *engine;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
u32 request_start;
u32 reserved_tail;
int ret;
@@ -454,7 +454,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
if (i915.enable_execlists)
ret = logical_ring_flush_all_caches(request);
else
- ret = intel_ring_flush_all_caches(request);
+ ret = intel_engine_flush_all_caches(request);
/* Not allowed to fail! */
WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index 68868d825d9d..382ca5a163eb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -61,7 +61,7 @@ struct drm_i915_gem_request {
*/
struct i915_gem_context *ctx;
struct intel_engine_cs *engine;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
struct intel_signal_node signaling;
/** GEM sequence number associated with the previous request,
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 491523c2deda..3d40b1dffc73 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -221,7 +221,7 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
}
}
-static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
+static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
{
switch (a) {
case HANGCHECK_IDLE:
@@ -889,7 +889,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
signal_offset = (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1))
/ 4;
tmp = error->semaphore_obj->pages[0];
- idx = intel_ring_sync_index(engine, to);
+ idx = intel_engine_sync_index(engine, to);
ering->semaphore_mboxes[idx] = tmp[signal_offset];
ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
@@ -990,7 +990,7 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
ering->waiting = intel_engine_has_waiter(engine);
ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
- ering->acthd = intel_ring_get_active_head(engine);
+ ering->acthd = intel_engine_get_active_head(engine);
ering->seqno = intel_engine_get_seqno(engine);
ering->last_seqno = engine->last_submitted_seqno;
ering->start = I915_READ_START(engine);
@@ -1099,7 +1099,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
request = i915_gem_find_active_request(engine);
if (request) {
struct i915_address_space *vm;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
vm = request->ctx->ppgtt ?
&request->ctx->ppgtt->base : &ggtt->base;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f5bf4f913a91..e58650096426 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2993,7 +2993,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
return stuck;
}
-static enum intel_ring_hangcheck_action
+static enum intel_engine_hangcheck_action
head_stuck(struct intel_engine_cs *engine, u64 acthd)
{
if (acthd != engine->hangcheck.acthd) {
@@ -3011,11 +3011,11 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
return HANGCHECK_HUNG;
}
-static enum intel_ring_hangcheck_action
-ring_stuck(struct intel_engine_cs *engine, u64 acthd)
+static enum intel_engine_hangcheck_action
+engine_stuck(struct intel_engine_cs *engine, u64 acthd)
{
struct drm_i915_private *dev_priv = engine->i915;
- enum intel_ring_hangcheck_action ha;
+ enum intel_engine_hangcheck_action ha;
u32 tmp;
ha = head_stuck(engine, acthd);
@@ -3124,7 +3124,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
if (engine->irq_seqno_barrier)
engine->irq_seqno_barrier(engine);
- acthd = intel_ring_get_active_head(engine);
+ acthd = intel_engine_get_active_head(engine);
seqno = intel_engine_get_seqno(engine);
/* Reset stuck interrupts between batch advances */
@@ -3154,8 +3154,8 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
* being repeatedly kicked and so responsible
* for stalling the machine.
*/
- engine->hangcheck.action = ring_stuck(engine,
- acthd);
+ engine->hangcheck.action =
+ engine_stuck(engine, acthd);
switch (engine->hangcheck.action) {
case HANGCHECK_IDLE:
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d1932840a268..bff172c45ff7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11123,7 +11123,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -11157,7 +11157,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -11188,7 +11188,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -11226,7 +11226,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -11261,7 +11261,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t plane_bit = 0;
int len, ret;
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index e28873cb0672..a97fd7f551a7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -154,7 +154,7 @@ cleanup:
if (i915.enable_execlists)
intel_logical_ring_cleanup(&dev_priv->engine[i]);
else
- intel_cleanup_engine(&dev_priv->engine[i]);
+ intel_engine_cleanup(&dev_priv->engine[i]);
}
return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5dce6fa5179a..0a664f258e2c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -767,7 +767,7 @@ err_unpin:
static int
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ring = request->ring;
+ struct intel_ring *ring = request->ring;
struct intel_engine_cs *engine = request->engine;
intel_ring_advance(ring);
@@ -818,7 +818,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
struct drm_device *dev = params->dev;
struct intel_engine_cs *engine = params->engine;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_ringbuffer *ring = params->request->ring;
+ struct intel_ring *ring = params->request->ring;
u64 exec_start;
int instp_mode;
u32 instp_mask;
@@ -973,7 +973,7 @@ static int intel_lr_context_pin(struct i915_gem_context *ctx,
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ce->ring);
+ ret = intel_pin_and_map_ring(dev_priv, ce->ring);
if (ret)
goto unpin_map;
@@ -1011,7 +1011,7 @@ void intel_lr_context_unpin(struct i915_gem_context *ctx,
if (--ce->pin_count)
return;
- intel_unpin_ringbuffer_obj(ce->ring);
+ intel_unpin_ring(ce->ring);
i915_gem_object_unpin_map(ce->state);
i915_gem_object_ggtt_unpin(ce->state);
@@ -1027,7 +1027,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
int ret, i;
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct i915_workarounds *w = &req->i915->workarounds;
if (w->count == 0)
@@ -1550,7 +1550,7 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
int i, ret;
@@ -1578,7 +1578,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
u64 offset, unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -1635,8 +1635,8 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 unused)
{
- struct intel_ringbuffer *ring = request->ring;
- uint32_t cmd;
+ struct intel_ring *ring = request->ring;
+ u32 cmd;
int ret;
ret = intel_ring_begin(request, 4);
@@ -1673,7 +1673,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = request->ring;
+ struct intel_ring *ring = request->ring;
struct intel_engine_cs *engine = request->engine;
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
bool vf_flush_wa = false, dc_flush_wa = false;
@@ -1787,7 +1787,7 @@ static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
static int gen8_emit_request(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ring = request->ring;
+ struct intel_ring *ring = request->ring;
int ret;
ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
@@ -1810,7 +1810,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ring = request->ring;
+ struct intel_ring *ring = request->ring;
int ret;
ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
@@ -2162,7 +2162,7 @@ static int
populate_lr_context(struct i915_gem_context *ctx,
struct drm_i915_gem_object *ctx_obj,
struct intel_engine_cs *engine,
- struct intel_ringbuffer *ringbuf)
+ struct intel_ring *ring)
{
struct drm_i915_private *dev_priv = ctx->i915;
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
@@ -2215,7 +2215,7 @@ populate_lr_context(struct i915_gem_context *ctx,
RING_START(engine->mmio_base), 0);
ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
RING_CTL(engine->mmio_base),
- ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
+ ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
RING_BBADDR_UDW(engine->mmio_base), 0);
ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
@@ -2343,7 +2343,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct drm_i915_gem_object *ctx_obj;
struct intel_context *ce = &ctx->engine[engine->id];
uint32_t context_size;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
int ret;
WARN_ON(ce->state);
@@ -2359,7 +2359,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
return PTR_ERR(ctx_obj);
}
- ring = intel_engine_create_ringbuffer(engine, ctx->ring_size);
+ ring = intel_engine_create_ring(engine, ctx->ring_size);
if (IS_ERR(ring)) {
ret = PTR_ERR(ring);
goto error_deref_obj;
@@ -2378,7 +2378,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
return 0;
error_ring_free:
- intel_ringbuffer_free(ring);
+ intel_ring_free(ring);
error_deref_obj:
i915_gem_object_put(ctx_obj);
ce->ring = NULL;
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 8534ec3648bd..80bb9247ce66 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -276,7 +276,7 @@ int intel_mocs_init_engine(struct intel_engine_cs *engine)
static int emit_mocs_control_table(struct drm_i915_gem_request *req,
const struct drm_i915_mocs_table *table)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
enum intel_engine_id engine = req->engine->id;
unsigned int index;
int ret;
@@ -336,7 +336,7 @@ static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
const struct drm_i915_mocs_table *table)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
unsigned int i;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index e750c0e3a267..8f1d4d9ef345 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -235,7 +235,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
struct drm_i915_private *dev_priv = overlay->i915;
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
int ret;
WARN_ON(overlay->active);
@@ -270,7 +270,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
struct drm_i915_private *dev_priv = overlay->i915;
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
u32 flip_addr = overlay->flip_addr;
u32 tmp;
int ret;
@@ -340,7 +340,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
struct drm_i915_private *dev_priv = overlay->i915;
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
u32 flip_addr = overlay->flip_addr;
int ret;
@@ -426,7 +426,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
/* synchronous slowpath */
struct drm_i915_gem_request *req;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
req = i915_gem_request_alloc(engine, NULL);
if (IS_ERR(req))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9d70d2f92de7..acbabbdececd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -47,7 +47,7 @@ int __intel_ring_space(int head, int tail, int size)
return space - I915_RING_FREE_SPACE;
}
-void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
+void intel_ring_update_space(struct intel_ring *ringbuf)
{
if (ringbuf->last_retired_head != -1) {
ringbuf->head = ringbuf->last_retired_head;
@@ -60,9 +60,10 @@ void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
static void __intel_engine_submit(struct intel_engine_cs *engine)
{
- struct intel_ringbuffer *ringbuf = engine->buffer;
- ringbuf->tail &= ringbuf->size - 1;
- engine->write_tail(engine, ringbuf->tail);
+ struct intel_ring *ring = engine->buffer;
+
+ ring->tail &= ring->size - 1;
+ engine->write_tail(engine, ring->tail);
}
static int
@@ -70,7 +71,7 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
u32 cmd;
int ret;
@@ -97,7 +98,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
u32 cmd;
int ret;
@@ -187,7 +188,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
static int
intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
u32 scratch_addr =
req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
@@ -224,7 +225,7 @@ static int
gen6_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
u32 scratch_addr =
req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
u32 flags = 0;
@@ -277,7 +278,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
static int
gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 4);
@@ -299,7 +300,7 @@ static int
gen7_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
u32 scratch_addr =
req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
u32 flags = 0;
@@ -364,7 +365,7 @@ static int
gen8_emit_pipe_control(struct drm_i915_gem_request *req,
u32 flags, u32 scratch_addr)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 6);
@@ -427,7 +428,7 @@ static void ring_write_tail(struct intel_engine_cs *engine,
I915_WRITE_TAIL(engine, value);
}
-u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
+u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
u64 acthd;
@@ -553,8 +554,8 @@ static bool stop_ring(struct intel_engine_cs *engine)
static int init_ring_common(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- struct intel_ringbuffer *ringbuf = engine->buffer;
- struct drm_i915_gem_object *obj = ringbuf->obj;
+ struct intel_ring *ring = engine->buffer;
+ struct drm_i915_gem_object *obj = ring->obj;
int ret = 0;
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
@@ -604,7 +605,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
(void)I915_READ_HEAD(engine);
I915_WRITE_CTL(engine,
- ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
+ ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
| RING_VALID);
/* If the head is still not zero, the ring is dead */
@@ -623,10 +624,10 @@ static int init_ring_common(struct intel_engine_cs *engine)
goto out;
}
- ringbuf->last_retired_head = -1;
- ringbuf->head = I915_READ_HEAD(engine);
- ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
- intel_ring_update_space(ringbuf);
+ ring->last_retired_head = -1;
+ ring->head = I915_READ_HEAD(engine);
+ ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
+ intel_ring_update_space(ring);
intel_engine_init_hangcheck(engine);
@@ -680,7 +681,7 @@ err:
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct i915_workarounds *w = &req->i915->workarounds;
int ret, i;
@@ -688,7 +689,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
return 0;
req->engine->gpu_caches_dirty = true;
- ret = intel_ring_flush_all_caches(req);
+ ret = intel_engine_flush_all_caches(req);
if (ret)
return ret;
@@ -706,7 +707,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
intel_ring_advance(ring);
req->engine->gpu_caches_dirty = true;
- ret = intel_ring_flush_all_caches(req);
+ ret = intel_engine_flush_all_caches(req);
if (ret)
return ret;
@@ -1338,7 +1339,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 8
- struct intel_ringbuffer *signaller = signaller_req->ring;
+ struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
@@ -1380,7 +1381,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 6
- struct intel_ringbuffer *signaller = signaller_req->ring;
+ struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
@@ -1419,7 +1420,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
- struct intel_ringbuffer *signaller = signaller_req->ring;
+ struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
enum intel_engine_id id;
@@ -1464,7 +1465,7 @@ static int
gen6_add_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
if (engine->semaphore.signal)
@@ -1488,7 +1489,7 @@ static int
gen8_render_add_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
if (engine->semaphore.signal)
@@ -1533,7 +1534,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_ringbuffer *waiter = waiter_req->ring;
+ struct intel_ring *waiter = waiter_req->ring;
struct drm_i915_private *dev_priv = waiter_req->i915;
u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id);
struct i915_hw_ppgtt *ppgtt;
@@ -1567,7 +1568,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_ringbuffer *waiter = waiter_req->ring;
+ struct intel_ring *waiter = waiter_req->ring;
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
@@ -1701,7 +1702,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1717,7 +1718,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
static int
i9xx_add_request(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 4);
@@ -1795,7 +1796,7 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1822,7 +1823,7 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
u32 cs_offset = req->engine->scratch.gtt_offset;
int ret;
@@ -1884,7 +1885,7 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1992,7 +1993,7 @@ static int init_phys_status_page(struct intel_engine_cs *engine)
return 0;
}
-void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
+void intel_unpin_ring(struct intel_ring *ringbuf)
{
GEM_BUG_ON(!ringbuf->vma);
GEM_BUG_ON(!ringbuf->vaddr);
@@ -2007,8 +2008,8 @@ void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
ringbuf->vma = NULL;
}
-int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
- struct intel_ringbuffer *ringbuf)
+int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
+ struct intel_ring *ringbuf)
{
struct drm_i915_gem_object *obj = ringbuf->obj;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
@@ -2060,14 +2061,14 @@ err_unpin:
return ret;
}
-static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
+static void intel_destroy_ringbuffer_obj(struct intel_ring *ringbuf)
{
i915_gem_object_put(ringbuf->obj);
ringbuf->obj = NULL;
}
static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
- struct intel_ringbuffer *ringbuf)
+ struct intel_ring *ringbuf)
{
struct drm_i915_gem_object *obj;
@@ -2087,10 +2088,10 @@ static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
return 0;
}
-struct intel_ringbuffer *
-intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
+struct intel_ring *
+intel_engine_create_ring(struct intel_engine_cs *engine, int size)
{
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
int ret;
ring = kzalloc(sizeof(*ring), GFP_KERNEL);
@@ -2128,7 +2129,7 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
}
void
-intel_ringbuffer_free(struct intel_ringbuffer *ring)
+intel_ring_free(struct intel_ring *ring)
{
intel_destroy_ringbuffer_obj(ring);
list_del(&ring->link);
@@ -2189,7 +2190,7 @@ static void intel_ring_context_unpin(struct i915_gem_context *ctx,
static int intel_init_ring_buffer(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ring *ringbuf;
int ret;
WARN_ON(engine->buffer);
@@ -2214,7 +2215,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
if (ret)
goto error;
- ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
+ ringbuf = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
if (IS_ERR(ringbuf)) {
ret = PTR_ERR(ringbuf);
goto error;
@@ -2232,7 +2233,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
goto error;
}
- ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
+ ret = intel_pin_and_map_ring(dev_priv, ringbuf);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
engine->name, ret);
@@ -2243,11 +2244,11 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
return 0;
error:
- intel_cleanup_engine(engine);
+ intel_engine_cleanup(engine);
return ret;
}
-void intel_cleanup_engine(struct intel_engine_cs *engine)
+void intel_engine_cleanup(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv;
@@ -2257,11 +2258,11 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
dev_priv = engine->i915;
if (engine->buffer) {
- intel_stop_engine(engine);
+ intel_engine_stop(engine);
WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
- intel_unpin_ringbuffer_obj(engine->buffer);
- intel_ringbuffer_free(engine->buffer);
+ intel_unpin_ring(engine->buffer);
+ intel_ring_free(engine->buffer);
engine->buffer = NULL;
}
@@ -2324,7 +2325,7 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *target;
@@ -2369,7 +2370,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int remain_actual = ring->size - ring->tail;
int remain_usable = ring->effective_size - ring->tail;
int bytes = num_dwords * sizeof(u32);
@@ -2426,7 +2427,7 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
/* Align the ring tail to a cacheline boundary */
int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int num_dwords =
(ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
int ret;
@@ -2447,7 +2448,7 @@ int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
return 0;
}
-void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
+void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -2533,7 +2534,7 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
uint32_t cmd;
int ret;
@@ -2579,7 +2580,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
bool ppgtt = USES_PPGTT(req->i915) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -2605,7 +2606,7 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2630,7 +2631,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2653,7 +2654,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_ringbuffer *ring = req->ring;
+ struct intel_ring *ring = req->ring;
uint32_t cmd;
int ret;
@@ -2970,7 +2971,7 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
}
int
-intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
+intel_engine_flush_all_caches(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -2989,7 +2990,7 @@ intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
}
int
-intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
+intel_engine_invalidate_all_caches(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
uint32_t flush_domains;
@@ -3009,8 +3010,7 @@ intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
return 0;
}
-void
-intel_stop_engine(struct intel_engine_cs *engine)
+void intel_engine_stop(struct intel_engine_cs *engine)
{
int ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 4f4b8ea4df82..8f94e9345819 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -62,7 +62,7 @@ struct intel_hw_status_page {
(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
-enum intel_ring_hangcheck_action {
+enum intel_engine_hangcheck_action {
HANGCHECK_IDLE = 0,
HANGCHECK_WAIT,
HANGCHECK_ACTIVE,
@@ -72,17 +72,17 @@ enum intel_ring_hangcheck_action {
#define HANGCHECK_SCORE_RING_HUNG 31
-struct intel_ring_hangcheck {
+struct intel_engine_hangcheck {
u64 acthd;
unsigned long user_interrupts;
u32 seqno;
int score;
- enum intel_ring_hangcheck_action action;
+ enum intel_engine_hangcheck_action action;
int deadlock;
u32 instdone[I915_NUM_INSTDONE_REG];
};
-struct intel_ringbuffer {
+struct intel_ring {
struct drm_i915_gem_object *obj;
void *vaddr;
struct i915_vma *vma;
@@ -149,7 +149,7 @@ struct intel_engine_cs {
u64 fence_context;
u32 mmio_base;
unsigned int irq_shift;
- struct intel_ringbuffer *buffer;
+ struct intel_ring *buffer;
struct list_head buffers;
/* Rather than have every client wait upon all user interrupts,
@@ -329,7 +329,7 @@ struct intel_engine_cs {
struct i915_gem_context *last_context;
- struct intel_ring_hangcheck hangcheck;
+ struct intel_engine_hangcheck hangcheck;
struct {
struct drm_i915_gem_object *obj;
@@ -376,8 +376,8 @@ intel_engine_flag(const struct intel_engine_cs *engine)
}
static inline u32
-intel_ring_sync_index(struct intel_engine_cs *engine,
- struct intel_engine_cs *other)
+intel_engine_sync_index(struct intel_engine_cs *engine,
+ struct intel_engine_cs *other)
{
int idx;
@@ -439,45 +439,44 @@ intel_write_status_page(struct intel_engine_cs *engine,
#define I915_GEM_HWS_SCRATCH_INDEX 0x40
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
-struct intel_ringbuffer *
-intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
-int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
- struct intel_ringbuffer *ringbuf);
-void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
-void intel_ringbuffer_free(struct intel_ringbuffer *ring);
+struct intel_ring *
+intel_engine_create_ring(struct intel_engine_cs *engine, int size);
+int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
+ struct intel_ring *ring);
+void intel_unpin_ring(struct intel_ring *ring);
+void intel_ring_free(struct intel_ring *ring);
-void intel_stop_engine(struct intel_engine_cs *engine);
-void intel_cleanup_engine(struct intel_engine_cs *engine);
+void intel_engine_stop(struct intel_engine_cs *engine);
+void intel_engine_cleanup(struct intel_engine_cs *engine);
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
-static inline void intel_ring_emit(struct intel_ringbuffer *ring, u32 data)
+static inline void intel_ring_emit(struct intel_ring *ring, u32 data)
{
*(uint32_t *)(ring->vaddr + ring->tail) = data;
ring->tail += 4;
}
-static inline void intel_ring_emit_reg(struct intel_ringbuffer *ring,
- i915_reg_t reg)
+static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg)
{
intel_ring_emit(ring, i915_mmio_reg_offset(reg));
}
-static inline void intel_ring_advance(struct intel_ringbuffer *ring)
+static inline void intel_ring_advance(struct intel_ring *ring)
{
ring->tail &= ring->size - 1;
}
int __intel_ring_space(int head, int tail, int size);
-void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
+void intel_ring_update_space(struct intel_ring *ringbuf);
int __must_check intel_engine_idle(struct intel_engine_cs *engine);
-void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
-int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
-int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
+void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
+int intel_engine_flush_all_caches(struct drm_i915_gem_request *req);
+int intel_engine_invalidate_all_caches(struct drm_i915_gem_request *req);
int intel_init_pipe_control(struct intel_engine_cs *engine, int size);
void intel_fini_pipe_control(struct intel_engine_cs *engine);
@@ -491,7 +490,7 @@ int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
-u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
+u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
{
return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
@@ -499,7 +498,7 @@ static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
int init_workarounds_ring(struct intel_engine_cs *engine);
-static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
+static inline u32 intel_ring_get_tail(struct intel_ring *ringbuf)
{
return ringbuf->tail;
}
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 14/55] drm/i915: Rename residual ringbuf parameters
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (12 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 13/55] drm/i915: Rename struct intel_ringbuffer to struct intel_ring Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 15/55] drm/i915: Rename intel_pin_and_map_ring() Chris Wilson
` (42 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Now that we have a clear ring/engine split and a struct intel_ring, we
no longer need the stopgap ringbuf names.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-16-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 66 ++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +--
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index acbabbdececd..5dd720e7feaa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -47,15 +47,15 @@ int __intel_ring_space(int head, int tail, int size)
return space - I915_RING_FREE_SPACE;
}
-void intel_ring_update_space(struct intel_ring *ringbuf)
+void intel_ring_update_space(struct intel_ring *ring)
{
- if (ringbuf->last_retired_head != -1) {
- ringbuf->head = ringbuf->last_retired_head;
- ringbuf->last_retired_head = -1;
+ if (ring->last_retired_head != -1) {
+ ring->head = ring->last_retired_head;
+ ring->last_retired_head = -1;
}
- ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
- ringbuf->tail, ringbuf->size);
+ ring->space = __intel_ring_space(ring->head & HEAD_ADDR,
+ ring->tail, ring->size);
}
static void __intel_engine_submit(struct intel_engine_cs *engine)
@@ -1993,25 +1993,25 @@ static int init_phys_status_page(struct intel_engine_cs *engine)
return 0;
}
-void intel_unpin_ring(struct intel_ring *ringbuf)
+void intel_unpin_ring(struct intel_ring *ring)
{
- GEM_BUG_ON(!ringbuf->vma);
- GEM_BUG_ON(!ringbuf->vaddr);
+ GEM_BUG_ON(!ring->vma);
+ GEM_BUG_ON(!ring->vaddr);
- if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
- i915_gem_object_unpin_map(ringbuf->obj);
+ if (HAS_LLC(ring->obj->base.dev) && !ring->obj->stolen)
+ i915_gem_object_unpin_map(ring->obj);
else
- i915_vma_unpin_iomap(ringbuf->vma);
- ringbuf->vaddr = NULL;
+ i915_vma_unpin_iomap(ring->vma);
+ ring->vaddr = NULL;
- i915_gem_object_ggtt_unpin(ringbuf->obj);
- ringbuf->vma = NULL;
+ i915_gem_object_ggtt_unpin(ring->obj);
+ ring->vma = NULL;
}
int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
- struct intel_ring *ringbuf)
+ struct intel_ring *ring)
{
- struct drm_i915_gem_object *obj = ringbuf->obj;
+ struct drm_i915_gem_object *obj = ring->obj;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
unsigned flags = PIN_OFFSET_BIAS | 4096;
void *addr;
@@ -2052,8 +2052,8 @@ int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
}
}
- ringbuf->vaddr = addr;
- ringbuf->vma = i915_gem_obj_to_ggtt(obj);
+ ring->vaddr = addr;
+ ring->vma = i915_gem_obj_to_ggtt(obj);
return 0;
err_unpin:
@@ -2061,29 +2061,29 @@ err_unpin:
return ret;
}
-static void intel_destroy_ringbuffer_obj(struct intel_ring *ringbuf)
+static void intel_destroy_ringbuffer_obj(struct intel_ring *ring)
{
- i915_gem_object_put(ringbuf->obj);
- ringbuf->obj = NULL;
+ i915_gem_object_put(ring->obj);
+ ring->obj = NULL;
}
static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
- struct intel_ring *ringbuf)
+ struct intel_ring *ring)
{
struct drm_i915_gem_object *obj;
obj = NULL;
if (!HAS_LLC(dev))
- obj = i915_gem_object_create_stolen(dev, ringbuf->size);
+ obj = i915_gem_object_create_stolen(dev, ring->size);
if (obj == NULL)
- obj = i915_gem_object_create(dev, ringbuf->size);
+ obj = i915_gem_object_create(dev, ring->size);
if (IS_ERR(obj))
return PTR_ERR(obj);
/* mark ring buffers as read-only from GPU side by default */
obj->gt_ro = 1;
- ringbuf->obj = obj;
+ ring->obj = obj;
return 0;
}
@@ -2190,7 +2190,7 @@ static void intel_ring_context_unpin(struct i915_gem_context *ctx,
static int intel_init_ring_buffer(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- struct intel_ring *ringbuf;
+ struct intel_ring *ring;
int ret;
WARN_ON(engine->buffer);
@@ -2215,12 +2215,12 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
if (ret)
goto error;
- ringbuf = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
- if (IS_ERR(ringbuf)) {
- ret = PTR_ERR(ringbuf);
+ ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
+ if (IS_ERR(ring)) {
+ ret = PTR_ERR(ring);
goto error;
}
- engine->buffer = ringbuf;
+ engine->buffer = ring;
if (I915_NEED_GFX_HWS(dev_priv)) {
ret = init_status_page(engine);
@@ -2233,11 +2233,11 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
goto error;
}
- ret = intel_pin_and_map_ring(dev_priv, ringbuf);
+ ret = intel_pin_and_map_ring(dev_priv, ring);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
engine->name, ret);
- intel_destroy_ringbuffer_obj(ringbuf);
+ intel_destroy_ringbuffer_obj(ring);
goto error;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8f94e9345819..2dfc418c5102 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -471,7 +471,7 @@ static inline void intel_ring_advance(struct intel_ring *ring)
}
int __intel_ring_space(int head, int tail, int size);
-void intel_ring_update_space(struct intel_ring *ringbuf);
+void intel_ring_update_space(struct intel_ring *ring);
int __must_check intel_engine_idle(struct intel_engine_cs *engine);
void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
@@ -498,9 +498,9 @@ static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
int init_workarounds_ring(struct intel_engine_cs *engine);
-static inline u32 intel_ring_get_tail(struct intel_ring *ringbuf)
+static inline u32 intel_ring_get_tail(struct intel_ring *ring)
{
- return ringbuf->tail;
+ return ring->tail;
}
/*
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 15/55] drm/i915: Rename intel_pin_and_map_ring()
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (13 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 14/55] drm/i915: Rename residual ringbuf parameters Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty Chris Wilson
` (41 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
For more consistent oop-naming, we would use intel_ring_verb, so pick
intel_ring_pin() and intel_ring_unpin().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-17-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 38 ++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++---
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a664f258e2c..86b8f41c254d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -973,7 +973,7 @@ static int intel_lr_context_pin(struct i915_gem_context *ctx,
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ret = intel_pin_and_map_ring(dev_priv, ce->ring);
+ ret = intel_ring_pin(ce->ring);
if (ret)
goto unpin_map;
@@ -1011,7 +1011,7 @@ void intel_lr_context_unpin(struct i915_gem_context *ctx,
if (--ce->pin_count)
return;
- intel_unpin_ring(ce->ring);
+ intel_ring_unpin(ce->ring);
i915_gem_object_unpin_map(ce->state);
i915_gem_object_ggtt_unpin(ce->state);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5dd720e7feaa..e7a7f67ab06d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1993,24 +1993,9 @@ static int init_phys_status_page(struct intel_engine_cs *engine)
return 0;
}
-void intel_unpin_ring(struct intel_ring *ring)
-{
- GEM_BUG_ON(!ring->vma);
- GEM_BUG_ON(!ring->vaddr);
-
- if (HAS_LLC(ring->obj->base.dev) && !ring->obj->stolen)
- i915_gem_object_unpin_map(ring->obj);
- else
- i915_vma_unpin_iomap(ring->vma);
- ring->vaddr = NULL;
-
- i915_gem_object_ggtt_unpin(ring->obj);
- ring->vma = NULL;
-}
-
-int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
- struct intel_ring *ring)
+int intel_ring_pin(struct intel_ring *ring)
{
+ struct drm_i915_private *dev_priv = ring->engine->i915;
struct drm_i915_gem_object *obj = ring->obj;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
unsigned flags = PIN_OFFSET_BIAS | 4096;
@@ -2061,6 +2046,21 @@ err_unpin:
return ret;
}
+void intel_ring_unpin(struct intel_ring *ring)
+{
+ GEM_BUG_ON(!ring->vma);
+ GEM_BUG_ON(!ring->vaddr);
+
+ if (HAS_LLC(ring->engine->i915) && !ring->obj->stolen)
+ i915_gem_object_unpin_map(ring->obj);
+ else
+ i915_vma_unpin_iomap(ring->vma);
+ ring->vaddr = NULL;
+
+ i915_gem_object_ggtt_unpin(ring->obj);
+ ring->vma = NULL;
+}
+
static void intel_destroy_ringbuffer_obj(struct intel_ring *ring)
{
i915_gem_object_put(ring->obj);
@@ -2233,7 +2233,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
goto error;
}
- ret = intel_pin_and_map_ring(dev_priv, ring);
+ ret = intel_ring_pin(ring);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
engine->name, ret);
@@ -2261,7 +2261,7 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
intel_engine_stop(engine);
WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
- intel_unpin_ring(engine->buffer);
+ intel_ring_unpin(engine->buffer);
intel_ring_free(engine->buffer);
engine->buffer = NULL;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 2dfc418c5102..ba54ffcdd55a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -441,9 +441,8 @@ intel_write_status_page(struct intel_engine_cs *engine,
struct intel_ring *
intel_engine_create_ring(struct intel_engine_cs *engine, int size);
-int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
- struct intel_ring *ring);
-void intel_unpin_ring(struct intel_ring *ring);
+int intel_ring_pin(struct intel_ring *ring);
+void intel_ring_unpin(struct intel_ring *ring);
void intel_ring_free(struct intel_ring *ring);
void intel_engine_stop(struct intel_engine_cs *engine);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (14 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 15/55] drm/i915: Rename intel_pin_and_map_ring() Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-26 5:06 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request Chris Wilson
` (40 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Space for flushing the GPU cache prior to completing the request is
preallocated and so cannot fail - the GPU caches will always be flushed
along with the completed request. This means we no longer have to track
whether the GPU cache is dirty between batches like we had to with the
outstanding_lazy_seqno.
With the removal of the duplication in the per-backend entry points for
emitting the obsolete lazy flush, we can then further unify the
engine->emit_flush.
v2: Expand a bit on the legacy of gpu_caches_dirty
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-18-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +++--
drivers/gpu/drm/i915/i915_gem_request.c | 8 ++--
drivers/gpu/drm/i915/intel_lrc.c | 47 +++----------------
drivers/gpu/drm/i915/intel_lrc.h | 2 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 72 +++++++-----------------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ---
8 files changed, 37 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 3336a5fcd029..beece8feb8fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -568,7 +568,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
* itlb_before_ctx_switch.
*/
if (IS_GEN6(dev_priv)) {
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
+ ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d0ef675fb169..35c4c595e5ba 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -998,10 +998,8 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
if (flush_domains & I915_GEM_DOMAIN_GTT)
wmb();
- /* Unconditionally invalidate gpu caches and ensure that we do flush
- * any residual writes from the previous batch.
- */
- return intel_engine_invalidate_all_caches(req);
+ /* Unconditionally invalidate GPU caches and TLBs. */
+ return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
}
static bool
@@ -1163,9 +1161,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
static void
i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
{
- /* Unconditionally force add_request to emit a full flush. */
- params->engine->gpu_caches_dirty = true;
-
/* Add a breadcrumb for the completion of the batch buffer */
__i915_add_request(params->request, params->batch_obj, true);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ebfa0406a6a1..39fa9eb10514 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1666,7 +1666,8 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = engine->emit_flush(req,
+ I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1693,7 +1694,8 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = engine->emit_flush(req,
+ I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1711,8 +1713,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
/* XXX: RCS is the only one to auto invalidate the TLBs? */
if (engine->id != RCS) {
- ret = engine->flush(req,
- I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = engine->emit_flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 942b5b1f1602..7e3206051ced 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -451,12 +451,10 @@ void __i915_add_request(struct drm_i915_gem_request *request,
* what.
*/
if (flush_caches) {
- if (i915.enable_execlists)
- ret = logical_ring_flush_all_caches(request);
- else
- ret = intel_engine_flush_all_caches(request);
+ ret = engine->emit_flush(request, 0, I915_GEM_GPU_DOMAINS);
+
/* Not allowed to fail! */
- WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
+ WARN(ret, "engine->emit_flush() failed: %d!\n", ret);
}
trace_i915_gem_request_add(request);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 86b8f41c254d..e8d971e81491 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -642,24 +642,6 @@ static void execlists_context_queue(struct drm_i915_gem_request *request)
spin_unlock_bh(&engine->execlist_lock);
}
-static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
-{
- struct intel_engine_cs *engine = req->engine;
- uint32_t flush_domains;
- int ret;
-
- flush_domains = 0;
- if (engine->gpu_caches_dirty)
- flush_domains = I915_GEM_GPU_DOMAINS;
-
- ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
- if (ret)
- return ret;
-
- engine->gpu_caches_dirty = false;
- return 0;
-}
-
static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
struct list_head *vmas)
{
@@ -690,7 +672,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
/* Unconditionally invalidate gpu caches and ensure that we do flush
* any residual writes from the previous batch.
*/
- return logical_ring_invalidate_all_caches(req);
+ return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
}
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
@@ -930,22 +912,6 @@ void intel_logical_ring_stop(struct intel_engine_cs *engine)
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
}
-int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
-{
- struct intel_engine_cs *engine = req->engine;
- int ret;
-
- if (!engine->gpu_caches_dirty)
- return 0;
-
- ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
- if (ret)
- return ret;
-
- engine->gpu_caches_dirty = false;
- return 0;
-}
-
static int intel_lr_context_pin(struct i915_gem_context *ctx,
struct intel_engine_cs *engine)
{
@@ -1026,15 +992,15 @@ void intel_lr_context_unpin(struct i915_gem_context *ctx,
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
int ret, i;
- struct intel_engine_cs *engine = req->engine;
struct intel_ring *ring = req->ring;
struct i915_workarounds *w = &req->i915->workarounds;
if (w->count == 0)
return 0;
- engine->gpu_caches_dirty = true;
- ret = logical_ring_flush_all_caches(req);
+ ret = req->engine->emit_flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1051,8 +1017,9 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
intel_ring_advance(ring);
- engine->gpu_caches_dirty = true;
- ret = logical_ring_flush_all_caches(req);
+ ret = req->engine->emit_flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index d26fb44549e5..33e0193e5451 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -72,8 +72,6 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine);
int intel_engines_init(struct drm_device *dev);
-int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
-
/* Logical Ring Contexts */
/* One extra page is added before LRC for GuC as shared data */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e7a7f67ab06d..9e4b49644553 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -688,8 +688,9 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (w->count == 0)
return 0;
- req->engine->gpu_caches_dirty = true;
- ret = intel_engine_flush_all_caches(req);
+ ret = req->engine->emit_flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -706,8 +707,9 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
intel_ring_advance(ring);
- req->engine->gpu_caches_dirty = true;
- ret = intel_engine_flush_all_caches(req);
+ ret = req->engine->emit_flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -2860,21 +2862,21 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
if (INTEL_GEN(dev_priv) >= 8) {
engine->init_context = intel_rcs_ctx_init;
engine->add_request = gen8_render_add_request;
- engine->flush = gen8_render_ring_flush;
+ engine->emit_flush = gen8_render_ring_flush;
if (i915.semaphores)
engine->semaphore.signal = gen8_rcs_signal;
} else if (INTEL_GEN(dev_priv) >= 6) {
engine->init_context = intel_rcs_ctx_init;
- engine->flush = gen7_render_ring_flush;
+ engine->emit_flush = gen7_render_ring_flush;
if (IS_GEN6(dev_priv))
- engine->flush = gen6_render_ring_flush;
+ engine->emit_flush = gen6_render_ring_flush;
} else if (IS_GEN5(dev_priv)) {
- engine->flush = gen4_render_ring_flush;
+ engine->emit_flush = gen4_render_ring_flush;
} else {
if (INTEL_GEN(dev_priv) < 4)
- engine->flush = gen2_render_ring_flush;
+ engine->emit_flush = gen2_render_ring_flush;
else
- engine->flush = gen4_render_ring_flush;
+ engine->emit_flush = gen4_render_ring_flush;
engine->irq_enable_mask = I915_USER_INTERRUPT;
}
@@ -2911,12 +2913,12 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
/* gen6 bsd needs a special wa for tail updates */
if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail;
- engine->flush = gen6_bsd_ring_flush;
+ engine->emit_flush = gen6_bsd_ring_flush;
if (INTEL_GEN(dev_priv) < 8)
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
} else {
engine->mmio_base = BSD_RING_BASE;
- engine->flush = bsd_ring_flush;
+ engine->emit_flush = bsd_ring_flush;
if (IS_GEN5(dev_priv))
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
else
@@ -2935,7 +2937,7 @@ int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
intel_ring_default_vfuncs(dev_priv, engine);
- engine->flush = gen6_bsd_ring_flush;
+ engine->emit_flush = gen6_bsd_ring_flush;
return intel_init_ring_buffer(engine);
}
@@ -2946,7 +2948,7 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
intel_ring_default_vfuncs(dev_priv, engine);
- engine->flush = gen6_ring_flush;
+ engine->emit_flush = gen6_ring_flush;
if (INTEL_GEN(dev_priv) < 8)
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
@@ -2959,7 +2961,7 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
intel_ring_default_vfuncs(dev_priv, engine);
- engine->flush = gen6_ring_flush;
+ engine->emit_flush = gen6_ring_flush;
if (INTEL_GEN(dev_priv) < 8) {
engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
@@ -2970,46 +2972,6 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
return intel_init_ring_buffer(engine);
}
-int
-intel_engine_flush_all_caches(struct drm_i915_gem_request *req)
-{
- struct intel_engine_cs *engine = req->engine;
- int ret;
-
- if (!engine->gpu_caches_dirty)
- return 0;
-
- ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
- if (ret)
- return ret;
-
- trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
-
- engine->gpu_caches_dirty = false;
- return 0;
-}
-
-int
-intel_engine_invalidate_all_caches(struct drm_i915_gem_request *req)
-{
- struct intel_engine_cs *engine = req->engine;
- uint32_t flush_domains;
- int ret;
-
- flush_domains = 0;
- if (engine->gpu_caches_dirty)
- flush_domains = I915_GEM_GPU_DOMAINS;
-
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
- if (ret)
- return ret;
-
- trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
-
- engine->gpu_caches_dirty = false;
- return 0;
-}
-
void intel_engine_stop(struct intel_engine_cs *engine)
{
int ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index ba54ffcdd55a..00723401f98c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -206,9 +206,6 @@ struct intel_engine_cs {
void (*write_tail)(struct intel_engine_cs *engine,
u32 value);
- int __must_check (*flush)(struct drm_i915_gem_request *req,
- u32 invalidate_domains,
- u32 flush_domains);
int (*add_request)(struct drm_i915_gem_request *req);
/* Some chipsets are not quite as coherent as advertised and need
* an expensive kick to force a true read of the up-to-date seqno.
@@ -325,8 +322,6 @@ struct intel_engine_cs {
*/
u32 last_submitted_seqno;
- bool gpu_caches_dirty;
-
struct i915_gem_context *last_context;
struct intel_engine_hangcheck hangcheck;
@@ -474,8 +469,6 @@ void intel_ring_update_space(struct intel_ring *ring);
int __must_check intel_engine_idle(struct intel_engine_cs *engine);
void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
-int intel_engine_flush_all_caches(struct drm_i915_gem_request *req);
-int intel_engine_invalidate_all_caches(struct drm_i915_gem_request *req);
int intel_init_pipe_control(struct intel_engine_cs *engine, int size);
void intel_fini_pipe_control(struct intel_engine_cs *engine);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (15 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-26 5:09 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 18/55] drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START Chris Wilson
` (39 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
If is simpler and leads to more readable code through the callstack if
the allocation returns the allocated struct through the return value.
The importance of this is that it no longer looks like we accidentally
allocate requests as side-effect of calling certain functions.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-19-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_gem.c | 75 ++++++++----------------------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 ++---
drivers/gpu/drm/i915/i915_gem_request.c | 58 ++++++++---------------
drivers/gpu/drm/i915/i915_trace.h | 13 +++---
drivers/gpu/drm/i915/intel_display.c | 36 ++++++--------
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_overlay.c | 20 ++++----
8 files changed, 79 insertions(+), 140 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7e298b4253e..2259983d2ec6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3171,8 +3171,7 @@ static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
- struct intel_engine_cs *to,
- struct drm_i915_gem_request **to_req);
+ struct drm_i915_gem_request *to);
void i915_vma_move_to_active(struct i915_vma *vma,
struct drm_i915_gem_request *req);
int i915_gem_dumb_create(struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 59890f523c5f..b6c4ff63725f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2845,51 +2845,35 @@ out:
static int
__i915_gem_object_sync(struct drm_i915_gem_object *obj,
- struct intel_engine_cs *to,
- struct drm_i915_gem_request *from_req,
- struct drm_i915_gem_request **to_req)
+ struct drm_i915_gem_request *to,
+ struct drm_i915_gem_request *from)
{
- struct intel_engine_cs *from;
int ret;
- from = i915_gem_request_get_engine(from_req);
- if (to == from)
+ if (to->engine == from->engine)
return 0;
- if (i915_gem_request_completed(from_req))
+ if (i915_gem_request_completed(from))
return 0;
if (!i915.semaphores) {
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
- ret = __i915_wait_request(from_req,
- i915->mm.interruptible,
+ ret = __i915_wait_request(from,
+ from->i915->mm.interruptible,
NULL,
NO_WAITBOOST);
if (ret)
return ret;
- i915_gem_object_retire_request(obj, from_req);
+ i915_gem_object_retire_request(obj, from);
} else {
- int idx = intel_engine_sync_index(from, to);
- u32 seqno = i915_gem_request_get_seqno(from_req);
+ int idx = intel_engine_sync_index(from->engine, to->engine);
+ u32 seqno = i915_gem_request_get_seqno(from);
- WARN_ON(!to_req);
-
- if (seqno <= from->semaphore.sync_seqno[idx])
+ if (seqno <= from->engine->semaphore.sync_seqno[idx])
return 0;
- if (*to_req == NULL) {
- struct drm_i915_gem_request *req;
-
- req = i915_gem_request_alloc(to, NULL);
- if (IS_ERR(req))
- return PTR_ERR(req);
-
- *to_req = req;
- }
-
- trace_i915_gem_ring_sync_to(*to_req, from, from_req);
- ret = to->semaphore.sync_to(*to_req, from, seqno);
+ trace_i915_gem_ring_sync_to(to, from);
+ ret = to->engine->semaphore.sync_to(to, from->engine, seqno);
if (ret)
return ret;
@@ -2897,8 +2881,8 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
* might have just caused seqno wrap under
* the radar.
*/
- from->semaphore.sync_seqno[idx] =
- i915_gem_request_get_seqno(obj->last_read_req[from->id]);
+ from->engine->semaphore.sync_seqno[idx] =
+ i915_gem_request_get_seqno(obj->last_read_req[from->engine->id]);
}
return 0;
@@ -2908,17 +2892,12 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
* i915_gem_object_sync - sync an object to a ring.
*
* @obj: object which may be in use on another ring.
- * @to: ring we wish to use the object on. May be NULL.
- * @to_req: request we wish to use the object for. See below.
- * This will be allocated and returned if a request is
- * required but not passed in.
+ * @to: request we are wishing to use
*
* This code is meant to abstract object synchronization with the GPU.
- * Calling with NULL implies synchronizing the object with the CPU
- * rather than a particular GPU ring. Conceptually we serialise writes
- * between engines inside the GPU. We only allow one engine to write
- * into a buffer at any time, but multiple readers. To ensure each has
- * a coherent view of memory, we must:
+ * Conceptually we serialise writes between engines inside the GPU.
+ * We only allow one engine to write into a buffer at any time, but
+ * multiple readers. To ensure each has a coherent view of memory, we must:
*
* - If there is an outstanding write request to the object, the new
* request must wait for it to complete (either CPU or in hw, requests
@@ -2927,22 +2906,11 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
* - If we are a write request (pending_write_domain is set), the new
* request must wait for outstanding read requests to complete.
*
- * For CPU synchronisation (NULL to) no request is required. For syncing with
- * rings to_req must be non-NULL. However, a request does not have to be
- * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
- * request will be allocated automatically and returned through *to_req. Note
- * that it is not guaranteed that commands will be emitted (because the system
- * might already be idle). Hence there is no need to create a request that
- * might never have any work submitted. Note further that if a request is
- * returned in *to_req, it is the responsibility of the caller to submit
- * that request (after potentially adding more work to it).
- *
* Returns 0 if successful, else propagates up the lower layer error.
*/
int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
- struct intel_engine_cs *to,
- struct drm_i915_gem_request **to_req)
+ struct drm_i915_gem_request *to)
{
const bool readonly = obj->base.pending_write_domain == 0;
struct drm_i915_gem_request *req[I915_NUM_ENGINES];
@@ -2951,9 +2919,6 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (!obj->active)
return 0;
- if (to == NULL)
- return i915_gem_object_wait_rendering(obj, readonly);
-
n = 0;
if (readonly) {
if (obj->last_write_req)
@@ -2964,7 +2929,7 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
req[n++] = obj->last_read_req[i];
}
for (i = 0; i < n; i++) {
- ret = __i915_gem_object_sync(obj, to, req[i], to_req);
+ ret = __i915_gem_object_sync(obj, to, req[i]);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 35c4c595e5ba..eacd78fc93c4 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -981,7 +981,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
struct drm_i915_gem_object *obj = vma->obj;
if (obj->active & other_rings) {
- ret = i915_gem_object_sync(obj, req->engine, &req);
+ ret = i915_gem_object_sync(obj, req);
if (ret)
return ret;
}
@@ -1427,7 +1427,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
- struct drm_i915_gem_request *req = NULL;
struct eb_vmas *eb;
struct drm_i915_gem_object *batch_obj;
struct drm_i915_gem_exec_object2 shadow_exec_entry;
@@ -1615,13 +1614,13 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
/* Allocate a request for this batch buffer nice and early. */
- req = i915_gem_request_alloc(engine, ctx);
- if (IS_ERR(req)) {
- ret = PTR_ERR(req);
+ params->request = i915_gem_request_alloc(engine, ctx);
+ if (IS_ERR(params->request)) {
+ ret = PTR_ERR(params->request);
goto err_batch_unpin;
}
- ret = i915_gem_request_add_to_client(req, file);
+ ret = i915_gem_request_add_to_client(params->request, file);
if (ret)
goto err_request;
@@ -1637,7 +1636,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
params->dispatch_flags = dispatch_flags;
params->batch_obj = batch_obj;
params->ctx = ctx;
- params->request = req;
ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
err_request:
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 7e3206051ced..47e46c9da4e7 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -292,10 +292,21 @@ static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
return 0;
}
-static inline int
-__i915_gem_request_alloc(struct intel_engine_cs *engine,
- struct i915_gem_context *ctx,
- struct drm_i915_gem_request **req_out)
+/**
+ * i915_gem_request_alloc - allocate a request structure
+ *
+ * @engine: engine that we wish to issue the request on.
+ * @ctx: context that the request will be associated with.
+ * This can be NULL if the request is not directly related to
+ * any specific user context, in which case this function will
+ * choose an appropriate context to use.
+ *
+ * Returns a pointer to the allocated request if successful,
+ * or an error code if not.
+ */
+struct drm_i915_gem_request *
+i915_gem_request_alloc(struct intel_engine_cs *engine,
+ struct i915_gem_context *ctx)
{
struct drm_i915_private *dev_priv = engine->i915;
unsigned int reset_counter = i915_reset_counter(&dev_priv->gpu_error);
@@ -303,18 +314,13 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
u32 seqno;
int ret;
- if (!req_out)
- return -EINVAL;
-
- *req_out = NULL;
-
/* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
* EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
* and restart.
*/
ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
if (ret)
- return ret;
+ return ERR_PTR(ret);
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(&engine->request_list,
@@ -324,7 +330,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
if (!req)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
ret = i915_gem_get_seqno(dev_priv, &seqno);
if (ret)
@@ -357,39 +363,13 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_ctx;
- *req_out = req;
- return 0;
+ return req;
err_ctx:
i915_gem_context_put(ctx);
err:
kmem_cache_free(dev_priv->requests, req);
- return ret;
-}
-
-/**
- * i915_gem_request_alloc - allocate a request structure
- *
- * @engine: engine that we wish to issue the request on.
- * @ctx: context that the request will be associated with.
- * This can be NULL if the request is not directly related to
- * any specific user context, in which case this function will
- * choose an appropriate context to use.
- *
- * Returns a pointer to the allocated request if successful,
- * or an error code if not.
- */
-struct drm_i915_gem_request *
-i915_gem_request_alloc(struct intel_engine_cs *engine,
- struct i915_gem_context *ctx)
-{
- struct drm_i915_gem_request *req;
- int err;
-
- if (!ctx)
- ctx = engine->i915->kernel_context;
- err = __i915_gem_request_alloc(engine, ctx, &req);
- return err ? ERR_PTR(err) : req;
+ return ERR_PTR(ret);
}
static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 007112d1e049..9e43c0aa6e3b 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -449,10 +449,9 @@ TRACE_EVENT(i915_gem_evict_vm,
);
TRACE_EVENT(i915_gem_ring_sync_to,
- TP_PROTO(struct drm_i915_gem_request *to_req,
- struct intel_engine_cs *from,
- struct drm_i915_gem_request *req),
- TP_ARGS(to_req, from, req),
+ TP_PROTO(struct drm_i915_gem_request *to,
+ struct drm_i915_gem_request *from),
+ TP_ARGS(to, from),
TP_STRUCT__entry(
__field(u32, dev)
@@ -463,9 +462,9 @@ TRACE_EVENT(i915_gem_ring_sync_to,
TP_fast_assign(
__entry->dev = from->i915->drm.primary->index;
- __entry->sync_from = from->id;
- __entry->sync_to = to_req->engine->id;
- __entry->seqno = req->fence.seqno;
+ __entry->sync_from = from->engine->id;
+ __entry->sync_to = to->engine->id;
+ __entry->seqno = from->fence.seqno;
),
TP_printk("dev=%u, sync-from=%u, sync-to=%u, seqno=%u",
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bff172c45ff7..5d4420b67642 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11583,7 +11583,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
struct intel_flip_work *work;
struct intel_engine_cs *engine;
bool mmio_flip;
- struct drm_i915_gem_request *request = NULL;
+ struct drm_i915_gem_request *request;
int ret;
/*
@@ -11690,22 +11690,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
mmio_flip = use_mmio_flip(engine, obj);
- /* When using CS flips, we want to emit semaphores between rings.
- * However, when using mmio flips we will create a task to do the
- * synchronisation, so all we want here is to pin the framebuffer
- * into the display plane and skip any waits.
- */
- if (!mmio_flip) {
- ret = i915_gem_object_sync(obj, engine, &request);
- if (!ret && !request) {
- request = i915_gem_request_alloc(engine, NULL);
- ret = PTR_ERR_OR_ZERO(request);
- }
-
- if (ret)
- goto cleanup_pending;
- }
-
ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
if (ret)
goto cleanup_pending;
@@ -11723,14 +11707,24 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
schedule_work(&work->mmio_work);
} else {
- i915_gem_request_assign(&work->flip_queued_req, request);
+ request = i915_gem_request_alloc(engine, engine->last_context);
+ if (IS_ERR(request)) {
+ ret = PTR_ERR(request);
+ goto cleanup_unpin;
+ }
+
+ ret = i915_gem_object_sync(obj, request);
+ if (ret)
+ goto cleanup_request;
+
ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
page_flip_flags);
if (ret)
- goto cleanup_unpin;
+ goto cleanup_request;
intel_mark_page_flip_active(intel_crtc, work);
+ work->flip_queued_req = i915_gem_request_get(request);
i915_add_request_no_flush(request);
}
@@ -11745,11 +11739,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
return 0;
+cleanup_request:
+ i915_add_request_no_flush(request);
cleanup_unpin:
intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
cleanup_pending:
- if (!IS_ERR_OR_NULL(request))
- i915_add_request_no_flush(request);
atomic_dec(&intel_crtc->unpin_work_count);
mutex_unlock(&dev->struct_mutex);
cleanup:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e8d971e81491..1e57f48250ce 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -655,7 +655,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
struct drm_i915_gem_object *obj = vma->obj;
if (obj->active & other_rings) {
- ret = i915_gem_object_sync(obj, req->engine, &req);
+ ret = i915_gem_object_sync(obj, req);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 8f1d4d9ef345..651efe4e468e 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -229,11 +229,18 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
return 0;
}
+static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
+{
+ struct drm_i915_private *dev_priv = overlay->i915;
+ struct intel_engine_cs *engine = &dev_priv->engine[RCS];
+
+ return i915_gem_request_alloc(engine, dev_priv->kernel_context);
+}
+
/* overlay needs to be disable in OCMD reg */
static int intel_overlay_on(struct intel_overlay *overlay)
{
struct drm_i915_private *dev_priv = overlay->i915;
- struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
struct intel_ring *ring;
int ret;
@@ -241,7 +248,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
WARN_ON(overlay->active);
WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
- req = i915_gem_request_alloc(engine, NULL);
+ req = alloc_request(overlay);
if (IS_ERR(req))
return PTR_ERR(req);
@@ -268,7 +275,6 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
bool load_polyphase_filter)
{
struct drm_i915_private *dev_priv = overlay->i915;
- struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
struct intel_ring *ring;
u32 flip_addr = overlay->flip_addr;
@@ -285,7 +291,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
if (tmp & (1 << 17))
DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
- req = i915_gem_request_alloc(engine, NULL);
+ req = alloc_request(overlay);
if (IS_ERR(req))
return PTR_ERR(req);
@@ -338,7 +344,6 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay)
static int intel_overlay_off(struct intel_overlay *overlay)
{
struct drm_i915_private *dev_priv = overlay->i915;
- struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct drm_i915_gem_request *req;
struct intel_ring *ring;
u32 flip_addr = overlay->flip_addr;
@@ -352,7 +357,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
* of the hw. Do it in both cases */
flip_addr |= OFC_UPDATE;
- req = i915_gem_request_alloc(engine, NULL);
+ req = alloc_request(overlay);
if (IS_ERR(req))
return PTR_ERR(req);
@@ -412,7 +417,6 @@ static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
{
struct drm_i915_private *dev_priv = overlay->i915;
- struct intel_engine_cs *engine = &dev_priv->engine[RCS];
int ret;
lockdep_assert_held(&dev_priv->drm.struct_mutex);
@@ -428,7 +432,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
struct drm_i915_gem_request *req;
struct intel_ring *ring;
- req = i915_gem_request_alloc(engine, NULL);
+ req = alloc_request(overlay);
if (IS_ERR(req))
return PTR_ERR(req);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 18/55] drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (16 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 19/55] drm/i915: Remove intel_ring_get_tail() Chris Wilson
` (38 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Both the ->dispatch_execbuffer and ->emit_bb_start callbacks do exactly
the same thing, add MI_BATCHBUFFER_START to the request's ringbuffer -
we need only one vfunc.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-20-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 ++--
drivers/gpu/drm/i915/i915_gem_render_state.c | 16 +++++-----
drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++++++++++++++--------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 12 +++----
5 files changed, 50 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index eacd78fc93c4..29407787b219 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1326,9 +1326,9 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
if (exec_len == 0)
exec_len = params->batch_obj->base.size;
- ret = params->engine->dispatch_execbuffer(params->request,
- exec_start, exec_len,
- params->dispatch_flags);
+ ret = params->engine->emit_bb_start(params->request,
+ exec_start, exec_len,
+ params->dispatch_flags);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index b2be4676a5cf..2ba759f3ab6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -234,18 +234,18 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
if (so.rodata == NULL)
return 0;
- ret = req->engine->dispatch_execbuffer(req, so.ggtt_offset,
- so.rodata->batch_items * 4,
- I915_DISPATCH_SECURE);
+ ret = req->engine->emit_bb_start(req, so.ggtt_offset,
+ so.rodata->batch_items * 4,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
if (so.aux_batch_size > 8) {
- ret = req->engine->dispatch_execbuffer(req,
- (so.ggtt_offset +
- so.aux_batch_offset),
- so.aux_batch_size,
- I915_DISPATCH_SECURE);
+ ret = req->engine->emit_bb_start(req,
+ (so.ggtt_offset +
+ so.aux_batch_offset),
+ so.aux_batch_size,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1e57f48250ce..80a28ebb5e06 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -859,7 +859,9 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
exec_start = params->batch_obj_vm_offset +
args->batch_start_offset;
- ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
+ ret = engine->emit_bb_start(params->request,
+ exec_start, args->batch_len,
+ params->dispatch_flags);
if (ret)
return ret;
@@ -1543,7 +1545,8 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
}
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
- u64 offset, unsigned dispatch_flags)
+ u64 offset, u32 len,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
@@ -1819,13 +1822,15 @@ static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
return 0;
ret = req->engine->emit_bb_start(req, so.ggtt_offset,
- I915_DISPATCH_SECURE);
+ so.rodata->batch_items * 4,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
ret = req->engine->emit_bb_start(req,
- (so.ggtt_offset + so.aux_batch_offset),
- I915_DISPATCH_SECURE);
+ (so.ggtt_offset + so.aux_batch_offset),
+ so.aux_batch_size,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9e4b49644553..b91dc6acb84a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1794,9 +1794,9 @@ gen8_irq_disable(struct intel_engine_cs *engine)
}
static int
-i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
- u64 offset, u32 length,
- unsigned dispatch_flags)
+i965_emit_bb_start(struct drm_i915_gem_request *req,
+ u64 offset, u32 length,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
int ret;
@@ -1821,9 +1821,9 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
#define I830_TLB_ENTRIES (2)
#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
static int
-i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
- u64 offset, u32 len,
- unsigned dispatch_flags)
+i830_emit_bb_start(struct drm_i915_gem_request *req,
+ u64 offset, u32 len,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
u32 cs_offset = req->engine->scratch.gtt_offset;
@@ -1883,9 +1883,9 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
}
static int
-i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
- u64 offset, u32 len,
- unsigned dispatch_flags)
+i915_emit_bb_start(struct drm_i915_gem_request *req,
+ u64 offset, u32 len,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
int ret;
@@ -2578,9 +2578,9 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
}
static int
-gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
- u64 offset, u32 len,
- unsigned dispatch_flags)
+gen8_emit_bb_start(struct drm_i915_gem_request *req,
+ u64 offset, u32 len,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
bool ppgtt = USES_PPGTT(req->i915) &&
@@ -2604,9 +2604,9 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
}
static int
-hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
- u64 offset, u32 len,
- unsigned dispatch_flags)
+hsw_emit_bb_start(struct drm_i915_gem_request *req,
+ u64 offset, u32 len,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
int ret;
@@ -2629,9 +2629,9 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
}
static int
-gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
- u64 offset, u32 len,
- unsigned dispatch_flags)
+gen6_emit_bb_start(struct drm_i915_gem_request *req,
+ u64 offset, u32 len,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
int ret;
@@ -2835,15 +2835,15 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
engine->add_request = gen6_add_request;
if (INTEL_GEN(dev_priv) >= 8)
- engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
+ engine->emit_bb_start = gen8_emit_bb_start;
else if (INTEL_GEN(dev_priv) >= 6)
- engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+ engine->emit_bb_start = gen6_emit_bb_start;
else if (INTEL_GEN(dev_priv) >= 4)
- engine->dispatch_execbuffer = i965_dispatch_execbuffer;
+ engine->emit_bb_start = i965_emit_bb_start;
else if (IS_I830(dev_priv) || IS_845G(dev_priv))
- engine->dispatch_execbuffer = i830_dispatch_execbuffer;
+ engine->emit_bb_start = i830_emit_bb_start;
else
- engine->dispatch_execbuffer = i915_dispatch_execbuffer;
+ engine->emit_bb_start = i915_emit_bb_start;
intel_ring_init_irq(dev_priv, engine);
intel_ring_init_semaphores(dev_priv, engine);
@@ -2881,7 +2881,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
}
if (IS_HASWELL(dev_priv))
- engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
+ engine->emit_bb_start = hsw_emit_bb_start;
engine->init_hw = init_render_ring;
engine->cleanup = render_ring_cleanup;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 00723401f98c..1ec7b47f6188 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -214,12 +214,6 @@ struct intel_engine_cs {
* monotonic, even if not coherent.
*/
void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
- int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
- u64 offset, u32 length,
- unsigned dispatch_flags);
-#define I915_DISPATCH_SECURE 0x1
-#define I915_DISPATCH_PINNED 0x2
-#define I915_DISPATCH_RS 0x4
void (*cleanup)(struct intel_engine_cs *engine);
/* GEN8 signal/wait table - never trust comments!
@@ -295,7 +289,11 @@ struct intel_engine_cs {
u32 invalidate_domains,
u32 flush_domains);
int (*emit_bb_start)(struct drm_i915_gem_request *req,
- u64 offset, unsigned dispatch_flags);
+ u64 offset, u32 length,
+ unsigned int dispatch_flags);
+#define I915_DISPATCH_SECURE 0x1
+#define I915_DISPATCH_PINNED 0x2
+#define I915_DISPATCH_RS 0x4
/**
* List of objects currently involved in rendering from the
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 19/55] drm/i915: Remove intel_ring_get_tail()
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (17 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 18/55] drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:31 ` [PATCH 20/55] drm/i915: Convert engine->write_tail to operate on a request Chris Wilson
` (37 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
Joonas doesn't like the tiny function, especially if I go around making
it more complicated and using it elsewhere. To remove that temptation,
remove the function!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-21-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_request.c | 8 ++++----
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -----
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 47e46c9da4e7..44cdca9a2194 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -419,7 +419,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
* should already have been reserved in the ring buffer. Let the ring
* know that it is time to use that space up.
*/
- request_start = intel_ring_get_tail(ring);
+ request_start = ring->tail;
reserved_tail = request->reserved_space;
request->reserved_space = 0;
@@ -464,19 +464,19 @@ void __i915_add_request(struct drm_i915_gem_request *request,
* GPU processing the request, we never over-estimate the
* position of the head.
*/
- request->postfix = intel_ring_get_tail(ring);
+ request->postfix = ring->tail;
if (i915.enable_execlists) {
ret = engine->emit_request(request);
} else {
ret = engine->add_request(request);
- request->tail = intel_ring_get_tail(ring);
+ request->tail = ring->tail;
}
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
/* Sanity check that the reserved size was large enough. */
- ret = intel_ring_get_tail(ring) - request_start;
+ ret = ring->tail - request_start;
if (ret < 0)
ret += ring->size;
WARN_ONCE(ret > reserved_tail,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1ec7b47f6188..d5a866ddaded 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -488,11 +488,6 @@ static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
int init_workarounds_ring(struct intel_engine_cs *engine);
-static inline u32 intel_ring_get_tail(struct intel_ring *ring)
-{
- return ring->tail;
-}
-
/*
* Arbitrary size for largest possible 'add request' sequence. The code paths
* are complex and variable. Empirical measurement shows that the worst case
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 20/55] drm/i915: Convert engine->write_tail to operate on a request
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (18 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 19/55] drm/i915: Remove intel_ring_get_tail() Chris Wilson
@ 2016-07-25 17:31 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 21/55] drm/i915: Unify request submission Chris Wilson
` (36 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:31 UTC (permalink / raw)
To: intel-gfx
If we rewrite the I915_WRITE_TAIL specialisation for the legacy
ringbuffer as submitting the request onto the ringbuffer, we can unify
the vfunc with both execlists and GuC in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-22-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_request.c | 8 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++++++++++++++++----------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +-
4 files changed, 32 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 44cdca9a2194..8af514e42c30 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -466,15 +466,13 @@ void __i915_add_request(struct drm_i915_gem_request *request,
*/
request->postfix = ring->tail;
- if (i915.enable_execlists) {
+ if (i915.enable_execlists)
ret = engine->emit_request(request);
- } else {
+ else
ret = engine->add_request(request);
-
- request->tail = ring->tail;
- }
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
+
/* Sanity check that the reserved size was large enough. */
ret = ring->tail - request_start;
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 80a28ebb5e06..5e08b95813fe 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -373,7 +373,7 @@ static void execlists_update_context(struct drm_i915_gem_request *rq)
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
- reg_state[CTX_RING_TAIL+1] = rq->tail;
+ reg_state[CTX_RING_TAIL+1] = rq->tail % (rq->ring->size - 1);
/* True 32b PPGTT with dynamic page allocation: update PDP
* registers and point the unallocated PDPs to scratch page.
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b91dc6acb84a..211b57614764 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -58,14 +58,6 @@ void intel_ring_update_space(struct intel_ring *ring)
ring->tail, ring->size);
}
-static void __intel_engine_submit(struct intel_engine_cs *engine)
-{
- struct intel_ring *ring = engine->buffer;
-
- ring->tail &= ring->size - 1;
- engine->write_tail(engine, ring->tail);
-}
-
static int
gen2_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
@@ -421,13 +413,6 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
return gen8_emit_pipe_control(req, flags, scratch_addr);
}
-static void ring_write_tail(struct intel_engine_cs *engine,
- u32 value)
-{
- struct drm_i915_private *dev_priv = engine->i915;
- I915_WRITE_TAIL(engine, value);
-}
-
u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -541,7 +526,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
I915_WRITE_CTL(engine, 0);
I915_WRITE_HEAD(engine, 0);
- engine->write_tail(engine, 0);
+ I915_WRITE_TAIL(engine, 0);
if (!IS_GEN2(dev_priv)) {
(void)I915_READ_CTL(engine);
@@ -1482,7 +1467,10 @@ gen6_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, req->fence.seqno);
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_engine_submit(engine);
+ intel_ring_advance(ring);
+
+ req->tail = ring->tail;
+ engine->submit_request(req);
return 0;
}
@@ -1512,7 +1500,9 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_USER_INTERRUPT);
intel_ring_emit(ring, MI_NOOP);
- __intel_engine_submit(engine);
+
+ req->tail = ring->tail;
+ engine->submit_request(req);
return 0;
}
@@ -1731,11 +1721,22 @@ i9xx_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, req->fence.seqno);
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_engine_submit(req->engine);
+ intel_ring_advance(ring);
+
+ req->tail = ring->tail;
+ req->engine->submit_request(req);
return 0;
}
+static void i9xx_submit_request(struct drm_i915_gem_request *request)
+{
+ struct drm_i915_private *dev_priv = request->i915;
+
+ I915_WRITE_TAIL(request->engine,
+ request->tail % (request->ring->size - 1));
+}
+
static void
gen6_irq_enable(struct intel_engine_cs *engine)
{
@@ -2494,10 +2495,9 @@ void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
rcu_read_unlock();
}
-static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
- u32 value)
+static void gen6_bsd_submit_request(struct drm_i915_gem_request *request)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ struct drm_i915_private *dev_priv = request->i915;
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
@@ -2521,8 +2521,9 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
/* Now that the ring is fully powered up, update the tail */
- I915_WRITE_FW(RING_TAIL(engine->mmio_base), value);
- POSTING_READ_FW(RING_TAIL(engine->mmio_base));
+ I915_WRITE_FW(RING_TAIL(request->engine->mmio_base),
+ request->tail % (request->ring->size - 1));
+ POSTING_READ_FW(RING_TAIL(request->engine->mmio_base));
/* Let the ring send IDLE messages to the GT again,
* and so let it sleep to conserve power when idle.
@@ -2828,7 +2829,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
engine->init_hw = init_ring_common;
- engine->write_tail = ring_write_tail;
+ engine->submit_request = i9xx_submit_request;
engine->add_request = i9xx_add_request;
if (INTEL_GEN(dev_priv) >= 6)
@@ -2912,7 +2913,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
if (INTEL_GEN(dev_priv) >= 6) {
/* gen6 bsd needs a special wa for tail updates */
if (IS_GEN6(dev_priv))
- engine->write_tail = gen6_bsd_ring_write_tail;
+ engine->submit_request = gen6_bsd_submit_request;
engine->emit_flush = gen6_bsd_ring_flush;
if (INTEL_GEN(dev_priv) < 8)
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index d5a866ddaded..38bea2bf9457 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -204,8 +204,6 @@ struct intel_engine_cs {
int (*init_context)(struct drm_i915_gem_request *req);
- void (*write_tail)(struct intel_engine_cs *engine,
- u32 value);
int (*add_request)(struct drm_i915_gem_request *req);
/* Some chipsets are not quite as coherent as advertised and need
* an expensive kick to force a true read of the up-to-date seqno.
@@ -294,6 +292,7 @@ struct intel_engine_cs {
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
#define I915_DISPATCH_RS 0x4
+ void (*submit_request)(struct drm_i915_gem_request *req);
/**
* List of objects currently involved in rendering from the
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 21/55] drm/i915: Unify request submission
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (19 preceding siblings ...)
2016-07-25 17:31 ` [PATCH 20/55] drm/i915: Convert engine->write_tail to operate on a request Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 22/55] drm/i915/lrc: Update function names to match request flow Chris Wilson
` (35 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Move request submission from emit_request into its own common vfunc
from i915_add_request().
v2: Convert I915_DISPATCH_flags to BIT(x) whilst passing
v3: Rename a few functions to match.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-23-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_request.c | 8 +++-----
drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++---
drivers/gpu/drm/i915/intel_guc.h | 1 -
drivers/gpu/drm/i915/intel_lrc.c | 18 +++++++-----------
drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++--------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +++++++++++------------
6 files changed, 36 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 8af514e42c30..e7f4cf559a41 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -466,12 +466,9 @@ void __i915_add_request(struct drm_i915_gem_request *request,
*/
request->postfix = ring->tail;
- if (i915.enable_execlists)
- ret = engine->emit_request(request);
- else
- ret = engine->add_request(request);
/* Not allowed to fail! */
- WARN(ret, "emit|add_request failed: %d!\n", ret);
+ ret = engine->emit_request(request);
+ WARN(ret, "(%s)->emit_request failed: %d!\n", engine->name, ret);
/* Sanity check that the reserved size was large enough. */
ret = ring->tail - request_start;
@@ -483,6 +480,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
reserved_tail, ret);
i915_gem_mark_busy(engine);
+ engine->submit_request(request);
}
static unsigned long local_clock_us(unsigned int *cpu)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index eccd34832fe6..32d0e1890950 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -585,7 +585,7 @@ static int guc_ring_doorbell(struct i915_guc_client *gc)
* The only error here arises if the doorbell hardware isn't functioning
* as expected, which really shouln't happen.
*/
-int i915_guc_submit(struct drm_i915_gem_request *rq)
+static void i915_guc_submit(struct drm_i915_gem_request *rq)
{
unsigned int engine_id = rq->engine->id;
struct intel_guc *guc = &rq->i915->guc;
@@ -602,8 +602,6 @@ int i915_guc_submit(struct drm_i915_gem_request *rq)
guc->submissions[engine_id] += 1;
guc->last_seqno[engine_id] = rq->fence.seqno;
-
- return b_ret;
}
/*
@@ -992,6 +990,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
struct i915_guc_client *client;
+ struct intel_engine_cs *engine;
/* client for execbuf submission */
client = guc_client_alloc(dev_priv,
@@ -1006,6 +1005,10 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
host2guc_sample_forcewake(guc, client);
guc_init_doorbell_hw(guc);
+ /* Take over from manual control of ELSP (execlists) */
+ for_each_engine(engine, dev_priv)
+ engine->submit_request = i915_guc_submit;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 3e3e743740c0..623cf26cd784 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -160,7 +160,6 @@ extern int intel_guc_resume(struct drm_device *dev);
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
-int i915_guc_submit(struct drm_i915_gem_request *rq);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5e08b95813fe..51818a883f0c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -738,7 +738,7 @@ err_unpin:
}
/*
- * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
+ * intel_logical_ring_advance() - advance the tail and prepare for submission
* @request: Request to advance the logical ringbuffer of.
*
* The tail is updated in our logical ringbuffer struct, not in the actual context. What
@@ -747,7 +747,7 @@ err_unpin:
* point, the tail *inside* the context is updated and the ELSP written to.
*/
static int
-intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
+intel_logical_ring_advance(struct drm_i915_gem_request *request)
{
struct intel_ring *ring = request->ring;
struct intel_engine_cs *engine = request->engine;
@@ -773,12 +773,6 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
*/
request->previous_context = engine->last_context;
engine->last_context = request->ctx;
-
- if (i915.enable_guc_submission)
- i915_guc_submit(request);
- else
- execlists_context_queue(request);
-
return 0;
}
@@ -1775,7 +1769,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
intel_ring_emit(ring, request->fence.seqno);
intel_ring_emit(ring, MI_USER_INTERRUPT);
intel_ring_emit(ring, MI_NOOP);
- return intel_logical_ring_advance_and_submit(request);
+ return intel_logical_ring_advance(request);
}
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
@@ -1806,7 +1800,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_USER_INTERRUPT);
intel_ring_emit(ring, MI_NOOP);
- return intel_logical_ring_advance_and_submit(request);
+ return intel_logical_ring_advance(request);
}
static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
@@ -1912,8 +1906,10 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
{
/* Default vfuncs which can be overriden by each engine. */
engine->init_hw = gen8_init_common_ring;
- engine->emit_request = gen8_emit_request;
engine->emit_flush = gen8_emit_flush;
+ engine->emit_request = gen8_emit_request;
+ engine->submit_request = execlists_context_queue;
+
engine->irq_enable = gen8_logical_ring_enable_irq;
engine->irq_disable = gen8_logical_ring_disable_irq;
engine->emit_bb_start = gen8_emit_bb_start;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 211b57614764..27e5f081893c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1441,15 +1441,14 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
}
/**
- * gen6_add_request - Update the semaphore mailbox registers
+ * gen6_emit_request - Update the semaphore mailbox registers
*
* @request - request to write to the ring
*
* Update the mailbox registers in the *other* rings with the current seqno.
* This acts like a signal in the canonical semaphore.
*/
-static int
-gen6_add_request(struct drm_i915_gem_request *req)
+static int gen6_emit_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
struct intel_ring *ring = req->ring;
@@ -1470,13 +1469,11 @@ gen6_add_request(struct drm_i915_gem_request *req)
intel_ring_advance(ring);
req->tail = ring->tail;
- engine->submit_request(req);
return 0;
}
-static int
-gen8_render_add_request(struct drm_i915_gem_request *req)
+static int gen8_render_emit_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
struct intel_ring *ring = req->ring;
@@ -1500,9 +1497,9 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_USER_INTERRUPT);
intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
req->tail = ring->tail;
- engine->submit_request(req);
return 0;
}
@@ -1707,8 +1704,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
return 0;
}
-static int
-i9xx_add_request(struct drm_i915_gem_request *req)
+static int i9xx_emit_request(struct drm_i915_gem_request *req)
{
struct intel_ring *ring = req->ring;
int ret;
@@ -1724,7 +1720,6 @@ i9xx_add_request(struct drm_i915_gem_request *req)
intel_ring_advance(ring);
req->tail = ring->tail;
- req->engine->submit_request(req);
return 0;
}
@@ -2829,11 +2824,11 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
engine->init_hw = init_ring_common;
- engine->submit_request = i9xx_submit_request;
- engine->add_request = i9xx_add_request;
+ engine->emit_request = i9xx_emit_request;
if (INTEL_GEN(dev_priv) >= 6)
- engine->add_request = gen6_add_request;
+ engine->emit_request = gen6_emit_request;
+ engine->submit_request = i9xx_submit_request;
if (INTEL_GEN(dev_priv) >= 8)
engine->emit_bb_start = gen8_emit_bb_start;
@@ -2862,7 +2857,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
if (INTEL_GEN(dev_priv) >= 8) {
engine->init_context = intel_rcs_ctx_init;
- engine->add_request = gen8_render_add_request;
+ engine->emit_request = gen8_render_emit_request;
engine->emit_flush = gen8_render_ring_flush;
if (i915.semaphores)
engine->semaphore.signal = gen8_rcs_signal;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 38bea2bf9457..81a41e6e6f1c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -204,7 +204,17 @@ struct intel_engine_cs {
int (*init_context)(struct drm_i915_gem_request *req);
- int (*add_request)(struct drm_i915_gem_request *req);
+ int (*emit_flush)(struct drm_i915_gem_request *request,
+ u32 invalidate_domains,
+ u32 flush_domains);
+ int (*emit_bb_start)(struct drm_i915_gem_request *req,
+ u64 offset, u32 length,
+ unsigned int dispatch_flags);
+#define I915_DISPATCH_SECURE BIT(0)
+#define I915_DISPATCH_PINNED BIT(1)
+#define I915_DISPATCH_RS BIT(2)
+ int (*emit_request)(struct drm_i915_gem_request *req);
+ void (*submit_request)(struct drm_i915_gem_request *req);
/* Some chipsets are not quite as coherent as advertised and need
* an expensive kick to force a true read of the up-to-date seqno.
* However, the up-to-date seqno is not always required and the last
@@ -282,17 +292,6 @@ struct intel_engine_cs {
unsigned int idle_lite_restore_wa;
bool disable_lite_restore_wa;
u32 ctx_desc_template;
- int (*emit_request)(struct drm_i915_gem_request *request);
- int (*emit_flush)(struct drm_i915_gem_request *request,
- u32 invalidate_domains,
- u32 flush_domains);
- int (*emit_bb_start)(struct drm_i915_gem_request *req,
- u64 offset, u32 length,
- unsigned int dispatch_flags);
-#define I915_DISPATCH_SECURE 0x1
-#define I915_DISPATCH_PINNED 0x2
-#define I915_DISPATCH_RS 0x4
- void (*submit_request)(struct drm_i915_gem_request *req);
/**
* List of objects currently involved in rendering from the
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 22/55] drm/i915/lrc: Update function names to match request flow
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (20 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 21/55] drm/i915: Unify request submission Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 23/55] drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal() Chris Wilson
` (34 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
With adding engine->submit_request, we now have a bunch of functions
with similar names used at different stages of the execlist submission.
Try a different coat of paint, to hopefully reduce confusion between the
requests, intel_engine_cs and the actual execlists submision process.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-24-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 51818a883f0c..42b50ec0719a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -384,8 +384,8 @@ static void execlists_update_context(struct drm_i915_gem_request *rq)
execlists_update_context_pdps(ppgtt, reg_state);
}
-static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
- struct drm_i915_gem_request *rq1)
+static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,
+ struct drm_i915_gem_request *rq1)
{
struct drm_i915_private *dev_priv = rq0->i915;
unsigned int fw_domains = rq0->engine->fw_domains;
@@ -418,7 +418,7 @@ static inline void execlists_context_status_change(
atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
}
-static void execlists_context_unqueue(struct intel_engine_cs *engine)
+static void execlists_unqueue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
struct drm_i915_gem_request *cursor, *tmp;
@@ -486,7 +486,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
req0->tail &= req0->ring->size - 1;
}
- execlists_submit_requests(req0, req1);
+ execlists_elsp_submit_contexts(req0, req1);
}
static unsigned int
@@ -597,7 +597,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (submit_contexts) {
if (!engine->disable_lite_restore_wa ||
(csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
- execlists_context_unqueue(engine);
+ execlists_unqueue(engine);
}
spin_unlock(&engine->execlist_lock);
@@ -606,7 +606,7 @@ static void intel_lrc_irq_handler(unsigned long data)
DRM_ERROR("More than two context complete events?\n");
}
-static void execlists_context_queue(struct drm_i915_gem_request *request)
+static void execlists_submit_request(struct drm_i915_gem_request *request)
{
struct intel_engine_cs *engine = request->engine;
struct drm_i915_gem_request *cursor;
@@ -637,7 +637,7 @@ static void execlists_context_queue(struct drm_i915_gem_request *request)
list_add_tail(&request->execlist_link, &engine->execlist_queue);
request->ctx_hw_id = request->ctx->hw_id;
if (num_elements == 0)
- execlists_context_unqueue(engine);
+ execlists_unqueue(engine);
spin_unlock_bh(&engine->execlist_lock);
}
@@ -1908,7 +1908,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->init_hw = gen8_init_common_ring;
engine->emit_flush = gen8_emit_flush;
engine->emit_request = gen8_emit_request;
- engine->submit_request = execlists_context_queue;
+ engine->submit_request = execlists_submit_request;
engine->irq_enable = gen8_logical_ring_enable_irq;
engine->irq_disable = gen8_logical_ring_disable_irq;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 23/55] drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal()
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (21 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 22/55] drm/i915/lrc: Update function names to match request flow Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 24/55] drm/i915: Reuse legacy breadcrumbs + tail emission Chris Wilson
` (33 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Rather than pass in the num_dwords that the caller wishes to use after
the signal command packet, split the breadcrumb emission into two phases
and have both the signal and breadcrumb individiually acquire space on
the ring. This makes the interface simpler for the reader, and will
simplify for patches.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-25-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 51 ++++++++++++++-------------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--
2 files changed, 23 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 27e5f081893c..fbda43841d7f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1322,10 +1322,8 @@ static void render_ring_cleanup(struct intel_engine_cs *engine)
intel_fini_pipe_control(engine);
}
-static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
- unsigned int num_dwords)
+static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req)
{
-#define MBOX_UPDATE_DWORDS 8
struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
@@ -1333,10 +1331,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
-#undef MBOX_UPDATE_DWORDS
-
- ret = intel_ring_begin(signaller_req, num_dwords);
+ ret = intel_ring_begin(signaller_req, (num_rings-1) * 8);
if (ret)
return ret;
@@ -1360,14 +1355,13 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
MI_SEMAPHORE_TARGET(waiter->hw_id));
intel_ring_emit(signaller, 0);
}
+ intel_ring_advance(signaller);
return 0;
}
-static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
- unsigned int num_dwords)
+static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req)
{
-#define MBOX_UPDATE_DWORDS 6
struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
@@ -1375,10 +1369,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
-#undef MBOX_UPDATE_DWORDS
-
- ret = intel_ring_begin(signaller_req, num_dwords);
+ ret = intel_ring_begin(signaller_req, (num_rings-1) * 6);
if (ret)
return ret;
@@ -1400,12 +1391,12 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
MI_SEMAPHORE_TARGET(waiter->hw_id));
intel_ring_emit(signaller, 0);
}
+ intel_ring_advance(signaller);
return 0;
}
-static int gen6_signal(struct drm_i915_gem_request *signaller_req,
- unsigned int num_dwords)
+static int gen6_signal(struct drm_i915_gem_request *signaller_req)
{
struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
@@ -1413,12 +1404,8 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
enum intel_engine_id id;
int ret, num_rings;
-#define MBOX_UPDATE_DWORDS 3
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
-#undef MBOX_UPDATE_DWORDS
-
- ret = intel_ring_begin(signaller_req, num_dwords);
+ ret = intel_ring_begin(signaller_req, round_up((num_rings-1) * 3, 2));
if (ret)
return ret;
@@ -1436,6 +1423,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
/* If num_dwords was rounded, make sure the tail pointer is correct */
if (num_rings % 2 == 0)
intel_ring_emit(signaller, MI_NOOP);
+ intel_ring_advance(signaller);
return 0;
}
@@ -1454,11 +1442,13 @@ static int gen6_emit_request(struct drm_i915_gem_request *req)
struct intel_ring *ring = req->ring;
int ret;
- if (engine->semaphore.signal)
- ret = engine->semaphore.signal(req, 4);
- else
- ret = intel_ring_begin(req, 4);
+ if (engine->semaphore.signal) {
+ ret = engine->semaphore.signal(req);
+ if (ret)
+ return ret;
+ }
+ ret = intel_ring_begin(req, 4);
if (ret)
return ret;
@@ -1479,10 +1469,13 @@ static int gen8_render_emit_request(struct drm_i915_gem_request *req)
struct intel_ring *ring = req->ring;
int ret;
- if (engine->semaphore.signal)
- ret = engine->semaphore.signal(req, 8);
- else
- ret = intel_ring_begin(req, 8);
+ if (engine->semaphore.signal) {
+ ret = engine->semaphore.signal(req);
+ if (ret)
+ return ret;
+ }
+
+ ret = intel_ring_begin(req, 8);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 81a41e6e6f1c..4a4fa903a748 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -278,9 +278,7 @@ struct intel_engine_cs {
int (*sync_to)(struct drm_i915_gem_request *to_req,
struct intel_engine_cs *from,
u32 seqno);
- int (*signal)(struct drm_i915_gem_request *signaller_req,
- /* num_dwords needed by caller */
- unsigned int num_dwords);
+ int (*signal)(struct drm_i915_gem_request *signaller_req);
} semaphore;
/* Execlists */
--
2.8.1
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^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 24/55] drm/i915: Reuse legacy breadcrumbs + tail emission
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (22 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 23/55] drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal() Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 25/55] drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores Chris Wilson
` (32 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
As GEN6+ is now a simple variant on the basic breadcrumbs + tail write,
reuse the common code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-26-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 74 +++++++++++++--------------------
1 file changed, 30 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fbda43841d7f..df87bb7aefbd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1428,26 +1428,19 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req)
return 0;
}
-/**
- * gen6_emit_request - Update the semaphore mailbox registers
- *
- * @request - request to write to the ring
- *
- * Update the mailbox registers in the *other* rings with the current seqno.
- * This acts like a signal in the canonical semaphore.
- */
-static int gen6_emit_request(struct drm_i915_gem_request *req)
+static void i9xx_submit_request(struct drm_i915_gem_request *request)
+{
+ struct drm_i915_private *dev_priv = request->i915;
+
+ I915_WRITE_TAIL(request->engine,
+ request->tail % (request->ring->size - 1));
+}
+
+static int i9xx_emit_request(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
struct intel_ring *ring = req->ring;
int ret;
- if (engine->semaphore.signal) {
- ret = engine->semaphore.signal(req);
- if (ret)
- return ret;
- }
-
ret = intel_ring_begin(req, 4);
if (ret)
return ret;
@@ -1463,6 +1456,27 @@ static int gen6_emit_request(struct drm_i915_gem_request *req)
return 0;
}
+/**
+ * gen6_emit_request - Update the semaphore mailbox registers
+ *
+ * @request - request to write to the ring
+ *
+ * Update the mailbox registers in the *other* rings with the current seqno.
+ * This acts like a signal in the canonical semaphore.
+ */
+static int gen6_emit_request(struct drm_i915_gem_request *req)
+{
+ if (req->engine->semaphore.signal) {
+ int ret;
+
+ ret = req->engine->semaphore.signal(req);
+ if (ret)
+ return ret;
+ }
+
+ return i9xx_emit_request(req);
+}
+
static int gen8_render_emit_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
@@ -1697,34 +1711,6 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
return 0;
}
-static int i9xx_emit_request(struct drm_i915_gem_request *req)
-{
- struct intel_ring *ring = req->ring;
- int ret;
-
- ret = intel_ring_begin(req, 4);
- if (ret)
- return ret;
-
- intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
- intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- intel_ring_emit(ring, req->fence.seqno);
- intel_ring_emit(ring, MI_USER_INTERRUPT);
- intel_ring_advance(ring);
-
- req->tail = ring->tail;
-
- return 0;
-}
-
-static void i9xx_submit_request(struct drm_i915_gem_request *request)
-{
- struct drm_i915_private *dev_priv = request->i915;
-
- I915_WRITE_TAIL(request->engine,
- request->tail % (request->ring->size - 1));
-}
-
static void
gen6_irq_enable(struct intel_engine_cs *engine)
{
--
2.8.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 25/55] drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (23 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 24/55] drm/i915: Reuse legacy breadcrumbs + tail emission Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 26/55] drm/i915: Remove duplicate golden render state init from execlists Chris Wilson
` (31 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
As gen6_emit_request() only differs from i9xx_emit_request() when
semaphores are enabled, only use the specialised vfunc in that scenario.
v2: Reorder semaphore init so as to keep engine->emit_request default
vfunc selection compact.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-27-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index df87bb7aefbd..3471e19fc784 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1457,22 +1457,20 @@ static int i9xx_emit_request(struct drm_i915_gem_request *req)
}
/**
- * gen6_emit_request - Update the semaphore mailbox registers
+ * gen6_sema_emit_request - Update the semaphore mailbox registers
*
* @request - request to write to the ring
*
* Update the mailbox registers in the *other* rings with the current seqno.
* This acts like a signal in the canonical semaphore.
*/
-static int gen6_emit_request(struct drm_i915_gem_request *req)
+static int gen6_sema_emit_request(struct drm_i915_gem_request *req)
{
- if (req->engine->semaphore.signal) {
- int ret;
+ int ret;
- ret = req->engine->semaphore.signal(req);
- if (ret)
- return ret;
- }
+ ret = req->engine->semaphore.signal(req);
+ if (ret)
+ return ret;
return i9xx_emit_request(req);
}
@@ -2802,12 +2800,15 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
+ intel_ring_init_irq(dev_priv, engine);
+ intel_ring_init_semaphores(dev_priv, engine);
+
engine->init_hw = init_ring_common;
engine->emit_request = i9xx_emit_request;
- if (INTEL_GEN(dev_priv) >= 6)
- engine->emit_request = gen6_emit_request;
engine->submit_request = i9xx_submit_request;
+ if (i915.semaphores)
+ engine->emit_request = gen6_sema_emit_request;
if (INTEL_GEN(dev_priv) >= 8)
engine->emit_bb_start = gen8_emit_bb_start;
@@ -2819,9 +2820,6 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
engine->emit_bb_start = i830_emit_bb_start;
else
engine->emit_bb_start = i915_emit_bb_start;
-
- intel_ring_init_irq(dev_priv, engine);
- intel_ring_init_semaphores(dev_priv, engine);
}
int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 26/55] drm/i915: Remove duplicate golden render state init from execlists
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (24 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 25/55] drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 27/55] drm/i915: Refactor golden render state emission to unconfuse gcc Chris Wilson
` (30 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Now that we use the same vfuncs for emitting the batch buffer in both
execlists and legacy, the golden render state initialisation is
identical between both.
v2: gcc wants so.ggtt_offset initialised (even though it is not used)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-28-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 23 +++++++++++++------
drivers/gpu/drm/i915/i915_gem_render_state.h | 18 ---------------
drivers/gpu/drm/i915/intel_lrc.c | 34 +---------------------------
drivers/gpu/drm/i915/intel_renderstate.h | 16 +++++++++----
4 files changed, 28 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 2ba759f3ab6f..a9b56d18a93b 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -28,6 +28,15 @@
#include "i915_drv.h"
#include "intel_renderstate.h"
+struct render_state {
+ const struct intel_renderstate_rodata *rodata;
+ struct drm_i915_gem_object *obj;
+ u64 ggtt_offset;
+ int gen;
+ u32 aux_batch_size;
+ u32 aux_batch_offset;
+};
+
static const struct intel_renderstate_rodata *
render_state_get_rodata(const int gen)
{
@@ -51,6 +60,7 @@ static int render_state_init(struct render_state *so,
int ret;
so->gen = INTEL_GEN(dev_priv);
+ so->ggtt_offset = 0; /* keep gcc quiet */
so->rodata = render_state_get_rodata(so->gen);
if (so->rodata == NULL)
return 0;
@@ -192,14 +202,14 @@ err_out:
#undef OUT_BATCH
-void i915_gem_render_state_fini(struct render_state *so)
+static void render_state_fini(struct render_state *so)
{
i915_gem_object_ggtt_unpin(so->obj);
i915_gem_object_put(so->obj);
}
-int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
- struct render_state *so)
+static int render_state_prepare(struct intel_engine_cs *engine,
+ struct render_state *so)
{
int ret;
@@ -215,7 +225,7 @@ int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
ret = render_state_setup(so);
if (ret) {
- i915_gem_render_state_fini(so);
+ render_state_fini(so);
return ret;
}
@@ -227,7 +237,7 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
struct render_state so;
int ret;
- ret = i915_gem_render_state_prepare(req->engine, &so);
+ ret = render_state_prepare(req->engine, &so);
if (ret)
return ret;
@@ -251,8 +261,7 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
}
i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
-
out:
- i915_gem_render_state_fini(&so);
+ render_state_fini(&so);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h b/drivers/gpu/drm/i915/i915_gem_render_state.h
index 6aaa3a10a630..c44fca8599bb 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.h
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
@@ -26,24 +26,6 @@
#include <linux/types.h>
-struct intel_renderstate_rodata {
- const u32 *reloc;
- const u32 *batch;
- const u32 batch_items;
-};
-
-struct render_state {
- const struct intel_renderstate_rodata *rodata;
- struct drm_i915_gem_object *obj;
- u64 ggtt_offset;
- int gen;
- u32 aux_batch_size;
- u32 aux_batch_offset;
-};
-
int i915_gem_render_state_init(struct drm_i915_gem_request *req);
-void i915_gem_render_state_fini(struct render_state *so);
-int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
- struct render_state *so);
#endif /* _I915_GEM_RENDER_STATE_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 42b50ec0719a..c86f8c453b6a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1803,38 +1803,6 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
return intel_logical_ring_advance(request);
}
-static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
-{
- struct render_state so;
- int ret;
-
- ret = i915_gem_render_state_prepare(req->engine, &so);
- if (ret)
- return ret;
-
- if (so.rodata == NULL)
- return 0;
-
- ret = req->engine->emit_bb_start(req, so.ggtt_offset,
- so.rodata->batch_items * 4,
- I915_DISPATCH_SECURE);
- if (ret)
- goto out;
-
- ret = req->engine->emit_bb_start(req,
- (so.ggtt_offset + so.aux_batch_offset),
- so.aux_batch_size,
- I915_DISPATCH_SECURE);
- if (ret)
- goto out;
-
- i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
-
-out:
- i915_gem_render_state_fini(&so);
- return ret;
-}
-
static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
{
int ret;
@@ -1851,7 +1819,7 @@ static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
if (ret)
DRM_ERROR("MOCS failed to program: expect performance issues.\n");
- return intel_lr_context_render_state_init(req);
+ return i915_gem_render_state_init(req);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_renderstate.h b/drivers/gpu/drm/i915/intel_renderstate.h
index 5bd69852752c..08f6fea05a2c 100644
--- a/drivers/gpu/drm/i915/intel_renderstate.h
+++ b/drivers/gpu/drm/i915/intel_renderstate.h
@@ -24,12 +24,13 @@
#ifndef _INTEL_RENDERSTATE_H
#define _INTEL_RENDERSTATE_H
-#include "i915_drv.h"
+#include <linux/types.h>
-extern const struct intel_renderstate_rodata gen6_null_state;
-extern const struct intel_renderstate_rodata gen7_null_state;
-extern const struct intel_renderstate_rodata gen8_null_state;
-extern const struct intel_renderstate_rodata gen9_null_state;
+struct intel_renderstate_rodata {
+ const u32 *reloc;
+ const u32 *batch;
+ const u32 batch_items;
+};
#define RO_RENDERSTATE(_g) \
const struct intel_renderstate_rodata gen ## _g ## _null_state = { \
@@ -38,4 +39,9 @@ extern const struct intel_renderstate_rodata gen9_null_state;
.batch_items = sizeof(gen ## _g ## _null_state_batch)/4, \
}
+extern const struct intel_renderstate_rodata gen6_null_state;
+extern const struct intel_renderstate_rodata gen7_null_state;
+extern const struct intel_renderstate_rodata gen8_null_state;
+extern const struct intel_renderstate_rodata gen9_null_state;
+
#endif /* INTEL_RENDERSTATE_H */
--
2.8.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 27/55] drm/i915: Refactor golden render state emission to unconfuse gcc
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (25 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 26/55] drm/i915: Remove duplicate golden render state init from execlists Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 28/55] drm/i915: Unify legacy/execlists submit_execbuf callbacks Chris Wilson
` (29 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
GCC was inlining the init and setup functions, but was getting itself
confused into thinking that variables could be used uninitialised. If we
do the inline for gcc, it is happy! As a bonus we shrink the code.
v2: A couple of minor tweaks from Joonas
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-29-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 95 ++++++++--------------------
1 file changed, 27 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index a9b56d18a93b..f85c5505bce2 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -32,15 +32,14 @@ struct render_state {
const struct intel_renderstate_rodata *rodata;
struct drm_i915_gem_object *obj;
u64 ggtt_offset;
- int gen;
u32 aux_batch_size;
u32 aux_batch_offset;
};
static const struct intel_renderstate_rodata *
-render_state_get_rodata(const int gen)
+render_state_get_rodata(const struct drm_i915_gem_request *req)
{
- switch (gen) {
+ switch (INTEL_GEN(req->i915)) {
case 6:
return &gen6_null_state;
case 7:
@@ -54,36 +53,6 @@ render_state_get_rodata(const int gen)
return NULL;
}
-static int render_state_init(struct render_state *so,
- struct drm_i915_private *dev_priv)
-{
- int ret;
-
- so->gen = INTEL_GEN(dev_priv);
- so->ggtt_offset = 0; /* keep gcc quiet */
- so->rodata = render_state_get_rodata(so->gen);
- if (so->rodata == NULL)
- return 0;
-
- if (so->rodata->batch_items * 4 > 4096)
- return -EINVAL;
-
- so->obj = i915_gem_object_create(&dev_priv->drm, 4096);
- if (IS_ERR(so->obj))
- return PTR_ERR(so->obj);
-
- ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0);
- if (ret)
- goto free_gem;
-
- so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj);
- return 0;
-
-free_gem:
- i915_gem_object_put(so->obj);
- return ret;
-}
-
/*
* Macro to add commands to auxiliary batch.
* This macro only checks for page overflow before inserting the commands,
@@ -106,6 +75,7 @@ static int render_state_setup(struct render_state *so)
{
struct drm_device *dev = so->obj->base.dev;
const struct intel_renderstate_rodata *rodata = so->rodata;
+ const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;
unsigned int i = 0, reloc_index = 0;
struct page *page;
u32 *d;
@@ -124,7 +94,7 @@ static int render_state_setup(struct render_state *so)
if (i * 4 == rodata->reloc[reloc_index]) {
u64 r = s + so->ggtt_offset;
s = lower_32_bits(r);
- if (so->gen >= 8) {
+ if (has_64bit_reloc) {
if (i + 1 >= rodata->batch_items ||
rodata->batch[i + 1] != 0) {
ret = -EINVAL;
@@ -202,53 +172,40 @@ err_out:
#undef OUT_BATCH
-static void render_state_fini(struct render_state *so)
-{
- i915_gem_object_ggtt_unpin(so->obj);
- i915_gem_object_put(so->obj);
-}
-
-static int render_state_prepare(struct intel_engine_cs *engine,
- struct render_state *so)
+int i915_gem_render_state_init(struct drm_i915_gem_request *req)
{
+ struct render_state so;
int ret;
- if (WARN_ON(engine->id != RCS))
+ if (WARN_ON(req->engine->id != RCS))
return -ENOENT;
- ret = render_state_init(so, engine->i915);
- if (ret)
- return ret;
-
- if (so->rodata == NULL)
+ so.rodata = render_state_get_rodata(req);
+ if (!so.rodata)
return 0;
- ret = render_state_setup(so);
- if (ret) {
- render_state_fini(so);
- return ret;
- }
-
- return 0;
-}
+ if (so.rodata->batch_items * 4 > 4096)
+ return -EINVAL;
-int i915_gem_render_state_init(struct drm_i915_gem_request *req)
-{
- struct render_state so;
- int ret;
+ so.obj = i915_gem_object_create(&req->i915->drm, 4096);
+ if (IS_ERR(so.obj))
+ return PTR_ERR(so.obj);
- ret = render_state_prepare(req->engine, &so);
+ ret = i915_gem_obj_ggtt_pin(so.obj, 4096, 0);
if (ret)
- return ret;
+ goto err_obj;
- if (so.rodata == NULL)
- return 0;
+ so.ggtt_offset = i915_gem_obj_ggtt_offset(so.obj);
+
+ ret = render_state_setup(&so);
+ if (ret)
+ goto err_unpin;
ret = req->engine->emit_bb_start(req, so.ggtt_offset,
so.rodata->batch_items * 4,
I915_DISPATCH_SECURE);
if (ret)
- goto out;
+ goto err_unpin;
if (so.aux_batch_size > 8) {
ret = req->engine->emit_bb_start(req,
@@ -257,11 +214,13 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
so.aux_batch_size,
I915_DISPATCH_SECURE);
if (ret)
- goto out;
+ goto err_unpin;
}
i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
-out:
- render_state_fini(&so);
+err_unpin:
+ i915_gem_object_ggtt_unpin(so.obj);
+err_obj:
+ i915_gem_object_put(so.obj);
return ret;
}
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 28/55] drm/i915: Unify legacy/execlists submit_execbuf callbacks
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (26 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 27/55] drm/i915: Refactor golden render state emission to unconfuse gcc Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 29/55] drm/i915: Simplify calling engine->sync_to Chris Wilson
` (28 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Now that emitting requests is identical between legacy and execlists, we
can use the same function to build up the ring for submitting to either
engine. (With the exception of i915_switch_contexts(), but in time that
will also be handled gracefully.)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-30-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 20 -----
drivers/gpu/drm/i915/i915_gem.c | 2 -
drivers/gpu/drm/i915/i915_gem_context.c | 7 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 24 ++++--
drivers/gpu/drm/i915/intel_lrc.c | 123 -----------------------------
drivers/gpu/drm/i915/intel_lrc.h | 4 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +-
7 files changed, 23 insertions(+), 163 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2259983d2ec6..4d8116ece0be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1705,18 +1705,6 @@ struct i915_virtual_gpu {
bool active;
};
-struct i915_execbuffer_params {
- struct drm_device *dev;
- struct drm_file *file;
- uint32_t dispatch_flags;
- uint32_t args_batch_start_offset;
- uint64_t batch_obj_vm_offset;
- struct intel_engine_cs *engine;
- struct drm_i915_gem_object *batch_obj;
- struct i915_gem_context *ctx;
- struct drm_i915_gem_request *request;
-};
-
/* used in computing the new watermarks state */
struct intel_wm_config {
unsigned int num_pipes_active;
@@ -2016,9 +2004,6 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
struct {
- int (*execbuf_submit)(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas);
void (*cleanup_engine)(struct intel_engine_cs *engine);
void (*stop_engine)(struct intel_engine_cs *engine);
@@ -2993,11 +2978,6 @@ int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
- struct drm_i915_gem_request *req);
-int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b6c4ff63725f..d79b949fb4c4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4534,11 +4534,9 @@ int i915_gem_init(struct drm_device *dev)
mutex_lock(&dev->struct_mutex);
if (!i915.enable_execlists) {
- dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
dev_priv->gt.cleanup_engine = intel_engine_cleanup;
dev_priv->gt.stop_engine = intel_engine_stop;
} else {
- dev_priv->gt.execbuf_submit = intel_execlists_submission;
dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
dev_priv->gt.stop_engine = intel_logical_ring_stop;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index beece8feb8fe..4e233dffb592 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -894,8 +894,9 @@ int i915_switch_context(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- WARN_ON(i915.enable_execlists);
lockdep_assert_held(&req->i915->drm.struct_mutex);
+ if (i915.enable_execlists)
+ return 0;
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -943,9 +944,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
if (IS_ERR(req))
return PTR_ERR(req);
- ret = 0;
- if (!i915.enable_execlists)
- ret = i915_switch_context(req);
+ ret = i915_switch_context(req);
i915_add_request_no_flush(req);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 29407787b219..83e76959a50c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -42,6 +42,18 @@
#define BATCH_OFFSET_BIAS (256*1024)
+struct i915_execbuffer_params {
+ struct drm_device *dev;
+ struct drm_file *file;
+ u32 dispatch_flags;
+ u32 args_batch_start_offset;
+ u32 batch_obj_vm_offset;
+ struct intel_engine_cs *engine;
+ struct drm_i915_gem_object *batch_obj;
+ struct i915_gem_context *ctx;
+ struct drm_i915_gem_request *request;
+};
+
struct eb_vmas {
struct list_head vmas;
int and;
@@ -1117,7 +1129,7 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
return ctx;
}
-void
+static void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
struct drm_i915_gem_request *req)
{
@@ -1244,10 +1256,10 @@ err:
return ERR_PTR(ret);
}
-int
-i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas)
+static int
+execbuf_submit(struct i915_execbuffer_params *params,
+ struct drm_i915_gem_execbuffer2 *args,
+ struct list_head *vmas)
{
struct drm_i915_private *dev_priv = params->request->i915;
u64 exec_start, exec_len;
@@ -1637,7 +1649,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
params->batch_obj = batch_obj;
params->ctx = ctx;
- ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
+ ret = execbuf_submit(params, args, &eb->vmas);
err_request:
i915_gem_execbuffer_retire_commands(params);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c86f8c453b6a..428901d12a12 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -642,39 +642,6 @@ static void execlists_submit_request(struct drm_i915_gem_request *request)
spin_unlock_bh(&engine->execlist_lock);
}
-static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
- struct list_head *vmas)
-{
- const unsigned other_rings = ~intel_engine_flag(req->engine);
- struct i915_vma *vma;
- uint32_t flush_domains = 0;
- bool flush_chipset = false;
- int ret;
-
- list_for_each_entry(vma, vmas, exec_list) {
- struct drm_i915_gem_object *obj = vma->obj;
-
- if (obj->active & other_rings) {
- ret = i915_gem_object_sync(obj, req);
- if (ret)
- return ret;
- }
-
- if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
- flush_chipset |= i915_gem_clflush_object(obj, false);
-
- flush_domains |= obj->base.write_domain;
- }
-
- if (flush_domains & I915_GEM_DOMAIN_GTT)
- wmb();
-
- /* Unconditionally invalidate gpu caches and ensure that we do flush
- * any residual writes from the previous batch.
- */
- return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
-}
-
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
{
struct intel_engine_cs *engine = request->engine;
@@ -776,96 +743,6 @@ intel_logical_ring_advance(struct drm_i915_gem_request *request)
return 0;
}
-/**
- * intel_execlists_submission() - submit a batchbuffer for execution, Execlists style
- * @params: execbuffer call parameters.
- * @args: execbuffer call arguments.
- * @vmas: list of vmas.
- *
- * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
- * away the submission details of the execbuffer ioctl call.
- *
- * Return: non-zero if the submission fails.
- */
-int intel_execlists_submission(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas)
-{
- struct drm_device *dev = params->dev;
- struct intel_engine_cs *engine = params->engine;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_ring *ring = params->request->ring;
- u64 exec_start;
- int instp_mode;
- u32 instp_mask;
- int ret;
-
- instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
- instp_mask = I915_EXEC_CONSTANTS_MASK;
- switch (instp_mode) {
- case I915_EXEC_CONSTANTS_REL_GENERAL:
- case I915_EXEC_CONSTANTS_ABSOLUTE:
- case I915_EXEC_CONSTANTS_REL_SURFACE:
- if (instp_mode != 0 && engine->id != RCS) {
- DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
- return -EINVAL;
- }
-
- if (instp_mode != dev_priv->relative_constants_mode) {
- if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
- DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
- return -EINVAL;
- }
-
- /* The HW changed the meaning on this bit on gen6 */
- instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
- }
- break;
- default:
- DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
- return -EINVAL;
- }
-
- if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
- DRM_DEBUG("sol reset is gen7 only\n");
- return -EINVAL;
- }
-
- ret = execlists_move_to_gpu(params->request, vmas);
- if (ret)
- return ret;
-
- if (engine->id == RCS &&
- instp_mode != dev_priv->relative_constants_mode) {
- ret = intel_ring_begin(params->request, 4);
- if (ret)
- return ret;
-
- intel_ring_emit(ring, MI_NOOP);
- intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(ring, INSTPM);
- intel_ring_emit(ring, instp_mask << 16 | instp_mode);
- intel_ring_advance(ring);
-
- dev_priv->relative_constants_mode = instp_mode;
- }
-
- exec_start = params->batch_obj_vm_offset +
- args->batch_start_offset;
-
- ret = engine->emit_bb_start(params->request,
- exec_start, args->batch_len,
- params->dispatch_flags);
- if (ret)
- return ret;
-
- trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
-
- i915_gem_execbuffer_move_to_active(vmas, params->request);
-
- return 0;
-}
-
void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *req, *tmp;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 33e0193e5451..a1d4e7f9c64c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -95,10 +95,6 @@ uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
/* Execlists */
int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
int enable_execlists);
-struct i915_execbuffer_params;
-int intel_execlists_submission(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas);
void intel_execlists_cancel_requests(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3471e19fc784..cb918d304c47 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2493,9 +2493,7 @@ static void gen6_bsd_submit_request(struct drm_i915_gem_request *request)
DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
/* Now that the ring is fully powered up, update the tail */
- I915_WRITE_FW(RING_TAIL(request->engine->mmio_base),
- request->tail % (request->ring->size - 1));
- POSTING_READ_FW(RING_TAIL(request->engine->mmio_base));
+ i9xx_submit_request(request);
/* Let the ring send IDLE messages to the GT again,
* and so let it sleep to conserve power when idle.
@@ -2806,9 +2804,9 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
engine->init_hw = init_ring_common;
engine->emit_request = i9xx_emit_request;
- engine->submit_request = i9xx_submit_request;
if (i915.semaphores)
engine->emit_request = gen6_sema_emit_request;
+ engine->submit_request = i9xx_submit_request;
if (INTEL_GEN(dev_priv) >= 8)
engine->emit_bb_start = gen8_emit_bb_start;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 29/55] drm/i915: Simplify calling engine->sync_to
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (27 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 28/55] drm/i915: Unify legacy/execlists submit_execbuf callbacks Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 30/55] drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals Chris Wilson
` (27 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Since requests can no longer be generated as a side-effect of
intel_ring_begin(), we know that the seqno will be unchanged during
ring-emission. This predicatablity then means we do not have to check
for the seqno wrapping around whilst emitting the semaphore for
engine->sync_to().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-31-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 13 ++-----
drivers/gpu/drm/i915/i915_gem_request.c | 9 +----
drivers/gpu/drm/i915/intel_ringbuffer.c | 64 ++++++++++++---------------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++-
5 files changed, 30 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4d8116ece0be..76ed215eb265 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1757,7 +1757,7 @@ struct drm_i915_private {
struct i915_gem_context *kernel_context;
struct intel_engine_cs engine[I915_NUM_ENGINES];
struct drm_i915_gem_object *semaphore_obj;
- uint32_t last_seqno, next_seqno;
+ u32 next_seqno;
struct drm_dma_handle *status_page_dmah;
struct resource mch_res;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d79b949fb4c4..3df6b485d2d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2867,22 +2867,15 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
i915_gem_object_retire_request(obj, from);
} else {
int idx = intel_engine_sync_index(from->engine, to->engine);
- u32 seqno = i915_gem_request_get_seqno(from);
-
- if (seqno <= from->engine->semaphore.sync_seqno[idx])
+ if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx])
return 0;
trace_i915_gem_ring_sync_to(to, from);
- ret = to->engine->semaphore.sync_to(to, from->engine, seqno);
+ ret = to->engine->semaphore.sync_to(to, from);
if (ret)
return ret;
- /* We use last_read_req because sync_to()
- * might have just caused seqno wrap under
- * the radar.
- */
- from->engine->semaphore.sync_seqno[idx] =
- i915_gem_request_get_seqno(obj->last_read_req[from->engine->id]);
+ from->engine->semaphore.sync_seqno[idx] = from->fence.seqno;
}
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index e7f4cf559a41..d7011185a4ee 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -264,14 +264,7 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
if (ret)
return ret;
- /* Carefully set the last_seqno value so that wrap
- * detection still works
- */
dev_priv->next_seqno = seqno;
- dev_priv->last_seqno = seqno - 1;
- if (dev_priv->last_seqno == 0)
- dev_priv->last_seqno--;
-
return 0;
}
@@ -288,7 +281,7 @@ static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
dev_priv->next_seqno = 1;
}
- *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
+ *seqno = dev_priv->next_seqno++;
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cb918d304c47..df9f8a58a519 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1509,12 +1509,6 @@ static int gen8_render_emit_request(struct drm_i915_gem_request *req)
return 0;
}
-static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
- u32 seqno)
-{
- return dev_priv->last_seqno < seqno;
-}
-
/**
* intel_ring_sync - sync the waiter to the signaller on seqno
*
@@ -1524,24 +1518,23 @@ static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
*/
static int
-gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
- struct intel_engine_cs *signaller,
- u32 seqno)
+gen8_ring_sync(struct drm_i915_gem_request *wait,
+ struct drm_i915_gem_request *signal)
{
- struct intel_ring *waiter = waiter_req->ring;
- struct drm_i915_private *dev_priv = waiter_req->i915;
- u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id);
+ struct intel_ring *waiter = wait->ring;
+ struct drm_i915_private *dev_priv = wait->i915;
+ u64 offset = GEN8_WAIT_OFFSET(wait->engine, signal->engine->id);
struct i915_hw_ppgtt *ppgtt;
int ret;
- ret = intel_ring_begin(waiter_req, 4);
+ ret = intel_ring_begin(wait, 4);
if (ret)
return ret;
intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
MI_SEMAPHORE_GLOBAL_GTT |
MI_SEMAPHORE_SAD_GTE_SDD);
- intel_ring_emit(waiter, seqno);
+ intel_ring_emit(waiter, signal->fence.seqno);
intel_ring_emit(waiter, lower_32_bits(offset));
intel_ring_emit(waiter, upper_32_bits(offset));
intel_ring_advance(waiter);
@@ -1551,48 +1544,37 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
* We do this on the i915_switch_context() following the wait and
* before the dispatch.
*/
- ppgtt = waiter_req->ctx->ppgtt;
- if (ppgtt && waiter_req->engine->id != RCS)
- ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
+ ppgtt = wait->ctx->ppgtt;
+ if (ppgtt && wait->engine->id != RCS)
+ ppgtt->pd_dirty_rings |= intel_engine_flag(wait->engine);
return 0;
}
static int
-gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
- struct intel_engine_cs *signaller,
- u32 seqno)
+gen6_ring_sync(struct drm_i915_gem_request *wait,
+ struct drm_i915_gem_request *signal)
{
- struct intel_ring *waiter = waiter_req->ring;
+ struct intel_ring *waiter = wait->ring;
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
- u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->engine->id];
+ u32 wait_mbox = signal->engine->semaphore.mbox.wait[wait->engine->id];
int ret;
- /* Throughout all of the GEM code, seqno passed implies our current
- * seqno is >= the last seqno executed. However for hardware the
- * comparison is strictly greater than.
- */
- seqno -= 1;
-
WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
- ret = intel_ring_begin(waiter_req, 4);
+ ret = intel_ring_begin(wait, 4);
if (ret)
return ret;
- /* If seqno wrap happened, omit the wait with no-ops */
- if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
- intel_ring_emit(waiter, dw1 | wait_mbox);
- intel_ring_emit(waiter, seqno);
- intel_ring_emit(waiter, 0);
- intel_ring_emit(waiter, MI_NOOP);
- } else {
- intel_ring_emit(waiter, MI_NOOP);
- intel_ring_emit(waiter, MI_NOOP);
- intel_ring_emit(waiter, MI_NOOP);
- intel_ring_emit(waiter, MI_NOOP);
- }
+ intel_ring_emit(waiter, dw1 | wait_mbox);
+ /* Throughout all of the GEM code, seqno passed implies our current
+ * seqno is >= the last seqno executed. However for hardware the
+ * comparison is strictly greater than.
+ */
+ intel_ring_emit(waiter, signal->fence.seqno - 1);
+ intel_ring_emit(waiter, 0);
+ intel_ring_emit(waiter, MI_NOOP);
intel_ring_advance(waiter);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 4a4fa903a748..350e4198f3d9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -275,9 +275,8 @@ struct intel_engine_cs {
};
/* AKA wait() */
- int (*sync_to)(struct drm_i915_gem_request *to_req,
- struct intel_engine_cs *from,
- u32 seqno);
+ int (*sync_to)(struct drm_i915_gem_request *to,
+ struct drm_i915_gem_request *from);
int (*signal)(struct drm_i915_gem_request *signaller_req);
} semaphore;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 30/55] drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (28 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 29/55] drm/i915: Simplify calling engine->sync_to Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers Chris Wilson
` (26 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
In order to be more consistent with the rest of the request construction
and ring emission, use the common names for the ring and request.
Rather than using signaler_req, waiter_req, and intel_ring *wait, we use
plain req and ring.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-32-git-send-email-chris@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 132 ++++++++++++++++----------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +-
2 files changed, 68 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index df9f8a58a519..7be7666c894e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1322,108 +1322,105 @@ static void render_ring_cleanup(struct intel_engine_cs *engine)
intel_fini_pipe_control(engine);
}
-static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req)
+static int gen8_rcs_signal(struct drm_i915_gem_request *req)
{
- struct intel_ring *signaller = signaller_req->ring;
- struct drm_i915_private *dev_priv = signaller_req->i915;
+ struct intel_ring *ring = req->ring;
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- ret = intel_ring_begin(signaller_req, (num_rings-1) * 8);
+ ret = intel_ring_begin(req, (num_rings-1) * 8);
if (ret)
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u64 gtt_offset =
- signaller_req->engine->semaphore.signal_ggtt[id];
+ u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(signaller,
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring,
PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_CS_STALL);
- intel_ring_emit(signaller, lower_32_bits(gtt_offset));
- intel_ring_emit(signaller, upper_32_bits(gtt_offset));
- intel_ring_emit(signaller, signaller_req->fence.seqno);
- intel_ring_emit(signaller, 0);
- intel_ring_emit(signaller,
+ intel_ring_emit(ring, lower_32_bits(gtt_offset));
+ intel_ring_emit(ring, upper_32_bits(gtt_offset));
+ intel_ring_emit(ring, req->fence.seqno);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring,
MI_SEMAPHORE_SIGNAL |
MI_SEMAPHORE_TARGET(waiter->hw_id));
- intel_ring_emit(signaller, 0);
+ intel_ring_emit(ring, 0);
}
- intel_ring_advance(signaller);
+ intel_ring_advance(ring);
return 0;
}
-static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req)
+static int gen8_xcs_signal(struct drm_i915_gem_request *req)
{
- struct intel_ring *signaller = signaller_req->ring;
- struct drm_i915_private *dev_priv = signaller_req->i915;
+ struct intel_ring *ring = req->ring;
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- ret = intel_ring_begin(signaller_req, (num_rings-1) * 6);
+ ret = intel_ring_begin(req, (num_rings-1) * 6);
if (ret)
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u64 gtt_offset =
- signaller_req->engine->semaphore.signal_ggtt[id];
+ u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- intel_ring_emit(signaller,
+ intel_ring_emit(ring,
(MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
- intel_ring_emit(signaller,
+ intel_ring_emit(ring,
lower_32_bits(gtt_offset) |
MI_FLUSH_DW_USE_GTT);
- intel_ring_emit(signaller, upper_32_bits(gtt_offset));
- intel_ring_emit(signaller, signaller_req->fence.seqno);
- intel_ring_emit(signaller,
+ intel_ring_emit(ring, upper_32_bits(gtt_offset));
+ intel_ring_emit(ring, req->fence.seqno);
+ intel_ring_emit(ring,
MI_SEMAPHORE_SIGNAL |
MI_SEMAPHORE_TARGET(waiter->hw_id));
- intel_ring_emit(signaller, 0);
+ intel_ring_emit(ring, 0);
}
- intel_ring_advance(signaller);
+ intel_ring_advance(ring);
return 0;
}
-static int gen6_signal(struct drm_i915_gem_request *signaller_req)
+static int gen6_signal(struct drm_i915_gem_request *req)
{
- struct intel_ring *signaller = signaller_req->ring;
- struct drm_i915_private *dev_priv = signaller_req->i915;
+ struct intel_ring *ring = req->ring;
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *useless;
enum intel_engine_id id;
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- ret = intel_ring_begin(signaller_req, round_up((num_rings-1) * 3, 2));
+ ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2));
if (ret)
return ret;
for_each_engine_id(useless, dev_priv, id) {
- i915_reg_t mbox_reg =
- signaller_req->engine->semaphore.mbox.signal[id];
+ i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id];
if (i915_mmio_reg_valid(mbox_reg)) {
- intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit_reg(signaller, mbox_reg);
- intel_ring_emit(signaller, signaller_req->fence.seqno);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit_reg(ring, mbox_reg);
+ intel_ring_emit(ring, req->fence.seqno);
}
}
/* If num_dwords was rounded, make sure the tail pointer is correct */
if (num_rings % 2 == 0)
- intel_ring_emit(signaller, MI_NOOP);
- intel_ring_advance(signaller);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -1518,64 +1515,65 @@ static int gen8_render_emit_request(struct drm_i915_gem_request *req)
*/
static int
-gen8_ring_sync(struct drm_i915_gem_request *wait,
- struct drm_i915_gem_request *signal)
+gen8_ring_sync_to(struct drm_i915_gem_request *req,
+ struct drm_i915_gem_request *signal)
{
- struct intel_ring *waiter = wait->ring;
- struct drm_i915_private *dev_priv = wait->i915;
- u64 offset = GEN8_WAIT_OFFSET(wait->engine, signal->engine->id);
+ struct intel_ring *ring = req->ring;
+ struct drm_i915_private *dev_priv = req->i915;
+ u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id);
struct i915_hw_ppgtt *ppgtt;
int ret;
- ret = intel_ring_begin(wait, 4);
+ ret = intel_ring_begin(req, 4);
if (ret)
return ret;
- intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
- MI_SEMAPHORE_GLOBAL_GTT |
- MI_SEMAPHORE_SAD_GTE_SDD);
- intel_ring_emit(waiter, signal->fence.seqno);
- intel_ring_emit(waiter, lower_32_bits(offset));
- intel_ring_emit(waiter, upper_32_bits(offset));
- intel_ring_advance(waiter);
+ intel_ring_emit(ring,
+ MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_SAD_GTE_SDD);
+ intel_ring_emit(ring, signal->fence.seqno);
+ intel_ring_emit(ring, lower_32_bits(offset));
+ intel_ring_emit(ring, upper_32_bits(offset));
+ intel_ring_advance(ring);
/* When the !RCS engines idle waiting upon a semaphore, they lose their
* pagetables and we must reload them before executing the batch.
* We do this on the i915_switch_context() following the wait and
* before the dispatch.
*/
- ppgtt = wait->ctx->ppgtt;
- if (ppgtt && wait->engine->id != RCS)
- ppgtt->pd_dirty_rings |= intel_engine_flag(wait->engine);
+ ppgtt = req->ctx->ppgtt;
+ if (ppgtt && req->engine->id != RCS)
+ ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine);
return 0;
}
static int
-gen6_ring_sync(struct drm_i915_gem_request *wait,
- struct drm_i915_gem_request *signal)
+gen6_ring_sync_to(struct drm_i915_gem_request *req,
+ struct drm_i915_gem_request *signal)
{
- struct intel_ring *waiter = wait->ring;
+ struct intel_ring *ring = req->ring;
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
- u32 wait_mbox = signal->engine->semaphore.mbox.wait[wait->engine->id];
+ u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id];
int ret;
WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
- ret = intel_ring_begin(wait, 4);
+ ret = intel_ring_begin(req, 4);
if (ret)
return ret;
- intel_ring_emit(waiter, dw1 | wait_mbox);
+ intel_ring_emit(ring, dw1 | wait_mbox);
/* Throughout all of the GEM code, seqno passed implies our current
* seqno is >= the last seqno executed. However for hardware the
* comparison is strictly greater than.
*/
- intel_ring_emit(waiter, signal->fence.seqno - 1);
- intel_ring_emit(waiter, 0);
- intel_ring_emit(waiter, MI_NOOP);
- intel_ring_advance(waiter);
+ intel_ring_emit(ring, signal->fence.seqno - 1);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -2684,7 +2682,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) >= 8) {
u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj);
- engine->semaphore.sync_to = gen8_ring_sync;
+ engine->semaphore.sync_to = gen8_ring_sync_to;
engine->semaphore.signal = gen8_xcs_signal;
for (i = 0; i < I915_NUM_ENGINES; i++) {
@@ -2698,7 +2696,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
engine->semaphore.signal_ggtt[i] = ring_offset;
}
} else if (INTEL_GEN(dev_priv) >= 6) {
- engine->semaphore.sync_to = gen6_ring_sync;
+ engine->semaphore.sync_to = gen6_ring_sync_to;
engine->semaphore.signal = gen6_signal;
/*
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 350e4198f3d9..21268d348d4e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -275,9 +275,9 @@ struct intel_engine_cs {
};
/* AKA wait() */
- int (*sync_to)(struct drm_i915_gem_request *to,
- struct drm_i915_gem_request *from);
- int (*signal)(struct drm_i915_gem_request *signaller_req);
+ int (*sync_to)(struct drm_i915_gem_request *req,
+ struct drm_i915_gem_request *signal);
+ int (*signal)(struct drm_i915_gem_request *req);
} semaphore;
/* Execlists */
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (29 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 30/55] drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 5:15 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 32/55] drm/i915: Split early global GTT initialisation Chris Wilson
` (25 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
As we can now have multiple VMA inside the global GTT (with partial
mappings, rotations, etc), it is no longer true that there may just be a
single GGTT entry and so we should walk the full vma_list to count up
the actual usage. In addition to unifying the two walkers, switch from
multiplying the object size for each vma to summing the bound vma sizes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 46 +++++++++++++++----------------------
1 file changed, 18 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index dccc72d63dd0..e9ff1ec19e61 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -335,6 +335,7 @@ static int per_file_stats(int id, void *ptr, void *data)
struct drm_i915_gem_object *obj = ptr;
struct file_stats *stats = data;
struct i915_vma *vma;
+ int bound = 0;
stats->count++;
stats->total += obj->base.size;
@@ -342,41 +343,30 @@ static int per_file_stats(int id, void *ptr, void *data)
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
- if (USES_FULL_PPGTT(obj->base.dev)) {
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
- struct i915_hw_ppgtt *ppgtt;
+ list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ if (!drm_mm_node_allocated(&vma->node))
+ continue;
- if (!drm_mm_node_allocated(&vma->node))
- continue;
+ bound++;
- if (vma->is_ggtt) {
- stats->global += obj->base.size;
- continue;
- }
-
- ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
+ if (vma->is_ggtt) {
+ stats->global += vma->node.size;
+ } else {
+ struct i915_hw_ppgtt *ppgtt
+ = container_of(vma->vm,
+ struct i915_hw_ppgtt,
+ base);
if (ppgtt->file_priv != stats->file_priv)
continue;
-
- if (obj->active) /* XXX per-vma statistic */
- stats->active += obj->base.size;
- else
- stats->inactive += obj->base.size;
-
- return 0;
- }
- } else {
- if (i915_gem_obj_ggtt_bound(obj)) {
- stats->global += obj->base.size;
- if (obj->active)
- stats->active += obj->base.size;
- else
- stats->inactive += obj->base.size;
- return 0;
}
+
+ if (obj->active) /* XXX per-vma statistic */
+ stats->active += vma->node.size;
+ else
+ stats->inactive += vma->node.size;
}
- if (!list_empty(&obj->global_list))
+ if (!bound)
stats->unbound += obj->base.size;
return 0;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 32/55] drm/i915: Split early global GTT initialisation
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (30 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 7:08 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 33/55] drm/i915: Store owning file on the i915_address_space Chris Wilson
` (24 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Initialising the global GTT is tricky as we wish to use the drm_mm range
manager during the modesetting initialisation (to capture stolen
allocations from the BIOS) before we actually enable GEM. To overcome
this, we currently setup the drm_mm first and then carefully rebind
them.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.c | 19 -------
drivers/gpu/drm/i915/i915_gem.c | 6 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 99 +++++++++++++---------------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 17 +++---
5 files changed, 50 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 83afdd0597b5..478e8168ad94 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -993,8 +993,6 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
- uint32_t aperture_size;
int ret;
if (i915_inject_load_failure())
@@ -1040,7 +1038,6 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
}
}
-
/* 965GM sometimes incorrectly writes to hardware status page (HWS)
* using 32bit addressing, overwriting memory if HWS is located
* above 4GB.
@@ -1059,19 +1056,6 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
}
}
- aperture_size = ggtt->mappable_end;
-
- ggtt->mappable =
- io_mapping_create_wc(ggtt->mappable_base,
- aperture_size);
- if (!ggtt->mappable) {
- ret = -EIO;
- goto out_ggtt;
- }
-
- ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
- aperture_size);
-
pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
@@ -1112,14 +1096,11 @@ out_ggtt:
static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
if (dev->pdev->msi_enabled)
pci_disable_msi(dev->pdev);
pm_qos_remove_request(&dev_priv->pm_qos);
- arch_phys_wc_del(ggtt->mtrr);
- io_mapping_free(ggtt->mappable);
i915_ggtt_cleanup_hw(dev);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3df6b485d2d4..a0ea1ee16f67 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4543,7 +4543,10 @@ int i915_gem_init(struct drm_device *dev)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
i915_gem_init_userptr(dev_priv);
- i915_gem_init_ggtt(dev);
+
+ ret = i915_gem_init_ggtt(dev);
+ if (ret)
+ goto out_unlock;
ret = i915_gem_context_init(dev);
if (ret)
@@ -4634,7 +4637,6 @@ i915_gem_load_init(struct drm_device *dev)
SLAB_HWCACHE_ALIGN,
NULL);
- INIT_LIST_HEAD(&dev_priv->vm_list);
INIT_LIST_HEAD(&dev_priv->context_list);
INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
INIT_LIST_HEAD(&dev_priv->mm.bound_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 39fa9eb10514..44007ec344fd 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2750,10 +2750,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node,
*end -= 4096;
}
-static int i915_gem_setup_global_gtt(struct drm_device *dev,
- u64 start,
- u64 mappable_end,
- u64 end)
+int i915_gem_init_ggtt(struct drm_device *dev)
{
/* Let GEM Manage all of the aperture.
*
@@ -2766,46 +2763,14 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
*/
struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
- struct drm_mm_node *entry;
- struct drm_i915_gem_object *obj;
unsigned long hole_start, hole_end;
+ struct drm_mm_node *entry;
int ret;
- BUG_ON(mappable_end > end);
-
- ggtt->base.start = start;
-
- /* Subtract the guard page before address space initialization to
- * shrink the range used by drm_mm */
- ggtt->base.total = end - start - PAGE_SIZE;
- i915_address_space_init(&ggtt->base, dev_priv);
- ggtt->base.total += PAGE_SIZE;
-
ret = intel_vgt_balloon(dev_priv);
if (ret)
return ret;
- if (!HAS_LLC(dev))
- ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
-
- /* Mark any preallocated objects as occupied */
- list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
- struct i915_vma *vma = i915_gem_obj_to_vma(obj, &ggtt->base);
-
- DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
- i915_gem_obj_ggtt_offset(obj), obj->base.size);
-
- WARN_ON(i915_gem_obj_ggtt_bound(obj));
- ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node);
- if (ret) {
- DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
- return ret;
- }
- vma->bound |= GLOBAL_BIND;
- __i915_vma_set_map_and_fenceable(vma);
- list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
- }
-
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
@@ -2815,9 +2780,11 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
}
/* And finally clear the reserved guard page */
- ggtt->base.clear_range(&ggtt->base, end - PAGE_SIZE, PAGE_SIZE, true);
+ ggtt->base.clear_range(&ggtt->base,
+ ggtt->base.total - PAGE_SIZE, PAGE_SIZE,
+ true);
- if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
+ if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
struct i915_hw_ppgtt *ppgtt;
ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
@@ -2853,16 +2820,21 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
return 0;
}
-/**
- * i915_gem_init_ggtt - Initialize GEM for Global GTT
- * @dev: DRM device
- */
-void i915_gem_init_ggtt(struct drm_device *dev)
+static void init_global_gtt(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_address_space *ggtt = &dev_priv->ggtt.base;
+
+ INIT_LIST_HEAD(&dev_priv->vm_list);
- i915_gem_setup_global_gtt(dev, 0, ggtt->mappable_end, ggtt->base.total);
+ /* Subtract the guard page before address space initialization to
+ * shrink the range used by drm_mm.
+ */
+ ggtt->total -= PAGE_SIZE;
+ i915_address_space_init(ggtt, dev_priv);
+ ggtt->total += PAGE_SIZE;
+
+ if (!HAS_LLC(dev_priv))
+ ggtt->mm.color_adjust = i915_gtt_color_adjust;
}
/**
@@ -2890,6 +2862,9 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
}
ggtt->base.cleanup(&ggtt->base);
+
+ arch_phys_wc_del(ggtt->mtrr);
+ io_mapping_free(ggtt->mappable);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3250,21 +3225,14 @@ int i915_ggtt_init_hw(struct drm_device *dev)
if (ret)
return ret;
- if ((ggtt->base.total - 1) >> 32) {
- DRM_ERROR("We never expected a Global GTT with more than 32bits"
- "of address space! Found %lldM!\n",
- ggtt->base.total >> 20);
- ggtt->base.total = 1ULL << 32;
- ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
- }
+ init_global_gtt(dev_priv);
- /*
- * Initialise stolen early so that we may reserve preallocated
- * objects for the BIOS to KMS transition.
- */
- ret = i915_gem_init_stolen(dev);
- if (ret)
- goto out_gtt_cleanup;
+ ggtt->mappable =
+ io_mapping_create_wc(ggtt->mappable_base, ggtt->mappable_end);
+ if (!ggtt->mappable)
+ return -EIO;
+
+ ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end);
/* GMADR is the PCI mmio aperture into the global GTT. */
DRM_INFO("Memory usable by graphics device = %lluM\n",
@@ -3276,11 +3244,18 @@ int i915_ggtt_init_hw(struct drm_device *dev)
DRM_INFO("VT-d active for gfx access\n");
#endif
+ /*
+ * Initialise stolen early so that we may reserve preallocated
+ * objects for the BIOS to KMS transition.
+ */
+ ret = i915_gem_init_stolen(dev);
+ if (ret)
+ goto out_gtt_cleanup;
+
return 0;
out_gtt_cleanup:
ggtt->base.cleanup(&ggtt->base);
-
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c4a657973cc6..c347e2a22c65 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -523,7 +523,7 @@ i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
int i915_ggtt_init_hw(struct drm_device *dev);
int i915_ggtt_enable_hw(struct drm_device *dev);
-void i915_gem_init_ggtt(struct drm_device *dev);
+int i915_gem_init_ggtt(struct drm_device *dev);
void i915_ggtt_cleanup_hw(struct drm_device *dev);
int i915_ppgtt_init_hw(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 310756c30723..9a8cc8c51077 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -698,18 +698,17 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
*/
vma->node.start = gtt_offset;
vma->node.size = size;
- if (drm_mm_initialized(&ggtt->base.mm)) {
- ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node);
- if (ret) {
- DRM_DEBUG_KMS("failed to allocate stolen GTT space\n");
- goto err;
- }
- vma->bound |= GLOBAL_BIND;
- __i915_vma_set_map_and_fenceable(vma);
- list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
+ ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node);
+ if (ret) {
+ DRM_DEBUG_KMS("failed to allocate stolen GTT space\n");
+ goto err;
}
+ vma->bound |= GLOBAL_BIND;
+ __i915_vma_set_map_and_fenceable(vma);
+ list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
+
list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
i915_gem_object_pin_pages(obj);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 33/55] drm/i915: Store owning file on the i915_address_space
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (31 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 32/55] drm/i915: Split early global GTT initialisation Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 7:15 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 34/55] drm/i915: Count how many VMA are bound for an object Chris Wilson
` (23 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
For the global GTT (and aliasing GTT), the address space is owned by the
device (it is a global resource) and so the per-file owner field is
NULL. For per-process GTT (where we create an address space per
context), each is owned by the opening file. We can use this ownership
information to both distinguish GGTT and ppGTT address spaces, as well
as occasionally inspect the owner.
v2: Whitespace, tells us who owns i915_address_space
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem_context.c | 3 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 30 +++++++++++++++---------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 17 +++++++++++------
5 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e9ff1ec19e61..2fc81865e657 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -356,7 +356,7 @@ static int per_file_stats(int id, void *ptr, void *data)
= container_of(vma->vm,
struct i915_hw_ppgtt,
base);
- if (ppgtt->file_priv != stats->file_priv)
+ if (ppgtt->base.file != stats->file_priv)
continue;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76ed215eb265..4c38307d2554 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3300,7 +3300,6 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
return container_of(vm, struct i915_hw_ppgtt, base);
}
-
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 4e233dffb592..60861f616f24 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -327,7 +327,8 @@ i915_gem_create_context(struct drm_device *dev,
return ctx;
if (USES_FULL_PPGTT(dev)) {
- struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
+ struct i915_hw_ppgtt *ppgtt =
+ i915_ppgtt_create(to_i915(dev), file_priv);
if (IS_ERR(ppgtt)) {
DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 44007ec344fd..9d493b8e3bfc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2108,11 +2108,12 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
return 0;
}
-static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
+ struct drm_i915_private *dev_priv)
{
- ppgtt->base.dev = dev;
+ ppgtt->base.dev = &dev_priv->drm;
- if (INTEL_INFO(dev)->gen < 8)
+ if (INTEL_INFO(dev_priv)->gen < 8)
return gen6_ppgtt_init(ppgtt);
else
return gen8_ppgtt_init(ppgtt);
@@ -2147,15 +2148,17 @@ static void gtt_write_workarounds(struct drm_device *dev)
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
}
-static int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
+ struct drm_i915_private *dev_priv,
+ struct drm_i915_file_private *file_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- int ret = 0;
+ int ret;
- ret = __hw_ppgtt_init(dev, ppgtt);
+ ret = __hw_ppgtt_init(ppgtt, dev_priv);
if (ret == 0) {
kref_init(&ppgtt->ref);
i915_address_space_init(&ppgtt->base, dev_priv);
+ ppgtt->base.file = file_priv;
}
return ret;
@@ -2187,7 +2190,8 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
}
struct i915_hw_ppgtt *
-i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
+i915_ppgtt_create(struct drm_i915_private *dev_priv,
+ struct drm_i915_file_private *fpriv)
{
struct i915_hw_ppgtt *ppgtt;
int ret;
@@ -2196,14 +2200,12 @@ i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ret = i915_ppgtt_init(dev, ppgtt);
+ ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv);
if (ret) {
kfree(ppgtt);
return ERR_PTR(ret);
}
- ppgtt->file_priv = fpriv;
-
trace_i915_ppgtt_create(&ppgtt->base);
return ppgtt;
@@ -2791,9 +2793,8 @@ int i915_gem_init_ggtt(struct drm_device *dev)
if (!ppgtt)
return -ENOMEM;
- ret = __hw_ppgtt_init(dev, ppgtt);
+ ret = __hw_ppgtt_init(ppgtt, dev_priv);
if (ret) {
- ppgtt->base.cleanup(&ppgtt->base);
kfree(ppgtt);
return ret;
}
@@ -3219,7 +3220,6 @@ int i915_ggtt_init_hw(struct drm_device *dev)
}
ggtt->base.dev = dev;
- ggtt->base.is_ggtt = true;
ret = ggtt->probe(ggtt);
if (ret)
@@ -3311,7 +3311,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
struct i915_hw_ppgtt *ppgtt;
- if (vm->is_ggtt)
+ if (i915_is_ggtt(vm))
ppgtt = dev_priv->mm.aliasing_ppgtt;
else
ppgtt = i915_vm_to_ppgtt(vm);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c347e2a22c65..529fb483afc8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -272,12 +272,19 @@ struct i915_pml4 {
struct i915_address_space {
struct drm_mm mm;
struct drm_device *dev;
+ /* Every address space belongs to a struct file - except for the global
+ * GTT that is owned by the driver (and so @file is set to NULL). In
+ * principle, no information should leak from one context to another
+ * (or between files/processes etc) unless explicitly shared by the
+ * owner. Tracking the owner is important in order to free up per-file
+ * objects along with the file, to aide resource tracking, and to
+ * assign blame.
+ */
+ struct drm_i915_file_private *file;
struct list_head global_link;
u64 start; /* Start offset always 0 for dri2 */
u64 total; /* size addr space maps (ex. 2GB for ggtt) */
- bool is_ggtt;
-
struct i915_page_scratch *scratch_page;
struct i915_page_table *scratch_pt;
struct i915_page_directory *scratch_pd;
@@ -338,7 +345,7 @@ struct i915_address_space {
u32 flags);
};
-#define i915_is_ggtt(V) ((V)->is_ggtt)
+#define i915_is_ggtt(V) (!(V)->file)
/* The Graphics Translation Table is the way in which GEN hardware translates a
* Graphics Virtual Address into a Physical Address. In addition to the normal
@@ -380,8 +387,6 @@ struct i915_hw_ppgtt {
struct i915_page_directory pd; /* GEN6-7 */
};
- struct drm_i915_file_private *file_priv;
-
gen6_pte_t __iomem *pd_addr;
int (*enable)(struct i915_hw_ppgtt *ppgtt);
@@ -528,7 +533,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev);
int i915_ppgtt_init_hw(struct drm_device *dev);
void i915_ppgtt_release(struct kref *kref);
-struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
+struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *fpriv);
static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
{
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 34/55] drm/i915: Count how many VMA are bound for an object
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (32 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 33/55] drm/i915: Store owning file on the i915_address_space Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 7:44 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 35/55] drm/i915: Be more careful when unbinding vma Chris Wilson
` (22 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Since we may have VMA allocated for an object, but we interrupted their
binding, there is a disparity between have elements on the obj->vma_list
and being bound. i915_gem_obj_bound_any() does this check, but this is
not rigorously observed - add an explicit count to make it easier.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++++------
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 34 +++++++++++++-------------------
drivers/gpu/drm/i915/i915_gem_shrinker.c | 17 +---------------
drivers/gpu/drm/i915/i915_gem_stolen.c | 1 +
5 files changed, 23 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2fc81865e657..b638ecea0c03 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -174,6 +174,9 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
if (obj->fence_reg != I915_FENCE_REG_NONE)
seq_printf(m, " (fence: %d)", obj->fence_reg);
list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ if (!drm_mm_node_allocated(&vma->node))
+ continue;
+
seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
vma->is_ggtt ? "g" : "pp",
vma->node.start, vma->node.size);
@@ -335,11 +338,11 @@ static int per_file_stats(int id, void *ptr, void *data)
struct drm_i915_gem_object *obj = ptr;
struct file_stats *stats = data;
struct i915_vma *vma;
- int bound = 0;
stats->count++;
stats->total += obj->base.size;
-
+ if (!obj->bind_count)
+ stats->unbound += obj->base.size;
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
@@ -347,8 +350,6 @@ static int per_file_stats(int id, void *ptr, void *data)
if (!drm_mm_node_allocated(&vma->node))
continue;
- bound++;
-
if (vma->is_ggtt) {
stats->global += vma->node.size;
} else {
@@ -366,9 +367,6 @@ static int per_file_stats(int id, void *ptr, void *data)
stats->inactive += vma->node.size;
}
- if (!bound)
- stats->unbound += obj->base.size;
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4c38307d2554..e28228c6f383 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2221,6 +2221,8 @@ struct drm_i915_gem_object {
unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
unsigned int has_wc_mmap;
+ /** Count of VMA actually bound by this object */
+ unsigned int bind_count;
unsigned int pin_display;
struct sg_table *pages;
@@ -3266,7 +3268,6 @@ i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
}
-bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
const struct i915_ggtt_view *view);
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a0ea1ee16f67..a3defd7b4046 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2107,7 +2107,7 @@ i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
if (obj->pages_pin_count)
return -EBUSY;
- BUG_ON(i915_gem_obj_bound_any(obj));
+ GEM_BUG_ON(obj->bind_count);
/* ->put_pages might need to allocate memory for the bit17 swizzle
* array, hence protect them from being reaped by removing them from gtt
@@ -2965,7 +2965,6 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
{
struct drm_i915_gem_object *obj = vma->obj;
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
int ret;
if (list_empty(&vma->obj_link))
@@ -2979,7 +2978,8 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
if (vma->pin_count)
return -EBUSY;
- BUG_ON(obj->pages == NULL);
+ GEM_BUG_ON(obj->bind_count == 0);
+ GEM_BUG_ON(!obj->pages);
if (wait) {
ret = i915_gem_object_wait_rendering(obj, false);
@@ -3019,8 +3019,9 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
/* Since the unbound list is global, only move to that list if
* no more VMAs exist. */
- if (list_empty(&obj->vma_list))
- list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
+ if (--obj->bind_count == 0)
+ list_move_tail(&obj->global_list,
+ &to_i915(obj->base.dev)->mm.unbound_list);
/* And finally now the object is completely decoupled from this vma,
* we can drop its hold on the backing storage and allow it to be
@@ -3255,6 +3256,7 @@ search_free:
list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
list_add_tail(&vma->vm_link, &vm->inactive_list);
+ obj->bind_count++;
return vma;
@@ -3450,7 +3452,6 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
{
struct drm_device *dev = obj->base.dev;
struct i915_vma *vma, *next;
- bool bound = false;
int ret = 0;
if (obj->cache_level == cache_level)
@@ -3474,8 +3475,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
ret = i915_vma_unbind(vma);
if (ret)
return ret;
- } else
- bound = true;
+ }
}
/* We can reuse the existing drm_mm nodes but need to change the
@@ -3485,7 +3485,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
* rewrite the PTE in the belief that doing so tramples upon less
* state and so involves less work.
*/
- if (bound) {
+ if (obj->bind_count) {
/* Before we change the PTE, the GPU must not be accessing it.
* If we wait upon the object, we know that all the bound
* VMA are no longer active.
@@ -3692,6 +3692,9 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
old_read_domains,
old_write_domain);
+ /* Increment the pages_pin_count to guard against the shrinker */
+ obj->pages_pin_count++;
+
return 0;
err_unpin_display:
@@ -3708,6 +3711,7 @@ i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
i915_gem_object_ggtt_unpin_view(obj, view);
+ obj->pages_pin_count--;
obj->pin_display--;
}
@@ -4223,6 +4227,7 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
dev_priv->mm.interruptible = was_interruptible;
}
}
+ GEM_BUG_ON(obj->bind_count);
/* Stolen objects don't hold a ref, but do hold pin count. Fix that up
* before progressing. */
@@ -4840,17 +4845,6 @@ bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
return false;
}
-bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
-{
- struct i915_vma *vma;
-
- list_for_each_entry(vma, &o->vma_list, obj_link)
- if (drm_mm_node_allocated(&vma->node))
- return true;
-
- return false;
-}
-
unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
{
struct i915_vma *vma;
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 5d4772c146b1..1b700afd6134 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -48,21 +48,6 @@ static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
#endif
}
-static int num_vma_bound(struct drm_i915_gem_object *obj)
-{
- struct i915_vma *vma;
- int count = 0;
-
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
- if (drm_mm_node_allocated(&vma->node))
- count++;
- if (vma->pin_count)
- count++;
- }
-
- return count;
-}
-
static bool swap_available(void)
{
return get_nr_swap_pages() > 0;
@@ -82,7 +67,7 @@ static bool can_release_pages(struct drm_i915_gem_object *obj)
* to the GPU, simply unbinding from the GPU is not going to succeed
* in releasing our pin count on the pages themselves.
*/
- if (obj->pages_pin_count != num_vma_bound(obj))
+ if (obj->pages_pin_count > obj->bind_count)
return false;
/* We can only return physical pages to the system if we can either
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 9a8cc8c51077..2c321c8df7c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -708,6 +708,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
vma->bound |= GLOBAL_BIND;
__i915_vma_set_map_and_fenceable(vma);
list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
+ obj->bind_count++;
list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
i915_gem_object_pin_pages(obj);
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 35/55] drm/i915: Be more careful when unbinding vma
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (33 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 34/55] drm/i915: Count how many VMA are bound for an object Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 7:59 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 36/55] drm/i915: Kill drop_pages() Chris Wilson
` (21 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
When we call i915_vma_unbind(), we will wait upon outstanding rendering.
This will also trigger a retirement phase, which may update the object
lists. If, we extend request tracking to the VMA itself (rather than
keep it at the encompassing object), then there is a potential that the
obj->vma_list be modified for other elements upon i915_vma_unbind(). As
a result, if we walk over the object list and call i915_vma_unbind(), we
need to be prepared for that list to change.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 57 +++++++++++++++++++++++---------
drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 +----
drivers/gpu/drm/i915/i915_gem_userptr.c | 4 +--
4 files changed, 46 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e28228c6f383..2abae63258a3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3052,6 +3052,8 @@ int __must_check i915_vma_unbind(struct i915_vma *vma);
* _guarantee_ VMA in question is _not in use_ anywhere.
*/
int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
+
+int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a3defd7b4046..9169f5f3d20c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -283,18 +283,38 @@ static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
.release = i915_gem_object_release_phys,
};
+int
+i915_gem_object_unbind(struct drm_i915_gem_object *obj)
+{
+ struct i915_vma *vma;
+ LIST_HEAD(still_in_list);
+ int ret;
+
+ /* The vma will only be freed if it is marked as closed, and if we wait
+ * upon rendering to the vma, we may unbind anything in the list.
+ */
+ while ((vma = list_first_entry_or_null(&obj->vma_list,
+ struct i915_vma,
+ obj_link))) {
+ list_move_tail(&vma->obj_link, &still_in_list);
+ ret = i915_vma_unbind(vma);
+ if (ret)
+ break;
+ }
+ list_splice(&still_in_list, &obj->vma_list);
+
+ return ret;
+}
+
static int
drop_pages(struct drm_i915_gem_object *obj)
{
- struct i915_vma *vma, *next;
int ret;
i915_gem_object_get(obj);
- list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
- if (i915_vma_unbind(vma))
- break;
-
- ret = i915_gem_object_put_pages(obj);
+ ret = i915_gem_object_unbind(obj);
+ if (ret == 0)
+ ret = i915_gem_object_put_pages(obj);
i915_gem_object_put(obj);
return ret;
@@ -3450,8 +3470,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level)
{
- struct drm_device *dev = obj->base.dev;
- struct i915_vma *vma, *next;
+ struct i915_vma *vma;
int ret = 0;
if (obj->cache_level == cache_level)
@@ -3462,7 +3481,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
* catch the issue of the CS prefetch crossing page boundaries and
* reading an invalid PTE on older architectures.
*/
- list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
+restart:
+ list_for_each_entry(vma, &obj->vma_list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -3471,11 +3491,18 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
return -EBUSY;
}
- if (!i915_gem_valid_gtt_space(vma, cache_level)) {
- ret = i915_vma_unbind(vma);
- if (ret)
- return ret;
- }
+ if (i915_gem_valid_gtt_space(vma, cache_level))
+ continue;
+
+ ret = i915_vma_unbind(vma);
+ if (ret)
+ return ret;
+
+ /* As unbinding may affect other elements in the
+ * obj->vma_list (due to side-effects from retiring
+ * an active vma), play safe and restart the iterator.
+ */
+ goto restart;
}
/* We can reuse the existing drm_mm nodes but need to change the
@@ -3494,7 +3521,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
if (ret)
return ret;
- if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
+ if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) {
/* Access to snoopable pages through the GTT is
* incoherent and on some machines causes a hard
* lockup. Relinquish the CPU mmaping to force
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 1b700afd6134..673999acc1f9 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -158,8 +158,6 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
(obj = list_first_entry_or_null(phase->list,
typeof(*obj),
global_list))) {
- struct i915_vma *vma, *v;
-
list_move_tail(&obj->global_list, &still_in_list);
if (flags & I915_SHRINK_PURGEABLE &&
@@ -179,11 +177,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
i915_gem_object_get(obj);
/* For the unbound phase, this should be a no-op! */
- list_for_each_entry_safe(vma, v,
- &obj->vma_list, obj_link)
- if (i915_vma_unbind(vma))
- break;
-
+ i915_gem_object_unbind(obj);
if (i915_gem_object_put_pages(obj) == 0)
count += obj->base.size >> PAGE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index ca8b82ab93d6..e935b327f3f9 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -104,7 +104,6 @@ static void cancel_userptr(struct work_struct *work)
if (obj->pages != NULL) {
struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_vma *vma, *tmp;
bool was_interruptible;
wait_rendering(obj);
@@ -112,8 +111,7 @@ static void cancel_userptr(struct work_struct *work)
was_interruptible = dev_priv->mm.interruptible;
dev_priv->mm.interruptible = false;
- list_for_each_entry_safe(vma, tmp, &obj->vma_list, obj_link)
- WARN_ON(i915_vma_unbind(vma));
+ WARN_ON(i915_gem_object_unbind(obj));
WARN_ON(i915_gem_object_put_pages(obj));
dev_priv->mm.interruptible = was_interruptible;
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 36/55] drm/i915: Kill drop_pages()
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (34 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 35/55] drm/i915: Be more careful when unbinding vma Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking Chris Wilson
` (20 subsequent siblings)
56 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
The drop_pages() function is a dangerous trap in that it can release the
passed in object pointer and so unless the caller is aware, it can
easily trick us into using the stale object afterwards. Move it into its
solitary callsite where we know it is safe.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 20 +++++---------------
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9169f5f3d20c..bcc05dd2be5a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -306,20 +306,6 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
return ret;
}
-static int
-drop_pages(struct drm_i915_gem_object *obj)
-{
- int ret;
-
- i915_gem_object_get(obj);
- ret = i915_gem_object_unbind(obj);
- if (ret == 0)
- ret = i915_gem_object_put_pages(obj);
- i915_gem_object_put(obj);
-
- return ret;
-}
-
int
i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int align)
@@ -340,7 +326,11 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
if (obj->base.filp == NULL)
return -EINVAL;
- ret = drop_pages(obj);
+ ret = i915_gem_object_unbind(obj);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_put_pages(obj);
if (ret)
return ret;
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (35 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 36/55] drm/i915: Kill drop_pages() Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 8:23 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations Chris Wilson
` (19 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
In the next patch, request tracking is made more generic and for that we
need a new expanded struct and to separate out the logic changes from
the mechanical churn, we split out the structure renaming into this
patch.
v2: Writer's block. Add some spiel about why we track requests.
v3: Now i915_gem_active.
v4: Now with i915_gem_active_set() for attaching to the active request.
v5: Use i915_gem_active_set() from inside the retirement handlers
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +++---
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/i915_gem.c | 58 +++++++++++++++---------------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +--
drivers/gpu/drm/i915/i915_gem_fence.c | 6 ++--
drivers/gpu/drm/i915/i915_gem_request.h | 41 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 7 ++--
drivers/gpu/drm/i915/intel_display.c | 8 ++---
10 files changed, 93 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b638ecea0c03..f67892215136 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -155,10 +155,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
obj->base.write_domain);
for_each_engine_id(engine, dev_priv, id)
seq_printf(m, "%x ",
- i915_gem_request_get_seqno(obj->last_read_req[id]));
+ i915_gem_request_get_seqno(obj->last_read[id].request));
seq_printf(m, "] %x %x%s%s%s",
- i915_gem_request_get_seqno(obj->last_write_req),
- i915_gem_request_get_seqno(obj->last_fenced_req),
+ i915_gem_request_get_seqno(obj->last_write.request),
+ i915_gem_request_get_seqno(obj->last_fence.request),
i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
@@ -195,9 +195,8 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
*t = '\0';
seq_printf(m, " (%s mappable)", s);
}
- if (obj->last_write_req != NULL)
- seq_printf(m, " (%s)",
- i915_gem_request_get_engine(obj->last_write_req)->name);
+ if (obj->last_write.request)
+ seq_printf(m, " (%s)", obj->last_write.request->engine->name);
if (obj->frontbuffer_bits)
seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2abae63258a3..76b5611aba9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2242,11 +2242,10 @@ struct drm_i915_gem_object {
* requests on one ring where the write request is older than the
* read request. This allows for the CPU to read from an active
* buffer by only waiting for the write to complete.
- * */
- struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
- struct drm_i915_gem_request *last_write_req;
- /** Breadcrumb of last fenced GPU access to the buffer. */
- struct drm_i915_gem_request *last_fenced_req;
+ */
+ struct i915_gem_active last_read[I915_NUM_ENGINES];
+ struct i915_gem_active last_write;
+ struct i915_gem_active last_fence;
/** Current tiling stride for the object, if it's tiled. */
uint32_t stride;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bcc05dd2be5a..98dc97c8c2bf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1353,23 +1353,23 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
int ret, i;
if (readonly) {
- if (obj->last_write_req != NULL) {
- ret = i915_wait_request(obj->last_write_req);
+ if (obj->last_write.request) {
+ ret = i915_wait_request(obj->last_write.request);
if (ret)
return ret;
- i = obj->last_write_req->engine->id;
- if (obj->last_read_req[i] == obj->last_write_req)
+ i = obj->last_write.request->engine->id;
+ if (obj->last_read[i].request == obj->last_write.request)
i915_gem_object_retire__read(obj, i);
else
i915_gem_object_retire__write(obj);
}
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
- if (obj->last_read_req[i] == NULL)
+ if (!obj->last_read[i].request)
continue;
- ret = i915_wait_request(obj->last_read_req[i]);
+ ret = i915_wait_request(obj->last_read[i].request);
if (ret)
return ret;
@@ -1397,9 +1397,9 @@ i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
{
int idx = req->engine->id;
- if (obj->last_read_req[idx] == req)
+ if (obj->last_read[idx].request == req)
i915_gem_object_retire__read(obj, idx);
- else if (obj->last_write_req == req)
+ else if (obj->last_write.request == req)
i915_gem_object_retire__write(obj);
if (!i915_reset_in_progress(&req->i915->gpu_error))
@@ -1428,7 +1428,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
if (readonly) {
struct drm_i915_gem_request *req;
- req = obj->last_write_req;
+ req = obj->last_write.request;
if (req == NULL)
return 0;
@@ -1437,7 +1437,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = obj->last_read_req[i];
+ req = obj->last_read[i].request;
if (req == NULL)
continue;
@@ -2375,7 +2375,7 @@ void i915_vma_move_to_active(struct i915_vma *vma,
obj->active |= intel_engine_flag(engine);
list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
- i915_gem_request_assign(&obj->last_read_req[engine->id], req);
+ i915_gem_active_set(&obj->last_read[engine->id], req);
list_move_tail(&vma->vm_link, &vma->vm->active_list);
}
@@ -2383,10 +2383,10 @@ void i915_vma_move_to_active(struct i915_vma *vma,
static void
i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
{
- GEM_BUG_ON(obj->last_write_req == NULL);
- GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
+ GEM_BUG_ON(!obj->last_write.request);
+ GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write.request->engine)));
- i915_gem_request_assign(&obj->last_write_req, NULL);
+ i915_gem_active_set(&obj->last_write, NULL);
intel_fb_obj_flush(obj, true, ORIGIN_CS);
}
@@ -2395,13 +2395,13 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
{
struct i915_vma *vma;
- GEM_BUG_ON(obj->last_read_req[idx] == NULL);
+ GEM_BUG_ON(!obj->last_read[idx].request);
GEM_BUG_ON(!(obj->active & (1 << idx)));
list_del_init(&obj->engine_list[idx]);
- i915_gem_request_assign(&obj->last_read_req[idx], NULL);
+ i915_gem_active_set(&obj->last_read[idx], NULL);
- if (obj->last_write_req && obj->last_write_req->engine->id == idx)
+ if (obj->last_write.request && obj->last_write.request->engine->id == idx)
i915_gem_object_retire__write(obj);
obj->active &= ~(1 << idx);
@@ -2420,7 +2420,7 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
}
- i915_gem_request_assign(&obj->last_fenced_req, NULL);
+ i915_gem_active_set(&obj->last_fence, NULL);
i915_gem_object_put(obj);
}
@@ -2621,7 +2621,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
struct drm_i915_gem_object,
engine_list[engine->id]);
- if (!list_empty(&obj->last_read_req[engine->id]->list))
+ if (!list_empty(&obj->last_read[engine->id].request->list))
break;
i915_gem_object_retire__read(obj, engine->id);
@@ -2754,7 +2754,7 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = obj->last_read_req[i];
+ req = obj->last_read[i].request;
if (req == NULL)
continue;
@@ -2830,10 +2830,10 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
i915_gem_object_put(obj);
for (i = 0; i < I915_NUM_ENGINES; i++) {
- if (obj->last_read_req[i] == NULL)
+ if (!obj->last_read[i].request)
continue;
- req[n++] = i915_gem_request_get(obj->last_read_req[i]);
+ req[n++] = i915_gem_request_get(obj->last_read[i].request);
}
mutex_unlock(&dev->struct_mutex);
@@ -2924,12 +2924,12 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
n = 0;
if (readonly) {
- if (obj->last_write_req)
- req[n++] = obj->last_write_req;
+ if (obj->last_write.request)
+ req[n++] = obj->last_write.request;
} else {
for (i = 0; i < I915_NUM_ENGINES; i++)
- if (obj->last_read_req[i])
- req[n++] = obj->last_read_req[i];
+ if (obj->last_read[i].request)
+ req[n++] = obj->last_read[i].request;
}
for (i = 0; i < n; i++) {
ret = __i915_gem_object_sync(obj, to, req[i]);
@@ -4030,12 +4030,12 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = obj->last_read_req[i];
+ req = obj->last_read[i].request;
if (req)
args->busy |= 1 << (16 + req->engine->exec_id);
}
- if (obj->last_write_req)
- args->busy |= obj->last_write_req->engine->exec_id;
+ if (obj->last_write.request)
+ args->busy |= obj->last_write.request->engine->exec_id;
}
unref:
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 83e76959a50c..e1dfdbd8fc2e 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1150,7 +1150,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
i915_vma_move_to_active(vma, req);
if (obj->base.write_domain) {
- i915_gem_request_assign(&obj->last_write_req, req);
+ i915_gem_active_set(&obj->last_write, req);
intel_fb_obj_invalidate(obj, ORIGIN_CS);
@@ -1158,7 +1158,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
}
if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
- i915_gem_request_assign(&obj->last_fenced_req, req);
+ i915_gem_active_set(&obj->last_fence, req);
if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
struct drm_i915_private *dev_priv = engine->i915;
list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 251d7a95af89..d16b385e79e9 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -261,12 +261,12 @@ static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
static int
i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
{
- if (obj->last_fenced_req) {
- int ret = i915_wait_request(obj->last_fenced_req);
+ if (obj->last_fence.request) {
+ int ret = i915_wait_request(obj->last_fence.request);
if (ret)
return ret;
- i915_gem_request_assign(&obj->last_fenced_req, NULL);
+ i915_gem_active_set(&obj->last_fence, NULL);
}
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index 382ca5a163eb..5d2ea5ee03c2 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -249,4 +249,45 @@ static inline bool i915_spin_request(const struct drm_i915_gem_request *request,
__i915_spin_request(request, state, timeout_us));
}
+/* We treat requests as fences. This is not be to confused with our
+ * "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
+ * We use the fences to synchronize access from the CPU with activity on the
+ * GPU, for example, we should not rewrite an object's PTE whilst the GPU
+ * is reading them. We also track fences at a higher level to provide
+ * implicit synchronisation around GEM objects, e.g. set-domain will wait
+ * for outstanding GPU rendering before marking the object ready for CPU
+ * access, or a pageflip will wait until the GPU is complete before showing
+ * the frame on the scanout.
+ *
+ * In order to use a fence, the object must track the fence it needs to
+ * serialise with. For example, GEM objects want to track both read and
+ * write access so that we can perform concurrent read operations between
+ * the CPU and GPU engines, as well as waiting for all rendering to
+ * complete, or waiting for the last GPU user of a "fence register". The
+ * object then embeds a @i915_gem_active to track the most recent (in
+ * retirment order) request relevant for the desired mode of access.
+ * The @i915_gem_active is updated with i915_gem_request_mark_active() to
+ * track the most recent fence request, typically this is done as part of
+ * i915_vma_move_to_active().
+ *
+ * When the @i915_gem_active completes (is retired), it will
+ * signal its completion to the owner through a callback as well as mark
+ * itself as idle (i915_gem_active.request == NULL). The owner
+ * can then perform any action, such as delayed freeing of an active
+ * resource including itself.
+ */
+struct i915_gem_active {
+ struct drm_i915_gem_request *request;
+};
+
+static inline void
+i915_gem_active_set(struct i915_gem_active *active,
+ struct drm_i915_gem_request *request)
+{
+ i915_gem_request_assign(&active->request, request);
+}
+
+#define for_each_active(mask, idx) \
+ for (; mask ? idx = ffs(mask) - 1, 1 : 0; mask &= ~(1 << idx))
+
#endif /* I915_GEM_REQUEST_H */
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index e83fc2d0433c..00d796da65fb 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -242,7 +242,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
}
obj->fence_dirty =
- obj->last_fenced_req ||
+ obj->last_fence.request ||
obj->fence_reg != I915_FENCE_REG_NONE;
obj->tiling_mode = args->tiling_mode;
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index e935b327f3f9..32f50a70ea42 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -74,7 +74,7 @@ static void wait_rendering(struct drm_i915_gem_object *obj)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = obj->last_read_req[i];
+ req = obj->last_read[i].request;
if (req == NULL)
continue;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3d40b1dffc73..b0e75b3de44a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -756,8 +756,8 @@ static void capture_bo(struct drm_i915_error_buffer *err,
err->size = obj->base.size;
err->name = obj->base.name;
for (i = 0; i < I915_NUM_ENGINES; i++)
- err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
- err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
+ err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read[i].request);
+ err->wseqno = i915_gem_request_get_seqno(obj->last_write.request);
err->gtt_offset = vma->node.start;
err->read_domains = obj->base.read_domains;
err->write_domain = obj->base.write_domain;
@@ -769,8 +769,7 @@ static void capture_bo(struct drm_i915_error_buffer *err,
err->dirty = obj->dirty;
err->purgeable = obj->madv != I915_MADV_WILLNEED;
err->userptr = obj->userptr.mm != NULL;
- err->engine = obj->last_write_req ?
- i915_gem_request_get_engine(obj->last_write_req)->id : -1;
+ err->engine = obj->last_write.request ? obj->last_write.request->engine->id : -1;
err->cache_level = obj->cache_level;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5d4420b67642..bc204d103674 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11378,7 +11378,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
if (resv && !reservation_object_test_signaled_rcu(resv, false))
return true;
- return engine != i915_gem_request_get_engine(obj->last_write_req);
+ return engine != i915_gem_request_get_engine(obj->last_write.request);
}
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
@@ -11681,7 +11681,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
engine = &dev_priv->engine[BCS];
} else if (INTEL_INFO(dev)->gen >= 7) {
- engine = i915_gem_request_get_engine(obj->last_write_req);
+ engine = i915_gem_request_get_engine(obj->last_write.request);
if (engine == NULL || engine->id != RCS)
engine = &dev_priv->engine[BCS];
} else {
@@ -11703,7 +11703,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
i915_gem_request_assign(&work->flip_queued_req,
- obj->last_write_req);
+ obj->last_write.request);
schedule_work(&work->mmio_work);
} else {
@@ -14051,7 +14051,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
to_intel_plane_state(new_state);
i915_gem_request_assign(&plane_state->wait_req,
- obj->last_write_req);
+ obj->last_write.request);
}
return ret;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (36 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 8:50 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation Chris Wilson
` (18 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
In the future, we will want to add annotations to the i915_gem_active
struct. The API is thus expanded to hide direct access to the contents
of i915_gem_active and mediated instead through a number of helpers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 ++--
drivers/gpu/drm/i915/i915_gem.c | 85 ++++++++++++---------
drivers/gpu/drm/i915/i915_gem_fence.c | 11 ++-
drivers/gpu/drm/i915/i915_gem_request.h | 131 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 8 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 9 ++-
drivers/gpu/drm/i915/intel_display.c | 15 ++--
8 files changed, 206 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f67892215136..b41561bdfb85 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -155,10 +155,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
obj->base.write_domain);
for_each_engine_id(engine, dev_priv, id)
seq_printf(m, "%x ",
- i915_gem_request_get_seqno(obj->last_read[id].request));
+ i915_gem_active_get_seqno(&obj->last_read[id]));
seq_printf(m, "] %x %x%s%s%s",
- i915_gem_request_get_seqno(obj->last_write.request),
- i915_gem_request_get_seqno(obj->last_fence.request),
+ i915_gem_active_get_seqno(&obj->last_write),
+ i915_gem_active_get_seqno(&obj->last_fence),
i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
@@ -195,8 +195,11 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
*t = '\0';
seq_printf(m, " (%s mappable)", s);
}
- if (obj->last_write.request)
- seq_printf(m, " (%s)", obj->last_write.request->engine->name);
+
+ engine = i915_gem_active_get_engine(&obj->last_write);
+ if (engine)
+ seq_printf(m, " (%s)", engine->name);
+
if (obj->frontbuffer_bits)
seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 98dc97c8c2bf..b8d541f212ff 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1349,27 +1349,30 @@ int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
bool readonly)
{
+ struct drm_i915_gem_request *request;
struct reservation_object *resv;
int ret, i;
if (readonly) {
- if (obj->last_write.request) {
- ret = i915_wait_request(obj->last_write.request);
+ request = i915_gem_active_peek(&obj->last_write);
+ if (request) {
+ ret = i915_wait_request(request);
if (ret)
return ret;
- i = obj->last_write.request->engine->id;
- if (obj->last_read[i].request == obj->last_write.request)
+ i = request->engine->id;
+ if (i915_gem_active_peek(&obj->last_read[i]) == request)
i915_gem_object_retire__read(obj, i);
else
i915_gem_object_retire__write(obj);
}
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
- if (!obj->last_read[i].request)
+ request = i915_gem_active_peek(&obj->last_read[i]);
+ if (!request)
continue;
- ret = i915_wait_request(obj->last_read[i].request);
+ ret = i915_wait_request(request);
if (ret)
return ret;
@@ -1397,9 +1400,9 @@ i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
{
int idx = req->engine->id;
- if (obj->last_read[idx].request == req)
+ if (i915_gem_active_peek(&obj->last_read[idx]) == req)
i915_gem_object_retire__read(obj, idx);
- else if (obj->last_write.request == req)
+ else if (i915_gem_active_peek(&obj->last_write) == req)
i915_gem_object_retire__write(obj);
if (!i915_reset_in_progress(&req->i915->gpu_error))
@@ -1428,20 +1431,20 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
if (readonly) {
struct drm_i915_gem_request *req;
- req = obj->last_write.request;
+ req = i915_gem_active_get(&obj->last_write);
if (req == NULL)
return 0;
- requests[n++] = i915_gem_request_get(req);
+ requests[n++] = req;
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = obj->last_read[i].request;
+ req = i915_gem_active_get(&obj->last_read[i]);
if (req == NULL)
continue;
- requests[n++] = i915_gem_request_get(req);
+ requests[n++] = req;
}
}
@@ -2383,8 +2386,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
static void
i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
{
- GEM_BUG_ON(!obj->last_write.request);
- GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write.request->engine)));
+ GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_write));
+ GEM_BUG_ON(!(obj->active & intel_engine_flag(i915_gem_active_get_engine(&obj->last_write))));
i915_gem_active_set(&obj->last_write, NULL);
intel_fb_obj_flush(obj, true, ORIGIN_CS);
@@ -2393,15 +2396,17 @@ i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
static void
i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
{
+ struct intel_engine_cs *engine;
struct i915_vma *vma;
- GEM_BUG_ON(!obj->last_read[idx].request);
+ GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_read[idx]));
GEM_BUG_ON(!(obj->active & (1 << idx)));
list_del_init(&obj->engine_list[idx]);
i915_gem_active_set(&obj->last_read[idx], NULL);
- if (obj->last_write.request && obj->last_write.request->engine->id == idx)
+ engine = i915_gem_active_get_engine(&obj->last_write);
+ if (engine && engine->id == idx)
i915_gem_object_retire__write(obj);
obj->active &= ~(1 << idx);
@@ -2621,7 +2626,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
struct drm_i915_gem_object,
engine_list[engine->id]);
- if (!list_empty(&obj->last_read[engine->id].request->list))
+ if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id])->list))
break;
i915_gem_object_retire__read(obj, engine->id);
@@ -2754,7 +2759,7 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = obj->last_read[i].request;
+ req = i915_gem_active_peek(&obj->last_read[i]);
if (req == NULL)
continue;
@@ -2794,7 +2799,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{
struct drm_i915_gem_wait *args = data;
struct drm_i915_gem_object *obj;
- struct drm_i915_gem_request *req[I915_NUM_ENGINES];
+ struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
int i, n = 0;
int ret;
@@ -2830,20 +2835,21 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
i915_gem_object_put(obj);
for (i = 0; i < I915_NUM_ENGINES; i++) {
- if (!obj->last_read[i].request)
- continue;
+ struct drm_i915_gem_request *req;
- req[n++] = i915_gem_request_get(obj->last_read[i].request);
+ req = i915_gem_active_get(&obj->last_read[i]);
+ if (req)
+ requests[n++] = req;
}
mutex_unlock(&dev->struct_mutex);
for (i = 0; i < n; i++) {
if (ret == 0)
- ret = __i915_wait_request(req[i], true,
+ ret = __i915_wait_request(requests[i], true,
args->timeout_ns > 0 ? &args->timeout_ns : NULL,
to_rps_client(file));
- i915_gem_request_put(req[i]);
+ i915_gem_request_put(requests[i]);
}
return ret;
@@ -2916,7 +2922,7 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *to)
{
const bool readonly = obj->base.pending_write_domain == 0;
- struct drm_i915_gem_request *req[I915_NUM_ENGINES];
+ struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
int ret, i, n;
if (!obj->active)
@@ -2924,15 +2930,22 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
n = 0;
if (readonly) {
- if (obj->last_write.request)
- req[n++] = obj->last_write.request;
+ struct drm_i915_gem_request *req;
+
+ req = i915_gem_active_peek(&obj->last_write);
+ if (req)
+ requests[n++] = req;
} else {
- for (i = 0; i < I915_NUM_ENGINES; i++)
- if (obj->last_read[i].request)
- req[n++] = obj->last_read[i].request;
+ for (i = 0; i < I915_NUM_ENGINES; i++) {
+ struct drm_i915_gem_request *req;
+
+ req = i915_gem_active_peek(&obj->last_read[i]);
+ if (req)
+ requests[n++] = req;
+ }
}
for (i = 0; i < n; i++) {
- ret = __i915_gem_object_sync(obj, to, req[i]);
+ ret = __i915_gem_object_sync(obj, to, requests[i]);
if (ret)
return ret;
}
@@ -4025,17 +4038,17 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
args->busy = 0;
if (obj->active) {
+ struct drm_i915_gem_request *req;
int i;
for (i = 0; i < I915_NUM_ENGINES; i++) {
- struct drm_i915_gem_request *req;
-
- req = obj->last_read[i].request;
+ req = i915_gem_active_peek(&obj->last_read[i]);
if (req)
args->busy |= 1 << (16 + req->engine->exec_id);
}
- if (obj->last_write.request)
- args->busy |= obj->last_write.request->engine->exec_id;
+ req = i915_gem_active_peek(&obj->last_write);
+ if (req)
+ args->busy |= req->engine->exec_id;
}
unref:
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index d16b385e79e9..9fdbd66128a6 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -261,14 +261,13 @@ static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
static int
i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
{
- if (obj->last_fence.request) {
- int ret = i915_wait_request(obj->last_fence.request);
- if (ret)
- return ret;
+ int ret;
- i915_gem_active_set(&obj->last_fence, NULL);
- }
+ ret = i915_gem_active_wait(&obj->last_fence);
+ if (ret)
+ return ret;
+ i915_gem_active_set(&obj->last_fence, NULL);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index 5d2ea5ee03c2..19cb20600830 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -277,14 +277,141 @@ static inline bool i915_spin_request(const struct drm_i915_gem_request *request,
* resource including itself.
*/
struct i915_gem_active {
- struct drm_i915_gem_request *request;
+ struct drm_i915_gem_request *__request;
};
+/**
+ * i915_gem_active_set - updates the tracker to watch the current request
+ * @active - the active tracker
+ * @request - the request to watch
+ *
+ * i915_gem_active_set() watches the given @request for completion. Whilst
+ * that @request is busy, the @active reports busy. When that @request is
+ * retired, the @active tracker is updated to report idle.
+ */
static inline void
i915_gem_active_set(struct i915_gem_active *active,
struct drm_i915_gem_request *request)
{
- i915_gem_request_assign(&active->request, request);
+ i915_gem_request_assign(&active->__request, request);
+}
+
+/**
+ * i915_gem_active_peek - report the request being monitored
+ * @active - the active tracker
+ *
+ * i915_gem_active_peek() returns the current request being tracked, or NULL.
+ * It does not obtain a reference on the request for the caller, so the
+ * caller must hold struct_mutex.
+ */
+static inline struct drm_i915_gem_request *
+i915_gem_active_peek(const struct i915_gem_active *active)
+{
+ return active->__request;
+}
+
+/**
+ * i915_gem_active_get - return a reference to the active request
+ * @active - the active tracker
+ *
+ * i915_gem_active_get() returns a reference to the active request, or NULL
+ * if the active tracker is idle. The caller must hold struct_mutex.
+ */
+static inline struct drm_i915_gem_request *
+i915_gem_active_get(const struct i915_gem_active *active)
+{
+ struct drm_i915_gem_request *request;
+
+ request = i915_gem_active_peek(active);
+ if (!request || i915_gem_request_completed(request))
+ return NULL;
+
+ return i915_gem_request_get(request);
+}
+
+/**
+ * __i915_gem_active_is_busy - report whether the active tracker is assigned
+ * @active - the active tracker
+ *
+ * __i915_gem_active_is_busy() returns true if the active tracker is currently
+ * assigned to a request. Due to the lazy retiring, that request may be idle
+ * and this may report stale information.
+ */
+static inline bool
+__i915_gem_active_is_busy(const struct i915_gem_active *active)
+{
+ return i915_gem_active_peek(active);
+}
+
+/**
+ * i915_gem_active_is_idle - report whether the active tracker is idle
+ * @active - the active tracker
+ *
+ * i915_gem_active_is_idle() returns true if the active tracker is currently
+ * unassigned or if the request is complete (but not yet retired). Requires
+ * the caller to hold struct_mutex (but that can be relaxed if desired).
+ */
+static inline bool
+i915_gem_active_is_idle(const struct i915_gem_active *active)
+{
+ struct drm_i915_gem_request *request;
+
+ request = i915_gem_active_peek(active);
+ if (!request || i915_gem_request_completed(request))
+ return true;
+
+ return false;
+}
+
+/**
+ * i915_gem_active_wait - waits until the request is completed
+ * @active - the active request on which to wait
+ *
+ * i915_gem_active_wait() waits until the request is completed before
+ * returning. Note that it does not guarantee that the request is
+ * retired first, see i915_gem_active_retire().
+ */
+static inline int __must_check
+i915_gem_active_wait(const struct i915_gem_active *active)
+{
+ struct drm_i915_gem_request *request;
+
+ request = i915_gem_active_peek(active);
+ if (!request)
+ return 0;
+
+ return i915_wait_request(request);
+}
+
+/**
+ * i915_gem_active_retire - waits until the request is retired
+ * @active - the active request on which to wait
+ *
+ * i915_gem_active_retire() waits until the request is completed,
+ * and then ensures that at least the retirement handler for this
+ * @active tracker is called before returning. If the @active
+ * tracker is idle, the function returns immediately.
+ */
+static inline int __must_check
+i915_gem_active_retire(const struct i915_gem_active *active)
+{
+ return i915_gem_active_wait(active);
+}
+
+/* Convenience functions for peeking at state inside active's request whilst
+ * guarded by the struct_mutex.
+ */
+
+static inline uint32_t
+i915_gem_active_get_seqno(const struct i915_gem_active *active)
+{
+ return i915_gem_request_get_seqno(i915_gem_active_peek(active));
+}
+
+static inline struct intel_engine_cs *
+i915_gem_active_get_engine(const struct i915_gem_active *active)
+{
+ return i915_gem_request_get_engine(i915_gem_active_peek(active));
}
#define for_each_active(mask, idx) \
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 00d796da65fb..8cef2d6b291a 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -242,7 +242,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
}
obj->fence_dirty =
- obj->last_fence.request ||
+ !i915_gem_active_is_idle(&obj->last_fence) ||
obj->fence_reg != I915_FENCE_REG_NONE;
obj->tiling_mode = args->tiling_mode;
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 32f50a70ea42..00ab5e9d2eb7 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -74,11 +74,9 @@ static void wait_rendering(struct drm_i915_gem_object *obj)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = obj->last_read[i].request;
- if (req == NULL)
- continue;
-
- requests[n++] = i915_gem_request_get(req);
+ req = i915_gem_active_get(&obj->last_read[i]);
+ if (req)
+ requests[n++] = req;
}
mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b0e75b3de44a..ce23d61fffe2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -751,13 +751,14 @@ static void capture_bo(struct drm_i915_error_buffer *err,
struct i915_vma *vma)
{
struct drm_i915_gem_object *obj = vma->obj;
+ struct intel_engine_cs *engine;
int i;
err->size = obj->base.size;
err->name = obj->base.name;
for (i = 0; i < I915_NUM_ENGINES; i++)
- err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read[i].request);
- err->wseqno = i915_gem_request_get_seqno(obj->last_write.request);
+ err->rseqno[i] = i915_gem_active_get_seqno(&obj->last_read[i]);
+ err->wseqno = i915_gem_active_get_seqno(&obj->last_write);
err->gtt_offset = vma->node.start;
err->read_domains = obj->base.read_domains;
err->write_domain = obj->base.write_domain;
@@ -769,8 +770,10 @@ static void capture_bo(struct drm_i915_error_buffer *err,
err->dirty = obj->dirty;
err->purgeable = obj->madv != I915_MADV_WILLNEED;
err->userptr = obj->userptr.mm != NULL;
- err->engine = obj->last_write.request ? obj->last_write.request->engine->id : -1;
err->cache_level = obj->cache_level;
+
+ engine = i915_gem_active_get_engine(&obj->last_write);
+ err->engine = engine ? engine->id : -1;
}
static u32 capture_active_bo(struct drm_i915_error_buffer *err,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bc204d103674..6ff4cb6068bf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11378,7 +11378,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
if (resv && !reservation_object_test_signaled_rcu(resv, false))
return true;
- return engine != i915_gem_request_get_engine(obj->last_write.request);
+ return engine != i915_gem_active_get_engine(&obj->last_write);
}
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
@@ -11681,7 +11681,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
engine = &dev_priv->engine[BCS];
} else if (INTEL_INFO(dev)->gen >= 7) {
- engine = i915_gem_request_get_engine(obj->last_write.request);
+ engine = i915_gem_active_get_engine(&obj->last_write);
if (engine == NULL || engine->id != RCS)
engine = &dev_priv->engine[BCS];
} else {
@@ -11702,9 +11702,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (mmio_flip) {
INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
- i915_gem_request_assign(&work->flip_queued_req,
- obj->last_write.request);
-
+ work->flip_queued_req = i915_gem_active_get(&obj->last_write);
schedule_work(&work->mmio_work);
} else {
request = i915_gem_request_alloc(engine, engine->last_context);
@@ -14047,11 +14045,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
}
if (ret == 0) {
- struct intel_plane_state *plane_state =
- to_intel_plane_state(new_state);
-
- i915_gem_request_assign(&plane_state->wait_req,
- obj->last_write.request);
+ to_intel_plane_state(new_state)->wait_req =
+ i915_gem_active_get(&obj->last_write);
}
return ret;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (37 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 8:54 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 40/55] drm/i915: Refactor blocking waits Chris Wilson
` (17 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
The future annotations will track the locking used for access to ensure
that it is always sufficient. We make the preparations now to present
the API ahead and to make sure that GCC can eliminate the unused
parameter.
Before: 6298417 3619610 696320 10614347 a1f64b vmlinux
After: 6298417 3619610 696320 10614347 a1f64b vmlinux
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++++---
drivers/gpu/drm/i915/i915_gem.c | 49 ++++++++++++++++++++++-----------
drivers/gpu/drm/i915/i915_gem_fence.c | 3 +-
drivers/gpu/drm/i915/i915_gem_request.h | 38 +++++++++++++++----------
drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 29 +++++++++++++++----
drivers/gpu/drm/i915/intel_display.c | 12 +++++---
8 files changed, 102 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b41561bdfb85..16fa1f527ef5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -155,10 +155,13 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
obj->base.write_domain);
for_each_engine_id(engine, dev_priv, id)
seq_printf(m, "%x ",
- i915_gem_active_get_seqno(&obj->last_read[id]));
+ i915_gem_active_get_seqno(&obj->last_read[id],
+ &obj->base.dev->struct_mutex));
seq_printf(m, "] %x %x%s%s%s",
- i915_gem_active_get_seqno(&obj->last_write),
- i915_gem_active_get_seqno(&obj->last_fence),
+ i915_gem_active_get_seqno(&obj->last_write,
+ &obj->base.dev->struct_mutex),
+ i915_gem_active_get_seqno(&obj->last_fence,
+ &obj->base.dev->struct_mutex),
i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
@@ -196,7 +199,8 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%s mappable)", s);
}
- engine = i915_gem_active_get_engine(&obj->last_write);
+ engine = i915_gem_active_get_engine(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (engine)
seq_printf(m, " (%s)", engine->name);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b8d541f212ff..3f6b69dcaccb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1354,21 +1354,24 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
int ret, i;
if (readonly) {
- request = i915_gem_active_peek(&obj->last_write);
+ request = i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (request) {
ret = i915_wait_request(request);
if (ret)
return ret;
i = request->engine->id;
- if (i915_gem_active_peek(&obj->last_read[i]) == request)
+ if (i915_gem_active_peek(&obj->last_read[i],
+ &obj->base.dev->struct_mutex) == request)
i915_gem_object_retire__read(obj, i);
else
i915_gem_object_retire__write(obj);
}
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
- request = i915_gem_active_peek(&obj->last_read[i]);
+ request = i915_gem_active_peek(&obj->last_read[i],
+ &obj->base.dev->struct_mutex);
if (!request)
continue;
@@ -1400,9 +1403,11 @@ i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
{
int idx = req->engine->id;
- if (i915_gem_active_peek(&obj->last_read[idx]) == req)
+ if (i915_gem_active_peek(&obj->last_read[idx],
+ &obj->base.dev->struct_mutex) == req)
i915_gem_object_retire__read(obj, idx);
- else if (i915_gem_active_peek(&obj->last_write) == req)
+ else if (i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex) == req)
i915_gem_object_retire__write(obj);
if (!i915_reset_in_progress(&req->i915->gpu_error))
@@ -1431,7 +1436,8 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
if (readonly) {
struct drm_i915_gem_request *req;
- req = i915_gem_active_get(&obj->last_write);
+ req = i915_gem_active_get(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (req == NULL)
return 0;
@@ -1440,7 +1446,8 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = i915_gem_active_get(&obj->last_read[i]);
+ req = i915_gem_active_get(&obj->last_read[i],
+ &obj->base.dev->struct_mutex);
if (req == NULL)
continue;
@@ -2387,7 +2394,9 @@ static void
i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
{
GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_write));
- GEM_BUG_ON(!(obj->active & intel_engine_flag(i915_gem_active_get_engine(&obj->last_write))));
+ GEM_BUG_ON(!(obj->active &
+ intel_engine_flag(i915_gem_active_get_engine(&obj->last_write,
+ &obj->base.dev->struct_mutex))));
i915_gem_active_set(&obj->last_write, NULL);
intel_fb_obj_flush(obj, true, ORIGIN_CS);
@@ -2405,7 +2414,8 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
list_del_init(&obj->engine_list[idx]);
i915_gem_active_set(&obj->last_read[idx], NULL);
- engine = i915_gem_active_get_engine(&obj->last_write);
+ engine = i915_gem_active_get_engine(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (engine && engine->id == idx)
i915_gem_object_retire__write(obj);
@@ -2626,7 +2636,8 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
struct drm_i915_gem_object,
engine_list[engine->id]);
- if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id])->list))
+ if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id],
+ &obj->base.dev->struct_mutex)->list))
break;
i915_gem_object_retire__read(obj, engine->id);
@@ -2759,7 +2770,8 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = i915_gem_active_peek(&obj->last_read[i]);
+ req = i915_gem_active_peek(&obj->last_read[i],
+ &obj->base.dev->struct_mutex);
if (req == NULL)
continue;
@@ -2837,7 +2849,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = i915_gem_active_get(&obj->last_read[i]);
+ req = i915_gem_active_get(&obj->last_read[i],
+ &obj->base.dev->struct_mutex);
if (req)
requests[n++] = req;
}
@@ -2932,14 +2945,16 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (readonly) {
struct drm_i915_gem_request *req;
- req = i915_gem_active_peek(&obj->last_write);
+ req = i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (req)
requests[n++] = req;
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = i915_gem_active_peek(&obj->last_read[i]);
+ req = i915_gem_active_peek(&obj->last_read[i],
+ &obj->base.dev->struct_mutex);
if (req)
requests[n++] = req;
}
@@ -4042,11 +4057,13 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
int i;
for (i = 0; i < I915_NUM_ENGINES; i++) {
- req = i915_gem_active_peek(&obj->last_read[i]);
+ req = i915_gem_active_peek(&obj->last_read[i],
+ &obj->base.dev->struct_mutex);
if (req)
args->busy |= 1 << (16 + req->engine->exec_id);
}
- req = i915_gem_active_peek(&obj->last_write);
+ req = i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (req)
args->busy |= req->engine->exec_id;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 9fdbd66128a6..a4ec4fecbea0 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -263,7 +263,8 @@ i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
{
int ret;
- ret = i915_gem_active_wait(&obj->last_fence);
+ ret = i915_gem_active_wait(&obj->last_fence,
+ &obj->base.dev->struct_mutex);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index 19cb20600830..2df01a6f5fbb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -296,6 +296,12 @@ i915_gem_active_set(struct i915_gem_active *active,
i915_gem_request_assign(&active->__request, request);
}
+static inline struct drm_i915_gem_request *
+__i915_gem_active_peek(const struct i915_gem_active *active)
+{
+ return active->__request;
+}
+
/**
* i915_gem_active_peek - report the request being monitored
* @active - the active tracker
@@ -305,7 +311,7 @@ i915_gem_active_set(struct i915_gem_active *active,
* caller must hold struct_mutex.
*/
static inline struct drm_i915_gem_request *
-i915_gem_active_peek(const struct i915_gem_active *active)
+i915_gem_active_peek(const struct i915_gem_active *active, struct mutex *mutex)
{
return active->__request;
}
@@ -318,11 +324,11 @@ i915_gem_active_peek(const struct i915_gem_active *active)
* if the active tracker is idle. The caller must hold struct_mutex.
*/
static inline struct drm_i915_gem_request *
-i915_gem_active_get(const struct i915_gem_active *active)
+i915_gem_active_get(const struct i915_gem_active *active, struct mutex *mutex)
{
struct drm_i915_gem_request *request;
- request = i915_gem_active_peek(active);
+ request = i915_gem_active_peek(active, mutex);
if (!request || i915_gem_request_completed(request))
return NULL;
@@ -340,7 +346,7 @@ i915_gem_active_get(const struct i915_gem_active *active)
static inline bool
__i915_gem_active_is_busy(const struct i915_gem_active *active)
{
- return i915_gem_active_peek(active);
+ return __i915_gem_active_peek(active);
}
/**
@@ -352,11 +358,12 @@ __i915_gem_active_is_busy(const struct i915_gem_active *active)
* the caller to hold struct_mutex (but that can be relaxed if desired).
*/
static inline bool
-i915_gem_active_is_idle(const struct i915_gem_active *active)
+i915_gem_active_is_idle(const struct i915_gem_active *active,
+ struct mutex *mutex)
{
struct drm_i915_gem_request *request;
- request = i915_gem_active_peek(active);
+ request = i915_gem_active_peek(active, mutex);
if (!request || i915_gem_request_completed(request))
return true;
@@ -372,11 +379,11 @@ i915_gem_active_is_idle(const struct i915_gem_active *active)
* retired first, see i915_gem_active_retire().
*/
static inline int __must_check
-i915_gem_active_wait(const struct i915_gem_active *active)
+i915_gem_active_wait(const struct i915_gem_active *active, struct mutex *mutex)
{
struct drm_i915_gem_request *request;
- request = i915_gem_active_peek(active);
+ request = i915_gem_active_peek(active, mutex);
if (!request)
return 0;
@@ -393,9 +400,10 @@ i915_gem_active_wait(const struct i915_gem_active *active)
* tracker is idle, the function returns immediately.
*/
static inline int __must_check
-i915_gem_active_retire(const struct i915_gem_active *active)
+i915_gem_active_retire(const struct i915_gem_active *active,
+ struct mutex *mutex)
{
- return i915_gem_active_wait(active);
+ return i915_gem_active_wait(active, mutex);
}
/* Convenience functions for peeking at state inside active's request whilst
@@ -403,15 +411,17 @@ i915_gem_active_retire(const struct i915_gem_active *active)
*/
static inline uint32_t
-i915_gem_active_get_seqno(const struct i915_gem_active *active)
+i915_gem_active_get_seqno(const struct i915_gem_active *active,
+ struct mutex *mutex)
{
- return i915_gem_request_get_seqno(i915_gem_active_peek(active));
+ return i915_gem_request_get_seqno(i915_gem_active_peek(active, mutex));
}
static inline struct intel_engine_cs *
-i915_gem_active_get_engine(const struct i915_gem_active *active)
+i915_gem_active_get_engine(const struct i915_gem_active *active,
+ struct mutex *mutex)
{
- return i915_gem_request_get_engine(i915_gem_active_peek(active));
+ return i915_gem_request_get_engine(i915_gem_active_peek(active, mutex));
}
#define for_each_active(mask, idx) \
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 8cef2d6b291a..fa2eb4a4f212 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -242,7 +242,8 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
}
obj->fence_dirty =
- !i915_gem_active_is_idle(&obj->last_fence) ||
+ !i915_gem_active_is_idle(&obj->last_fence,
+ &dev->struct_mutex) ||
obj->fence_reg != I915_FENCE_REG_NONE;
obj->tiling_mode = args->tiling_mode;
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 00ab5e9d2eb7..e57521dbddc6 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -74,7 +74,8 @@ static void wait_rendering(struct drm_i915_gem_object *obj)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
- req = i915_gem_active_get(&obj->last_read[i]);
+ req = i915_gem_active_get(&obj->last_read[i],
+ &obj->base.dev->struct_mutex);
if (req)
requests[n++] = req;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index ce23d61fffe2..f6fe6b46f4b1 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -747,18 +747,38 @@ unwind:
#define i915_error_ggtt_object_create(dev_priv, src) \
i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base)
+/* The error capture is special as tries to run underneath the normal
+ * locking rules - so we use the raw version of the i915_gem_active lookup.
+ */
+static inline uint32_t
+__active_get_seqno(struct i915_gem_active *active)
+{
+ return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
+}
+
+static inline int
+__active_get_engine_id(struct i915_gem_active *active)
+{
+ struct intel_engine_cs *engine;
+
+ engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
+ return engine ? engine->id : -1;
+}
+
static void capture_bo(struct drm_i915_error_buffer *err,
struct i915_vma *vma)
{
struct drm_i915_gem_object *obj = vma->obj;
- struct intel_engine_cs *engine;
int i;
err->size = obj->base.size;
err->name = obj->base.name;
+
for (i = 0; i < I915_NUM_ENGINES; i++)
- err->rseqno[i] = i915_gem_active_get_seqno(&obj->last_read[i]);
- err->wseqno = i915_gem_active_get_seqno(&obj->last_write);
+ err->rseqno[i] = __active_get_seqno(&obj->last_read[i]);
+ err->wseqno = __active_get_seqno(&obj->last_write);
+ err->engine = __active_get_engine_id(&obj->last_write);
+
err->gtt_offset = vma->node.start;
err->read_domains = obj->base.read_domains;
err->write_domain = obj->base.write_domain;
@@ -771,9 +791,6 @@ static void capture_bo(struct drm_i915_error_buffer *err,
err->purgeable = obj->madv != I915_MADV_WILLNEED;
err->userptr = obj->userptr.mm != NULL;
err->cache_level = obj->cache_level;
-
- engine = i915_gem_active_get_engine(&obj->last_write);
- err->engine = engine ? engine->id : -1;
}
static u32 capture_active_bo(struct drm_i915_error_buffer *err,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6ff4cb6068bf..8ea9d5a301d4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11378,7 +11378,8 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
if (resv && !reservation_object_test_signaled_rcu(resv, false))
return true;
- return engine != i915_gem_active_get_engine(&obj->last_write);
+ return engine != i915_gem_active_get_engine(&obj->last_write,
+ &obj->base.dev->struct_mutex);
}
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
@@ -11681,7 +11682,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
engine = &dev_priv->engine[BCS];
} else if (INTEL_INFO(dev)->gen >= 7) {
- engine = i915_gem_active_get_engine(&obj->last_write);
+ engine = i915_gem_active_get_engine(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (engine == NULL || engine->id != RCS)
engine = &dev_priv->engine[BCS];
} else {
@@ -11702,7 +11704,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (mmio_flip) {
INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
- work->flip_queued_req = i915_gem_active_get(&obj->last_write);
+ work->flip_queued_req = i915_gem_active_get(&obj->last_write,
+ &obj->base.dev->struct_mutex);
schedule_work(&work->mmio_work);
} else {
request = i915_gem_request_alloc(engine, engine->last_context);
@@ -14046,7 +14049,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
if (ret == 0) {
to_intel_plane_state(new_state)->wait_req =
- i915_gem_active_get(&obj->last_write);
+ i915_gem_active_get(&obj->last_write,
+ &obj->base.dev->struct_mutex);
}
return ret;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (38 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-27 6:04 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 41/55] drm/i915: Rename request->list to link for consistency Chris Wilson
` (16 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Tidy up the for loops that handle waiting for read/write vs read-only
access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 158 +++++++++++++++++++---------------------
1 file changed, 75 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3f6b69dcaccb..2d86a0c3f295 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1339,6 +1339,23 @@ put_rpm:
return ret;
}
+static void
+i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
+ struct drm_i915_gem_request *req)
+{
+ int idx = req->engine->id;
+
+ if (i915_gem_active_peek(&obj->last_read[idx],
+ &obj->base.dev->struct_mutex) == req)
+ i915_gem_object_retire__read(obj, idx);
+ else if (i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex) == req)
+ i915_gem_object_retire__write(obj);
+
+ if (!i915_reset_in_progress(&req->i915->gpu_error))
+ i915_gem_request_retire_upto(req);
+}
+
/**
* Ensures that all rendering to the object has completed and the object is
* safe to unbind from the GTT or access from the CPU.
@@ -1349,39 +1366,34 @@ int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
bool readonly)
{
- struct drm_i915_gem_request *request;
struct reservation_object *resv;
- int ret, i;
+ struct i915_gem_active *active;
+ unsigned long active_mask;
+ int idx, ret;
- if (readonly) {
- request = i915_gem_active_peek(&obj->last_write,
- &obj->base.dev->struct_mutex);
- if (request) {
- ret = i915_wait_request(request);
- if (ret)
- return ret;
+ lockdep_assert_held(&obj->base.dev->struct_mutex);
- i = request->engine->id;
- if (i915_gem_active_peek(&obj->last_read[i],
- &obj->base.dev->struct_mutex) == request)
- i915_gem_object_retire__read(obj, i);
- else
- i915_gem_object_retire__write(obj);
- }
+ if (!readonly) {
+ active = obj->last_read;
+ active_mask = obj->active;
} else {
- for (i = 0; i < I915_NUM_ENGINES; i++) {
- request = i915_gem_active_peek(&obj->last_read[i],
- &obj->base.dev->struct_mutex);
- if (!request)
- continue;
+ active_mask = 1;
+ active = &obj->last_write;
+ }
- ret = i915_wait_request(request);
- if (ret)
- return ret;
+ for_each_active(active_mask, idx) {
+ struct drm_i915_gem_request *request;
- i915_gem_object_retire__read(obj, i);
- }
- GEM_BUG_ON(obj->active);
+ request = i915_gem_active_peek(&active[idx],
+ &obj->base.dev->struct_mutex);
+ if (!request)
+ continue;
+
+ ret = i915_wait_request(request);
+ if (ret)
+ return ret;
+
+ i915_gem_object_retire_request(obj, request);
}
resv = i915_gem_object_get_dmabuf_resv(obj);
@@ -1397,23 +1409,6 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
return 0;
}
-static void
-i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
- struct drm_i915_gem_request *req)
-{
- int idx = req->engine->id;
-
- if (i915_gem_active_peek(&obj->last_read[idx],
- &obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__read(obj, idx);
- else if (i915_gem_active_peek(&obj->last_write,
- &obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__write(obj);
-
- if (!i915_reset_in_progress(&req->i915->gpu_error))
- i915_gem_request_retire_upto(req);
-}
-
/* A nonblocking variant of the above wait. This is a highly dangerous routine
* as the object state may change during this call.
*/
@@ -1425,34 +1420,31 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
+ struct i915_gem_active *active;
+ unsigned long active_mask;
int ret, i, n = 0;
BUG_ON(!mutex_is_locked(&dev->struct_mutex));
BUG_ON(!dev_priv->mm.interruptible);
- if (!obj->active)
+ active_mask = obj->active;
+ if (!active_mask)
return 0;
- if (readonly) {
- struct drm_i915_gem_request *req;
-
- req = i915_gem_active_get(&obj->last_write,
- &obj->base.dev->struct_mutex);
- if (req == NULL)
- return 0;
-
- requests[n++] = req;
+ if (!readonly) {
+ active = obj->last_read;
} else {
- for (i = 0; i < I915_NUM_ENGINES; i++) {
- struct drm_i915_gem_request *req;
+ active_mask = 1;
+ active = &obj->last_write;
+ }
- req = i915_gem_active_get(&obj->last_read[i],
- &obj->base.dev->struct_mutex);
- if (req == NULL)
- continue;
+ for_each_active(active_mask, i) {
+ struct drm_i915_gem_request *req;
+ req = i915_gem_active_get(&active[i],
+ &obj->base.dev->struct_mutex);
+ if (req)
requests[n++] = req;
- }
}
mutex_unlock(&dev->struct_mutex);
@@ -2934,33 +2926,33 @@ int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *to)
{
- const bool readonly = obj->base.pending_write_domain == 0;
- struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
- int ret, i, n;
+ struct i915_gem_active *active;
+ unsigned long active_mask;
+ int idx;
- if (!obj->active)
- return 0;
+ lockdep_assert_held(&obj->base.dev->struct_mutex);
- n = 0;
- if (readonly) {
- struct drm_i915_gem_request *req;
+ active_mask = obj->active;
+ if (!active_mask)
+ return 0;
- req = i915_gem_active_peek(&obj->last_write,
- &obj->base.dev->struct_mutex);
- if (req)
- requests[n++] = req;
+ if (obj->base.pending_write_domain) {
+ active = obj->last_read;
} else {
- for (i = 0; i < I915_NUM_ENGINES; i++) {
- struct drm_i915_gem_request *req;
-
- req = i915_gem_active_peek(&obj->last_read[i],
- &obj->base.dev->struct_mutex);
- if (req)
- requests[n++] = req;
- }
+ active_mask = 1;
+ active = &obj->last_write;
}
- for (i = 0; i < n; i++) {
- ret = __i915_gem_object_sync(obj, to, requests[i]);
+
+ for_each_active(active_mask, idx) {
+ struct drm_i915_gem_request *request;
+ int ret;
+
+ request = i915_gem_active_peek(&active[idx],
+ &obj->base.dev->struct_mutex);
+ if (!request)
+ continue;
+
+ ret = __i915_gem_object_sync(obj, to, request);
if (ret)
return ret;
}
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 41/55] drm/i915: Rename request->list to link for consistency
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (39 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 40/55] drm/i915: Refactor blocking waits Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 9:26 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active() Chris Wilson
` (15 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
We use "list" to denote the list and "link" to denote an element on that
list. Rename request->list to match this idiom.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 10 +++++-----
drivers/gpu/drm/i915/i915_gem_request.c | 12 ++++++------
drivers/gpu/drm/i915/i915_gem_request.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
6 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 16fa1f527ef5..6693dfbca4f1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -748,13 +748,13 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
int count;
count = 0;
- list_for_each_entry(req, &engine->request_list, list)
+ list_for_each_entry(req, &engine->request_list, link)
count++;
if (count == 0)
continue;
seq_printf(m, "%s requests: %d\n", engine->name, count);
- list_for_each_entry(req, &engine->request_list, list) {
+ list_for_each_entry(req, &engine->request_list, link) {
struct task_struct *task;
rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2d86a0c3f295..e5be4eb0a397 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2475,7 +2475,7 @@ i915_gem_find_active_request(struct intel_engine_cs *engine)
* extra delay for a recent interrupt is pointless. Hence, we do
* not need an engine->irq_seqno_barrier() before the seqno reads.
*/
- list_for_each_entry(request, &engine->request_list, list) {
+ list_for_each_entry(request, &engine->request_list, link) {
if (i915_gem_request_completed(request))
continue;
@@ -2497,7 +2497,7 @@ static void i915_gem_reset_engine_status(struct intel_engine_cs *engine)
ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
i915_set_reset_status(request->ctx, ring_hung);
- list_for_each_entry_continue(request, &engine->request_list, list)
+ list_for_each_entry_continue(request, &engine->request_list, link)
i915_set_reset_status(request->ctx, false);
}
@@ -2546,7 +2546,7 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
request = list_last_entry(&engine->request_list,
struct drm_i915_gem_request,
- list);
+ link);
i915_gem_request_retire_upto(request);
}
@@ -2609,7 +2609,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
request = list_first_entry(&engine->request_list,
struct drm_i915_gem_request,
- list);
+ link);
if (!i915_gem_request_completed(request))
break;
@@ -2629,7 +2629,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
engine_list[engine->id]);
if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id],
- &obj->base.dev->struct_mutex)->list))
+ &obj->base.dev->struct_mutex)->link))
break;
i915_gem_object_retire__read(obj, engine->id);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index d7011185a4ee..065e9e61265b 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -160,7 +160,7 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
static void i915_gem_request_retire(struct drm_i915_gem_request *request)
{
trace_i915_gem_request_retire(request);
- list_del_init(&request->list);
+ list_del_init(&request->link);
/* We know the GPU must have read the request to have
* sent us the seqno + interrupt, so use the position
@@ -191,12 +191,12 @@ void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
lockdep_assert_held(&req->i915->drm.struct_mutex);
- if (list_empty(&req->list))
+ if (list_empty(&req->link))
return;
do {
tmp = list_first_entry(&engine->request_list,
- typeof(*tmp), list);
+ typeof(*tmp), link);
i915_gem_request_retire(tmp);
} while (tmp != req);
@@ -317,7 +317,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(&engine->request_list,
- typeof(*req), list);
+ typeof(*req), link);
if (req && i915_gem_request_completed(req))
i915_gem_request_retire(req);
@@ -450,7 +450,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
request->emitted_jiffies = jiffies;
request->previous_seqno = engine->last_submitted_seqno;
smp_store_mb(engine->last_submitted_seqno, request->fence.seqno);
- list_add_tail(&request->list, &engine->request_list);
+ list_add_tail(&request->link, &engine->request_list);
/* Record the position of the start of the request so that
* should we detect the updated seqno part-way through the
@@ -570,7 +570,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
might_sleep();
- if (list_empty(&req->list))
+ if (list_empty(&req->link))
return 0;
if (i915_gem_request_completed(req))
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index 2df01a6f5fbb..dc93051a68d8 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -105,8 +105,8 @@ struct drm_i915_gem_request {
/** Time at which this request was emitted, in jiffies. */
unsigned long emitted_jiffies;
- /** global list entry for this request */
- struct list_head list;
+ /** engine->request_list entry for this request */
+ struct list_head link;
struct drm_i915_file_private *file_priv;
/** file_priv list entry for this request */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index f6fe6b46f4b1..2b431e22addf 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1171,7 +1171,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
i915_gem_record_active_context(engine, error, ering);
count = 0;
- list_for_each_entry(request, &engine->request_list, list)
+ list_for_each_entry(request, &engine->request_list, link)
count++;
ering->num_requests = count;
@@ -1183,7 +1183,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
}
count = 0;
- list_for_each_entry(request, &engine->request_list, list) {
+ list_for_each_entry(request, &engine->request_list, link) {
struct drm_i915_error_request *erq;
if (count >= ering->num_requests) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7be7666c894e..5e0ba9416bd9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2250,7 +2250,7 @@ int intel_engine_idle(struct intel_engine_cs *engine)
req = list_entry(engine->request_list.prev,
struct drm_i915_gem_request,
- list);
+ link);
/* Make sure we do not trigger any retires */
return __i915_wait_request(req,
@@ -2299,7 +2299,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
*/
GEM_BUG_ON(!req->reserved_space);
- list_for_each_entry(target, &engine->request_list, list) {
+ list_for_each_entry(target, &engine->request_list, link) {
unsigned space;
/*
@@ -2317,7 +2317,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
break;
}
- if (WARN_ON(&target->list == &engine->request_list))
+ if (WARN_ON(&target->link == &engine->request_list))
return -ENOSPC;
return i915_wait_request(target);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active()
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (40 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 41/55] drm/i915: Rename request->list to link for consistency Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 9:31 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 43/55] drm/i915: Refactor activity tracking for requests Chris Wilson
` (14 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Since we track requests, and requests are always added to the GPU fully
formed, we never have to flush the incomplete request and know that the
given request will eventually complete without any further action on our
part.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 59 +++--------------------------------------
1 file changed, 3 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5be4eb0a397..3bff6b560f97 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2746,35 +2746,6 @@ out_rearm:
}
/**
- * Ensures that an object will eventually get non-busy by flushing any required
- * write domains, emitting any outstanding lazy request and retiring and
- * completed requests.
- * @obj: object to flush
- */
-static int
-i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
-{
- int i;
-
- if (!obj->active)
- return 0;
-
- for (i = 0; i < I915_NUM_ENGINES; i++) {
- struct drm_i915_gem_request *req;
-
- req = i915_gem_active_peek(&obj->last_read[i],
- &obj->base.dev->struct_mutex);
- if (req == NULL)
- continue;
-
- if (i915_gem_request_completed(req))
- i915_gem_object_retire__read(obj, i);
- }
-
- return 0;
-}
-
-/**
* i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
* @dev: drm device pointer
* @data: ioctl data blob
@@ -2820,24 +2791,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
return -ENOENT;
}
- /* Need to make sure the object gets inactive eventually. */
- ret = i915_gem_object_flush_active(obj);
- if (ret)
- goto out;
-
if (!obj->active)
goto out;
- /* Do this after OLR check to make sure we make forward progress polling
- * on this IOCTL with a timeout == 0 (like busy ioctl)
- */
- if (args->timeout_ns == 0) {
- ret = -ETIME;
- goto out;
- }
-
- i915_gem_object_put(obj);
-
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
@@ -2847,6 +2803,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
requests[n++] = req;
}
+out:
+ i915_gem_object_put(obj);
mutex_unlock(&dev->struct_mutex);
for (i = 0; i < n; i++) {
@@ -2857,11 +2815,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
i915_gem_request_put(requests[i]);
}
return ret;
-
-out:
- i915_gem_object_put(obj);
- mutex_unlock(&dev->struct_mutex);
- return ret;
}
static int
@@ -4036,13 +3989,8 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
/* Count all active objects as busy, even if they are currently not used
* by the gpu. Users of this interface expect objects to eventually
- * become non-busy without any further actions, therefore emit any
- * necessary flushes here.
+ * become non-busy without any further actions.
*/
- ret = i915_gem_object_flush_active(obj);
- if (ret)
- goto unref;
-
args->busy = 0;
if (obj->active) {
struct drm_i915_gem_request *req;
@@ -4060,7 +4008,6 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
args->busy |= req->engine->exec_id;
}
-unref:
i915_gem_object_put(obj);
unlock:
mutex_unlock(&dev->struct_mutex);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 43/55] drm/i915: Refactor activity tracking for requests
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (41 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active() Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-27 7:40 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 44/55] drm/i915: Track requests inside each intel_ring Chris Wilson
` (13 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
With the introduction of requests, we amplified the number of atomic
refcounted objects we use and update every execbuffer; from none to
several references, and a set of references that need to be changed. We
also introduced interesting side-effects in the order of retiring
requests and objects.
Instead of independently tracking the last request for an object, track
the active objects for each request. The object will reside in the
buffer list of its most recent active request and so we reduce the kref
interchange to a list_move. Now retirements are entirely driven by the
request, dramatically simplifying activity tracking on the object
themselves, and removing the ambiguity between retiring objects and
retiring requests.
Furthermore with the consolidation of managing the activity tracking
centrally, we can look forward to using RCU to enable lockless lookup of
the current active requests for an object. In the future, we will be
able to query the status or wait upon rendering to an object without
even touching the struct_mutex BKL.
All told, less code, simpler and faster, and more extensible.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/i915_drv.h | 10 ---
drivers/gpu/drm/i915/i915_gem.c | 139 +++++++-------------------------
drivers/gpu/drm/i915/i915_gem_debug.c | 70 ----------------
drivers/gpu/drm/i915/i915_gem_fence.c | 11 +--
drivers/gpu/drm/i915/i915_gem_request.c | 35 ++++++--
drivers/gpu/drm/i915/i915_gem_request.h | 90 +++++++++++++++------
drivers/gpu/drm/i915/intel_engine_cs.c | 1 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 12 ---
9 files changed, 125 insertions(+), 244 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/i915_gem_debug.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6092f0ea24df..dda724f04445 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -25,7 +25,6 @@ i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o
i915-y += i915_cmd_parser.o \
i915_gem_batch_pool.o \
i915_gem_context.o \
- i915_gem_debug.o \
i915_gem_dmabuf.o \
i915_gem_evict.o \
i915_gem_execbuffer.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76b5611aba9e..03f12304308a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -432,8 +432,6 @@ void intel_link_compute_m_n(int bpp, int nlanes,
#define DRIVER_MINOR 6
#define DRIVER_PATCHLEVEL 0
-#define WATCH_LISTS 0
-
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
@@ -2153,7 +2151,6 @@ struct drm_i915_gem_object {
struct drm_mm_node *stolen;
struct list_head global_list;
- struct list_head engine_list[I915_NUM_ENGINES];
/** Used in execbuf to temporarily hold a ref */
struct list_head obj_exec_link;
@@ -3463,13 +3460,6 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
obj->tiling_mode != I915_TILING_NONE;
}
-/* i915_gem_debug.c */
-#if WATCH_LISTS
-int i915_verify_lists(struct drm_device *dev);
-#else
-#define i915_verify_lists(dev) 0
-#endif
-
/* i915_debugfs.c */
#ifdef CONFIG_DEBUG_FS
int i915_debugfs_register(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3bff6b560f97..b9874a99ae04 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -43,10 +43,6 @@
static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
-static void
-i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
-static void
-i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
static bool cpu_cache_is_coherent(struct drm_device *dev,
enum i915_cache_level level)
@@ -141,7 +137,6 @@ int i915_mutex_lock_interruptible(struct drm_device *dev)
if (ret)
return ret;
- WARN_ON(i915_verify_lists(dev));
return 0;
}
@@ -1339,23 +1334,6 @@ put_rpm:
return ret;
}
-static void
-i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
- struct drm_i915_gem_request *req)
-{
- int idx = req->engine->id;
-
- if (i915_gem_active_peek(&obj->last_read[idx],
- &obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__read(obj, idx);
- else if (i915_gem_active_peek(&obj->last_write,
- &obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__write(obj);
-
- if (!i915_reset_in_progress(&req->i915->gpu_error))
- i915_gem_request_retire_upto(req);
-}
-
/**
* Ensures that all rendering to the object has completed and the object is
* safe to unbind from the GTT or access from the CPU.
@@ -1382,18 +1360,10 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
}
for_each_active(active_mask, idx) {
- struct drm_i915_gem_request *request;
-
- request = i915_gem_active_peek(&active[idx],
- &obj->base.dev->struct_mutex);
- if (!request)
- continue;
-
- ret = i915_wait_request(request);
+ ret = i915_gem_active_wait(&active[idx],
+ &obj->base.dev->struct_mutex);
if (ret)
return ret;
-
- i915_gem_object_retire_request(obj, request);
}
resv = i915_gem_object_get_dmabuf_resv(obj);
@@ -1453,11 +1423,8 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
ret = __i915_wait_request(requests[i], true, NULL, rps);
mutex_lock(&dev->struct_mutex);
- for (i = 0; i < n; i++) {
- if (ret == 0)
- i915_gem_object_retire_request(obj, requests[i]);
+ for (i = 0; i < n; i++)
i915_gem_request_put(requests[i]);
- }
return ret;
}
@@ -2376,40 +2343,38 @@ void i915_vma_move_to_active(struct i915_vma *vma,
i915_gem_object_get(obj);
obj->active |= intel_engine_flag(engine);
- list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
i915_gem_active_set(&obj->last_read[engine->id], req);
list_move_tail(&vma->vm_link, &vma->vm->active_list);
}
static void
-i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
+i915_gem_object_retire__fence(struct i915_gem_active *active,
+ struct drm_i915_gem_request *req)
{
- GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_write));
- GEM_BUG_ON(!(obj->active &
- intel_engine_flag(i915_gem_active_get_engine(&obj->last_write,
- &obj->base.dev->struct_mutex))));
+}
- i915_gem_active_set(&obj->last_write, NULL);
- intel_fb_obj_flush(obj, true, ORIGIN_CS);
+static void
+i915_gem_object_retire__write(struct i915_gem_active *active,
+ struct drm_i915_gem_request *request)
+{
+ intel_fb_obj_flush(container_of(active,
+ struct drm_i915_gem_object,
+ last_write),
+ true,
+ ORIGIN_CS);
}
static void
-i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
+i915_gem_object_retire__read(struct i915_gem_active *active,
+ struct drm_i915_gem_request *request)
{
- struct intel_engine_cs *engine;
+ int idx = request->engine->id;
+ struct drm_i915_gem_object *obj =
+ container_of(active, struct drm_i915_gem_object, last_read[idx]);
struct i915_vma *vma;
- GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_read[idx]));
- GEM_BUG_ON(!(obj->active & (1 << idx)));
-
- list_del_init(&obj->engine_list[idx]);
- i915_gem_active_set(&obj->last_read[idx], NULL);
-
- engine = i915_gem_active_get_engine(&obj->last_write,
- &obj->base.dev->struct_mutex);
- if (engine && engine->id == idx)
- i915_gem_object_retire__write(obj);
+ GEM_BUG_ON((obj->active & (1 << idx)) == 0);
obj->active &= ~(1 << idx);
if (obj->active)
@@ -2419,15 +2384,13 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
* so that we don't steal from recently used but inactive objects
* (unless we are forced to ofc!)
*/
- list_move_tail(&obj->global_list,
- &to_i915(obj->base.dev)->mm.bound_list);
+ list_move_tail(&obj->global_list, &request->i915->mm.bound_list);
list_for_each_entry(vma, &obj->vma_list, obj_link) {
if (!list_empty(&vma->vm_link))
list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
}
- i915_gem_active_set(&obj->last_fence, NULL);
i915_gem_object_put(obj);
}
@@ -2505,16 +2468,6 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
{
struct intel_ring *ring;
- while (!list_empty(&engine->active_list)) {
- struct drm_i915_gem_object *obj;
-
- obj = list_first_entry(&engine->active_list,
- struct drm_i915_gem_object,
- engine_list[engine->id]);
-
- i915_gem_object_retire__read(obj, engine->id);
- }
-
/* Mark all pending requests as complete so that any concurrent
* (lockless) lookup doesn't try and wait upon the request as we
* reset it.
@@ -2586,8 +2539,6 @@ void i915_gem_reset(struct drm_device *dev)
i915_gem_context_reset(dev);
i915_gem_restore_fences(dev);
-
- WARN_ON(i915_verify_lists(dev));
}
/**
@@ -2597,13 +2548,6 @@ void i915_gem_reset(struct drm_device *dev)
void
i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
{
- WARN_ON(i915_verify_lists(engine->dev));
-
- /* Retire requests first as we use it above for the early return.
- * If we retire requests last, we may use a later seqno and so clear
- * the requests lists without clearing the active list, leading to
- * confusion.
- */
while (!list_empty(&engine->request_list)) {
struct drm_i915_gem_request *request;
@@ -2616,26 +2560,6 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
i915_gem_request_retire_upto(request);
}
-
- /* Move any buffers on the active list that are no longer referenced
- * by the ringbuffer to the flushing/inactive lists as appropriate,
- * before we free the context associated with the requests.
- */
- while (!list_empty(&engine->active_list)) {
- struct drm_i915_gem_object *obj;
-
- obj = list_first_entry(&engine->active_list,
- struct drm_i915_gem_object,
- engine_list[engine->id]);
-
- if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id],
- &obj->base.dev->struct_mutex)->link))
- break;
-
- i915_gem_object_retire__read(obj, engine->id);
- }
-
- WARN_ON(i915_verify_lists(engine->dev));
}
void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
@@ -2818,8 +2742,7 @@ out:
}
static int
-__i915_gem_object_sync(struct drm_i915_gem_object *obj,
- struct drm_i915_gem_request *to,
+__i915_gem_object_sync(struct drm_i915_gem_request *to,
struct drm_i915_gem_request *from)
{
int ret;
@@ -2827,9 +2750,6 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (to->engine == from->engine)
return 0;
- if (i915_gem_request_completed(from))
- return 0;
-
if (!i915.semaphores) {
ret = __i915_wait_request(from,
from->i915->mm.interruptible,
@@ -2837,8 +2757,6 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
NO_WAITBOOST);
if (ret)
return ret;
-
- i915_gem_object_retire_request(obj, from);
} else {
int idx = intel_engine_sync_index(from->engine, to->engine);
if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx])
@@ -2905,7 +2823,7 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (!request)
continue;
- ret = __i915_gem_object_sync(obj, to, request);
+ ret = __i915_gem_object_sync(to, request);
if (ret)
return ret;
}
@@ -3041,7 +2959,6 @@ int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
return ret;
}
- WARN_ON(i915_verify_lists(dev));
return 0;
}
@@ -4085,7 +4002,12 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
INIT_LIST_HEAD(&obj->global_list);
for (i = 0; i < I915_NUM_ENGINES; i++)
- INIT_LIST_HEAD(&obj->engine_list[i]);
+ init_request_active(&obj->last_read[i],
+ i915_gem_object_retire__read);
+ init_request_active(&obj->last_write,
+ i915_gem_object_retire__write);
+ init_request_active(&obj->last_fence,
+ i915_gem_object_retire__fence);
INIT_LIST_HEAD(&obj->obj_exec_link);
INIT_LIST_HEAD(&obj->vma_list);
INIT_LIST_HEAD(&obj->batch_pool_link);
@@ -4578,7 +4500,6 @@ i915_gem_cleanup_engines(struct drm_device *dev)
static void
init_engine_lists(struct intel_engine_cs *engine)
{
- INIT_LIST_HEAD(&engine->active_list);
INIT_LIST_HEAD(&engine->request_list);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c
deleted file mode 100644
index a56516482394..000000000000
--- a/drivers/gpu/drm/i915/i915_gem_debug.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright © 2008 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp@keithp.com>
- *
- */
-
-#include <drm/drmP.h>
-#include <drm/i915_drm.h>
-#include "i915_drv.h"
-
-#if WATCH_LISTS
-int
-i915_verify_lists(struct drm_device *dev)
-{
- static int warned;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj;
- struct intel_engine_cs *engine;
- int err = 0;
-
- if (warned)
- return 0;
-
- for_each_engine(engine, dev_priv) {
- list_for_each_entry(obj, &engine->active_list,
- engine_list[engine->id]) {
- if (obj->base.dev != dev ||
- !atomic_read(&obj->base.refcount.refcount)) {
- DRM_ERROR("%s: freed active obj %p\n",
- engine->name, obj);
- err++;
- break;
- } else if (!obj->active ||
- obj->last_read_req[engine->id] == NULL) {
- DRM_ERROR("%s: invalid active obj %p\n",
- engine->name, obj);
- err++;
- } else if (obj->base.write_domain) {
- DRM_ERROR("%s: invalid write obj %p (w %x)\n",
- engine->name,
- obj, obj->base.write_domain);
- err++;
- }
- }
- }
-
- return warned = err;
-}
-#endif /* WATCH_LIST */
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index a4ec4fecbea0..dbaab9ce29c9 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -261,15 +261,8 @@ static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
static int
i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
{
- int ret;
-
- ret = i915_gem_active_wait(&obj->last_fence,
- &obj->base.dev->struct_mutex);
- if (ret)
- return ret;
-
- i915_gem_active_set(&obj->last_fence, NULL);
- return 0;
+ return i915_gem_active_retire(&obj->last_fence,
+ &obj->base.dev->struct_mutex);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 065e9e61265b..0216d6c093da 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -22,6 +22,8 @@
*
*/
+#include <linux/prefetch.h>
+
#include "i915_drv.h"
static const char *i915_fence_get_driver_name(struct fence *fence)
@@ -159,6 +161,8 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
static void i915_gem_request_retire(struct drm_i915_gem_request *request)
{
+ struct i915_gem_active *active, *next;
+
trace_i915_gem_request_retire(request);
list_del_init(&request->link);
@@ -172,6 +176,24 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
*/
request->ring->last_retired_head = request->postfix;
+ /* Walk through the active list, calling retire on each. This allows
+ * objects to track their GPU activity and mark themselves as idle
+ * when their *last* active request is completed (updating state
+ * tracking lists for eviction, active references for GEM, etc).
+ *
+ * As the ->retire() may free the node, we decouple it first and
+ * pass along the auxiliary information (to avoid dereferencing
+ * the node after the callback).
+ */
+ list_for_each_entry_safe(active, next, &request->active_list, link) {
+ prefetchw(next);
+
+ INIT_LIST_HEAD(&active->link);
+ active->__request = NULL;
+
+ active->retire(active, request);
+ }
+
i915_gem_request_remove_from_client(request);
if (request->previous_context) {
@@ -200,8 +222,6 @@ void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
i915_gem_request_retire(tmp);
} while (tmp != req);
-
- WARN_ON(i915_verify_lists(engine->dev));
}
static int i915_gem_check_wedge(unsigned int reset_counter, bool interruptible)
@@ -336,6 +356,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
engine->fence_context,
seqno);
+ INIT_LIST_HEAD(&req->active_list);
req->i915 = dev_priv;
req->engine = engine;
req->ctx = i915_gem_context_get(ctx);
@@ -570,9 +591,6 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
might_sleep();
- if (list_empty(&req->link))
- return 0;
-
if (i915_gem_request_completed(req))
return 0;
@@ -705,10 +723,13 @@ int i915_wait_request(struct drm_i915_gem_request *req)
{
int ret;
- GEM_BUG_ON(!req);
lockdep_assert_held(&req->i915->drm.struct_mutex);
+ GEM_BUG_ON(list_empty(&req->link));
- ret = __i915_wait_request(req, req->i915->mm.interruptible, NULL, NULL);
+ ret = __i915_wait_request(req,
+ req->i915->mm.interruptible,
+ NULL,
+ NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index dc93051a68d8..f0b91207aaa4 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -101,6 +101,7 @@ struct drm_i915_gem_request {
* error state dump only).
*/
struct drm_i915_gem_object *batch_obj;
+ struct list_head active_list;
/** Time at which this request was emitted, in jiffies. */
unsigned long emitted_jiffies;
@@ -213,8 +214,12 @@ struct intel_rps_client;
int __i915_wait_request(struct drm_i915_gem_request *req,
bool interruptible,
s64 *timeout,
- struct intel_rps_client *rps);
-int __must_check i915_wait_request(struct drm_i915_gem_request *req);
+ struct intel_rps_client *rps)
+ __attribute__((nonnull(1)));
+
+int __must_check
+i915_wait_request(struct drm_i915_gem_request *req)
+ __attribute__((nonnull));
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
@@ -278,9 +283,31 @@ static inline bool i915_spin_request(const struct drm_i915_gem_request *request,
*/
struct i915_gem_active {
struct drm_i915_gem_request *__request;
+ struct list_head link;
+ void (*retire)(struct i915_gem_active *,
+ struct drm_i915_gem_request *);
};
/**
+ * init_request_active - prepares the activity tracker for use
+ * @active - the active tracker
+ * @func - a callback when then the tracker is retired (becomes idle)
+ *
+ * init_request_active() prepares the embedded @active struct for use as
+ * an activity tracker, that is for tracking the last known active request
+ * associated with it. When the last request becomes idle, when it is retired
+ * after completion, the callback @func is invoked.
+ */
+static inline void
+init_request_active(struct i915_gem_active *active,
+ void (*func)(struct i915_gem_active *,
+ struct drm_i915_gem_request *))
+{
+ INIT_LIST_HEAD(&active->link);
+ active->retire = func;
+}
+
+/**
* i915_gem_active_set - updates the tracker to watch the current request
* @active - the active tracker
* @request - the request to watch
@@ -293,7 +320,8 @@ static inline void
i915_gem_active_set(struct i915_gem_active *active,
struct drm_i915_gem_request *request)
{
- i915_gem_request_assign(&active->__request, request);
+ list_move(&active->link, &request->active_list);
+ active->__request = request;
}
static inline struct drm_i915_gem_request *
@@ -303,17 +331,23 @@ __i915_gem_active_peek(const struct i915_gem_active *active)
}
/**
- * i915_gem_active_peek - report the request being monitored
+ * i915_gem_active_peek - report the active request being monitored
* @active - the active tracker
*
- * i915_gem_active_peek() returns the current request being tracked, or NULL.
- * It does not obtain a reference on the request for the caller, so the
- * caller must hold struct_mutex.
+ * i915_gem_active_peek() returns the current request being tracked if
+ * still active, or NULL. It does not obtain a reference on the request
+ * for the caller, so the caller must hold struct_mutex.
*/
static inline struct drm_i915_gem_request *
i915_gem_active_peek(const struct i915_gem_active *active, struct mutex *mutex)
{
- return active->__request;
+ struct drm_i915_gem_request *request;
+
+ request = active->__request;
+ if (!request || i915_gem_request_completed(request))
+ return NULL;
+
+ return request;
}
/**
@@ -326,13 +360,7 @@ i915_gem_active_peek(const struct i915_gem_active *active, struct mutex *mutex)
static inline struct drm_i915_gem_request *
i915_gem_active_get(const struct i915_gem_active *active, struct mutex *mutex)
{
- struct drm_i915_gem_request *request;
-
- request = i915_gem_active_peek(active, mutex);
- if (!request || i915_gem_request_completed(request))
- return NULL;
-
- return i915_gem_request_get(request);
+ return i915_gem_request_get(i915_gem_active_peek(active, mutex));
}
/**
@@ -361,13 +389,7 @@ static inline bool
i915_gem_active_is_idle(const struct i915_gem_active *active,
struct mutex *mutex)
{
- struct drm_i915_gem_request *request;
-
- request = i915_gem_active_peek(active, mutex);
- if (!request || i915_gem_request_completed(request))
- return true;
-
- return false;
+ return !i915_gem_active_peek(active, mutex);
}
/**
@@ -377,6 +399,9 @@ i915_gem_active_is_idle(const struct i915_gem_active *active,
* i915_gem_active_wait() waits until the request is completed before
* returning. Note that it does not guarantee that the request is
* retired first, see i915_gem_active_retire().
+ *
+ * i915_gem_active_wait() returns immediately if the active
+ * request is already complete.
*/
static inline int __must_check
i915_gem_active_wait(const struct i915_gem_active *active, struct mutex *mutex)
@@ -387,7 +412,7 @@ i915_gem_active_wait(const struct i915_gem_active *active, struct mutex *mutex)
if (!request)
return 0;
- return i915_wait_request(request);
+ return __i915_wait_request(request, true, NULL, NULL);
}
/**
@@ -400,10 +425,25 @@ i915_gem_active_wait(const struct i915_gem_active *active, struct mutex *mutex)
* tracker is idle, the function returns immediately.
*/
static inline int __must_check
-i915_gem_active_retire(const struct i915_gem_active *active,
+i915_gem_active_retire(struct i915_gem_active *active,
struct mutex *mutex)
{
- return i915_gem_active_wait(active, mutex);
+ struct drm_i915_gem_request *request;
+ int ret;
+
+ request = active->__request;
+ if (!request)
+ return 0;
+
+ ret = __i915_wait_request(request, true, NULL, NULL);
+ if (ret)
+ return ret;
+
+ list_del_init(&active->link);
+ active->__request = NULL;
+ active->retire(active, request);
+
+ return 0;
}
/* Convenience functions for peeking at state inside active's request whilst
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a97fd7f551a7..821ea10c885c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -176,7 +176,6 @@ void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
*/
void intel_engine_setup_common(struct intel_engine_cs *engine)
{
- INIT_LIST_HEAD(&engine->active_list);
INIT_LIST_HEAD(&engine->request_list);
INIT_LIST_HEAD(&engine->buffers);
INIT_LIST_HEAD(&engine->execlist_queue);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 21268d348d4e..51c059d8c917 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -291,18 +291,6 @@ struct intel_engine_cs {
u32 ctx_desc_template;
/**
- * List of objects currently involved in rendering from the
- * ringbuffer.
- *
- * Includes buffers having the contents of their GPU caches
- * flushed, not necessarily primitives. last_read_req
- * represents when the rendering involved will be completed.
- *
- * A reference is held on the buffer while on this list.
- */
- struct list_head active_list;
-
- /**
* List of breadcrumbs associated with GPU requests currently
* outstanding.
*/
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 44/55] drm/i915: Track requests inside each intel_ring
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (42 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 43/55] drm/i915: Refactor activity tracking for requests Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 10:10 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking Chris Wilson
` (12 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
By tracking each request occupying space inside an individual
intel_ring, we can greatly simplify the logic of tracking available
space and not worry about other timelines. (Each ring is an ordered
timeline of committed requests.)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_request.c | 2 ++
drivers/gpu/drm/i915/i915_gem_request.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++-----------
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 0216d6c093da..f1c37b7891cb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -174,6 +174,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
* Note this requires that we are always called in request
* completion order.
*/
+ list_del(&request->ring_link);
request->ring->last_retired_head = request->postfix;
/* Walk through the active list, calling retire on each. This allows
@@ -472,6 +473,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
request->previous_seqno = engine->last_submitted_seqno;
smp_store_mb(engine->last_submitted_seqno, request->fence.seqno);
list_add_tail(&request->link, &engine->request_list);
+ list_add_tail(&request->ring_link, &ring->request_list);
/* Record the position of the start of the request so that
* should we detect the updated seqno part-way through the
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index f0b91207aaa4..b1ee37896feb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -109,6 +109,9 @@ struct drm_i915_gem_request {
/** engine->request_list entry for this request */
struct list_head link;
+ /** ring->request_list entry for this request */
+ struct list_head ring_link;
+
struct drm_i915_file_private *file_priv;
/** file_priv list entry for this request */
struct list_head client_list;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5e0ba9416bd9..af76869c8db2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2059,6 +2059,8 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size)
ring->engine = engine;
list_add(&ring->link, &engine->buffers);
+ INIT_LIST_HEAD(&ring->request_list);
+
ring->size = size;
/* Workaround an erratum on the i830 which causes a hang if
* the TAIL pointer points to within the last 2 cachelines
@@ -2281,7 +2283,6 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
struct intel_ring *ring = req->ring;
- struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *target;
intel_ring_update_space(ring);
@@ -2299,17 +2300,9 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
*/
GEM_BUG_ON(!req->reserved_space);
- list_for_each_entry(target, &engine->request_list, link) {
+ list_for_each_entry(target, &ring->request_list, ring_link) {
unsigned space;
- /*
- * The request queue is per-engine, so can contain requests
- * from multiple ringbuffers. Here, we must ignore any that
- * aren't from the ringbuffer we're considering.
- */
- if (target->ring != ring)
- continue;
-
/* Would completion of this request free enough space? */
space = __intel_ring_space(target->postfix, ring->tail,
ring->size);
@@ -2317,7 +2310,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
break;
}
- if (WARN_ON(&target->link == &engine->request_list))
+ if (WARN_ON(&target->ring_link == &ring->request_list))
return -ENOSPC;
return i915_wait_request(target);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 51c059d8c917..2681106948a5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -90,6 +90,8 @@ struct intel_ring {
struct intel_engine_cs *engine;
struct list_head link;
+ struct list_head request_list;
+
u32 head;
u32 tail;
int space;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (43 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 44/55] drm/i915: Track requests inside each intel_ring Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-27 8:12 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 46/55] drm/i915: Move the special case wait-request handling to its one caller Chris Wilson
` (11 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
intel_overlay already tracks its last flip request, along with action to
take after its completion. Refactor intel_overlay to reuse the common
i915_gem_active tracker.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_overlay.c | 84 ++++++++++++++++--------------------
1 file changed, 36 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 651efe4e468e..1a42efb4f263 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -183,8 +183,7 @@ struct intel_overlay {
u32 flip_addr;
struct drm_i915_gem_object *reg_bo;
/* flip handling */
- struct drm_i915_gem_request *last_flip_req;
- void (*flip_tail)(struct intel_overlay *);
+ struct i915_gem_active last_flip;
};
static struct overlay_registers __iomem *
@@ -210,23 +209,26 @@ static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
io_mapping_unmap(regs);
}
-static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
+static void intel_overlay_submit_request(struct intel_overlay *overlay,
struct drm_i915_gem_request *req,
- void (*tail)(struct intel_overlay *))
+ void (*retire)(struct i915_gem_active *,
+ struct drm_i915_gem_request *))
{
- int ret;
-
- WARN_ON(overlay->last_flip_req);
- i915_gem_request_assign(&overlay->last_flip_req, req);
+ GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
+ &overlay->i915->drm.struct_mutex));
+ overlay->last_flip.retire = retire;
+ i915_gem_active_set(&overlay->last_flip, req);
i915_add_request(req);
+}
- overlay->flip_tail = tail;
- ret = i915_wait_request(overlay->last_flip_req);
- if (ret)
- return ret;
-
- i915_gem_request_assign(&overlay->last_flip_req, NULL);
- return 0;
+static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
+ struct drm_i915_gem_request *req,
+ void (*retire)(struct i915_gem_active *,
+ struct drm_i915_gem_request *))
+{
+ intel_overlay_submit_request(overlay, req, retire);
+ return i915_gem_active_retire(&overlay->last_flip,
+ &overlay->i915->drm.struct_mutex);
}
static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
@@ -306,25 +308,32 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
intel_ring_emit(ring, flip_addr);
intel_ring_advance(ring);
- WARN_ON(overlay->last_flip_req);
- i915_gem_request_assign(&overlay->last_flip_req, req);
- i915_add_request(req);
+ intel_overlay_submit_request(overlay, req, NULL);
return 0;
}
-static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
+static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
+ struct drm_i915_gem_request *req)
{
+ struct intel_overlay *overlay =
+ container_of(active, typeof(*overlay), last_flip);
struct drm_i915_gem_object *obj = overlay->old_vid_bo;
+ i915_gem_track_fb(obj, NULL,
+ INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
+
i915_gem_object_ggtt_unpin(obj);
i915_gem_object_put(obj);
overlay->old_vid_bo = NULL;
}
-static void intel_overlay_off_tail(struct intel_overlay *overlay)
+static void intel_overlay_off_tail(struct i915_gem_active *active,
+ struct drm_i915_gem_request *req)
{
+ struct intel_overlay *overlay =
+ container_of(active, typeof(*overlay), last_flip);
struct drm_i915_gem_object *obj = overlay->vid_bo;
/* never have the overlay hw on without showing a frame */
@@ -387,27 +396,16 @@ static int intel_overlay_off(struct intel_overlay *overlay)
}
intel_ring_advance(ring);
- return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
+ return intel_overlay_do_wait_request(overlay, req,
+ intel_overlay_off_tail);
}
/* recover from an interruption due to a signal
* We have to be careful not to repeat work forever an make forward progess. */
static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
{
- int ret;
-
- if (overlay->last_flip_req == NULL)
- return 0;
-
- ret = i915_wait_request(overlay->last_flip_req);
- if (ret)
- return ret;
-
- if (overlay->flip_tail)
- overlay->flip_tail(overlay);
-
- i915_gem_request_assign(&overlay->last_flip_req, NULL);
- return 0;
+ return i915_gem_active_retire(&overlay->last_flip,
+ &overlay->i915->drm.struct_mutex);
}
/* Wait for pending overlay flip and release old frame.
@@ -452,13 +450,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
intel_overlay_release_old_vid_tail);
if (ret)
return ret;
- }
+ } else
+ intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
- intel_overlay_release_old_vid_tail(overlay);
-
-
- i915_gem_track_fb(overlay->old_vid_bo, NULL,
- INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
return 0;
}
@@ -471,7 +465,6 @@ void intel_overlay_reset(struct drm_i915_private *dev_priv)
intel_overlay_release_old_vid(overlay);
- overlay->last_flip_req = NULL;
overlay->old_xscale = 0;
overlay->old_yscale = 0;
overlay->crtc = NULL;
@@ -882,12 +875,7 @@ int intel_overlay_switch_off(struct intel_overlay *overlay)
iowrite32(0, ®s->OCMD);
intel_overlay_unmap_regs(overlay, regs);
- ret = intel_overlay_off(overlay);
- if (ret != 0)
- return ret;
-
- intel_overlay_off_tail(overlay);
- return 0;
+ return intel_overlay_off(overlay);
}
static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
--
2.8.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 46/55] drm/i915: Move the special case wait-request handling to its one caller
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (44 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 12:39 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine Chris Wilson
` (10 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_request.c | 25 -------------------------
drivers/gpu/drm/i915/i915_gem_request.h | 4 ----
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++++++-----
3 files changed, 13 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index f1c37b7891cb..2c0c6a37f46a 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -716,28 +716,3 @@ complete:
return ret;
}
-
-/**
- * Waits for a request to be signaled, and cleans up the
- * request and object lists appropriately for that event.
- */
-int i915_wait_request(struct drm_i915_gem_request *req)
-{
- int ret;
-
- lockdep_assert_held(&req->i915->drm.struct_mutex);
- GEM_BUG_ON(list_empty(&req->link));
-
- ret = __i915_wait_request(req,
- req->i915->mm.interruptible,
- NULL,
- NULL);
- if (ret)
- return ret;
-
- /* If the GPU hung, we want to keep the requests to find the guilty. */
- if (!i915_reset_in_progress(&req->i915->gpu_error))
- i915_gem_request_retire_upto(req);
-
- return 0;
-}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index b1ee37896feb..f4aab8e60c9e 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -220,10 +220,6 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
struct intel_rps_client *rps)
__attribute__((nonnull(1)));
-int __must_check
-i915_wait_request(struct drm_i915_gem_request *req)
- __attribute__((nonnull));
-
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
/**
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index af76869c8db2..507576ef8077 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2284,6 +2284,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
struct intel_ring *ring = req->ring;
struct drm_i915_gem_request *target;
+ int ret;
intel_ring_update_space(ring);
if (ring->space >= bytes)
@@ -2313,7 +2314,18 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
if (WARN_ON(&target->ring_link == &ring->request_list))
return -ENOSPC;
- return i915_wait_request(target);
+ ret = __i915_wait_request(target, true, NULL, NULL);
+ if (ret)
+ return ret;
+
+ if (i915_reset_in_progress(&target->i915->gpu_error))
+ return -EAGAIN;
+
+ i915_gem_request_retire_upto(target);
+
+ intel_ring_update_space(ring);
+ GEM_BUG_ON(ring->space < bytes);
+ return 0;
}
int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
@@ -2351,10 +2363,6 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
int ret = wait_for_space(req, wait_bytes);
if (unlikely(ret))
return ret;
-
- intel_ring_update_space(ring);
- if (unlikely(ring->space < wait_bytes))
- return -EAGAIN;
}
if (unlikely(need_wrap)) {
--
2.8.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (45 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 46/55] drm/i915: Move the special case wait-request handling to its one caller Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 12:40 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 48/55] drm/i915: s/__i915_wait_request/i915_wait_request/ Chris Wilson
` (9 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
If the user floods the GPU with so many requests that the engine stalls
waiting for free space, don't automatically promote the GPU to maximum
frequencies. If the GPU really is saturated with work, it will migrate
to high clocks by itself, otherwise it is merely a user flooding us with
busy-work.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 507576ef8077..90e46d1b04e2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2314,7 +2314,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
if (WARN_ON(&target->ring_link == &ring->request_list))
return -ENOSPC;
- ret = __i915_wait_request(target, true, NULL, NULL);
+ ret = __i915_wait_request(target, true, NULL, NO_WAITBOOST);
if (ret)
return ret;
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 48/55] drm/i915: s/__i915_wait_request/i915_wait_request/
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (46 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 12:42 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 49/55] drm/i915: Double check activity before relocations Chris Wilson
` (8 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
There is onl one wait on request function now, so drop the "expert"
indication of leading __.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 18 +++++++++---------
drivers/gpu/drm/i915/i915_gem_request.c | 16 ++++++++--------
drivers/gpu/drm/i915/i915_gem_request.h | 12 ++++++------
drivers/gpu/drm/i915/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 14 +++++++-------
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
6 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b9874a99ae04..cc84f00cf883 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1420,7 +1420,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
mutex_unlock(&dev->struct_mutex);
ret = 0;
for (i = 0; ret == 0 && i < n; i++)
- ret = __i915_wait_request(requests[i], true, NULL, rps);
+ ret = i915_wait_request(requests[i], true, NULL, rps);
mutex_lock(&dev->struct_mutex);
for (i = 0; i < n; i++)
@@ -2733,9 +2733,9 @@ out:
for (i = 0; i < n; i++) {
if (ret == 0)
- ret = __i915_wait_request(requests[i], true,
- args->timeout_ns > 0 ? &args->timeout_ns : NULL,
- to_rps_client(file));
+ ret = i915_wait_request(requests[i], true,
+ args->timeout_ns > 0 ? &args->timeout_ns : NULL,
+ to_rps_client(file));
i915_gem_request_put(requests[i]);
}
return ret;
@@ -2751,10 +2751,10 @@ __i915_gem_object_sync(struct drm_i915_gem_request *to,
return 0;
if (!i915.semaphores) {
- ret = __i915_wait_request(from,
- from->i915->mm.interruptible,
- NULL,
- NO_WAITBOOST);
+ ret = i915_wait_request(from,
+ from->i915->mm.interruptible,
+ NULL,
+ NO_WAITBOOST);
if (ret)
return ret;
} else {
@@ -3723,7 +3723,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
if (target == NULL)
return 0;
- ret = __i915_wait_request(target, true, NULL, NULL);
+ ret = i915_wait_request(target, true, NULL, NULL);
i915_gem_request_put(target);
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 2c0c6a37f46a..1935591a98c1 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -70,9 +70,9 @@ static signed long i915_fence_wait(struct fence *fence,
timeout = NULL;
}
- ret = __i915_wait_request(to_request(fence),
- interruptible, timeout,
- NO_WAITBOOST);
+ ret = i915_wait_request(to_request(fence),
+ interruptible, timeout,
+ NO_WAITBOOST);
if (ret == -ETIME)
return 0;
@@ -564,7 +564,7 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req,
}
/**
- * __i915_wait_request - wait until execution of request has finished
+ * i915_wait_request - wait until execution of request has finished
* @req: duh!
* @interruptible: do an interruptible wait (normally yes)
* @timeout: in - how long to wait (NULL forever); out - how much time remaining
@@ -580,10 +580,10 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req,
* Returns 0 if the request was found within the alloted time. Else returns the
* errno with remaining time filled in timeout argument.
*/
-int __i915_wait_request(struct drm_i915_gem_request *req,
- bool interruptible,
- s64 *timeout,
- struct intel_rps_client *rps)
+int i915_wait_request(struct drm_i915_gem_request *req,
+ bool interruptible,
+ s64 *timeout,
+ struct intel_rps_client *rps)
{
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
DEFINE_WAIT(reset);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index f4aab8e60c9e..828e304b2f11 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -214,10 +214,10 @@ struct intel_rps_client;
#define IS_RPS_CLIENT(p) (!IS_ERR(p))
#define IS_RPS_USER(p) (!IS_ERR_OR_NULL(p))
-int __i915_wait_request(struct drm_i915_gem_request *req,
- bool interruptible,
- s64 *timeout,
- struct intel_rps_client *rps)
+int i915_wait_request(struct drm_i915_gem_request *req,
+ bool interruptible,
+ s64 *timeout,
+ struct intel_rps_client *rps)
__attribute__((nonnull(1)));
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
@@ -411,7 +411,7 @@ i915_gem_active_wait(const struct i915_gem_active *active, struct mutex *mutex)
if (!request)
return 0;
- return __i915_wait_request(request, true, NULL, NULL);
+ return i915_wait_request(request, true, NULL, NULL);
}
/**
@@ -434,7 +434,7 @@ i915_gem_active_retire(struct i915_gem_active *active,
if (!request)
return 0;
- ret = __i915_wait_request(request, true, NULL, NULL);
+ ret = i915_wait_request(request, true, NULL, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index e57521dbddc6..651a84ba840c 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -83,7 +83,7 @@ static void wait_rendering(struct drm_i915_gem_object *obj)
mutex_unlock(&dev->struct_mutex);
for (i = 0; i < n; i++)
- __i915_wait_request(requests[i], false, NULL, NULL);
+ i915_wait_request(requests[i], false, NULL, NULL);
mutex_lock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8ea9d5a301d4..ed2069c56036 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11471,9 +11471,9 @@ static void intel_mmio_flip_work_func(struct work_struct *w)
struct reservation_object *resv;
if (work->flip_queued_req)
- WARN_ON(__i915_wait_request(work->flip_queued_req,
- false, NULL,
- NO_WAITBOOST));
+ WARN_ON(i915_wait_request(work->flip_queued_req,
+ false, NULL,
+ NO_WAITBOOST));
/* For framebuffer backed by dmabuf, wait for fence */
resv = i915_gem_object_get_dmabuf_resv(obj);
@@ -13516,8 +13516,8 @@ static int intel_atomic_prepare_commit(struct drm_device *dev,
if (!intel_plane_state->wait_req)
continue;
- ret = __i915_wait_request(intel_plane_state->wait_req,
- true, NULL, NULL);
+ ret = i915_wait_request(intel_plane_state->wait_req,
+ true, NULL, NULL);
if (ret) {
/* Any hang should be swallowed by the wait */
WARN_ON(ret == -EIO);
@@ -13629,8 +13629,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
if (!intel_plane_state->wait_req)
continue;
- ret = __i915_wait_request(intel_plane_state->wait_req,
- true, NULL, NULL);
+ ret = i915_wait_request(intel_plane_state->wait_req,
+ true, NULL, NULL);
/* EIO should be eaten, and we can't get interrupted in the
* worker, and blocking commits have waited already. */
WARN_ON(ret);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 90e46d1b04e2..924aba1db22d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2255,9 +2255,9 @@ int intel_engine_idle(struct intel_engine_cs *engine)
link);
/* Make sure we do not trigger any retires */
- return __i915_wait_request(req,
- req->i915->mm.interruptible,
- NULL, NULL);
+ return i915_wait_request(req,
+ req->i915->mm.interruptible,
+ NULL, NULL);
}
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
@@ -2314,7 +2314,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
if (WARN_ON(&target->ring_link == &ring->request_list))
return -ENOSPC;
- ret = __i915_wait_request(target, true, NULL, NO_WAITBOOST);
+ ret = i915_wait_request(target, true, NULL, NO_WAITBOOST);
if (ret)
return ret;
--
2.8.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 49/55] drm/i915: Double check activity before relocations
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (47 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 48/55] drm/i915: s/__i915_wait_request/i915_wait_request/ Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 12:45 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c Chris Wilson
` (7 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
If the object is active and we need to perform a relocation upon it, we
need to take the slow relocation path. Before we do, double check the
active requests to see if they have completed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e1dfdbd8fc2e..9778b1bc6336 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -441,6 +441,20 @@ relocate_entry_clflush(struct drm_i915_gem_object *obj,
return 0;
}
+static bool object_is_idle(struct drm_i915_gem_object *obj)
+{
+ unsigned long active = obj->active;
+ int idx;
+
+ for_each_active(active, idx) {
+ if (!i915_gem_active_is_idle(&obj->last_read[idx],
+ &obj->base.dev->struct_mutex))
+ return false;
+ }
+
+ return true;
+}
+
static int
i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
struct eb_vmas *eb,
@@ -524,7 +538,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
}
/* We can't wait for rendering with pagefaults disabled */
- if (obj->active && pagefault_disabled())
+ if (pagefault_disabled() && !object_is_idle(obj))
return -EFAULT;
if (use_cpu_reloc(obj))
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (48 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 49/55] drm/i915: Double check activity before relocations Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 12:48 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 51/55] drm/i915: i915_vma_move_to_active prep patch Chris Wilson
` (6 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
As the list retirement is now clean of implementation details, we can
move it closer to the request management.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 44 ---------------------------------
drivers/gpu/drm/i915/i915_gem_request.c | 35 ++++++++++++++++++++++++++
2 files changed, 35 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cc84f00cf883..c572c80a6604 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2541,50 +2541,6 @@ void i915_gem_reset(struct drm_device *dev)
i915_gem_restore_fences(dev);
}
-/**
- * This function clears the request list as sequence numbers are passed.
- * @engine: engine to retire requests on
- */
-void
-i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
-{
- while (!list_empty(&engine->request_list)) {
- struct drm_i915_gem_request *request;
-
- request = list_first_entry(&engine->request_list,
- struct drm_i915_gem_request,
- link);
-
- if (!i915_gem_request_completed(request))
- break;
-
- i915_gem_request_retire_upto(request);
- }
-}
-
-void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
-{
- struct intel_engine_cs *engine;
-
- lockdep_assert_held(&dev_priv->drm.struct_mutex);
-
- if (dev_priv->gt.active_engines == 0)
- return;
-
- GEM_BUG_ON(!dev_priv->gt.awake);
-
- for_each_engine(engine, dev_priv) {
- i915_gem_retire_requests_ring(engine);
- if (list_empty(&engine->request_list))
- dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
- }
-
- if (dev_priv->gt.active_engines == 0)
- queue_delayed_work(dev_priv->wq,
- &dev_priv->gt.idle_work,
- msecs_to_jiffies(100));
-}
-
static void
i915_gem_retire_work_handler(struct work_struct *work)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 1935591a98c1..f41572aa53d4 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -716,3 +716,38 @@ complete:
return ret;
}
+
+void i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
+{
+ struct drm_i915_gem_request *request, *next;
+
+ list_for_each_entry_safe(request, next, &engine->request_list, link) {
+ if (!i915_gem_request_completed(request))
+ break;
+
+ i915_gem_request_retire(request);
+ }
+}
+
+void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
+{
+ struct intel_engine_cs *engine;
+
+ lockdep_assert_held(&dev_priv->drm.struct_mutex);
+
+ if (dev_priv->gt.active_engines == 0)
+ return;
+
+ GEM_BUG_ON(!dev_priv->gt.awake);
+
+ for_each_engine(engine, dev_priv) {
+ i915_gem_retire_requests_ring(engine);
+ if (list_empty(&engine->request_list))
+ dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
+ }
+
+ if (dev_priv->gt.active_engines == 0)
+ queue_delayed_work(dev_priv->wq,
+ &dev_priv->gt.idle_work,
+ msecs_to_jiffies(100));
+}
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 51/55] drm/i915: i915_vma_move_to_active prep patch
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (49 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-26 12:53 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 52/55] drm/i915: Track active vma requests Chris Wilson
` (5 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
This patch is broken out of the next just to remove the code motion from
that patch and make it more readable. What we do here is move the
i915_vma_move_to_active() to i915_gem_execbuffer.c and put the three
stages (read, write, fenced) together so that future modifications to
active handling are all located in the same spot. The importance of this
is so that we can more simply control the order in which the requests
are place in the retirement list (i.e. control the order at which we
retire and so control the lifetimes to avoid having to hold onto
references).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_gem.c | 18 --------
drivers/gpu/drm/i915/i915_gem_context.c | 9 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 65 ++++++++++++++++++----------
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
5 files changed, 51 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 03f12304308a..4876d2a6c2c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3153,7 +3153,8 @@ int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *to);
void i915_vma_move_to_active(struct i915_vma *vma,
- struct drm_i915_gem_request *req);
+ struct drm_i915_gem_request *req,
+ unsigned int flags);
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c572c80a6604..2e0b54fa03f9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2330,24 +2330,6 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
return obj->mapping;
}
-void i915_vma_move_to_active(struct i915_vma *vma,
- struct drm_i915_gem_request *req)
-{
- struct drm_i915_gem_object *obj = vma->obj;
- struct intel_engine_cs *engine;
-
- engine = i915_gem_request_get_engine(req);
-
- /* Add a reference if we're newly entering the active list. */
- if (obj->active == 0)
- i915_gem_object_get(obj);
- obj->active |= intel_engine_flag(engine);
-
- i915_gem_active_set(&obj->last_read[engine->id], req);
-
- list_move_tail(&vma->vm_link, &vma->vm->active_list);
-}
-
static void
i915_gem_object_retire__fence(struct i915_gem_active *active,
struct drm_i915_gem_request *req)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 60861f616f24..29b2547a2b4c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -816,8 +816,8 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
* MI_SET_CONTEXT instead of when the next seqno has completed.
*/
if (from != NULL) {
- from->engine[RCS].state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
- i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req);
+ struct drm_i915_gem_object *obj = from->engine[RCS].state;
+
/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
* whole damn pipeline, we don't need to explicitly mark the
* object dirty. The only exception is that the context must be
@@ -825,10 +825,11 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
* able to defer doing this until we know the object would be
* swapped, but there is no way to do that yet.
*/
- from->engine[RCS].state->dirty = 1;
+ obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+ i915_vma_move_to_active(i915_gem_obj_to_ggtt(obj), req, 0);
/* obj is kept alive until the next request by its active ref */
- i915_gem_object_ggtt_unpin(from->engine[RCS].state);
+ i915_gem_object_ggtt_unpin(obj);
i915_gem_context_put(from);
}
engine->last_context = i915_gem_context_get(to);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9778b1bc6336..d0f1da2863e4 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1143,43 +1143,64 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
return ctx;
}
+void i915_vma_move_to_active(struct i915_vma *vma,
+ struct drm_i915_gem_request *req,
+ unsigned int flags)
+{
+ struct drm_i915_gem_object *obj = vma->obj;
+ const unsigned int idx = req->engine->id;
+
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+
+ obj->dirty = 1; /* be paranoid */
+
+ /* Add a reference if we're newly entering the active list. */
+ if (obj->active == 0)
+ i915_gem_object_get(obj);
+ obj->active |= 1 << idx;
+ i915_gem_active_set(&obj->last_read[idx], req);
+
+ if (flags & EXEC_OBJECT_WRITE) {
+ i915_gem_active_set(&obj->last_write, req);
+
+ intel_fb_obj_invalidate(obj, ORIGIN_CS);
+
+ /* update for the implicit flush after a batch */
+ obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+ }
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE) {
+ i915_gem_active_set(&obj->last_fence, req);
+ if (flags & __EXEC_OBJECT_HAS_FENCE) {
+ struct drm_i915_private *dev_priv = req->i915;
+
+ list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
+ &dev_priv->mm.fence_list);
+ }
+ }
+
+ list_move_tail(&vma->vm_link, &vma->vm->active_list);
+}
+
static void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
struct i915_vma *vma;
list_for_each_entry(vma, vmas, exec_list) {
- struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
struct drm_i915_gem_object *obj = vma->obj;
u32 old_read = obj->base.read_domains;
u32 old_write = obj->base.write_domain;
- obj->dirty = 1; /* be paranoid */
obj->base.write_domain = obj->base.pending_write_domain;
- if (obj->base.write_domain == 0)
+ if (obj->base.write_domain)
+ vma->exec_entry->flags |= EXEC_OBJECT_WRITE;
+ else
obj->base.pending_read_domains |= obj->base.read_domains;
obj->base.read_domains = obj->base.pending_read_domains;
- i915_vma_move_to_active(vma, req);
- if (obj->base.write_domain) {
- i915_gem_active_set(&obj->last_write, req);
-
- intel_fb_obj_invalidate(obj, ORIGIN_CS);
-
- /* update for the implicit flush after a batch */
- obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
- }
- if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
- i915_gem_active_set(&obj->last_fence, req);
- if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
- struct drm_i915_private *dev_priv = engine->i915;
- list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
- &dev_priv->mm.fence_list);
- }
- }
-
+ i915_vma_move_to_active(vma, req, vma->exec_entry->flags);
trace_i915_gem_object_change_domain(obj, old_read, old_write);
}
}
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index f85c5505bce2..90236672ac1e 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -217,7 +217,7 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
goto err_unpin;
}
- i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
+ i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req, 0);
err_unpin:
i915_gem_object_ggtt_unpin(so.obj);
err_obj:
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 52/55] drm/i915: Track active vma requests
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (50 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 51/55] drm/i915: i915_vma_move_to_active prep patch Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-27 9:47 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 53/55] drm/i915: Release vma when the handle is closed Chris Wilson
` (4 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
Hook the vma itself into the i915_gem_request_retire() so that we can
accurately track when a solitary vma is inactive (as opposed to having
to wait for the entire object to be idle). This improves the interaction
when using multiple contexts (with full-ppgtt) and eliminates some
frequent list walking when retiring objects after a completed request.
A side-effect is that we get an active vma reference for free. The
consequence of this is shown in the next patch...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 50 +++++++++++++++++-------------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +++++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 28 +++++++++++++++++
5 files changed, 86 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6693dfbca4f1..3870eaeeddb4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -367,7 +367,7 @@ static int per_file_stats(int id, void *ptr, void *data)
continue;
}
- if (obj->active) /* XXX per-vma statistic */
+ if (i915_vma_is_active(vma))
stats->active += vma->node.size;
else
stats->inactive += vma->node.size;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2e0b54fa03f9..61fa8049076e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2354,7 +2354,6 @@ i915_gem_object_retire__read(struct i915_gem_active *active,
int idx = request->engine->id;
struct drm_i915_gem_object *obj =
container_of(active, struct drm_i915_gem_object, last_read[idx]);
- struct i915_vma *vma;
GEM_BUG_ON((obj->active & (1 << idx)) == 0);
@@ -2366,12 +2365,9 @@ i915_gem_object_retire__read(struct i915_gem_active *active,
* so that we don't steal from recently used but inactive objects
* (unless we are forced to ofc!)
*/
- list_move_tail(&obj->global_list, &request->i915->mm.bound_list);
-
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
- if (!list_empty(&vma->vm_link))
- list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
- }
+ if (obj->bind_count)
+ list_move_tail(&obj->global_list,
+ &request->i915->mm.bound_list);
i915_gem_object_put(obj);
}
@@ -2804,8 +2800,29 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
{
struct drm_i915_gem_object *obj = vma->obj;
+ unsigned long active;
int ret;
+ /* First wait upon any activity as retiring the request may
+ * have side-effects such as unpinning or even unbinding this vma.
+ */
+ active = vma->active;
+ if (active && wait) {
+ int idx;
+
+ for_each_active(active, idx) {
+ ret = i915_gem_active_retire(&vma->last_read[idx],
+ &vma->vm->dev->struct_mutex);
+ if (ret)
+ return ret;
+ }
+
+ GEM_BUG_ON(i915_vma_is_active(vma));
+ }
+
+ if (vma->pin_count)
+ return -EBUSY;
+
if (list_empty(&vma->obj_link))
return 0;
@@ -2814,18 +2831,9 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
return 0;
}
- if (vma->pin_count)
- return -EBUSY;
-
GEM_BUG_ON(obj->bind_count == 0);
GEM_BUG_ON(!obj->pages);
- if (wait) {
- ret = i915_gem_object_wait_rendering(obj, false);
- if (ret)
- return ret;
- }
-
if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
i915_gem_object_finish_gtt(obj);
@@ -3208,9 +3216,6 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
int
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
{
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
uint32_t old_write_domain, old_read_domains;
struct i915_vma *vma;
int ret;
@@ -3263,9 +3268,10 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
/* And bump the LRU for this access */
vma = i915_gem_obj_to_ggtt(obj);
- if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
- list_move_tail(&vma->vm_link,
- &ggtt->base.inactive_list);
+ if (vma &&
+ drm_mm_node_allocated(&vma->node) &&
+ !i915_vma_is_active(vma))
+ list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d0f1da2863e4..366ae72d479e 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1154,7 +1154,13 @@ void i915_vma_move_to_active(struct i915_vma *vma,
obj->dirty = 1; /* be paranoid */
- /* Add a reference if we're newly entering the active list. */
+ /* Add a reference if we're newly entering the active list.
+ * The order in which we add operations to the retirement queue is
+ * vital here: mark_active adds to the start of the callback list,
+ * such that subsequent callbacks are called first. Therefore we
+ * add the active reference first and queue for it to be dropped
+ * *last*.
+ */
if (obj->active == 0)
i915_gem_object_get(obj);
obj->active |= 1 << idx;
@@ -1179,6 +1185,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
}
}
+ i915_vma_set_active(vma, idx);
+ i915_gem_active_set(&vma->last_read[idx], req);
list_move_tail(&vma->vm_link, &vma->vm->active_list);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9d493b8e3bfc..ef0dc7131808 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3324,12 +3324,30 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
i915_ggtt_flush(dev_priv);
}
+static void
+i915_vma_retire(struct i915_gem_active *active,
+ struct drm_i915_gem_request *rq)
+{
+ const unsigned int idx = rq->engine->id;
+ struct i915_vma *vma =
+ container_of(active, struct i915_vma, last_read[idx]);
+
+ GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx));
+
+ i915_vma_unset_active(vma, idx);
+ if (i915_vma_is_active(vma))
+ return;
+
+ list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
+}
+
static struct i915_vma *
__i915_gem_vma_create(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
const struct i915_ggtt_view *ggtt_view)
{
struct i915_vma *vma;
+ int i;
if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
return ERR_PTR(-EINVAL);
@@ -3341,6 +3359,8 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
INIT_LIST_HEAD(&vma->vm_link);
INIT_LIST_HEAD(&vma->obj_link);
INIT_LIST_HEAD(&vma->exec_list);
+ for (i = 0; i < ARRAY_SIZE(vma->last_read); i++)
+ init_request_active(&vma->last_read[i], i915_vma_retire);
vma->vm = vm;
vma->obj = obj;
vma->is_ggtt = i915_is_ggtt(vm);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 529fb483afc8..d2206f40f7b2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -36,6 +36,8 @@
#include <linux/io-mapping.h>
+#include "i915_gem_request.h"
+
struct drm_i915_file_private;
typedef uint32_t gen6_pte_t;
@@ -179,6 +181,9 @@ struct i915_vma {
struct i915_address_space *vm;
void __iomem *iomap;
+ unsigned int active;
+ struct i915_gem_active last_read[I915_NUM_ENGINES];
+
/** Flags and address space this VMA is bound to */
#define GLOBAL_BIND (1<<0)
#define LOCAL_BIND (1<<1)
@@ -222,6 +227,29 @@ struct i915_vma {
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
};
+static inline bool i915_vma_is_active(const struct i915_vma *vma)
+{
+ return vma->active;
+}
+
+static inline void i915_vma_set_active(struct i915_vma *vma,
+ unsigned int engine)
+{
+ vma->active |= BIT(engine);
+}
+
+static inline void i915_vma_unset_active(struct i915_vma *vma,
+ unsigned int engine)
+{
+ vma->active &= ~BIT(engine);
+}
+
+static inline bool i915_vma_has_active_engine(const struct i915_vma *vma,
+ unsigned int engine)
+{
+ return vma->active & BIT(engine);
+}
+
struct i915_page_dma {
struct page *page;
union {
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 53/55] drm/i915: Release vma when the handle is closed
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (51 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 52/55] drm/i915: Track active vma requests Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-27 10:00 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 54/55] drm/i915: Mark the context and address space as closed Chris Wilson
` (3 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
In order to prevent a leak of the vma on shared objects, we need to
hook into the object_close callback to destroy the vma on the object for
this file. However, if we destroyed that vma immediately we may cause
unexpected application stalls as we try to unbind a busy vma - hence we
defer the unbind to when we retire the vma.
v2: Keep vma allocated until closed. This is useful for a later
optimisation, but it is required now in order to handle potential
recursion of i915_vma_unbind() by retiring itself.
v3: Comments are important.
Testcase: igt/gem_ppggtt/flink-and-close-vma-leak
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 88 ++++++++++++++++++-----------------
drivers/gpu/drm/i915/i915_gem_evict.c | 8 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 25 ++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
6 files changed, 77 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 478e8168ad94..869baa6a5196 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2574,6 +2574,7 @@ static struct drm_driver driver = {
.postclose = i915_driver_postclose,
.set_busid = drm_pci_set_busid,
+ .gem_close_object = i915_gem_close_object,
.gem_free_object = i915_gem_free_object,
.gem_vm_ops = &i915_gem_vm_ops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4876d2a6c2c4..56d6cf1749a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3014,8 +3014,8 @@ struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
size_t size);
struct drm_i915_gem_object *i915_gem_object_create_from_data(
struct drm_device *dev, const void *data, size_t size);
+void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
void i915_gem_free_object(struct drm_gem_object *obj);
-void i915_gem_vma_destroy(struct i915_vma *vma);
/* Flags used by pin/bind&friends. */
#define PIN_MAPPABLE (1<<0)
@@ -3048,6 +3048,8 @@ int __must_check i915_vma_unbind(struct i915_vma *vma);
* _guarantee_ VMA in question is _not in use_ anywhere.
*/
int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
+void i915_vma_close(struct i915_vma *vma);
+void i915_vma_destroy(struct i915_vma *vma);
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61fa8049076e..9d9dcb3c817f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2603,6 +2603,19 @@ out_rearm:
}
}
+void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
+{
+ struct drm_i915_gem_object *obj = to_intel_bo(gem);
+ struct drm_i915_file_private *fpriv = file->driver_priv;
+ struct i915_vma *vma, *vn;
+
+ mutex_lock(&obj->base.dev->struct_mutex);
+ list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
+ if (vma->vm->file == fpriv)
+ i915_vma_close(vma);
+ mutex_unlock(&obj->base.dev->struct_mutex);
+}
+
/**
* i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
* @dev: drm device pointer
@@ -2810,26 +2823,32 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
if (active && wait) {
int idx;
+ /* When a closed VMA is retired, it is unbound - eek.
+ * In order to prevent it from being recursively closed,
+ * take a pin on the vma so that the second unbind is
+ * aborted.
+ */
+ vma->pin_count++;
+
for_each_active(active, idx) {
ret = i915_gem_active_retire(&vma->last_read[idx],
&vma->vm->dev->struct_mutex);
if (ret)
- return ret;
+ break;
}
+ vma->pin_count--;
+ if (ret)
+ return ret;
+
GEM_BUG_ON(i915_vma_is_active(vma));
}
if (vma->pin_count)
return -EBUSY;
- if (list_empty(&vma->obj_link))
- return 0;
-
- if (!drm_mm_node_allocated(&vma->node)) {
- i915_gem_vma_destroy(vma);
- return 0;
- }
+ if (!drm_mm_node_allocated(&vma->node))
+ goto destroy;
GEM_BUG_ON(obj->bind_count == 0);
GEM_BUG_ON(!obj->pages);
@@ -2862,7 +2881,6 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
}
drm_mm_remove_node(&vma->node);
- i915_gem_vma_destroy(vma);
/* Since the unbound list is global, only move to that list if
* no more VMAs exist. */
@@ -2876,6 +2894,10 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
*/
i915_gem_object_unpin_pages(obj);
+destroy:
+ if (unlikely(vma->closed))
+ i915_vma_destroy(vma);
+
return 0;
}
@@ -3050,7 +3072,7 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
if (offset & (alignment - 1) || offset + size > end) {
ret = -EINVAL;
- goto err_free_vma;
+ goto err_vma;
}
vma->node.start = offset;
vma->node.size = size;
@@ -3062,7 +3084,7 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
ret = drm_mm_reserve_node(&vm->mm, &vma->node);
}
if (ret)
- goto err_free_vma;
+ goto err_vma;
} else {
if (flags & PIN_HIGH) {
search_flag = DRM_MM_SEARCH_BELOW;
@@ -3087,7 +3109,7 @@ search_free:
if (ret == 0)
goto search_free;
- goto err_free_vma;
+ goto err_vma;
}
}
if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
@@ -3108,8 +3130,7 @@ search_free:
err_remove_node:
drm_mm_remove_node(&vma->node);
-err_free_vma:
- i915_gem_vma_destroy(vma);
+err_vma:
vma = ERR_PTR(ret);
err_unpin:
i915_gem_object_unpin_pages(obj);
@@ -4063,21 +4084,18 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
trace_i915_gem_object_destroy(obj);
+ /* All file-owned VMA should have been released by this point through
+ * i915_gem_close_object(), or earlier by i915_gem_context_close().
+ * However, the object may also be bound into the global GTT (e.g.
+ * older GPUs without per-process support, or for direct access through
+ * the GTT either for the user or for scanout). Those VMA still need to
+ * unbound now.
+ */
list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
- int ret;
-
+ GEM_BUG_ON(!vma->is_ggtt);
+ GEM_BUG_ON(i915_vma_is_active(vma));
vma->pin_count = 0;
- ret = __i915_vma_unbind_no_wait(vma);
- if (WARN_ON(ret == -ERESTARTSYS)) {
- bool was_interruptible;
-
- was_interruptible = dev_priv->mm.interruptible;
- dev_priv->mm.interruptible = false;
-
- WARN_ON(i915_vma_unbind(vma));
-
- dev_priv->mm.interruptible = was_interruptible;
- }
+ i915_vma_close(vma);
}
GEM_BUG_ON(obj->bind_count);
@@ -4141,22 +4159,6 @@ struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
return NULL;
}
-void i915_gem_vma_destroy(struct i915_vma *vma)
-{
- WARN_ON(vma->node.allocated);
-
- /* Keep the vma as a placeholder in the execbuffer reservation lists */
- if (!list_empty(&vma->exec_list))
- return;
-
- if (!vma->is_ggtt)
- i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
-
- list_del(&vma->obj_link);
-
- kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
-}
-
static void
i915_gem_stop_engines(struct drm_device *dev)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index 81f7b4383d5e..3437ced76cb6 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -182,8 +182,8 @@ found:
struct i915_vma,
exec_list);
if (drm_mm_scan_remove_block(&vma->node)) {
+ vma->pin_count++;
list_move(&vma->exec_list, &eviction_list);
- i915_gem_object_get(vma->obj);
continue;
}
list_del_init(&vma->exec_list);
@@ -191,18 +191,14 @@ found:
/* Unbinding will emit any required flushes */
while (!list_empty(&eviction_list)) {
- struct drm_i915_gem_object *obj;
-
vma = list_first_entry(&eviction_list,
struct i915_vma,
exec_list);
- obj = vma->obj;
list_del_init(&vma->exec_list);
+ vma->pin_count--;
if (ret == 0)
ret = i915_vma_unbind(vma);
-
- i915_gem_object_put(obj);
}
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ef0dc7131808..bfac2448ba04 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3339,6 +3339,31 @@ i915_vma_retire(struct i915_gem_active *active,
return;
list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
+ if (unlikely(vma->closed && !vma->pin_count))
+ WARN_ON(i915_vma_unbind(vma));
+}
+
+void i915_vma_destroy(struct i915_vma *vma)
+{
+ GEM_BUG_ON(vma->node.allocated);
+ GEM_BUG_ON(i915_vma_is_active(vma));
+ GEM_BUG_ON(!vma->closed);
+
+ list_del(&vma->vm_link);
+ if (!vma->is_ggtt)
+ i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
+
+ kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
+}
+
+void i915_vma_close(struct i915_vma *vma)
+{
+ GEM_BUG_ON(vma->closed);
+ vma->closed = true;
+
+ list_del_init(&vma->obj_link);
+ if (!i915_vma_is_active(vma) && !vma->pin_count)
+ WARN_ON(__i915_vma_unbind_no_wait(vma));
}
static struct i915_vma *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index d2206f40f7b2..bef861e40e7c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -189,6 +189,7 @@ struct i915_vma {
#define LOCAL_BIND (1<<1)
unsigned int bound : 4;
bool is_ggtt : 1;
+ bool closed : 1;
/**
* Support different GGTT views into the same object.
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 54/55] drm/i915: Mark the context and address space as closed
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (52 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 53/55] drm/i915: Release vma when the handle is closed Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-27 10:13 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 55/55] Revert "drm/i915: Clean up associated VMAs on context destruction" Chris Wilson
` (2 subsequent siblings)
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
When the user closes the context mark it and the dependent address space
as closed. As we use an asynchronous destruct method, this has two
purposes. First it allows us to flag the closed context and detect
internal errors if we to create any new objects for it (as it is removed
from the user's namespace, these should be internal bugs only). And
secondly, it allows us to immediately reap stale vma.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 15 ++++++------
drivers/gpu/drm/i915/i915_gem_context.c | 43 ++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +++++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 9 +++++++
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
6 files changed, 63 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56d6cf1749a9..c6c64003504f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -907,6 +907,7 @@ struct i915_gem_context {
struct list_head link;
u8 remap_slice;
+ bool closed:1;
};
enum fb_op_origin {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9d9dcb3c817f..0d9a80b41101 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2864,12 +2864,15 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
__i915_vma_iounmap(vma);
}
- trace_i915_vma_unbind(vma);
-
- vma->vm->unbind_vma(vma);
+ if (likely(!vma->vm->closed)) {
+ trace_i915_vma_unbind(vma);
+ vma->vm->unbind_vma(vma);
+ }
vma->bound = 0;
- list_del_init(&vma->vm_link);
+ drm_mm_remove_node(&vma->node);
+ list_move_tail(&vma->vm_link, &vma->vm->unbound_list);
+
if (vma->is_ggtt) {
if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
obj->map_and_fenceable = false;
@@ -2880,8 +2883,6 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
vma->ggtt_view.pages = NULL;
}
- drm_mm_remove_node(&vma->node);
-
/* Since the unbound list is global, only move to that list if
* no more VMAs exist. */
if (--obj->bind_count == 0)
@@ -3123,7 +3124,7 @@ search_free:
goto err_remove_node;
list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
- list_add_tail(&vma->vm_link, &vm->inactive_list);
+ list_move_tail(&vma->vm_link, &vm->inactive_list);
obj->bind_count++;
return vma;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 29b2547a2b4c..1ba6c0bb856a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -156,6 +156,7 @@ void i915_gem_context_free(struct kref *ctx_ref)
lockdep_assert_held(&ctx->i915->drm.struct_mutex);
trace_i915_context_free(ctx);
+ GEM_BUG_ON(!ctx->closed);
/*
* This context is going away and we need to remove all VMAs still
@@ -224,6 +225,37 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
return obj;
}
+static void i915_ppgtt_close(struct i915_address_space *vm)
+{
+ struct list_head *phases[] = {
+ &vm->active_list,
+ &vm->inactive_list,
+ &vm->unbound_list,
+ NULL,
+ }, **phase;
+
+ GEM_BUG_ON(vm->closed);
+ vm->closed = true;
+
+ for (phase = phases; *phase; phase++) {
+ struct i915_vma *vma, *vn;
+
+ list_for_each_entry_safe(vma, vn, *phase, vm_link)
+ if (!vma->closed)
+ i915_vma_close(vma);
+ }
+}
+
+static void context_close(struct i915_gem_context *ctx)
+{
+ GEM_BUG_ON(ctx->closed);
+ ctx->closed = true;
+ if (ctx->ppgtt)
+ i915_ppgtt_close(&ctx->ppgtt->base);
+ ctx->file_priv = ERR_PTR(-EBADF);
+ i915_gem_context_put(ctx);
+}
+
static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
{
int ret;
@@ -305,7 +337,7 @@ __create_hw_context(struct drm_device *dev,
return ctx;
err_out:
- i915_gem_context_put(ctx);
+ context_close(ctx);
return ERR_PTR(ret);
}
@@ -334,7 +366,7 @@ i915_gem_create_context(struct drm_device *dev,
DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
idr_remove(&file_priv->context_idr, ctx->user_handle);
- i915_gem_context_put(ctx);
+ context_close(ctx);
return ERR_CAST(ppgtt);
}
@@ -505,7 +537,7 @@ void i915_gem_context_fini(struct drm_device *dev)
lockdep_assert_held(&dev->struct_mutex);
- i915_gem_context_put(dctx);
+ context_close(dctx);
dev_priv->kernel_context = NULL;
ida_destroy(&dev_priv->context_hw_ida);
@@ -515,8 +547,7 @@ static int context_idr_cleanup(int id, void *p, void *data)
{
struct i915_gem_context *ctx = p;
- ctx->file_priv = ERR_PTR(-EBADF);
- i915_gem_context_put(ctx);
+ context_close(ctx);
return 0;
}
@@ -1014,7 +1045,7 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
}
idr_remove(&file_priv->context_idr, ctx->user_handle);
- i915_gem_context_put(ctx);
+ context_close(ctx);
mutex_unlock(&dev->struct_mutex);
DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bfac2448ba04..d2130da3de9d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2126,6 +2126,7 @@ static void i915_address_space_init(struct i915_address_space *vm,
vm->dev = &dev_priv->drm;
INIT_LIST_HEAD(&vm->active_list);
INIT_LIST_HEAD(&vm->inactive_list);
+ INIT_LIST_HEAD(&vm->unbound_list);
list_add_tail(&vm->global_link, &dev_priv->vm_list);
}
@@ -2218,9 +2219,10 @@ void i915_ppgtt_release(struct kref *kref)
trace_i915_ppgtt_release(&ppgtt->base);
- /* vmas should already be unbound */
+ /* vmas should already be unbound and destroyed */
WARN_ON(!list_empty(&ppgtt->base.active_list));
WARN_ON(!list_empty(&ppgtt->base.inactive_list));
+ WARN_ON(!list_empty(&ppgtt->base.unbound_list));
list_del(&ppgtt->base.global_link);
drm_mm_takedown(&ppgtt->base.mm);
@@ -3374,6 +3376,8 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
struct i915_vma *vma;
int i;
+ GEM_BUG_ON(vm->closed);
+
if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
return ERR_PTR(-EINVAL);
@@ -3381,11 +3385,11 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
if (vma == NULL)
return ERR_PTR(-ENOMEM);
- INIT_LIST_HEAD(&vma->vm_link);
INIT_LIST_HEAD(&vma->obj_link);
INIT_LIST_HEAD(&vma->exec_list);
for (i = 0; i < ARRAY_SIZE(vma->last_read); i++)
init_request_active(&vma->last_read[i], i915_vma_retire);
+ list_add(&vma->vm_link, &vm->unbound_list);
vma->vm = vm;
vma->obj = obj;
vma->is_ggtt = i915_is_ggtt(vm);
@@ -3426,6 +3430,7 @@ i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
if (!vma)
vma = __i915_gem_vma_create(obj, &ggtt->base, view);
+ GEM_BUG_ON(vma->closed);
return vma;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index bef861e40e7c..a79015bf7261 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -314,6 +314,8 @@ struct i915_address_space {
u64 start; /* Start offset always 0 for dri2 */
u64 total; /* size addr space maps (ex. 2GB for ggtt) */
+ bool closed;
+
struct i915_page_scratch *scratch_page;
struct i915_page_table *scratch_pt;
struct i915_page_directory *scratch_pd;
@@ -342,6 +344,13 @@ struct i915_address_space {
*/
struct list_head inactive_list;
+ /**
+ * List of vma that have been unbound.
+ *
+ * A reference is not held on the buffer while on this list.
+ */
+ struct list_head unbound_list;
+
/* FIXME: Need a more generic return type */
gen6_pte_t (*pte_encode)(dma_addr_t addr,
enum i915_cache_level level,
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 2c321c8df7c3..bc91ffe614e2 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -707,7 +707,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
vma->bound |= GLOBAL_BIND;
__i915_vma_set_map_and_fenceable(vma);
- list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
+ list_move_tail(&vma->vm_link, &ggtt->base.inactive_list);
obj->bind_count++;
list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
--
2.8.1
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^ permalink raw reply related [flat|nested] 124+ messages in thread
* [PATCH 55/55] Revert "drm/i915: Clean up associated VMAs on context destruction"
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (53 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 54/55] drm/i915: Mark the context and address space as closed Chris Wilson
@ 2016-07-25 17:32 ` Chris Wilson
2016-07-27 10:18 ` Joonas Lahtinen
2016-07-26 5:18 ` ✗ Ro.CI.BAT: warning for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Patchwork
2016-07-26 10:48 ` ✗ Ro.CI.BAT: failure for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() (rev2) Patchwork
56 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-25 17:32 UTC (permalink / raw)
To: intel-gfx
This reverts commit e9f24d5fb7cf3628b195b18ff3ac4e37937ceeae.
The patch was only a stop-gap measure that fixed half the problem - the
leak of the fbcon when restarting X. A complete solution required
releasing the VMA when the object itself was closed rather than rely on
file/process exit. The previous patches add the VMA tracking necessary
to do close them along with the object, context or file, and so the time
has come to remove the partial fix.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 5 -----
drivers/gpu/drm/i915/i915_gem.c | 14 ++------------
drivers/gpu/drm/i915/i915_gem_context.c | 22 ----------------------
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
4 files changed, 3 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c6c64003504f..40033ca30e55 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3044,11 +3044,6 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
u32 flags);
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
int __must_check i915_vma_unbind(struct i915_vma *vma);
-/*
- * BEWARE: Do not use the function below unless you can _absolutely_
- * _guarantee_ VMA in question is _not in use_ anywhere.
- */
-int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
void i915_vma_close(struct i915_vma *vma);
void i915_vma_destroy(struct i915_vma *vma);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0d9a80b41101..e3278f4e1ad2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2810,7 +2810,7 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
vma->iomap = NULL;
}
-static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
+int i915_vma_unbind(struct i915_vma *vma)
{
struct drm_i915_gem_object *obj = vma->obj;
unsigned long active;
@@ -2820,7 +2820,7 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
* have side-effects such as unpinning or even unbinding this vma.
*/
active = vma->active;
- if (active && wait) {
+ if (active) {
int idx;
/* When a closed VMA is retired, it is unbound - eek.
@@ -2902,16 +2902,6 @@ destroy:
return 0;
}
-int i915_vma_unbind(struct i915_vma *vma)
-{
- return __i915_vma_unbind(vma, true);
-}
-
-int __i915_vma_unbind_no_wait(struct i915_vma *vma)
-{
- return __i915_vma_unbind(vma, false);
-}
-
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 1ba6c0bb856a..e9da8aaaa41d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -134,21 +134,6 @@ static int get_context_size(struct drm_i915_private *dev_priv)
return ret;
}
-static void i915_gem_context_clean(struct i915_gem_context *ctx)
-{
- struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
- struct i915_vma *vma, *next;
-
- if (!ppgtt)
- return;
-
- list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
- vm_link) {
- if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
- break;
- }
-}
-
void i915_gem_context_free(struct kref *ctx_ref)
{
struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
@@ -158,13 +143,6 @@ void i915_gem_context_free(struct kref *ctx_ref)
trace_i915_context_free(ctx);
GEM_BUG_ON(!ctx->closed);
- /*
- * This context is going away and we need to remove all VMAs still
- * around. This is to handle imported shared objects for which
- * destructor did not run when their handles were closed.
- */
- i915_gem_context_clean(ctx);
-
i915_ppgtt_put(ctx->ppgtt);
for (i = 0; i < I915_NUM_ENGINES; i++) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d2130da3de9d..e19a5fd5f15f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3365,7 +3365,7 @@ void i915_vma_close(struct i915_vma *vma)
list_del_init(&vma->obj_link);
if (!i915_vma_is_active(vma) && !vma->pin_count)
- WARN_ON(__i915_vma_unbind_no_wait(vma));
+ WARN_ON(i915_vma_unbind(vma));
}
static struct i915_vma *
--
2.8.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* Re: [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
2016-07-25 17:31 ` [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture Chris Wilson
@ 2016-07-26 4:59 ` Joonas Lahtinen
2016-07-26 8:19 ` Chris Wilson
2016-07-26 10:21 ` [PATCH v2] " Chris Wilson
0 siblings, 2 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 4:59 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> Inside the error capture itself, we refer to not only the hardware
> engine, its ringbuffer but also the capture state. Finding clear names
> for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
> compromise we keep using ering for the error capture.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-chris@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 255 +++++++++++++++++-----------------
> 2 files changed, 134 insertions(+), 127 deletions(-)
>
<SNIP>
> @@ -240,69 +240,71 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
> }
>
> static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
> - struct drm_device *dev,
> - struct drm_i915_error_state *error,
> - int ring_idx)
> + struct drm_device *dev,
> + struct drm_i915_error_state *error,
> + int engine_idx)
> {
> - struct drm_i915_error_ring *ring = &error->ring[ring_idx];
> + struct drm_i915_error_engine *ering = &error->engine[engine_idx];
>
I'd be inclined keeping the struct and variable names close, so rather
eengine. Even though the error state is a mashup. We fill the ring
state to the engine error state. Function could be
i915_engine_error_ring_state() or so, to "reduce" confusion?
> @@ -414,7 +416,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> if (IS_GEN7(dev))
> err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
>
> - for (i = 0; i < ARRAY_SIZE(error->ring); i++)
> + for (i = 0; i < ARRAY_SIZE(error->engine); i++)
> i915_ring_error_state(m, dev, error, i);
>
This captures the engine related ring state, I think it's even worth a
comment when there is engine vs. error disparity.
And how about the messages? Should we update them more agressively
where necessary.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
2016-07-25 17:31 ` [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c Chris Wilson
@ 2016-07-26 5:02 ` Joonas Lahtinen
2016-07-26 8:12 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 5:02 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> A few places we use ring when referring to the struct intel_engine_cs. An
> anachronism we are pruning out.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-9-git-send-email-chris@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_gem.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e155e8dd28ed..7bfce1d5c61b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -46,7 +46,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
> static void
> i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
> static void
> -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
> +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
I vote for engine_idx variable name, that much I dislike differing
naming in signature and implementation.
Regards, Joonas
>
> static bool cpu_cache_is_coherent(struct drm_device *dev,
> enum i915_cache_level level)
> @@ -1385,10 +1385,10 @@ static void
> i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> struct drm_i915_gem_request *req)
> {
> - int ring = req->engine->id;
> + int idx = req->engine->id;
>
> - if (obj->last_read_req[ring] == req)
> - i915_gem_object_retire__read(obj, ring);
> + if (obj->last_read_req[idx] == req)
> + i915_gem_object_retire__read(obj, idx);
> else if (obj->last_write_req == req)
> i915_gem_object_retire__write(obj);
>
> @@ -2381,20 +2381,20 @@ i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> }
>
> static void
> -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
> +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> {
> struct i915_vma *vma;
>
> - GEM_BUG_ON(obj->last_read_req[ring] == NULL);
> - GEM_BUG_ON(!(obj->active & (1 << ring)));
> + GEM_BUG_ON(obj->last_read_req[idx] == NULL);
> + GEM_BUG_ON(!(obj->active & (1 << idx)));
>
> - list_del_init(&obj->engine_list[ring]);
> - i915_gem_request_assign(&obj->last_read_req[ring], NULL);
> + list_del_init(&obj->engine_list[idx]);
> + i915_gem_request_assign(&obj->last_read_req[idx], NULL);
>
> - if (obj->last_write_req && obj->last_write_req->engine->id == ring)
> + if (obj->last_write_req && obj->last_write_req->engine->id == idx)
> i915_gem_object_retire__write(obj);
>
> - obj->active &= ~(1 << ring);
> + obj->active &= ~(1 << idx);
> if (obj->active)
> return;
>
> @@ -4599,7 +4599,7 @@ int i915_gem_init(struct drm_device *dev)
>
> ret = i915_gem_init_hw(dev);
> if (ret == -EIO) {
> - /* Allow ring initialisation to fail by marking the GPU as
> + /* Allow engine initialisation to fail by marking the GPU as
> * wedged. But we only want to do this where the GPU is angry,
> * for all other failure, such as an allocation failure, bail.
> */
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty
2016-07-25 17:31 ` [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty Chris Wilson
@ 2016-07-26 5:06 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 5:06 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> Space for flushing the GPU cache prior to completing the request is
> preallocated and so cannot fail - the GPU caches will always be flushed
> along with the completed request. This means we no longer have to track
> whether the GPU cache is dirty between batches like we had to with the
> outstanding_lazy_seqno.
>
> With the removal of the duplication in the per-backend entry points for
> emitting the obsolete lazy flush, we can then further unify the
> engine->emit_flush.
>
> v2: Expand a bit on the legacy of gpu_caches_dirty
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-18-git-send-email-chris@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 +---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +++--
> drivers/gpu/drm/i915/i915_gem_request.c | 8 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 47 +++----------------
> drivers/gpu/drm/i915/intel_lrc.h | 2 -
> drivers/gpu/drm/i915/intel_ringbuffer.c | 72 +++++++-----------------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ---
> 8 files changed, 37 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 3336a5fcd029..beece8feb8fe 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -568,7 +568,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> * itlb_before_ctx_switch.
> */
> if (IS_GEN6(dev_priv)) {
> - ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
> + ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index d0ef675fb169..35c4c595e5ba 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -998,10 +998,8 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
> if (flush_domains & I915_GEM_DOMAIN_GTT)
> wmb();
>
> - /* Unconditionally invalidate gpu caches and ensure that we do flush
> - * any residual writes from the previous batch.
> - */
> - return intel_engine_invalidate_all_caches(req);
> + /* Unconditionally invalidate GPU caches and TLBs. */
> + return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
> }
>
> static bool
> @@ -1163,9 +1161,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
> static void
> i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
> {
> - /* Unconditionally force add_request to emit a full flush. */
> - params->engine->gpu_caches_dirty = true;
> -
> /* Add a breadcrumb for the completion of the batch buffer */
> __i915_add_request(params->request, params->batch_obj, true);
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ebfa0406a6a1..39fa9eb10514 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1666,7 +1666,8 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1693,7 +1694,8 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1711,8 +1713,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
>
> /* XXX: RCS is the only one to auto invalidate the TLBs? */
> if (engine->id != RCS) {
> - ret = engine->flush(req,
> - I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 942b5b1f1602..7e3206051ced 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -451,12 +451,10 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> * what.
> */
> if (flush_caches) {
> - if (i915.enable_execlists)
> - ret = logical_ring_flush_all_caches(request);
> - else
> - ret = intel_engine_flush_all_caches(request);
> + ret = engine->emit_flush(request, 0, I915_GEM_GPU_DOMAINS);
> +
> /* Not allowed to fail! */
> - WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
> + WARN(ret, "engine->emit_flush() failed: %d!\n", ret);
> }
>
> trace_i915_gem_request_add(request);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 86b8f41c254d..e8d971e81491 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -642,24 +642,6 @@ static void execlists_context_queue(struct drm_i915_gem_request *request)
> spin_unlock_bh(&engine->execlist_lock);
> }
>
> -static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - uint32_t flush_domains;
> - int ret;
> -
> - flush_domains = 0;
> - if (engine->gpu_caches_dirty)
> - flush_domains = I915_GEM_GPU_DOMAINS;
> -
> - ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
> - if (ret)
> - return ret;
> -
> - engine->gpu_caches_dirty = false;
> - return 0;
> -}
> -
> static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
> struct list_head *vmas)
> {
> @@ -690,7 +672,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
> /* Unconditionally invalidate gpu caches and ensure that we do flush
> * any residual writes from the previous batch.
> */
> - return logical_ring_invalidate_all_caches(req);
> + return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
> }
>
> int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
> @@ -930,22 +912,6 @@ void intel_logical_ring_stop(struct intel_engine_cs *engine)
> I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
> }
>
> -int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - int ret;
> -
> - if (!engine->gpu_caches_dirty)
> - return 0;
> -
> - ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
> - if (ret)
> - return ret;
> -
> - engine->gpu_caches_dirty = false;
> - return 0;
> -}
> -
> static int intel_lr_context_pin(struct i915_gem_context *ctx,
> struct intel_engine_cs *engine)
> {
> @@ -1026,15 +992,15 @@ void intel_lr_context_unpin(struct i915_gem_context *ctx,
> static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> int ret, i;
> - struct intel_engine_cs *engine = req->engine;
> struct intel_ring *ring = req->ring;
> struct i915_workarounds *w = &req->i915->workarounds;
>
> if (w->count == 0)
> return 0;
>
> - engine->gpu_caches_dirty = true;
> - ret = logical_ring_flush_all_caches(req);
> + ret = req->engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1051,8 +1017,9 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
>
> intel_ring_advance(ring);
>
> - engine->gpu_caches_dirty = true;
> - ret = logical_ring_flush_all_caches(req);
> + ret = req->engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index d26fb44549e5..33e0193e5451 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -72,8 +72,6 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine);
>
> int intel_engines_init(struct drm_device *dev);
>
> -int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
> -
> /* Logical Ring Contexts */
>
> /* One extra page is added before LRC for GuC as shared data */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index e7a7f67ab06d..9e4b49644553 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -688,8 +688,9 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
> if (w->count == 0)
> return 0;
>
> - req->engine->gpu_caches_dirty = true;
> - ret = intel_engine_flush_all_caches(req);
> + ret = req->engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -706,8 +707,9 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
>
> intel_ring_advance(ring);
>
> - req->engine->gpu_caches_dirty = true;
> - ret = intel_engine_flush_all_caches(req);
> + ret = req->engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -2860,21 +2862,21 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
> if (INTEL_GEN(dev_priv) >= 8) {
> engine->init_context = intel_rcs_ctx_init;
> engine->add_request = gen8_render_add_request;
> - engine->flush = gen8_render_ring_flush;
> + engine->emit_flush = gen8_render_ring_flush;
> if (i915.semaphores)
> engine->semaphore.signal = gen8_rcs_signal;
> } else if (INTEL_GEN(dev_priv) >= 6) {
> engine->init_context = intel_rcs_ctx_init;
> - engine->flush = gen7_render_ring_flush;
> + engine->emit_flush = gen7_render_ring_flush;
> if (IS_GEN6(dev_priv))
> - engine->flush = gen6_render_ring_flush;
> + engine->emit_flush = gen6_render_ring_flush;
> } else if (IS_GEN5(dev_priv)) {
> - engine->flush = gen4_render_ring_flush;
> + engine->emit_flush = gen4_render_ring_flush;
> } else {
> if (INTEL_GEN(dev_priv) < 4)
> - engine->flush = gen2_render_ring_flush;
> + engine->emit_flush = gen2_render_ring_flush;
> else
> - engine->flush = gen4_render_ring_flush;
> + engine->emit_flush = gen4_render_ring_flush;
> engine->irq_enable_mask = I915_USER_INTERRUPT;
> }
>
> @@ -2911,12 +2913,12 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
> /* gen6 bsd needs a special wa for tail updates */
> if (IS_GEN6(dev_priv))
> engine->write_tail = gen6_bsd_ring_write_tail;
> - engine->flush = gen6_bsd_ring_flush;
> + engine->emit_flush = gen6_bsd_ring_flush;
> if (INTEL_GEN(dev_priv) < 8)
> engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> } else {
> engine->mmio_base = BSD_RING_BASE;
> - engine->flush = bsd_ring_flush;
> + engine->emit_flush = bsd_ring_flush;
> if (IS_GEN5(dev_priv))
> engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> else
> @@ -2935,7 +2937,7 @@ int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
>
> intel_ring_default_vfuncs(dev_priv, engine);
>
> - engine->flush = gen6_bsd_ring_flush;
> + engine->emit_flush = gen6_bsd_ring_flush;
>
> return intel_init_ring_buffer(engine);
> }
> @@ -2946,7 +2948,7 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
>
> intel_ring_default_vfuncs(dev_priv, engine);
>
> - engine->flush = gen6_ring_flush;
> + engine->emit_flush = gen6_ring_flush;
> if (INTEL_GEN(dev_priv) < 8)
> engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>
> @@ -2959,7 +2961,7 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
>
> intel_ring_default_vfuncs(dev_priv, engine);
>
> - engine->flush = gen6_ring_flush;
> + engine->emit_flush = gen6_ring_flush;
>
> if (INTEL_GEN(dev_priv) < 8) {
> engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
> @@ -2970,46 +2972,6 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
> return intel_init_ring_buffer(engine);
> }
>
> -int
> -intel_engine_flush_all_caches(struct drm_i915_gem_request *req)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - int ret;
> -
> - if (!engine->gpu_caches_dirty)
> - return 0;
> -
> - ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
> - if (ret)
> - return ret;
> -
> - trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
> -
> - engine->gpu_caches_dirty = false;
> - return 0;
> -}
> -
> -int
> -intel_engine_invalidate_all_caches(struct drm_i915_gem_request *req)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - uint32_t flush_domains;
> - int ret;
> -
> - flush_domains = 0;
> - if (engine->gpu_caches_dirty)
> - flush_domains = I915_GEM_GPU_DOMAINS;
> -
> - ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
> - if (ret)
> - return ret;
> -
> - trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
> -
> - engine->gpu_caches_dirty = false;
> - return 0;
> -}
> -
> void intel_engine_stop(struct intel_engine_cs *engine)
> {
> int ret;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index ba54ffcdd55a..00723401f98c 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -206,9 +206,6 @@ struct intel_engine_cs {
>
> void (*write_tail)(struct intel_engine_cs *engine,
> u32 value);
> - int __must_check (*flush)(struct drm_i915_gem_request *req,
> - u32 invalidate_domains,
> - u32 flush_domains);
> int (*add_request)(struct drm_i915_gem_request *req);
> /* Some chipsets are not quite as coherent as advertised and need
> * an expensive kick to force a true read of the up-to-date seqno.
> @@ -325,8 +322,6 @@ struct intel_engine_cs {
> */
> u32 last_submitted_seqno;
>
> - bool gpu_caches_dirty;
> -
> struct i915_gem_context *last_context;
>
> struct intel_engine_hangcheck hangcheck;
> @@ -474,8 +469,6 @@ void intel_ring_update_space(struct intel_ring *ring);
>
> int __must_check intel_engine_idle(struct intel_engine_cs *engine);
> void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
> -int intel_engine_flush_all_caches(struct drm_i915_gem_request *req);
> -int intel_engine_invalidate_all_caches(struct drm_i915_gem_request *req);
>
> int intel_init_pipe_control(struct intel_engine_cs *engine, int size);
> void intel_fini_pipe_control(struct intel_engine_cs *engine);
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
2016-07-25 17:31 ` [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Chris Wilson
@ 2016-07-26 5:07 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 5:07 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> Since intel_engine_enable_signaling() is now only called via
> fence_enable_sw_signaling(), we can rely on it to provide serialisation
> and run-once for us and so make ourselves slightly simpler.
>
Done in previous series, copying here;
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-2-git-send-email-chris@chris-wilson.co.uk
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/intel_breadcrumbs.c | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index d893ccdd62ac..90867446f1a5 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -480,19 +480,15 @@ void intel_engine_enable_signaling(struct drm_i915_gem_request *request)
> struct rb_node *parent, **p;
> bool first, wakeup;
>
> - if (unlikely(READ_ONCE(request->signaling.wait.tsk)))
> - return;
> -
> - spin_lock(&b->lock);
> - if (unlikely(request->signaling.wait.tsk)) {
> - wakeup = false;
> - goto unlock;
> - }
> + /* locked by fence_enable_sw_signaling() */
> + assert_spin_locked(&request->lock);
>
> request->signaling.wait.tsk = b->signaler;
> request->signaling.wait.seqno = request->fence.seqno;
> i915_gem_request_get(request);
>
> + spin_lock(&b->lock);
> +
> /* First add ourselves into the list of waiters, but register our
> * bottom-half as the signaller thread. As per usual, only the oldest
> * waiter (not just signaller) is tasked as the bottom-half waking
> @@ -525,7 +521,6 @@ void intel_engine_enable_signaling(struct drm_i915_gem_request *request)
> if (first)
> smp_store_mb(b->first_signal, request);
>
> -unlock:
> spin_unlock(&b->lock);
>
> if (wakeup)
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request
2016-07-25 17:31 ` [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request Chris Wilson
@ 2016-07-26 5:09 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 5:09 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> If is simpler and leads to more readable code through the callstack if
> the allocation returns the allocated struct through the return value.
>
> The importance of this is that it no longer looks like we accidentally
> allocate requests as side-effect of calling certain functions.
>
I already added in previous series; CC'ing Dave again.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-19-git-send-email-chris@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/i915_gem.c | 75 ++++++++----------------------
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 ++---
> drivers/gpu/drm/i915/i915_gem_request.c | 58 ++++++++---------------
> drivers/gpu/drm/i915/i915_trace.h | 13 +++---
> drivers/gpu/drm/i915/intel_display.c | 36 ++++++--------
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_overlay.c | 20 ++++----
> 8 files changed, 79 insertions(+), 140 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b7e298b4253e..2259983d2ec6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3171,8 +3171,7 @@ static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
>
> int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
> int i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct intel_engine_cs *to,
> - struct drm_i915_gem_request **to_req);
> + struct drm_i915_gem_request *to);
> void i915_vma_move_to_active(struct i915_vma *vma,
> struct drm_i915_gem_request *req);
> int i915_gem_dumb_create(struct drm_file *file_priv,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 59890f523c5f..b6c4ff63725f 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2845,51 +2845,35 @@ out:
>
> static int
> __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct intel_engine_cs *to,
> - struct drm_i915_gem_request *from_req,
> - struct drm_i915_gem_request **to_req)
> + struct drm_i915_gem_request *to,
> + struct drm_i915_gem_request *from)
> {
> - struct intel_engine_cs *from;
> int ret;
>
> - from = i915_gem_request_get_engine(from_req);
> - if (to == from)
> + if (to->engine == from->engine)
> return 0;
>
> - if (i915_gem_request_completed(from_req))
> + if (i915_gem_request_completed(from))
> return 0;
>
> if (!i915.semaphores) {
> - struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - ret = __i915_wait_request(from_req,
> - i915->mm.interruptible,
> + ret = __i915_wait_request(from,
> + from->i915->mm.interruptible,
> NULL,
> NO_WAITBOOST);
> if (ret)
> return ret;
>
> - i915_gem_object_retire_request(obj, from_req);
> + i915_gem_object_retire_request(obj, from);
> } else {
> - int idx = intel_engine_sync_index(from, to);
> - u32 seqno = i915_gem_request_get_seqno(from_req);
> + int idx = intel_engine_sync_index(from->engine, to->engine);
> + u32 seqno = i915_gem_request_get_seqno(from);
>
> - WARN_ON(!to_req);
> -
> - if (seqno <= from->semaphore.sync_seqno[idx])
> + if (seqno <= from->engine->semaphore.sync_seqno[idx])
> return 0;
>
> - if (*to_req == NULL) {
> - struct drm_i915_gem_request *req;
> -
> - req = i915_gem_request_alloc(to, NULL);
> - if (IS_ERR(req))
> - return PTR_ERR(req);
> -
> - *to_req = req;
> - }
> -
> - trace_i915_gem_ring_sync_to(*to_req, from, from_req);
> - ret = to->semaphore.sync_to(*to_req, from, seqno);
> + trace_i915_gem_ring_sync_to(to, from);
> + ret = to->engine->semaphore.sync_to(to, from->engine, seqno);
> if (ret)
> return ret;
>
> @@ -2897,8 +2881,8 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> * might have just caused seqno wrap under
> * the radar.
> */
> - from->semaphore.sync_seqno[idx] =
> - i915_gem_request_get_seqno(obj->last_read_req[from->id]);
> + from->engine->semaphore.sync_seqno[idx] =
> + i915_gem_request_get_seqno(obj->last_read_req[from->engine->id]);
> }
>
> return 0;
> @@ -2908,17 +2892,12 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> * i915_gem_object_sync - sync an object to a ring.
> *
> * @obj: object which may be in use on another ring.
> - * @to: ring we wish to use the object on. May be NULL.
> - * @to_req: request we wish to use the object for. See below.
> - * This will be allocated and returned if a request is
> - * required but not passed in.
> + * @to: request we are wishing to use
> *
> * This code is meant to abstract object synchronization with the GPU.
> - * Calling with NULL implies synchronizing the object with the CPU
> - * rather than a particular GPU ring. Conceptually we serialise writes
> - * between engines inside the GPU. We only allow one engine to write
> - * into a buffer at any time, but multiple readers. To ensure each has
> - * a coherent view of memory, we must:
> + * Conceptually we serialise writes between engines inside the GPU.
> + * We only allow one engine to write into a buffer at any time, but
> + * multiple readers. To ensure each has a coherent view of memory, we must:
> *
> * - If there is an outstanding write request to the object, the new
> * request must wait for it to complete (either CPU or in hw, requests
> @@ -2927,22 +2906,11 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> * - If we are a write request (pending_write_domain is set), the new
> * request must wait for outstanding read requests to complete.
> *
> - * For CPU synchronisation (NULL to) no request is required. For syncing with
> - * rings to_req must be non-NULL. However, a request does not have to be
> - * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
> - * request will be allocated automatically and returned through *to_req. Note
> - * that it is not guaranteed that commands will be emitted (because the system
> - * might already be idle). Hence there is no need to create a request that
> - * might never have any work submitted. Note further that if a request is
> - * returned in *to_req, it is the responsibility of the caller to submit
> - * that request (after potentially adding more work to it).
> - *
> * Returns 0 if successful, else propagates up the lower layer error.
> */
> int
> i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct intel_engine_cs *to,
> - struct drm_i915_gem_request **to_req)
> + struct drm_i915_gem_request *to)
> {
> const bool readonly = obj->base.pending_write_domain == 0;
> struct drm_i915_gem_request *req[I915_NUM_ENGINES];
> @@ -2951,9 +2919,6 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
> if (!obj->active)
> return 0;
>
> - if (to == NULL)
> - return i915_gem_object_wait_rendering(obj, readonly);
> -
> n = 0;
> if (readonly) {
> if (obj->last_write_req)
> @@ -2964,7 +2929,7 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
> req[n++] = obj->last_read_req[i];
> }
> for (i = 0; i < n; i++) {
> - ret = __i915_gem_object_sync(obj, to, req[i], to_req);
> + ret = __i915_gem_object_sync(obj, to, req[i]);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 35c4c595e5ba..eacd78fc93c4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -981,7 +981,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
> struct drm_i915_gem_object *obj = vma->obj;
>
> if (obj->active & other_rings) {
> - ret = i915_gem_object_sync(obj, req->engine, &req);
> + ret = i915_gem_object_sync(obj, req);
> if (ret)
> return ret;
> }
> @@ -1427,7 +1427,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct i915_ggtt *ggtt = &dev_priv->ggtt;
> - struct drm_i915_gem_request *req = NULL;
> struct eb_vmas *eb;
> struct drm_i915_gem_object *batch_obj;
> struct drm_i915_gem_exec_object2 shadow_exec_entry;
> @@ -1615,13 +1614,13 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
>
> /* Allocate a request for this batch buffer nice and early. */
> - req = i915_gem_request_alloc(engine, ctx);
> - if (IS_ERR(req)) {
> - ret = PTR_ERR(req);
> + params->request = i915_gem_request_alloc(engine, ctx);
> + if (IS_ERR(params->request)) {
> + ret = PTR_ERR(params->request);
> goto err_batch_unpin;
> }
>
> - ret = i915_gem_request_add_to_client(req, file);
> + ret = i915_gem_request_add_to_client(params->request, file);
> if (ret)
> goto err_request;
>
> @@ -1637,7 +1636,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> params->dispatch_flags = dispatch_flags;
> params->batch_obj = batch_obj;
> params->ctx = ctx;
> - params->request = req;
>
> ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
> err_request:
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 7e3206051ced..47e46c9da4e7 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -292,10 +292,21 @@ static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
> return 0;
> }
>
> -static inline int
> -__i915_gem_request_alloc(struct intel_engine_cs *engine,
> - struct i915_gem_context *ctx,
> - struct drm_i915_gem_request **req_out)
> +/**
> + * i915_gem_request_alloc - allocate a request structure
> + *
> + * @engine: engine that we wish to issue the request on.
> + * @ctx: context that the request will be associated with.
> + * This can be NULL if the request is not directly related to
> + * any specific user context, in which case this function will
> + * choose an appropriate context to use.
> + *
> + * Returns a pointer to the allocated request if successful,
> + * or an error code if not.
> + */
> +struct drm_i915_gem_request *
> +i915_gem_request_alloc(struct intel_engine_cs *engine,
> + struct i915_gem_context *ctx)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> unsigned int reset_counter = i915_reset_counter(&dev_priv->gpu_error);
> @@ -303,18 +314,13 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
> u32 seqno;
> int ret;
>
> - if (!req_out)
> - return -EINVAL;
> -
> - *req_out = NULL;
> -
> /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
> * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
> * and restart.
> */
> ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
> if (ret)
> - return ret;
> + return ERR_PTR(ret);
>
> /* Move the oldest request to the slab-cache (if not in use!) */
> req = list_first_entry_or_null(&engine->request_list,
> @@ -324,7 +330,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
>
> req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
> if (!req)
> - return -ENOMEM;
> + return ERR_PTR(-ENOMEM);
>
> ret = i915_gem_get_seqno(dev_priv, &seqno);
> if (ret)
> @@ -357,39 +363,13 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
> if (ret)
> goto err_ctx;
>
> - *req_out = req;
> - return 0;
> + return req;
>
> err_ctx:
> i915_gem_context_put(ctx);
> err:
> kmem_cache_free(dev_priv->requests, req);
> - return ret;
> -}
> -
> -/**
> - * i915_gem_request_alloc - allocate a request structure
> - *
> - * @engine: engine that we wish to issue the request on.
> - * @ctx: context that the request will be associated with.
> - * This can be NULL if the request is not directly related to
> - * any specific user context, in which case this function will
> - * choose an appropriate context to use.
> - *
> - * Returns a pointer to the allocated request if successful,
> - * or an error code if not.
> - */
> -struct drm_i915_gem_request *
> -i915_gem_request_alloc(struct intel_engine_cs *engine,
> - struct i915_gem_context *ctx)
> -{
> - struct drm_i915_gem_request *req;
> - int err;
> -
> - if (!ctx)
> - ctx = engine->i915->kernel_context;
> - err = __i915_gem_request_alloc(engine, ctx, &req);
> - return err ? ERR_PTR(err) : req;
> + return ERR_PTR(ret);
> }
>
> static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index 007112d1e049..9e43c0aa6e3b 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -449,10 +449,9 @@ TRACE_EVENT(i915_gem_evict_vm,
> );
>
> TRACE_EVENT(i915_gem_ring_sync_to,
> - TP_PROTO(struct drm_i915_gem_request *to_req,
> - struct intel_engine_cs *from,
> - struct drm_i915_gem_request *req),
> - TP_ARGS(to_req, from, req),
> + TP_PROTO(struct drm_i915_gem_request *to,
> + struct drm_i915_gem_request *from),
> + TP_ARGS(to, from),
>
> TP_STRUCT__entry(
> __field(u32, dev)
> @@ -463,9 +462,9 @@ TRACE_EVENT(i915_gem_ring_sync_to,
>
> TP_fast_assign(
> __entry->dev = from->i915->drm.primary->index;
> - __entry->sync_from = from->id;
> - __entry->sync_to = to_req->engine->id;
> - __entry->seqno = req->fence.seqno;
> + __entry->sync_from = from->engine->id;
> + __entry->sync_to = to->engine->id;
> + __entry->seqno = from->fence.seqno;
> ),
>
> TP_printk("dev=%u, sync-from=%u, sync-to=%u, seqno=%u",
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bff172c45ff7..5d4420b67642 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11583,7 +11583,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> struct intel_flip_work *work;
> struct intel_engine_cs *engine;
> bool mmio_flip;
> - struct drm_i915_gem_request *request = NULL;
> + struct drm_i915_gem_request *request;
> int ret;
>
> /*
> @@ -11690,22 +11690,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>
> mmio_flip = use_mmio_flip(engine, obj);
>
> - /* When using CS flips, we want to emit semaphores between rings.
> - * However, when using mmio flips we will create a task to do the
> - * synchronisation, so all we want here is to pin the framebuffer
> - * into the display plane and skip any waits.
> - */
> - if (!mmio_flip) {
> - ret = i915_gem_object_sync(obj, engine, &request);
> - if (!ret && !request) {
> - request = i915_gem_request_alloc(engine, NULL);
> - ret = PTR_ERR_OR_ZERO(request);
> - }
> -
> - if (ret)
> - goto cleanup_pending;
> - }
> -
> ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
> if (ret)
> goto cleanup_pending;
> @@ -11723,14 +11707,24 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>
> schedule_work(&work->mmio_work);
> } else {
> - i915_gem_request_assign(&work->flip_queued_req, request);
> + request = i915_gem_request_alloc(engine, engine->last_context);
> + if (IS_ERR(request)) {
> + ret = PTR_ERR(request);
> + goto cleanup_unpin;
> + }
> +
> + ret = i915_gem_object_sync(obj, request);
> + if (ret)
> + goto cleanup_request;
> +
> ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
> page_flip_flags);
> if (ret)
> - goto cleanup_unpin;
> + goto cleanup_request;
>
> intel_mark_page_flip_active(intel_crtc, work);
>
> + work->flip_queued_req = i915_gem_request_get(request);
> i915_add_request_no_flush(request);
> }
>
> @@ -11745,11 +11739,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>
> return 0;
>
> +cleanup_request:
> + i915_add_request_no_flush(request);
> cleanup_unpin:
> intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
> cleanup_pending:
> - if (!IS_ERR_OR_NULL(request))
> - i915_add_request_no_flush(request);
> atomic_dec(&intel_crtc->unpin_work_count);
> mutex_unlock(&dev->struct_mutex);
> cleanup:
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index e8d971e81491..1e57f48250ce 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -655,7 +655,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
> struct drm_i915_gem_object *obj = vma->obj;
>
> if (obj->active & other_rings) {
> - ret = i915_gem_object_sync(obj, req->engine, &req);
> + ret = i915_gem_object_sync(obj, req);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 8f1d4d9ef345..651efe4e468e 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -229,11 +229,18 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
> return 0;
> }
>
> +static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
> +{
> + struct drm_i915_private *dev_priv = overlay->i915;
> + struct intel_engine_cs *engine = &dev_priv->engine[RCS];
> +
> + return i915_gem_request_alloc(engine, dev_priv->kernel_context);
> +}
> +
> /* overlay needs to be disable in OCMD reg */
> static int intel_overlay_on(struct intel_overlay *overlay)
> {
> struct drm_i915_private *dev_priv = overlay->i915;
> - struct intel_engine_cs *engine = &dev_priv->engine[RCS];
> struct drm_i915_gem_request *req;
> struct intel_ring *ring;
> int ret;
> @@ -241,7 +248,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
> WARN_ON(overlay->active);
> WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
>
> - req = i915_gem_request_alloc(engine, NULL);
> + req = alloc_request(overlay);
> if (IS_ERR(req))
> return PTR_ERR(req);
>
> @@ -268,7 +275,6 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
> bool load_polyphase_filter)
> {
> struct drm_i915_private *dev_priv = overlay->i915;
> - struct intel_engine_cs *engine = &dev_priv->engine[RCS];
> struct drm_i915_gem_request *req;
> struct intel_ring *ring;
> u32 flip_addr = overlay->flip_addr;
> @@ -285,7 +291,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
> if (tmp & (1 << 17))
> DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
>
> - req = i915_gem_request_alloc(engine, NULL);
> + req = alloc_request(overlay);
> if (IS_ERR(req))
> return PTR_ERR(req);
>
> @@ -338,7 +344,6 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay)
> static int intel_overlay_off(struct intel_overlay *overlay)
> {
> struct drm_i915_private *dev_priv = overlay->i915;
> - struct intel_engine_cs *engine = &dev_priv->engine[RCS];
> struct drm_i915_gem_request *req;
> struct intel_ring *ring;
> u32 flip_addr = overlay->flip_addr;
> @@ -352,7 +357,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
> * of the hw. Do it in both cases */
> flip_addr |= OFC_UPDATE;
>
> - req = i915_gem_request_alloc(engine, NULL);
> + req = alloc_request(overlay);
> if (IS_ERR(req))
> return PTR_ERR(req);
>
> @@ -412,7 +417,6 @@ static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
> static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> {
> struct drm_i915_private *dev_priv = overlay->i915;
> - struct intel_engine_cs *engine = &dev_priv->engine[RCS];
> int ret;
>
> lockdep_assert_held(&dev_priv->drm.struct_mutex);
> @@ -428,7 +432,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> struct drm_i915_gem_request *req;
> struct intel_ring *ring;
>
> - req = i915_gem_request_alloc(engine, NULL);
> + req = alloc_request(overlay);
> if (IS_ERR(req))
> return PTR_ERR(req);
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers
2016-07-25 17:32 ` [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers Chris Wilson
@ 2016-07-26 5:15 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 5:15 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> As we can now have multiple VMA inside the global GTT (with partial
> mappings, rotations, etc), it is no longer true that there may just be a
> single GGTT entry and so we should walk the full vma_list to count up
> the actual usage. In addition to unifying the two walkers, switch from
> multiplying the object size for each vma to summing the bound vma sizes.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 46 +++++++++++++++----------------------
> 1 file changed, 18 insertions(+), 28 deletions(-)
>
<SNIP>
>
> @@ -342,41 +343,30 @@ static int per_file_stats(int id, void *ptr, void *data)
> if (obj->base.name || obj->base.dma_buf)
> stats->shared += obj->base.size;
>
> - if (USES_FULL_PPGTT(obj->base.dev)) {
> - list_for_each_entry(vma, &obj->vma_list, obj_link) {
> - struct i915_hw_ppgtt *ppgtt;
> + list_for_each_entry(vma, &obj->vma_list, obj_link) {
> + if (!drm_mm_node_allocated(&vma->node))
> + continue;
>
> - if (!drm_mm_node_allocated(&vma->node))
> - continue;
> + bound++;
>
> - if (vma->is_ggtt) {
> - stats->global += obj->base.size;
> - continue;
> - }
> -
> - ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
> + if (vma->is_ggtt) {
> + stats->global += vma->node.size;
> + } else {
> + struct i915_hw_ppgtt *ppgtt
> + = container_of(vma->vm,
> + struct i915_hw_ppgtt,
> + base);
Use i915_vm_to_ppgtt(vma->vm). With that,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* ✗ Ro.CI.BAT: warning for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (54 preceding siblings ...)
2016-07-25 17:32 ` [PATCH 55/55] Revert "drm/i915: Clean up associated VMAs on context destruction" Chris Wilson
@ 2016-07-26 5:18 ` Patchwork
2016-07-26 10:48 ` ✗ Ro.CI.BAT: failure for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() (rev2) Patchwork
56 siblings, 0 replies; 124+ messages in thread
From: Patchwork @ 2016-07-26 5:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
URL : https://patchwork.freedesktop.org/series/10246/
State : warning
== Summary ==
Series 10246v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/10246/revisions/1/mbox
Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-warn -> PASS (fi-skl-i5-6260u)
Test gem_sync:
Subgroup basic-store-each:
pass -> SKIP (ro-bdw-i7-5600u)
pass -> SKIP (ro-bdw-i5-5250u)
fi-skl-i5-6260u total:235 pass:223 dwarn:0 dfail:0 fail:0 skip:12
fi-skl-i7-6700k total:235 pass:209 dwarn:0 dfail:0 fail:0 skip:26
fi-snb-i7-2600 total:235 pass:195 dwarn:0 dfail:0 fail:0 skip:40
ro-bdw-i5-5250u total:235 pass:217 dwarn:4 dfail:0 fail:0 skip:14
ro-bdw-i7-5557U total:235 pass:218 dwarn:3 dfail:0 fail:0 skip:14
ro-bdw-i7-5600u total:235 pass:203 dwarn:0 dfail:0 fail:0 skip:32
ro-bsw-n3050 total:235 pass:191 dwarn:0 dfail:0 fail:1 skip:43
ro-byt-n2820 total:235 pass:196 dwarn:0 dfail:0 fail:1 skip:38
ro-hsw-i3-4010u total:235 pass:211 dwarn:0 dfail:0 fail:0 skip:24
ro-hsw-i7-4770r total:235 pass:211 dwarn:0 dfail:0 fail:0 skip:24
ro-ilk-i7-620lm total:235 pass:171 dwarn:0 dfail:0 fail:1 skip:63
ro-ilk1-i5-650 total:230 pass:171 dwarn:0 dfail:0 fail:1 skip:58
ro-ivb-i7-3770 total:235 pass:202 dwarn:0 dfail:0 fail:0 skip:33
ro-skl3-i5-6260u total:235 pass:223 dwarn:0 dfail:0 fail:0 skip:12
ro-snb-i7-2620M total:235 pass:193 dwarn:0 dfail:0 fail:1 skip:41
fi-hsw-i7-4770k failed to connect after reboot
fi-kbl-qkkr failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1600/
5c9e3d9 drm-intel-nightly: 2016y-07m-25d-06h-32m-37s UTC integration manifest
3a6c9ea Revert "drm/i915: Clean up associated VMAs on context destruction"
104e392 drm/i915: Mark the context and address space as closed
ab44ea4 drm/i915: Release vma when the handle is closed
036a52b drm/i915: Track active vma requests
2228d78 drm/i915: i915_vma_move_to_active prep patch
ed8d84b drm/i915: Move request list retirement to i915_gem_request.c
859cf08 drm/i915: Double check activity before relocations
6b6e54a drm/i915: s/__i915_wait_request/i915_wait_request/
a982b45 drm/i915: Disable waitboosting for a saturated engine
82ae751 drm/i915: Move the special case wait-request handling to its one caller
c3068e1 drm/i915: Convert intel_overlay to request tracking
c8e87f4 drm/i915: Track requests inside each intel_ring
16410e2 drm/i915: Refactor activity tracking for requests
dc9a175 drm/i915: Remove obsolete i915_gem_object_flush_active()
344267b drm/i915: Rename request->list to link for consistency
847bf87 drm/i915: Refactor blocking waits
129d043 drm/i915: Mark up i915_gem_active for locking annotation
35ae483 drm/i915: Prepare i915_gem_active for annotations
e3d1035 drm/i915: Introduce i915_gem_active for request tracking
d30434e drm/i915: Kill drop_pages()
9dea465 drm/i915: Be more careful when unbinding vma
6a05061 drm/i915: Count how many VMA are bound for an object
bfaea2a drm/i915: Store owning file on the i915_address_space
efc808f drm/i915: Split early global GTT initialisation
c880e6e drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers
67995be drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals
59f8fce drm/i915: Simplify calling engine->sync_to
18b15e1 drm/i915: Unify legacy/execlists submit_execbuf callbacks
e08e8c3 drm/i915: Refactor golden render state emission to unconfuse gcc
dfe4e0f drm/i915: Remove duplicate golden render state init from execlists
d129ca2 drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores
d75b5e2 drm/i915: Reuse legacy breadcrumbs + tail emission
c8ef3d6 drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal()
651c830 drm/i915/lrc: Update function names to match request flow
ab762f1 drm/i915: Unify request submission
9538f16 drm/i915: Convert engine->write_tail to operate on a request
021c340 drm/i915: Remove intel_ring_get_tail()
991637b drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START
a8a086d drm/i915: Simplify request_alloc by returning the allocated request
10bda31 drm/i915: Remove obsolete engine->gpu_caches_dirty
b66909e drm/i915: Rename intel_pin_and_map_ring()
d1c2132 drm/i915: Rename residual ringbuf parameters
db81db7 drm/i915: Rename struct intel_ringbuffer to struct intel_ring
edf9a57 drm/i915: Rename intel_context[engine].ringbuf
3bb63b1 drm/i915: Rename request->ringbuf to request->ring
c085269 drm/i915: Unify intel_logical_ring_emit and intel_ring_emit
5806a2f drm/i915: Update a couple of hangcheck comments to talk about engines
64de0a6 drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
c3ebb54 drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
a9842a7 drm/i915: Use engine to refer to the user's BSD intel_engine_cs
2627bb7 drm/i915/cmdparser: Remove stray intel_engine_cs *ring
944c9a0 drm/i915: Only drop the batch-pool's object reference
70eb608 drm/i915: Only clear the client pointer when tearing down the file
4426131 drm/i915: Prefer list_first_entry_or_null
db60209 drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 32/55] drm/i915: Split early global GTT initialisation
2016-07-25 17:32 ` [PATCH 32/55] drm/i915: Split early global GTT initialisation Chris Wilson
@ 2016-07-26 7:08 ` Joonas Lahtinen
2016-07-26 7:42 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 7:08 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> -/**
> - * i915_gem_init_ggtt - Initialize GEM for Global GTT
> - * @dev: DRM device
> - */
> -void i915_gem_init_ggtt(struct drm_device *dev)
>
> +static void init_global_gtt(struct drm_i915_private *dev_priv)
Why not s/global_gtt/ggtt/ for easier grepping.
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct i915_ggtt *ggtt = &dev_priv->ggtt;
> + struct i915_address_space *ggtt = &dev_priv->ggtt.base;
Nope, I did quite a job making sure every ggtt variable is of
i915_ggtt. And we agreed (a compromise :P) on ggtt->base for the
address space
> +
> + INIT_LIST_HEAD(&dev_priv->vm_list);
>
> - i915_gem_setup_global_gtt(dev, 0, ggtt->mappable_end, ggtt->base.total);
> + /* Subtract the guard page before address space initialization to
> + * shrink the range used by drm_mm.
> + */
> + ggtt->total -= PAGE_SIZE;
> + i915_address_space_init(ggtt, dev_priv);
> + ggtt->total += PAGE_SIZE;
> +
> + if (!HAS_LLC(dev_priv))
> + ggtt->mm.color_adjust = i915_gtt_color_adjust;
> }
>
> /**
> @@ -2890,6 +2862,9 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
> }
>
> ggtt->base.cleanup(&ggtt->base);
> +
> + arch_phys_wc_del(ggtt->mtrr);
> + io_mapping_free(ggtt->mappable);
> }
>
> static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
> @@ -3250,21 +3225,14 @@ int i915_ggtt_init_hw(struct drm_device *dev)
> if (ret)
> return ret;
>
> - if ((ggtt->base.total - 1) >> 32) {
> - DRM_ERROR("We never expected a Global GTT with more than 32bits"
> - "of address space! Found %lldM!\n",
> - ggtt->base.total >> 20);
> - ggtt->base.total = 1ULL << 32;
> - ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
> - }
> + init_global_gtt(dev_priv);
>
> - /*
> - * Initialise stolen early so that we may reserve preallocated
> - * objects for the BIOS to KMS transition.
> - */
> - ret = i915_gem_init_stolen(dev);
> - if (ret)
> - goto out_gtt_cleanup;
> + ggtt->mappable =
> + io_mapping_create_wc(ggtt->mappable_base, ggtt->mappable_end);
Splitting between arguments might look leaner.
Otherwise looks OK, plenty of code motion so not super easy to track.
With above addressed;
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 33/55] drm/i915: Store owning file on the i915_address_space
2016-07-25 17:32 ` [PATCH 33/55] drm/i915: Store owning file on the i915_address_space Chris Wilson
@ 2016-07-26 7:15 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 7:15 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> -static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
> +static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
> + struct drm_i915_private *dev_priv)
> {
> - ppgtt->base.dev = dev;
> + ppgtt->base.dev = &dev_priv->drm;
>
> - if (INTEL_INFO(dev)->gen < 8)
> + if (INTEL_INFO(dev_priv)->gen < 8)
INTEL_GEN()
> return gen6_ppgtt_init(ppgtt);
> else
> return gen8_ppgtt_init(ppgtt);
>
> struct i915_hw_ppgtt *
> -i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
> +i915_ppgtt_create(struct drm_i915_private *dev_priv,
> + struct drm_i915_file_private *fpriv)
While touching, fix the name to file_priv.
> int i915_ppgtt_init_hw(struct drm_device *dev);
> void i915_ppgtt_release(struct kref *kref);
> -struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
> +struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
> struct drm_i915_file_private *fpriv);
I'd change file_priv again when touching.
> static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
> {
Otherwise, looks good.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 32/55] drm/i915: Split early global GTT initialisation
2016-07-26 7:08 ` Joonas Lahtinen
@ 2016-07-26 7:42 ` Chris Wilson
2016-07-27 10:20 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 7:42 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 10:08:32AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > -/**
> > - * i915_gem_init_ggtt - Initialize GEM for Global GTT
> > - * @dev: DRM device
> > - */
> > -void i915_gem_init_ggtt(struct drm_device *dev)
> >
> > +static void init_global_gtt(struct drm_i915_private *dev_priv)
>
> Why not s/global_gtt/ggtt/ for easier grepping.
init_global_vm() so that you don't think it is just about the ggtt.
> > - /*
> > - * Initialise stolen early so that we may reserve preallocated
> > - * objects for the BIOS to KMS transition.
> > - */
> > - ret = i915_gem_init_stolen(dev);
> > - if (ret)
> > - goto out_gtt_cleanup;
> > + ggtt->mappable =
> > + io_mapping_create_wc(ggtt->mappable_base, ggtt->mappable_end);
>
> Splitting between arguments might look leaner.
I much prefer splitting like above.
> Otherwise looks OK, plenty of code motion so not super easy to track.
Looks like it has been a rebase victim.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 34/55] drm/i915: Count how many VMA are bound for an object
2016-07-25 17:32 ` [PATCH 34/55] drm/i915: Count how many VMA are bound for an object Chris Wilson
@ 2016-07-26 7:44 ` Joonas Lahtinen
2016-07-26 8:02 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 7:44 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> @@ -3692,6 +3692,9 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> old_read_domains,
> old_write_domain);
>
> + /* Increment the pages_pin_count to guard against the shrinker */
> + obj->pages_pin_count++;
> +
This is new unrelated code/fix?
> return 0;
>
> err_unpin_display:
> @@ -3708,6 +3711,7 @@ i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
>
> i915_gem_object_ggtt_unpin_view(obj, view);
>
> + obj->pages_pin_count--;
Ditto.
Above code two changes explained or moved to separate patch, then;
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
> obj->pin_display--;
> }
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 35/55] drm/i915: Be more careful when unbinding vma
2016-07-25 17:32 ` [PATCH 35/55] drm/i915: Be more careful when unbinding vma Chris Wilson
@ 2016-07-26 7:59 ` Joonas Lahtinen
2016-07-26 8:08 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 7:59 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> When we call i915_vma_unbind(), we will wait upon outstanding rendering.
> This will also trigger a retirement phase, which may update the object
> lists. If, we extend request tracking to the VMA itself (rather than
> keep it at the encompassing object), then there is a potential that the
> obj->vma_list be modified for other elements upon i915_vma_unbind(). As
> a result, if we walk over the object list and call i915_vma_unbind(), we
> need to be prepared for that list to change.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_gem.c | 57 +++++++++++++++++++++++---------
> drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 +----
> drivers/gpu/drm/i915/i915_gem_userptr.c | 4 +--
> 4 files changed, 46 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e28228c6f383..2abae63258a3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3052,6 +3052,8 @@ int __must_check i915_vma_unbind(struct i915_vma *vma);
> * _guarantee_ VMA in question is _not in use_ anywhere.
> */
> int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
> +
> +int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
> int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
> void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
> void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a3defd7b4046..9169f5f3d20c 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -283,18 +283,38 @@ static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
> .release = i915_gem_object_release_phys,
> };
>
> +int
> +i915_gem_object_unbind(struct drm_i915_gem_object *obj)
> +{
> + struct i915_vma *vma;
> + LIST_HEAD(still_in_list);
> + int ret;
> +
> + /* The vma will only be freed if it is marked as closed, and if we wait
> + * upon rendering to the vma, we may unbind anything in the list.
> + */
> + while ((vma = list_first_entry_or_null(&obj->vma_list,
> + struct i915_vma,
> + obj_link))) {
> + list_move_tail(&vma->obj_link, &still_in_list);
> + ret = i915_vma_unbind(vma);
> + if (ret)
> + break;
> + }
> + list_splice(&still_in_list, &obj->vma_list);
> +
> + return ret;
> +}
> +
> static int
> drop_pages(struct drm_i915_gem_object *obj)
> {
> - struct i915_vma *vma, *next;
> int ret;
>
> i915_gem_object_get(obj);
> - list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
> - if (i915_vma_unbind(vma))
> - break;
> -
> - ret = i915_gem_object_put_pages(obj);
> + ret = i915_gem_object_unbind(obj);
> + if (ret == 0)
(!ret)
Other than that, looks good.
The list_for_each loops are fancy to review because we have so many
levels of functions and you never know where the corresponding list_add
or list_del is, in this case two different files O_o
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Now I notice Tvrtko already reviewed this, well.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 34/55] drm/i915: Count how many VMA are bound for an object
2016-07-26 7:44 ` Joonas Lahtinen
@ 2016-07-26 8:02 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 8:02 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 10:44:00AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > @@ -3692,6 +3692,9 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> > old_read_domains,
> > old_write_domain);
> >
> > + /* Increment the pages_pin_count to guard against the shrinker */
> > + obj->pages_pin_count++;
> > +
>
> This is new unrelated code/fix?
No. It is a change in accounting due to this patch.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 35/55] drm/i915: Be more careful when unbinding vma
2016-07-26 7:59 ` Joonas Lahtinen
@ 2016-07-26 8:08 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 8:08 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 10:59:35AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > - ret = i915_gem_object_put_pages(obj);
> > + ret = i915_gem_object_unbind(obj);
> > + if (ret == 0)
>
> (!ret)
>
> Other than that, looks good.
I still think ret == 0 expresses the intent of checking for success much
more clearly than !ret.
I suppose if we used err rather than ret, if (!err) works better.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
2016-07-26 5:02 ` Joonas Lahtinen
@ 2016-07-26 8:12 ` Chris Wilson
2016-07-27 6:12 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 8:12 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 08:02:25AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> > A few places we use ring when referring to the struct intel_engine_cs. An
> > anachronism we are pruning out.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-9-git-send-email-chris@chris-wilson.co.uk
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 24 ++++++++++++------------
> > 1 file changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index e155e8dd28ed..7bfce1d5c61b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -46,7 +46,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
> > static void
> > i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
> > static void
> > -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
> > +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
>
> I vote for engine_idx variable name, that much I dislike differing
> naming in signature and implementation.
I think engine_idx is pretty repugnant. I'll wait until you get to
"Refactor activity tracking for requests" so you see how this function
looks closer to its final form (in this series at least).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
2016-07-26 4:59 ` Joonas Lahtinen
@ 2016-07-26 8:19 ` Chris Wilson
2016-07-27 11:08 ` Joonas Lahtinen
2016-07-26 10:21 ` [PATCH v2] " Chris Wilson
1 sibling, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 8:19 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 07:59:29AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
>
> > Inside the error capture itself, we refer to not only the hardware
> > engine, its ringbuffer but also the capture state. Finding clear names
> > for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
> > compromise we keep using ering for the error capture.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-chris@chris-wilson.co.uk
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 6 +-
> > drivers/gpu/drm/i915/i915_gpu_error.c | 255 +++++++++++++++++-----------------
> > 2 files changed, 134 insertions(+), 127 deletions(-)
> >
>
> <SNIP>
>
> > @@ -240,69 +240,71 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
> > }
> >
> > static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
> > - struct drm_device *dev,
> > - struct drm_i915_error_state *error,
> > - int ring_idx)
> > + struct drm_device *dev,
> > + struct drm_i915_error_state *error,
> > + int engine_idx)
> > {
> > - struct drm_i915_error_ring *ring = &error->ring[ring_idx];
> > + struct drm_i915_error_engine *ering = &error->engine[engine_idx];
> >
>
> I'd be inclined keeping the struct and variable names close, so rather
> eengine. Even though the error state is a mashup. We fill the ring
> state to the engine error state. Function could be
> i915_engine_error_ring_state() or so, to "reduce" confusion?
i915_error_print_engine()
(We may eventually get to the point where the capture/error functions
are clearly and distinctly labelled!)
>
> > @@ -414,7 +416,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> > if (IS_GEN7(dev))
> > err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
> >
> > - for (i = 0; i < ARRAY_SIZE(error->ring); i++)
> > + for (i = 0; i < ARRAY_SIZE(error->engine); i++)
> > i915_ring_error_state(m, dev, error, i);
> >
>
> This captures the engine related ring state, I think it's even worth a
> comment when there is engine vs. error disparity.
This becomes
for (i = 0; i < ARRAY_SIZE(error->engine); i++)
i915_error_print_engine(m, &error->engine[i]);
> And how about the messages? Should we update them more agressively
> where necessary.
Ignoring the tautology in engine->name, in the actual error print the
only times we explicitly refer to ring we do mean the ring.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking
2016-07-25 17:32 ` [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking Chris Wilson
@ 2016-07-26 8:23 ` Joonas Lahtinen
2016-07-26 8:28 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 8:23 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -155,10 +155,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> obj->base.write_domain);
> for_each_engine_id(engine, dev_priv, id)
> seq_printf(m, "%x ",
> - i915_gem_request_get_seqno(obj->last_read_req[id]));
> + i915_gem_request_get_seqno(obj->last_read[id].request));
I hate i915_gem_request_get_seqno already, it's just NULL protection,
but subject to different patch. Although, I see you got rid
of i915_gem_request_get_engine already.
> @@ -2383,10 +2383,10 @@ void i915_vma_move_to_active(struct i915_vma *vma,
> static void
> i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> {
> - GEM_BUG_ON(obj->last_write_req == NULL);
> - GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
> + GEM_BUG_ON(!obj->last_write.request);
> + GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write.request->engine)));
Over 80 ch line.
intel_engine_flag seems rather dull, there's also this thing called
BIT(), but again subject to another series.
> @@ -2395,13 +2395,13 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> {
> struct i915_vma *vma;
>
> - GEM_BUG_ON(obj->last_read_req[idx] == NULL);
> + GEM_BUG_ON(!obj->last_read[idx].request);
> GEM_BUG_ON(!(obj->active & (1 << idx)));
BIT(idx)?
> +/* We treat requests as fences. This is not be to confused with our
> + * "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
> + * We use the fences to synchronize access from the CPU with activity on the
> + * GPU, for example, we should not rewrite an object's PTE whilst the GPU
> + * is reading them. We also track fences at a higher level to provide
> + * implicit synchronisation around GEM objects, e.g. set-domain will wait
> + * for outstanding GPU rendering before marking the object ready for CPU
> + * access, or a pageflip will wait until the GPU is complete before showing
> + * the frame on the scanout.
> + *
> + * In order to use a fence, the object must track the fence it needs to
> + * serialise with. For example, GEM objects want to track both read and
> + * write access so that we can perform concurrent read operations between
> + * the CPU and GPU engines, as well as waiting for all rendering to
> + * complete, or waiting for the last GPU user of a "fence register". The
> + * object then embeds a @i915_gem_active to track the most recent (in
> + * retirment order) request relevant for the desired mode of access.
> + * The @i915_gem_active is updated with i915_gem_request_mark_active() to
> + * track the most recent fence request, typically this is done as part of
> + * i915_vma_move_to_active().
> + *
> + * When the @i915_gem_active completes (is retired), it will
> + * signal its completion to the owner through a callback as well as mark
> + * itself as idle (i915_gem_active.request == NULL). The owner
> + * can then perform any action, such as delayed freeing of an active
> + * resource including itself.
> + */
> +struct i915_gem_active {
Not sure if this is a good descriptive struct name. Would not this be
in the sync terminology a fence? active.request reads nicely though.
> + struct drm_i915_gem_request *request;
> +};
> +
> +static inline void
> +i915_gem_active_set(struct i915_gem_active *active,
> + struct drm_i915_gem_request *request)
> +{
> + i915_gem_request_assign(&active->request, request);
> +}
> +
> +#define for_each_active(mask, idx) \
> + for (; mask ? idx = ffs(mask) - 1, 1 : 0; mask &= ~(1 << idx))
BIT()
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11378,7 +11378,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
> if (resv && !reservation_object_test_signaled_rcu(resv, false))
> return true;
>
> - return engine != i915_gem_request_get_engine(obj->last_write_req);
> + return engine != i915_gem_request_get_engine(obj->last_write.request);
What's been the obsession with NULL protecting simple accessor
functions? Makes the code look overly complicated. One more function to
nuke.
The changes itself make sense, with above tweaks;
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking
2016-07-26 8:23 ` Joonas Lahtinen
@ 2016-07-26 8:28 ` Chris Wilson
2016-07-28 7:21 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 8:28 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 11:23:44AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -155,10 +155,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> > obj->base.write_domain);
> > for_each_engine_id(engine, dev_priv, id)
> > seq_printf(m, "%x ",
> > - i915_gem_request_get_seqno(obj->last_read_req[id]));
> > + i915_gem_request_get_seqno(obj->last_read[id].request));
>
> I hate i915_gem_request_get_seqno already, it's just NULL protection,
> but subject to different patch. Although, I see you got rid
> of i915_gem_request_get_engine already.
>
> > @@ -2383,10 +2383,10 @@ void i915_vma_move_to_active(struct i915_vma *vma,
> > static void
> > i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> > {
> > - GEM_BUG_ON(obj->last_write_req == NULL);
> > - GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
> > + GEM_BUG_ON(!obj->last_write.request);
> > + GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write.request->engine)));
>
> Over 80 ch line.
Don't care in this patch.
> intel_engine_flag seems rather dull, there's also this thing called
> BIT(), but again subject to another series.
>
> > @@ -2395,13 +2395,13 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> > {
> > struct i915_vma *vma;
> >
> > - GEM_BUG_ON(obj->last_read_req[idx] == NULL);
> > + GEM_BUG_ON(!obj->last_read[idx].request);
> > GEM_BUG_ON(!(obj->active & (1 << idx)));
>
> BIT(idx)?
Not in this patch.
>
> > +/* We treat requests as fences. This is not be to confused with our
> > + * "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
> > + * We use the fences to synchronize access from the CPU with activity on the
> > + * GPU, for example, we should not rewrite an object's PTE whilst the GPU
> > + * is reading them. We also track fences at a higher level to provide
> > + * implicit synchronisation around GEM objects, e.g. set-domain will wait
> > + * for outstanding GPU rendering before marking the object ready for CPU
> > + * access, or a pageflip will wait until the GPU is complete before showing
> > + * the frame on the scanout.
> > + *
> > + * In order to use a fence, the object must track the fence it needs to
> > + * serialise with. For example, GEM objects want to track both read and
> > + * write access so that we can perform concurrent read operations between
> > + * the CPU and GPU engines, as well as waiting for all rendering to
> > + * complete, or waiting for the last GPU user of a "fence register". The
> > + * object then embeds a @i915_gem_active to track the most recent (in
> > + * retirment order) request relevant for the desired mode of access.
> > + * The @i915_gem_active is updated with i915_gem_request_mark_active() to
> > + * track the most recent fence request, typically this is done as part of
> > + * i915_vma_move_to_active().
> > + *
> > + * When the @i915_gem_active completes (is retired), it will
> > + * signal its completion to the owner through a callback as well as mark
> > + * itself as idle (i915_gem_active.request == NULL). The owner
> > + * can then perform any action, such as delayed freeing of an active
> > + * resource including itself.
> > + */
> > +struct i915_gem_active {
>
> Not sure if this is a good descriptive struct name. Would not this be
> in the sync terminology a fence? active.request reads nicely though.
No. The active.request is the fence, this keeps track of the most recent
fence we are interested in.
> > + struct drm_i915_gem_request *request;
> > +};
> > +
> > +static inline void
> > +i915_gem_active_set(struct i915_gem_active *active,
> > + struct drm_i915_gem_request *request)
> > +{
> > + i915_gem_request_assign(&active->request, request);
> > +}
> > +
> > +#define for_each_active(mask, idx) \
> > + for (; mask ? idx = ffs(mask) - 1, 1 : 0; mask &= ~(1 << idx))
>
> BIT()
>
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -11378,7 +11378,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
> > if (resv && !reservation_object_test_signaled_rcu(resv, false))
> > return true;
> >
> > - return engine != i915_gem_request_get_engine(obj->last_write_req);
> > + return engine != i915_gem_request_get_engine(obj->last_write.request);
>
> What's been the obsession with NULL protecting simple accessor
> functions? Makes the code look overly complicated. One more function to
> nuke.
That was against my wishes. This patch was only to introduce the new
struct, actually making use of it comes later.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations
2016-07-25 17:32 ` [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations Chris Wilson
@ 2016-07-26 8:50 ` Joonas Lahtinen
2016-07-26 9:03 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 8:50 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 98dc97c8c2bf..b8d541f212ff 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1349,27 +1349,30 @@ int
> i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
> bool readonly)
> {
> + struct drm_i915_gem_request *request;
'req' is rather de facto. One bad name is better than two names of any
grade. I see much of your new code is with *request, which direction
should we have?
>
> @@ -2383,8 +2386,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
> static void
> i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> {
> - GEM_BUG_ON(!obj->last_write.request);
> - GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write.request->engine)));
> + GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_write));
> + GEM_BUG_ON(!(obj->active & intel_engine_flag(i915_gem_active_get_engine(&obj->last_write))));
Already mentioned in previous, long line. You added new functions to
_gem_active which do useful stuff, then you could nuke the dummy ones?
> @@ -2621,7 +2626,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
> struct drm_i915_gem_object,
> engine_list[engine->id]);
>
> - if (!list_empty(&obj->last_read[engine->id].request->list))
> + if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id])->list))
Long line.
> break;
>
> i915_gem_object_retire__read(obj, engine->id);
> @@ -2754,7 +2759,7 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
> for (i = 0; i < I915_NUM_ENGINES; i++) {
> struct drm_i915_gem_request *req;
>
> - req = obj->last_read[i].request;
> + req = i915_gem_active_peek(&obj->last_read[i]);
> if (req == NULL)
> continue;
>
> @@ -2794,7 +2799,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> {
> struct drm_i915_gem_wait *args = data;
> struct drm_i915_gem_object *obj;
> - struct drm_i915_gem_request *req[I915_NUM_ENGINES];
> + struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
I think this answers my previous question.
<SNIP>
> + struct drm_i915_gem_request *req;
>
>
> n = 0;
> if (readonly) {
> - if (obj->last_write.request)
> - req[n++] = obj->last_write.request;
> + struct drm_i915_gem_request *req;
> +
> + req = i915_gem_active_peek(&obj->last_write);
> + if (req)
> + requests[n++] = req;
> } else {
> - for (i = 0; i < I915_NUM_ENGINES; i++)
> - if (obj->last_read[i].request)
> - req[n++] = obj->last_read[i].request;
> + for (i = 0; i < I915_NUM_ENGINES; i++) {
> + struct drm_i915_gem_request *req;
But some consistency is lacking with dem names. How's it going to be?
> +static inline uint32_t
> +i915_gem_active_get_seqno(const struct i915_gem_active *active)
> +{
> + return i915_gem_request_get_seqno(i915_gem_active_peek(active));
Nuke the i915_gem_request_get_seqno wrapper, it's insanity. Now or an
another patch.
> +}
> +
> +static inline struct intel_engine_cs *
> +i915_gem_active_get_engine(const struct i915_gem_active *active)
> +{
> + return i915_gem_request_get_engine(i915_gem_active_peek(active));
Ditto.
With the nitpicking,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation
2016-07-25 17:32 ` [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation Chris Wilson
@ 2016-07-26 8:54 ` Joonas Lahtinen
2016-07-26 9:06 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 8:54 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> The future annotations will track the locking used for access to ensure
> that it is always sufficient. We make the preparations now to present
> the API ahead and to make sure that GCC can eliminate the unused
> parameter.
>
Is it at some point going to be other than struct_mutex? I do not feel
the API change intuitive at all as it is.
> Before: 6298417 3619610 696320 10614347 a1f64b vmlinux
> After: 6298417 3619610 696320 10614347 a1f64b vmlinux
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +++++---
> drivers/gpu/drm/i915/i915_gem.c | 49 ++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/i915_gem_fence.c | 3 +-
> drivers/gpu/drm/i915/i915_gem_request.h | 38 +++++++++++++++----------
> drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +-
> drivers/gpu/drm/i915/i915_gem_userptr.c | 3 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 29 +++++++++++++++----
> drivers/gpu/drm/i915/intel_display.c | 12 +++++---
> 8 files changed, 102 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b41561bdfb85..16fa1f527ef5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -155,10 +155,13 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> obj->base.write_domain);
> for_each_engine_id(engine, dev_priv, id)
> seq_printf(m, "%x ",
> - i915_gem_active_get_seqno(&obj->last_read[id]));
> + i915_gem_active_get_seqno(&obj->last_read[id],
> + &obj->base.dev->struct_mutex));
In functions where you use plenty of this, maybe make struct_mutex
alias. But before that, what's wrong with passing dev_priv?
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations
2016-07-26 8:50 ` Joonas Lahtinen
@ 2016-07-26 9:03 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 9:03 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 11:50:23AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 98dc97c8c2bf..b8d541f212ff 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -1349,27 +1349,30 @@ int
> > i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
> > bool readonly)
> > {
> > + struct drm_i915_gem_request *request;
>
> 'req' is rather de facto. One bad name is better than two names of any
> grade. I see much of your new code is with *request, which direction
> should we have?
>
> >
> > @@ -2383,8 +2386,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
> > static void
> > i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> > {
> > - GEM_BUG_ON(!obj->last_write.request);
> > - GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write.request->engine)));
> > + GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_write));
> > + GEM_BUG_ON(!(obj->active & intel_engine_flag(i915_gem_active_get_engine(&obj->last_write))));
>
> Already mentioned in previous, long line. You added new functions to
> _gem_active which do useful stuff, then you could nuke the dummy ones?
>
> > @@ -2621,7 +2626,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
> > struct drm_i915_gem_object,
> > engine_list[engine->id]);
> >
> > - if (!list_empty(&obj->last_read[engine->id].request->list))
> > + if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id])->list))
>
> Long line.
Not touching the long lines in intermediate patches for code that will
be deleted.
> > break;
> >
> > i915_gem_object_retire__read(obj, engine->id);
> > @@ -2754,7 +2759,7 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
> > for (i = 0; i < I915_NUM_ENGINES; i++) {
> > struct drm_i915_gem_request *req;
> >
> > - req = obj->last_read[i].request;
> > + req = i915_gem_active_peek(&obj->last_read[i]);
> > if (req == NULL)
> > continue;
> >
> > @@ -2794,7 +2799,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> > {
> > struct drm_i915_gem_wait *args = data;
> > struct drm_i915_gem_object *obj;
> > - struct drm_i915_gem_request *req[I915_NUM_ENGINES];
> > + struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
>
> I think this answers my previous question.
>
> <SNIP>
>
> > + struct drm_i915_gem_request *req;
> >
> >
> > n = 0;
> > if (readonly) {
> > - if (obj->last_write.request)
> > - req[n++] = obj->last_write.request;
> > + struct drm_i915_gem_request *req;
> > +
> > + req = i915_gem_active_peek(&obj->last_write);
> > + if (req)
> > + requests[n++] = req;
> > } else {
> > - for (i = 0; i < I915_NUM_ENGINES; i++)
> > - if (obj->last_read[i].request)
> > - req[n++] = obj->last_read[i].request;
> > + for (i = 0; i < I915_NUM_ENGINES; i++) {
> > + struct drm_i915_gem_request *req;
>
> But some consistency is lacking with dem names. How's it going to be?
What I always had was requests for member names, rq for locals. But
apparently rq was too much like run-queue, which is how we use the
requests! In userspace I always used requests for members and rq for
locals.
Where I have been adding functions, I have been using request as the
local as well. Where I have been inheriting the ugly name, it has mostly
stuck.
> > +static inline uint32_t
> > +i915_gem_active_get_seqno(const struct i915_gem_active *active)
> > +{
> > + return i915_gem_request_get_seqno(i915_gem_active_peek(active));
>
> Nuke the i915_gem_request_get_seqno wrapper, it's insanity. Now or an
> another patch.
They are (or will be) only used in a couple of places where the NULL
guard is required.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation
2016-07-26 8:54 ` Joonas Lahtinen
@ 2016-07-26 9:06 ` Chris Wilson
2016-07-28 7:26 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 9:06 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 11:54:16AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > The future annotations will track the locking used for access to ensure
> > that it is always sufficient. We make the preparations now to present
> > the API ahead and to make sure that GCC can eliminate the unused
> > parameter.
> >
>
> Is it at some point going to be other than struct_mutex?
Yes.
> I do not feel
> the API change intuitive at all as it is.
The API change here is solely for RCU markup later, i.e. we can access
the active.request lockless but have to be very careful when we do.
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index b41561bdfb85..16fa1f527ef5 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -155,10 +155,13 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> > obj->base.write_domain);
> > for_each_engine_id(engine, dev_priv, id)
> > seq_printf(m, "%x ",
> > - i915_gem_active_get_seqno(&obj->last_read[id]));
> > + i915_gem_active_get_seqno(&obj->last_read[id],
> > + &obj->base.dev->struct_mutex));
>
> In functions where you use plenty of this, maybe make struct_mutex
> alias. But before that, what's wrong with passing dev_priv?
What dev_priv? See earlier answer about this should not be struct_mutex
in the long run.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 41/55] drm/i915: Rename request->list to link for consistency
2016-07-25 17:32 ` [PATCH 41/55] drm/i915: Rename request->list to link for consistency Chris Wilson
@ 2016-07-26 9:26 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 9:26 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> We use "list" to denote the list and "link" to denote an element on that
> list. Rename request->list to match this idiom.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_gem.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_gem_request.c | 12 ++++++------
> drivers/gpu/drm/i915/i915_gem_request.h | 4 ++--
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
> 6 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 16fa1f527ef5..6693dfbca4f1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -748,13 +748,13 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
> int count;
>
> count = 0;
> - list_for_each_entry(req, &engine->request_list, list)
> + list_for_each_entry(req, &engine->request_list, link)
> count++;
> if (count == 0)
> continue;
>
> seq_printf(m, "%s requests: %d\n", engine->name, count);
> - list_for_each_entry(req, &engine->request_list, list) {
> + list_for_each_entry(req, &engine->request_list, link) {
> struct task_struct *task;
>
> rcu_read_lock();
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 2d86a0c3f295..e5be4eb0a397 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2475,7 +2475,7 @@ i915_gem_find_active_request(struct intel_engine_cs *engine)
> * extra delay for a recent interrupt is pointless. Hence, we do
> * not need an engine->irq_seqno_barrier() before the seqno reads.
> */
> - list_for_each_entry(request, &engine->request_list, list) {
> + list_for_each_entry(request, &engine->request_list, link) {
> if (i915_gem_request_completed(request))
> continue;
>
> @@ -2497,7 +2497,7 @@ static void i915_gem_reset_engine_status(struct intel_engine_cs *engine)
> ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
>
> i915_set_reset_status(request->ctx, ring_hung);
> - list_for_each_entry_continue(request, &engine->request_list, list)
> + list_for_each_entry_continue(request, &engine->request_list, link)
> i915_set_reset_status(request->ctx, false);
> }
>
> @@ -2546,7 +2546,7 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
>
> request = list_last_entry(&engine->request_list,
> struct drm_i915_gem_request,
> - list);
> + link);
>
> i915_gem_request_retire_upto(request);
> }
> @@ -2609,7 +2609,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
>
> request = list_first_entry(&engine->request_list,
> struct drm_i915_gem_request,
> - list);
> + link);
>
> if (!i915_gem_request_completed(request))
> break;
> @@ -2629,7 +2629,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
> engine_list[engine->id]);
>
> if (!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id],
> - &obj->base.dev->struct_mutex)->list))
> + &obj->base.dev->struct_mutex)->link))
> break;
>
> i915_gem_object_retire__read(obj, engine->id);
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index d7011185a4ee..065e9e61265b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -160,7 +160,7 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
> static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> {
> trace_i915_gem_request_retire(request);
> - list_del_init(&request->list);
> + list_del_init(&request->link);
>
> /* We know the GPU must have read the request to have
> * sent us the seqno + interrupt, so use the position
> @@ -191,12 +191,12 @@ void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
>
> lockdep_assert_held(&req->i915->drm.struct_mutex);
>
> - if (list_empty(&req->list))
> + if (list_empty(&req->link))
> return;
>
> do {
> tmp = list_first_entry(&engine->request_list,
> - typeof(*tmp), list);
> + typeof(*tmp), link);
>
> i915_gem_request_retire(tmp);
> } while (tmp != req);
> @@ -317,7 +317,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
>
> /* Move the oldest request to the slab-cache (if not in use!) */
> req = list_first_entry_or_null(&engine->request_list,
> - typeof(*req), list);
> + typeof(*req), link);
> if (req && i915_gem_request_completed(req))
> i915_gem_request_retire(req);
>
> @@ -450,7 +450,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> request->emitted_jiffies = jiffies;
> request->previous_seqno = engine->last_submitted_seqno;
> smp_store_mb(engine->last_submitted_seqno, request->fence.seqno);
> - list_add_tail(&request->list, &engine->request_list);
> + list_add_tail(&request->link, &engine->request_list);
>
> /* Record the position of the start of the request so that
> * should we detect the updated seqno part-way through the
> @@ -570,7 +570,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
>
> might_sleep();
>
> - if (list_empty(&req->list))
> + if (list_empty(&req->link))
> return 0;
>
> if (i915_gem_request_completed(req))
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
> index 2df01a6f5fbb..dc93051a68d8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.h
> +++ b/drivers/gpu/drm/i915/i915_gem_request.h
> @@ -105,8 +105,8 @@ struct drm_i915_gem_request {
> /** Time at which this request was emitted, in jiffies. */
> unsigned long emitted_jiffies;
>
> - /** global list entry for this request */
> - struct list_head list;
> + /** engine->request_list entry for this request */
> + struct list_head link;
>
> struct drm_i915_file_private *file_priv;
> /** file_priv list entry for this request */
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index f6fe6b46f4b1..2b431e22addf 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1171,7 +1171,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> i915_gem_record_active_context(engine, error, ering);
>
> count = 0;
> - list_for_each_entry(request, &engine->request_list, list)
> + list_for_each_entry(request, &engine->request_list, link)
> count++;
>
> ering->num_requests = count;
> @@ -1183,7 +1183,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> }
>
> count = 0;
> - list_for_each_entry(request, &engine->request_list, list) {
> + list_for_each_entry(request, &engine->request_list, link) {
> struct drm_i915_error_request *erq;
>
> if (count >= ering->num_requests) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 7be7666c894e..5e0ba9416bd9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2250,7 +2250,7 @@ int intel_engine_idle(struct intel_engine_cs *engine)
>
> req = list_entry(engine->request_list.prev,
> struct drm_i915_gem_request,
> - list);
> + link);
>
> /* Make sure we do not trigger any retires */
> return __i915_wait_request(req,
> @@ -2299,7 +2299,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> */
> GEM_BUG_ON(!req->reserved_space);
>
> - list_for_each_entry(target, &engine->request_list, list) {
> + list_for_each_entry(target, &engine->request_list, link) {
> unsigned space;
>
> /*
> @@ -2317,7 +2317,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> break;
> }
>
> - if (WARN_ON(&target->list == &engine->request_list))
> + if (WARN_ON(&target->link == &engine->request_list))
> return -ENOSPC;
>
> return i915_wait_request(target);
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active()
2016-07-25 17:32 ` [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active() Chris Wilson
@ 2016-07-26 9:31 ` Joonas Lahtinen
2016-07-26 9:47 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 9:31 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> Since we track requests, and requests are always added to the GPU fully
> formed, we never have to flush the incomplete request and know that the
> given request will eventually complete without any further action on our
> part.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This series will need plenty of CI regression and benchmark testing...
Regards, Joonas
> ---
> drivers/gpu/drm/i915/i915_gem.c | 59 +++--------------------------------------
> 1 file changed, 3 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e5be4eb0a397..3bff6b560f97 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2746,35 +2746,6 @@ out_rearm:
> }
>
> /**
> - * Ensures that an object will eventually get non-busy by flushing any required
> - * write domains, emitting any outstanding lazy request and retiring and
> - * completed requests.
> - * @obj: object to flush
> - */
> -static int
> -i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
> -{
> - int i;
> -
> - if (!obj->active)
> - return 0;
> -
> - for (i = 0; i < I915_NUM_ENGINES; i++) {
> - struct drm_i915_gem_request *req;
> -
> - req = i915_gem_active_peek(&obj->last_read[i],
> - &obj->base.dev->struct_mutex);
> - if (req == NULL)
> - continue;
> -
> - if (i915_gem_request_completed(req))
> - i915_gem_object_retire__read(obj, i);
> - }
> -
> - return 0;
> -}
> -
> -/**
> * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
> * @dev: drm device pointer
> * @data: ioctl data blob
> @@ -2820,24 +2791,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> return -ENOENT;
> }
>
> - /* Need to make sure the object gets inactive eventually. */
> - ret = i915_gem_object_flush_active(obj);
> - if (ret)
> - goto out;
> -
> if (!obj->active)
> goto out;
>
> - /* Do this after OLR check to make sure we make forward progress polling
> - * on this IOCTL with a timeout == 0 (like busy ioctl)
> - */
> - if (args->timeout_ns == 0) {
> - ret = -ETIME;
> - goto out;
> - }
> -
> - i915_gem_object_put(obj);
> -
> for (i = 0; i < I915_NUM_ENGINES; i++) {
> struct drm_i915_gem_request *req;
>
> @@ -2847,6 +2803,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> requests[n++] = req;
> }
>
> +out:
> + i915_gem_object_put(obj);
> mutex_unlock(&dev->struct_mutex);
>
> for (i = 0; i < n; i++) {
> @@ -2857,11 +2815,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> i915_gem_request_put(requests[i]);
> }
> return ret;
> -
> -out:
> - i915_gem_object_put(obj);
> - mutex_unlock(&dev->struct_mutex);
> - return ret;
> }
>
> static int
> @@ -4036,13 +3989,8 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
>
> /* Count all active objects as busy, even if they are currently not used
> * by the gpu. Users of this interface expect objects to eventually
> - * become non-busy without any further actions, therefore emit any
> - * necessary flushes here.
> + * become non-busy without any further actions.
> */
> - ret = i915_gem_object_flush_active(obj);
> - if (ret)
> - goto unref;
> -
> args->busy = 0;
> if (obj->active) {
> struct drm_i915_gem_request *req;
> @@ -4060,7 +4008,6 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
> args->busy |= req->engine->exec_id;
> }
>
> -unref:
> i915_gem_object_put(obj);
> unlock:
> mutex_unlock(&dev->struct_mutex);
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active()
2016-07-26 9:31 ` Joonas Lahtinen
@ 2016-07-26 9:47 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 9:47 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 12:31:29PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > Since we track requests, and requests are always added to the GPU fully
> > formed, we never have to flush the incomplete request and know that the
> > given request will eventually complete without any further action on our
> > part.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> This series will need plenty of CI regression and benchmark testing...
CI? Maybe one day they will run the tests that exercise this code.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 44/55] drm/i915: Track requests inside each intel_ring
2016-07-25 17:32 ` [PATCH 44/55] drm/i915: Track requests inside each intel_ring Chris Wilson
@ 2016-07-26 10:10 ` Joonas Lahtinen
2016-07-26 10:15 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 10:10 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> By tracking each request occupying space inside an individual
> intel_ring, we can greatly simplify the logic of tracking available
> space and not worry about other timelines. (Each ring is an ordered
> timeline of committed requests.)
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Not such an amazing simplification in this patch, but I assume later.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
> ---
> drivers/gpu/drm/i915/i915_gem_request.c | 2 ++
> drivers/gpu/drm/i915/i915_gem_request.h | 3 +++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++-----------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
> 4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 0216d6c093da..f1c37b7891cb 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -174,6 +174,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> * Note this requires that we are always called in request
> * completion order.
> */
> + list_del(&request->ring_link);
> request->ring->last_retired_head = request->postfix;
>
> /* Walk through the active list, calling retire on each. This allows
> @@ -472,6 +473,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> request->previous_seqno = engine->last_submitted_seqno;
> smp_store_mb(engine->last_submitted_seqno, request->fence.seqno);
> list_add_tail(&request->link, &engine->request_list);
> + list_add_tail(&request->ring_link, &ring->request_list);
>
> /* Record the position of the start of the request so that
> * should we detect the updated seqno part-way through the
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
> index f0b91207aaa4..b1ee37896feb 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.h
> +++ b/drivers/gpu/drm/i915/i915_gem_request.h
> @@ -109,6 +109,9 @@ struct drm_i915_gem_request {
> /** engine->request_list entry for this request */
> struct list_head link;
>
> + /** ring->request_list entry for this request */
> + struct list_head ring_link;
> +
> struct drm_i915_file_private *file_priv;
> /** file_priv list entry for this request */
> struct list_head client_list;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 5e0ba9416bd9..af76869c8db2 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2059,6 +2059,8 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size)
> ring->engine = engine;
> list_add(&ring->link, &engine->buffers);
>
> + INIT_LIST_HEAD(&ring->request_list);
> +
> ring->size = size;
> /* Workaround an erratum on the i830 which causes a hang if
> * the TAIL pointer points to within the last 2 cachelines
> @@ -2281,7 +2283,6 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
> static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> {
> struct intel_ring *ring = req->ring;
> - struct intel_engine_cs *engine = req->engine;
> struct drm_i915_gem_request *target;
>
> intel_ring_update_space(ring);
> @@ -2299,17 +2300,9 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> */
> GEM_BUG_ON(!req->reserved_space);
>
> - list_for_each_entry(target, &engine->request_list, link) {
> + list_for_each_entry(target, &ring->request_list, ring_link) {
> unsigned space;
>
> - /*
> - * The request queue is per-engine, so can contain requests
> - * from multiple ringbuffers. Here, we must ignore any that
> - * aren't from the ringbuffer we're considering.
> - */
> - if (target->ring != ring)
> - continue;
> -
> /* Would completion of this request free enough space? */
> space = __intel_ring_space(target->postfix, ring->tail,
> ring->size);
> @@ -2317,7 +2310,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> break;
> }
>
> - if (WARN_ON(&target->link == &engine->request_list))
> + if (WARN_ON(&target->ring_link == &ring->request_list))
> return -ENOSPC;
>
> return i915_wait_request(target);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 51c059d8c917..2681106948a5 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -90,6 +90,8 @@ struct intel_ring {
> struct intel_engine_cs *engine;
> struct list_head link;
>
> + struct list_head request_list;
> +
> u32 head;
> u32 tail;
> int space;
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 44/55] drm/i915: Track requests inside each intel_ring
2016-07-26 10:10 ` Joonas Lahtinen
@ 2016-07-26 10:15 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 10:15 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 01:10:16PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > By tracking each request occupying space inside an individual
> > intel_ring, we can greatly simplify the logic of tracking available
> > space and not worry about other timelines. (Each ring is an ordered
> > timeline of committed requests.)
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Not such an amazing simplification in this patch, but I assume later.
:) Yes, you don't get to see the contortions now. A stitch in time is
worth nine!
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* [PATCH v2] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
2016-07-26 4:59 ` Joonas Lahtinen
2016-07-26 8:19 ` Chris Wilson
@ 2016-07-26 10:21 ` Chris Wilson
2016-07-26 12:35 ` Joonas Lahtinen
1 sibling, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 10:21 UTC (permalink / raw)
To: intel-gfx
Inside the error capture itself, we refer to not only the hardware
engine, its ringbuffer but also the capture state. Finding clear names
for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
compromise we keep using ering for the error capture.
v2: Use 'ee' locals for struct drm_i915_error_engine
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-chris@chris-wilson.co.uk
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 403 +++++++++++++++++-----------------
2 files changed, 208 insertions(+), 203 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97f827979a66..65ada5d2f88c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -512,8 +512,8 @@ struct drm_i915_error_state {
struct intel_display_error_state *display;
struct drm_i915_error_object *semaphore_obj;
- struct drm_i915_error_ring {
- bool valid;
+ struct drm_i915_error_engine {
+ int engine_id;
/* Software tracked state */
bool waiting;
int num_waiters;
@@ -578,7 +578,7 @@ struct drm_i915_error_state {
pid_t pid;
char comm[TASK_COMM_LEN];
- } ring[I915_NUM_ENGINES];
+ } engine[I915_NUM_ENGINES];
struct drm_i915_error_buffer {
u32 size;
@@ -593,7 +593,7 @@ struct drm_i915_error_state {
u32 dirty:1;
u32 purgeable:1;
u32 userptr:1;
- s32 ring:4;
+ s32 engine:4;
u32 cache_level:3;
} **active_bo, **pinned_bo;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4d39c7284605..bc4a3ebc2662 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -30,9 +30,9 @@
#include <generated/utsrelease.h>
#include "i915_drv.h"
-static const char *ring_str(int ring)
+static const char *engine_str(int engine)
{
- switch (ring) {
+ switch (engine) {
case RCS: return "render";
case VCS: return "bsd";
case BCS: return "blt";
@@ -207,8 +207,8 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
err_puts(m, dirty_flag(err->dirty));
err_puts(m, purgeable_flag(err->purgeable));
err_puts(m, err->userptr ? " userptr" : "");
- err_puts(m, err->ring != -1 ? " " : "");
- err_puts(m, ring_str(err->ring));
+ err_puts(m, err->engine != -1 ? " " : "");
+ err_puts(m, engine_str(err->engine));
err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
if (err->name)
@@ -239,70 +239,65 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
return "unknown";
}
-static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
- struct drm_device *dev,
- struct drm_i915_error_state *error,
- int ring_idx)
+static void error_print_engine(struct drm_i915_error_state_buf *m,
+ struct drm_i915_error_engine *ee)
{
- struct drm_i915_error_ring *ring = &error->ring[ring_idx];
-
- if (!ring->valid)
- return;
-
- err_printf(m, "%s command stream:\n", ring_str(ring_idx));
- err_printf(m, " START: 0x%08x\n", ring->start);
- err_printf(m, " HEAD: 0x%08x\n", ring->head);
- err_printf(m, " TAIL: 0x%08x\n", ring->tail);
- err_printf(m, " CTL: 0x%08x\n", ring->ctl);
- err_printf(m, " HWS: 0x%08x\n", ring->hws);
- err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
- err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
- err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
- err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
- if (INTEL_INFO(dev)->gen >= 4) {
- err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
- err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
- err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
+ err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
+ err_printf(m, " START: 0x%08x\n", ee->start);
+ err_printf(m, " HEAD: 0x%08x\n", ee->head);
+ err_printf(m, " TAIL: 0x%08x\n", ee->tail);
+ err_printf(m, " CTL: 0x%08x\n", ee->ctl);
+ err_printf(m, " HWS: 0x%08x\n", ee->hws);
+ err_printf(m, " ACTHD: 0x%08x %08x\n",
+ (u32)(ee->acthd>>32), (u32)ee->acthd);
+ err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
+ err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
+ err_printf(m, " INSTDONE: 0x%08x\n", ee->instdone);
+ if (INTEL_GEN(m->i915) >= 4) {
+ err_printf(m, " BBADDR: 0x%08x %08x\n",
+ (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
+ err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
+ err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
}
- err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
- err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
- lower_32_bits(ring->faddr));
- if (INTEL_INFO(dev)->gen >= 6) {
- err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
- err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
+ err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
+ err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
+ lower_32_bits(ee->faddr));
+ if (INTEL_GEN(m->i915) >= 6) {
+ err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
+ err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
- ring->semaphore_mboxes[0],
- ring->semaphore_seqno[0]);
+ ee->semaphore_mboxes[0],
+ ee->semaphore_seqno[0]);
err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
- ring->semaphore_mboxes[1],
- ring->semaphore_seqno[1]);
- if (HAS_VEBOX(dev)) {
+ ee->semaphore_mboxes[1],
+ ee->semaphore_seqno[1]);
+ if (HAS_VEBOX(m->i915)) {
err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
- ring->semaphore_mboxes[2],
- ring->semaphore_seqno[2]);
+ ee->semaphore_mboxes[2],
+ ee->semaphore_seqno[2]);
}
}
- if (USES_PPGTT(dev)) {
- err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
+ if (USES_PPGTT(m->i915)) {
+ err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(m->i915) >= 8) {
int i;
for (i = 0; i < 4; i++)
err_printf(m, " PDP%d: 0x%016llx\n",
- i, ring->vm_info.pdp[i]);
+ i, ee->vm_info.pdp[i]);
} else {
err_printf(m, " PP_DIR_BASE: 0x%08x\n",
- ring->vm_info.pp_dir_base);
+ ee->vm_info.pp_dir_base);
}
}
- err_printf(m, " seqno: 0x%08x\n", ring->seqno);
- err_printf(m, " last_seqno: 0x%08x\n", ring->last_seqno);
- err_printf(m, " waiting: %s\n", yesno(ring->waiting));
- err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
- err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
+ err_printf(m, " seqno: 0x%08x\n", ee->seqno);
+ err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
+ err_printf(m, " waiting: %s\n", yesno(ee->waiting));
+ err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
+ err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
err_printf(m, " hangcheck: %s [%d]\n",
- hangcheck_action_to_str(ring->hangcheck_action),
- ring->hangcheck_score);
+ hangcheck_action_to_str(ee->hangcheck_action),
+ ee->hangcheck_score);
}
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
@@ -348,17 +343,17 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
error->time.tv_usec);
err_printf(m, "Kernel: " UTS_RELEASE "\n");
max_hangcheck_score = 0;
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- if (error->ring[i].hangcheck_score > max_hangcheck_score)
- max_hangcheck_score = error->ring[i].hangcheck_score;
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ if (error->engine[i].hangcheck_score > max_hangcheck_score)
+ max_hangcheck_score = error->engine[i].hangcheck_score;
}
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- if (error->ring[i].hangcheck_score == max_hangcheck_score &&
- error->ring[i].pid != -1) {
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ if (error->engine[i].hangcheck_score == max_hangcheck_score &&
+ error->engine[i].pid != -1) {
err_printf(m, "Active process (on ring %s): %s [%d]\n",
- ring_str(i),
- error->ring[i].comm,
- error->ring[i].pid);
+ engine_str(i),
+ error->engine[i].comm,
+ error->engine[i].pid);
}
}
err_printf(m, "Reset count: %u\n", error->reset_count);
@@ -414,8 +409,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
if (IS_GEN7(dev))
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
- for (i = 0; i < ARRAY_SIZE(error->ring); i++)
- i915_ring_error_state(m, dev, error, i);
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ if (error->engine[i].engine_id != -1)
+ error_print_engine(m, &error->engine[i]);
+ }
for (i = 0; i < error->vm_count; i++) {
err_printf(m, "vm[%d]\n", i);
@@ -429,21 +426,23 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
error->pinned_bo_count[i]);
}
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- obj = error->ring[i].batchbuffer;
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ struct drm_i915_error_engine *ee = &error->engine[i];
+
+ obj = ee->batchbuffer;
if (obj) {
err_puts(m, dev_priv->engine[i].name);
- if (error->ring[i].pid != -1)
+ if (ee->pid != -1)
err_printf(m, " (submitted by %s [%d])",
- error->ring[i].comm,
- error->ring[i].pid);
+ ee->comm,
+ ee->pid);
err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
upper_32_bits(obj->gtt_offset),
lower_32_bits(obj->gtt_offset));
print_error_obj(m, obj);
}
- obj = error->ring[i].wa_batchbuffer;
+ obj = ee->wa_batchbuffer;
if (obj) {
err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
dev_priv->engine[i].name,
@@ -451,38 +450,38 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
print_error_obj(m, obj);
}
- if (error->ring[i].num_requests) {
+ if (ee->num_requests) {
err_printf(m, "%s --- %d requests\n",
dev_priv->engine[i].name,
- error->ring[i].num_requests);
- for (j = 0; j < error->ring[i].num_requests; j++) {
+ ee->num_requests);
+ for (j = 0; j < ee->num_requests; j++) {
err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
- error->ring[i].requests[j].seqno,
- error->ring[i].requests[j].jiffies,
- error->ring[i].requests[j].tail);
+ ee->requests[j].seqno,
+ ee->requests[j].jiffies,
+ ee->requests[j].tail);
}
}
- if (error->ring[i].num_waiters) {
+ if (ee->num_waiters) {
err_printf(m, "%s --- %d waiters\n",
dev_priv->engine[i].name,
- error->ring[i].num_waiters);
- for (j = 0; j < error->ring[i].num_waiters; j++) {
+ ee->num_waiters);
+ for (j = 0; j < ee->num_waiters; j++) {
err_printf(m, " seqno 0x%08x for %s [%d]\n",
- error->ring[i].waiters[j].seqno,
- error->ring[i].waiters[j].comm,
- error->ring[i].waiters[j].pid);
+ ee->waiters[j].seqno,
+ ee->waiters[j].comm,
+ ee->waiters[j].pid);
}
}
- if ((obj = error->ring[i].ringbuffer)) {
+ if ((obj = ee->ringbuffer)) {
err_printf(m, "%s --- ringbuffer = 0x%08x\n",
dev_priv->engine[i].name,
lower_32_bits(obj->gtt_offset));
print_error_obj(m, obj);
}
- if ((obj = error->ring[i].hws_page)) {
+ if ((obj = ee->hws_page)) {
u64 hws_offset = obj->gtt_offset;
u32 *hws_page = &obj->pages[0][0];
@@ -504,7 +503,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
}
}
- obj = error->ring[i].wa_ctx;
+ obj = ee->wa_ctx;
if (obj) {
u64 wa_ctx_offset = obj->gtt_offset;
u32 *wa_ctx_page = &obj->pages[0][0];
@@ -526,7 +525,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
}
}
- if ((obj = error->ring[i].ctx)) {
+ if ((obj = ee->ctx)) {
err_printf(m, "%s --- HW Context = 0x%08x\n",
dev_priv->engine[i].name,
lower_32_bits(obj->gtt_offset));
@@ -611,15 +610,18 @@ static void i915_error_state_free(struct kref *error_ref)
typeof(*error), ref);
int i;
- for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
- i915_error_object_free(error->ring[i].batchbuffer);
- i915_error_object_free(error->ring[i].wa_batchbuffer);
- i915_error_object_free(error->ring[i].ringbuffer);
- i915_error_object_free(error->ring[i].hws_page);
- i915_error_object_free(error->ring[i].ctx);
- i915_error_object_free(error->ring[i].wa_ctx);
- kfree(error->ring[i].requests);
- kfree(error->ring[i].waiters);
+ for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
+ struct drm_i915_error_engine *ee = &error->engine[i];
+
+ i915_error_object_free(ee->batchbuffer);
+ i915_error_object_free(ee->wa_batchbuffer);
+ i915_error_object_free(ee->ringbuffer);
+ i915_error_object_free(ee->hws_page);
+ i915_error_object_free(ee->ctx);
+ i915_error_object_free(ee->wa_ctx);
+
+ kfree(ee->requests);
+ kfree(ee->waiters);
}
i915_error_object_free(error->semaphore_obj);
@@ -762,8 +764,8 @@ static void capture_bo(struct drm_i915_error_buffer *err,
err->dirty = obj->dirty;
err->purgeable = obj->madv != I915_MADV_WILLNEED;
err->userptr = obj->userptr.mm != NULL;
- err->ring = obj->last_write_req ?
- i915_gem_request_get_engine(obj->last_write_req)->id : -1;
+ err->engine = obj->last_write_req ?
+ i915_gem_request_get_engine(obj->last_write_req)->id : -1;
err->cache_level = obj->cache_level;
}
@@ -815,7 +817,7 @@ static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
*/
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
- int *ring_id)
+ int *engine_id)
{
uint32_t error_code = 0;
int i;
@@ -826,11 +828,11 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
* strictly a client bug. Use instdone to differentiate those some.
*/
for (i = 0; i < I915_NUM_ENGINES; i++) {
- if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
- if (ring_id)
- *ring_id = i;
+ if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
+ if (engine_id)
+ *engine_id = i;
- return error->ring[i].ipehr ^ error->ring[i].instdone;
+ return error->engine[i].ipehr ^ error->engine[i].instdone;
}
}
@@ -855,21 +857,16 @@ static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
}
-static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
- struct drm_i915_error_state *error,
+static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+ struct drm_i915_error_engine *ee)
{
+ struct drm_i915_private *dev_priv = engine->i915;
struct intel_engine_cs *to;
enum intel_engine_id id;
- if (!i915.semaphores)
- return;
-
if (!error->semaphore_obj)
- error->semaphore_obj =
- i915_error_ggtt_object_create(dev_priv,
- dev_priv->semaphore_obj);
+ return;
for_each_engine_id(to, dev_priv, id) {
int idx;
@@ -879,42 +876,43 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
if (engine == to)
continue;
- signal_offset = (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1))
- / 4;
+ signal_offset =
+ (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
tmp = error->semaphore_obj->pages[0];
idx = intel_ring_sync_index(engine, to);
- ering->semaphore_mboxes[idx] = tmp[signal_offset];
- ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
+ ee->semaphore_mboxes[idx] = tmp[signal_offset];
+ ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
}
}
-static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
- struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
+ struct drm_i915_error_engine *ee)
{
- ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
- ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
- ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
- ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
+ struct drm_i915_private *dev_priv = engine->i915;
+
+ ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
+ ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
+ ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
+ ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
if (HAS_VEBOX(dev_priv)) {
- ering->semaphore_mboxes[2] =
+ ee->semaphore_mboxes[2] =
I915_READ(RING_SYNC_2(engine->mmio_base));
- ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
+ ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
}
}
-static void engine_record_waiters(struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+static void error_record_engine_waiters(struct intel_engine_cs *engine,
+ struct drm_i915_error_engine *ee)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
struct drm_i915_error_waiter *waiter;
struct rb_node *rb;
int count;
- ering->num_waiters = 0;
- ering->waiters = NULL;
+ ee->num_waiters = 0;
+ ee->waiters = NULL;
spin_lock(&b->lock);
count = 0;
@@ -930,7 +928,7 @@ static void engine_record_waiters(struct intel_engine_cs *engine,
if (!waiter)
return;
- ering->waiters = waiter;
+ ee->waiters = waiter;
spin_lock(&b->lock);
for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
@@ -941,55 +939,55 @@ static void engine_record_waiters(struct intel_engine_cs *engine,
waiter->seqno = w->seqno;
waiter++;
- if (++ering->num_waiters == count)
+ if (++ee->num_waiters == count)
break;
}
spin_unlock(&b->lock);
}
-static void i915_record_ring_state(struct drm_i915_private *dev_priv,
- struct drm_i915_error_state *error,
- struct intel_engine_cs *engine,
- struct drm_i915_error_ring *ering)
+static void error_record_engine_registers(struct drm_i915_error_state *error,
+ struct intel_engine_cs *engine,
+ struct drm_i915_error_engine *ee)
{
+ struct drm_i915_private *dev_priv = engine->i915;
+
if (INTEL_GEN(dev_priv) >= 6) {
- ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
- ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
+ ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
+ ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
if (INTEL_GEN(dev_priv) >= 8)
- gen8_record_semaphore_state(dev_priv, error, engine,
- ering);
+ gen8_record_semaphore_state(error, engine, ee);
else
- gen6_record_semaphore_state(dev_priv, engine, ering);
+ gen6_record_semaphore_state(engine, ee);
}
if (INTEL_GEN(dev_priv) >= 4) {
- ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
- ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
- ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
- ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
- ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
- ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
+ ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
+ ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
+ ee->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
+ ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
+ ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
if (INTEL_GEN(dev_priv) >= 8) {
- ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
- ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
+ ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
+ ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
}
- ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
+ ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
} else {
- ering->faddr = I915_READ(DMA_FADD_I8XX);
- ering->ipeir = I915_READ(IPEIR);
- ering->ipehr = I915_READ(IPEHR);
- ering->instdone = I915_READ(GEN2_INSTDONE);
+ ee->faddr = I915_READ(DMA_FADD_I8XX);
+ ee->ipeir = I915_READ(IPEIR);
+ ee->ipehr = I915_READ(IPEHR);
+ ee->instdone = I915_READ(GEN2_INSTDONE);
}
- ering->waiting = intel_engine_has_waiter(engine);
- ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
- ering->acthd = intel_ring_get_active_head(engine);
- ering->seqno = intel_engine_get_seqno(engine);
- ering->last_seqno = engine->last_submitted_seqno;
- ering->start = I915_READ_START(engine);
- ering->head = I915_READ_HEAD(engine);
- ering->tail = I915_READ_TAIL(engine);
- ering->ctl = I915_READ_CTL(engine);
+ ee->waiting = intel_engine_has_waiter(engine);
+ ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
+ ee->acthd = intel_ring_get_active_head(engine);
+ ee->seqno = intel_engine_get_seqno(engine);
+ ee->last_seqno = engine->last_submitted_seqno;
+ ee->start = I915_READ_START(engine);
+ ee->head = I915_READ_HEAD(engine);
+ ee->tail = I915_READ_TAIL(engine);
+ ee->ctl = I915_READ_CTL(engine);
if (I915_NEED_GFX_HWS(dev_priv)) {
i915_reg_t mmio;
@@ -1017,29 +1015,29 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
mmio = RING_HWS_PGA(engine->mmio_base);
}
- ering->hws = I915_READ(mmio);
+ ee->hws = I915_READ(mmio);
}
- ering->hangcheck_score = engine->hangcheck.score;
- ering->hangcheck_action = engine->hangcheck.action;
+ ee->hangcheck_score = engine->hangcheck.score;
+ ee->hangcheck_action = engine->hangcheck.action;
if (USES_PPGTT(dev_priv)) {
int i;
- ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
+ ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
if (IS_GEN6(dev_priv))
- ering->vm_info.pp_dir_base =
+ ee->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE_READ(engine));
else if (IS_GEN7(dev_priv))
- ering->vm_info.pp_dir_base =
+ ee->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE(engine));
else if (INTEL_GEN(dev_priv) >= 8)
for (i = 0; i < 4; i++) {
- ering->vm_info.pdp[i] =
+ ee->vm_info.pdp[i] =
I915_READ(GEN8_RING_PDP_UDW(engine, i));
- ering->vm_info.pdp[i] <<= 32;
- ering->vm_info.pdp[i] |=
+ ee->vm_info.pdp[i] <<= 32;
+ ee->vm_info.pdp[i] |=
I915_READ(GEN8_RING_PDP_LDW(engine, i));
}
}
@@ -1048,7 +1046,7 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
static void i915_gem_record_active_context(struct intel_engine_cs *engine,
struct drm_i915_error_state *error,
- struct drm_i915_error_ring *ering)
+ struct drm_i915_error_engine *ee)
{
struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_gem_object *obj;
@@ -1062,7 +1060,7 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
continue;
if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
- ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
+ ee->ctx = i915_error_ggtt_object_create(dev_priv, obj);
break;
}
}
@@ -1075,18 +1073,26 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
struct drm_i915_gem_request *request;
int i, count;
+ if (dev_priv->semaphore_obj) {
+ error->semaphore_obj =
+ i915_error_ggtt_object_create(dev_priv,
+ dev_priv->semaphore_obj);
+ }
+
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct intel_engine_cs *engine = &dev_priv->engine[i];
+ struct drm_i915_error_engine *ee = &error->engine[i];
- error->ring[i].pid = -1;
+ ee->pid = -1;
+ ee->engine_id = -1;
if (!intel_engine_initialized(engine))
continue;
- error->ring[i].valid = true;
+ ee->engine_id = i;
- i915_record_ring_state(dev_priv, error, engine, &error->ring[i]);
- engine_record_waiters(engine, &error->ring[i]);
+ error_record_engine_registers(error, engine, ee);
+ error_record_engine_waiters(engine, ee);
request = i915_gem_find_active_request(engine);
if (request) {
@@ -1100,13 +1106,13 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
* as the simplest method to avoid being overwritten
* by userspace.
*/
- error->ring[i].batchbuffer =
+ ee->batchbuffer =
i915_error_object_create(dev_priv,
request->batch_obj,
vm);
if (HAS_BROKEN_CS_TLB(dev_priv))
- error->ring[i].wa_batchbuffer =
+ ee->wa_batchbuffer =
i915_error_ggtt_object_create(dev_priv,
engine->scratch.obj);
@@ -1116,8 +1122,8 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
rcu_read_lock();
task = pid_task(request->pid, PIDTYPE_PID);
if (task) {
- strcpy(error->ring[i].comm, task->comm);
- error->ring[i].pid = task->pid;
+ strcpy(ee->comm, task->comm);
+ ee->pid = task->pid;
}
rcu_read_unlock();
}
@@ -1126,35 +1132,34 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
rb = request->ringbuf;
- error->ring[i].cpu_ring_head = rb->head;
- error->ring[i].cpu_ring_tail = rb->tail;
- error->ring[i].ringbuffer =
+ ee->cpu_ring_head = rb->head;
+ ee->cpu_ring_tail = rb->tail;
+ ee->ringbuffer =
i915_error_ggtt_object_create(dev_priv,
rb->obj);
}
- error->ring[i].hws_page =
+ ee->hws_page =
i915_error_ggtt_object_create(dev_priv,
engine->status_page.obj);
if (engine->wa_ctx.obj) {
- error->ring[i].wa_ctx =
+ ee->wa_ctx =
i915_error_ggtt_object_create(dev_priv,
engine->wa_ctx.obj);
}
- i915_gem_record_active_context(engine, error, &error->ring[i]);
+ i915_gem_record_active_context(engine, error, ee);
count = 0;
list_for_each_entry(request, &engine->request_list, list)
count++;
- error->ring[i].num_requests = count;
- error->ring[i].requests =
- kcalloc(count, sizeof(*error->ring[i].requests),
- GFP_ATOMIC);
- if (error->ring[i].requests == NULL) {
- error->ring[i].num_requests = 0;
+ ee->num_requests = count;
+ ee->requests =
+ kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
+ if (!ee->requests) {
+ ee->num_requests = 0;
continue;
}
@@ -1162,7 +1167,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
list_for_each_entry(request, &engine->request_list, list) {
struct drm_i915_error_request *erq;
- if (count >= error->ring[i].num_requests) {
+ if (count >= ee->num_requests) {
/*
* If the ring request list was changed in
* between the point where the error request
@@ -1181,7 +1186,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
break;
}
- erq = &error->ring[i].requests[count++];
+ erq = &ee->requests[count++];
erq->seqno = request->fence.seqno;
erq->jiffies = request->emitted_jiffies;
erq->tail = request->postfix;
@@ -1352,20 +1357,20 @@ static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
const char *error_msg)
{
u32 ecode;
- int ring_id = -1, len;
+ int engine_id = -1, len;
- ecode = i915_error_generate_code(dev_priv, error, &ring_id);
+ ecode = i915_error_generate_code(dev_priv, error, &engine_id);
len = scnprintf(error->error_msg, sizeof(error->error_msg),
"GPU HANG: ecode %d:%d:0x%08x",
- INTEL_GEN(dev_priv), ring_id, ecode);
+ INTEL_GEN(dev_priv), engine_id, ecode);
- if (ring_id != -1 && error->ring[ring_id].pid != -1)
+ if (engine_id != -1 && error->engine[engine_id].pid != -1)
len += scnprintf(error->error_msg + len,
sizeof(error->error_msg) - len,
", in %s [%d]",
- error->ring[ring_id].comm,
- error->ring[ring_id].pid);
+ error->engine[engine_id].comm,
+ error->engine[engine_id].pid);
scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
", reason: %s, action: %s",
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 124+ messages in thread
* ✗ Ro.CI.BAT: failure for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() (rev2)
2016-07-25 17:31 Fix the vma leak Chris Wilson
` (55 preceding siblings ...)
2016-07-26 5:18 ` ✗ Ro.CI.BAT: warning for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Patchwork
@ 2016-07-26 10:48 ` Patchwork
56 siblings, 0 replies; 124+ messages in thread
From: Patchwork @ 2016-07-26 10:48 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() (rev2)
URL : https://patchwork.freedesktop.org/series/10246/
State : failure
== Summary ==
Applying: drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
Applying: drm/i915: Prefer list_first_entry_or_null
Applying: drm/i915: Only clear the client pointer when tearing down the file
Applying: drm/i915: Only drop the batch-pool's object reference
Applying: drm/i915/cmdparser: Remove stray intel_engine_cs *ring
Applying: drm/i915: Use engine to refer to the user's BSD intel_engine_cs
Applying: drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
Applying: drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
Applying: drm/i915: Update a couple of hangcheck comments to talk about engines
Applying: drm/i915: Unify intel_logical_ring_emit and intel_ring_emit
Applying: drm/i915: Rename request->ringbuf to request->ring
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_gpu_error.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_gpu_error.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gpu_error.c
error: Failed to merge in the changes.
Patch failed at 0011 drm/i915: Rename request->ringbuf to request->ring
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH v2] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
2016-07-26 10:21 ` [PATCH v2] " Chris Wilson
@ 2016-07-26 12:35 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 12:35 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ti, 2016-07-26 at 11:21 +0100, Chris Wilson wrote:
> Inside the error capture itself, we refer to not only the hardware
> engine, its ringbuffer but also the capture state. Finding clear names
> for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
> compromise we keep using ering for the error capture.
>
> v2: Use 'ee' locals for struct drm_i915_error_engine
Assuming this is the change, looks good now;
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-chris@chris-wilson.co.uk
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 403 +++++++++++++++++-----------------
> 2 files changed, 208 insertions(+), 203 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 97f827979a66..65ada5d2f88c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -512,8 +512,8 @@ struct drm_i915_error_state {
> struct intel_display_error_state *display;
> struct drm_i915_error_object *semaphore_obj;
>
> - struct drm_i915_error_ring {
> - bool valid;
> + struct drm_i915_error_engine {
> + int engine_id;
> /* Software tracked state */
> bool waiting;
> int num_waiters;
> @@ -578,7 +578,7 @@ struct drm_i915_error_state {
>
> pid_t pid;
> char comm[TASK_COMM_LEN];
> - } ring[I915_NUM_ENGINES];
> + } engine[I915_NUM_ENGINES];
>
> struct drm_i915_error_buffer {
> u32 size;
> @@ -593,7 +593,7 @@ struct drm_i915_error_state {
> u32 dirty:1;
> u32 purgeable:1;
> u32 userptr:1;
> - s32 ring:4;
> + s32 engine:4;
> u32 cache_level:3;
> } **active_bo, **pinned_bo;
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 4d39c7284605..bc4a3ebc2662 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -30,9 +30,9 @@
> #include
> #include "i915_drv.h"
>
> -static const char *ring_str(int ring)
> +static const char *engine_str(int engine)
> {
> - switch (ring) {
> + switch (engine) {
> case RCS: return "render";
> case VCS: return "bsd";
> case BCS: return "blt";
> @@ -207,8 +207,8 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
> err_puts(m, dirty_flag(err->dirty));
> err_puts(m, purgeable_flag(err->purgeable));
> err_puts(m, err->userptr ? " userptr" : "");
> - err_puts(m, err->ring != -1 ? " " : "");
> - err_puts(m, ring_str(err->ring));
> + err_puts(m, err->engine != -1 ? " " : "");
> + err_puts(m, engine_str(err->engine));
> err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
>
> if (err->name)
> @@ -239,70 +239,65 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
> return "unknown";
> }
>
> -static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
> - struct drm_device *dev,
> - struct drm_i915_error_state *error,
> - int ring_idx)
> +static void error_print_engine(struct drm_i915_error_state_buf *m,
> + struct drm_i915_error_engine *ee)
> {
> - struct drm_i915_error_ring *ring = &error->ring[ring_idx];
> -
> - if (!ring->valid)
> - return;
> -
> - err_printf(m, "%s command stream:\n", ring_str(ring_idx));
> - err_printf(m, " START: 0x%08x\n", ring->start);
> - err_printf(m, " HEAD: 0x%08x\n", ring->head);
> - err_printf(m, " TAIL: 0x%08x\n", ring->tail);
> - err_printf(m, " CTL: 0x%08x\n", ring->ctl);
> - err_printf(m, " HWS: 0x%08x\n", ring->hws);
> - err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
> - err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
> - err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
> - err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
> - if (INTEL_INFO(dev)->gen >= 4) {
> - err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
> - err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
> - err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
> + err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
> + err_printf(m, " START: 0x%08x\n", ee->start);
> + err_printf(m, " HEAD: 0x%08x\n", ee->head);
> + err_printf(m, " TAIL: 0x%08x\n", ee->tail);
> + err_printf(m, " CTL: 0x%08x\n", ee->ctl);
> + err_printf(m, " HWS: 0x%08x\n", ee->hws);
> + err_printf(m, " ACTHD: 0x%08x %08x\n",
> + (u32)(ee->acthd>>32), (u32)ee->acthd);
> + err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
> + err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
> + err_printf(m, " INSTDONE: 0x%08x\n", ee->instdone);
> + if (INTEL_GEN(m->i915) >= 4) {
> + err_printf(m, " BBADDR: 0x%08x %08x\n",
> + (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
> + err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
> + err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
> }
> - err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
> - err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
> - lower_32_bits(ring->faddr));
> - if (INTEL_INFO(dev)->gen >= 6) {
> - err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
> - err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
> + err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
> + err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
> + lower_32_bits(ee->faddr));
> + if (INTEL_GEN(m->i915) >= 6) {
> + err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
> + err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
> err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
> - ring->semaphore_mboxes[0],
> - ring->semaphore_seqno[0]);
> + ee->semaphore_mboxes[0],
> + ee->semaphore_seqno[0]);
> err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
> - ring->semaphore_mboxes[1],
> - ring->semaphore_seqno[1]);
> - if (HAS_VEBOX(dev)) {
> + ee->semaphore_mboxes[1],
> + ee->semaphore_seqno[1]);
> + if (HAS_VEBOX(m->i915)) {
> err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
> - ring->semaphore_mboxes[2],
> - ring->semaphore_seqno[2]);
> + ee->semaphore_mboxes[2],
> + ee->semaphore_seqno[2]);
> }
> }
> - if (USES_PPGTT(dev)) {
> - err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
> + if (USES_PPGTT(m->i915)) {
> + err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
>
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(m->i915) >= 8) {
> int i;
> for (i = 0; i < 4; i++)
> err_printf(m, " PDP%d: 0x%016llx\n",
> - i, ring->vm_info.pdp[i]);
> + i, ee->vm_info.pdp[i]);
> } else {
> err_printf(m, " PP_DIR_BASE: 0x%08x\n",
> - ring->vm_info.pp_dir_base);
> + ee->vm_info.pp_dir_base);
> }
> }
> - err_printf(m, " seqno: 0x%08x\n", ring->seqno);
> - err_printf(m, " last_seqno: 0x%08x\n", ring->last_seqno);
> - err_printf(m, " waiting: %s\n", yesno(ring->waiting));
> - err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
> - err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
> + err_printf(m, " seqno: 0x%08x\n", ee->seqno);
> + err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
> + err_printf(m, " waiting: %s\n", yesno(ee->waiting));
> + err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
> + err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
> err_printf(m, " hangcheck: %s [%d]\n",
> - hangcheck_action_to_str(ring->hangcheck_action),
> - ring->hangcheck_score);
> + hangcheck_action_to_str(ee->hangcheck_action),
> + ee->hangcheck_score);
> }
>
> void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
> @@ -348,17 +343,17 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> error->time.tv_usec);
> err_printf(m, "Kernel: " UTS_RELEASE "\n");
> max_hangcheck_score = 0;
> - for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
> - if (error->ring[i].hangcheck_score > max_hangcheck_score)
> - max_hangcheck_score = error->ring[i].hangcheck_score;
> + for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> + if (error->engine[i].hangcheck_score > max_hangcheck_score)
> + max_hangcheck_score = error->engine[i].hangcheck_score;
> }
> - for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
> - if (error->ring[i].hangcheck_score == max_hangcheck_score &&
> - error->ring[i].pid != -1) {
> + for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> + if (error->engine[i].hangcheck_score == max_hangcheck_score &&
> + error->engine[i].pid != -1) {
> err_printf(m, "Active process (on ring %s): %s [%d]\n",
> - ring_str(i),
> - error->ring[i].comm,
> - error->ring[i].pid);
> + engine_str(i),
> + error->engine[i].comm,
> + error->engine[i].pid);
> }
> }
> err_printf(m, "Reset count: %u\n", error->reset_count);
> @@ -414,8 +409,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> if (IS_GEN7(dev))
> err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
>
> - for (i = 0; i < ARRAY_SIZE(error->ring); i++)
> - i915_ring_error_state(m, dev, error, i);
> + for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> + if (error->engine[i].engine_id != -1)
> + error_print_engine(m, &error->engine[i]);
> + }
>
> for (i = 0; i < error->vm_count; i++) {
> err_printf(m, "vm[%d]\n", i);
> @@ -429,21 +426,23 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> error->pinned_bo_count[i]);
> }
>
> - for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
> - obj = error->ring[i].batchbuffer;
> + for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> + struct drm_i915_error_engine *ee = &error->engine[i];
> +
> + obj = ee->batchbuffer;
> if (obj) {
> err_puts(m, dev_priv->engine[i].name);
> - if (error->ring[i].pid != -1)
> + if (ee->pid != -1)
> err_printf(m, " (submitted by %s [%d])",
> - error->ring[i].comm,
> - error->ring[i].pid);
> + ee->comm,
> + ee->pid);
> err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
> upper_32_bits(obj->gtt_offset),
> lower_32_bits(obj->gtt_offset));
> print_error_obj(m, obj);
> }
>
> - obj = error->ring[i].wa_batchbuffer;
> + obj = ee->wa_batchbuffer;
> if (obj) {
> err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
> dev_priv->engine[i].name,
> @@ -451,38 +450,38 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> print_error_obj(m, obj);
> }
>
> - if (error->ring[i].num_requests) {
> + if (ee->num_requests) {
> err_printf(m, "%s --- %d requests\n",
> dev_priv->engine[i].name,
> - error->ring[i].num_requests);
> - for (j = 0; j < error->ring[i].num_requests; j++) {
> + ee->num_requests);
> + for (j = 0; j < ee->num_requests; j++) {
> err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
> - error->ring[i].requests[j].seqno,
> - error->ring[i].requests[j].jiffies,
> - error->ring[i].requests[j].tail);
> + ee->requests[j].seqno,
> + ee->requests[j].jiffies,
> + ee->requests[j].tail);
> }
> }
>
> - if (error->ring[i].num_waiters) {
> + if (ee->num_waiters) {
> err_printf(m, "%s --- %d waiters\n",
> dev_priv->engine[i].name,
> - error->ring[i].num_waiters);
> - for (j = 0; j < error->ring[i].num_waiters; j++) {
> + ee->num_waiters);
> + for (j = 0; j < ee->num_waiters; j++) {
> err_printf(m, " seqno 0x%08x for %s [%d]\n",
> - error->ring[i].waiters[j].seqno,
> - error->ring[i].waiters[j].comm,
> - error->ring[i].waiters[j].pid);
> + ee->waiters[j].seqno,
> + ee->waiters[j].comm,
> + ee->waiters[j].pid);
> }
> }
>
> - if ((obj = error->ring[i].ringbuffer)) {
> + if ((obj = ee->ringbuffer)) {
> err_printf(m, "%s --- ringbuffer = 0x%08x\n",
> dev_priv->engine[i].name,
> lower_32_bits(obj->gtt_offset));
> print_error_obj(m, obj);
> }
>
> - if ((obj = error->ring[i].hws_page)) {
> + if ((obj = ee->hws_page)) {
> u64 hws_offset = obj->gtt_offset;
> u32 *hws_page = &obj->pages[0][0];
>
> @@ -504,7 +503,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> }
> }
>
> - obj = error->ring[i].wa_ctx;
> + obj = ee->wa_ctx;
> if (obj) {
> u64 wa_ctx_offset = obj->gtt_offset;
> u32 *wa_ctx_page = &obj->pages[0][0];
> @@ -526,7 +525,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> }
> }
>
> - if ((obj = error->ring[i].ctx)) {
> + if ((obj = ee->ctx)) {
> err_printf(m, "%s --- HW Context = 0x%08x\n",
> dev_priv->engine[i].name,
> lower_32_bits(obj->gtt_offset));
> @@ -611,15 +610,18 @@ static void i915_error_state_free(struct kref *error_ref)
> typeof(*error), ref);
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
> - i915_error_object_free(error->ring[i].batchbuffer);
> - i915_error_object_free(error->ring[i].wa_batchbuffer);
> - i915_error_object_free(error->ring[i].ringbuffer);
> - i915_error_object_free(error->ring[i].hws_page);
> - i915_error_object_free(error->ring[i].ctx);
> - i915_error_object_free(error->ring[i].wa_ctx);
> - kfree(error->ring[i].requests);
> - kfree(error->ring[i].waiters);
> + for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> + struct drm_i915_error_engine *ee = &error->engine[i];
> +
> + i915_error_object_free(ee->batchbuffer);
> + i915_error_object_free(ee->wa_batchbuffer);
> + i915_error_object_free(ee->ringbuffer);
> + i915_error_object_free(ee->hws_page);
> + i915_error_object_free(ee->ctx);
> + i915_error_object_free(ee->wa_ctx);
> +
> + kfree(ee->requests);
> + kfree(ee->waiters);
> }
>
> i915_error_object_free(error->semaphore_obj);
> @@ -762,8 +764,8 @@ static void capture_bo(struct drm_i915_error_buffer *err,
> err->dirty = obj->dirty;
> err->purgeable = obj->madv != I915_MADV_WILLNEED;
> err->userptr = obj->userptr.mm != NULL;
> - err->ring = obj->last_write_req ?
> - i915_gem_request_get_engine(obj->last_write_req)->id : -1;
> + err->engine = obj->last_write_req ?
> + i915_gem_request_get_engine(obj->last_write_req)->id : -1;
> err->cache_level = obj->cache_level;
> }
>
> @@ -815,7 +817,7 @@ static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
> */
> static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error,
> - int *ring_id)
> + int *engine_id)
> {
> uint32_t error_code = 0;
> int i;
> @@ -826,11 +828,11 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
> * strictly a client bug. Use instdone to differentiate those some.
> */
> for (i = 0; i < I915_NUM_ENGINES; i++) {
> - if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
> - if (ring_id)
> - *ring_id = i;
> + if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
> + if (engine_id)
> + *engine_id = i;
>
> - return error->ring[i].ipehr ^ error->ring[i].instdone;
> + return error->engine[i].ipehr ^ error->engine[i].instdone;
> }
> }
>
> @@ -855,21 +857,16 @@ static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
> }
>
>
> -static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
> - struct drm_i915_error_state *error,
> +static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
> struct intel_engine_cs *engine,
> - struct drm_i915_error_ring *ering)
> + struct drm_i915_error_engine *ee)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> struct intel_engine_cs *to;
> enum intel_engine_id id;
>
> - if (!i915.semaphores)
> - return;
> -
> if (!error->semaphore_obj)
> - error->semaphore_obj =
> - i915_error_ggtt_object_create(dev_priv,
> - dev_priv->semaphore_obj);
> + return;
>
> for_each_engine_id(to, dev_priv, id) {
> int idx;
> @@ -879,42 +876,43 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
> if (engine == to)
> continue;
>
> - signal_offset = (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1))
> - / 4;
> + signal_offset =
> + (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
> tmp = error->semaphore_obj->pages[0];
> idx = intel_ring_sync_index(engine, to);
>
> - ering->semaphore_mboxes[idx] = tmp[signal_offset];
> - ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
> + ee->semaphore_mboxes[idx] = tmp[signal_offset];
> + ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
> }
> }
>
> -static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
> - struct intel_engine_cs *engine,
> - struct drm_i915_error_ring *ering)
> +static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
> + struct drm_i915_error_engine *ee)
> {
> - ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
> - ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
> - ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
> - ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
> + struct drm_i915_private *dev_priv = engine->i915;
> +
> + ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
> + ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
> + ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
> + ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
>
> if (HAS_VEBOX(dev_priv)) {
> - ering->semaphore_mboxes[2] =
> + ee->semaphore_mboxes[2] =
> I915_READ(RING_SYNC_2(engine->mmio_base));
> - ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
> + ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
> }
> }
>
> -static void engine_record_waiters(struct intel_engine_cs *engine,
> - struct drm_i915_error_ring *ering)
> +static void error_record_engine_waiters(struct intel_engine_cs *engine,
> + struct drm_i915_error_engine *ee)
> {
> struct intel_breadcrumbs *b = &engine->breadcrumbs;
> struct drm_i915_error_waiter *waiter;
> struct rb_node *rb;
> int count;
>
> - ering->num_waiters = 0;
> - ering->waiters = NULL;
> + ee->num_waiters = 0;
> + ee->waiters = NULL;
>
> spin_lock(&b->lock);
> count = 0;
> @@ -930,7 +928,7 @@ static void engine_record_waiters(struct intel_engine_cs *engine,
> if (!waiter)
> return;
>
> - ering->waiters = waiter;
> + ee->waiters = waiter;
>
> spin_lock(&b->lock);
> for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
> @@ -941,55 +939,55 @@ static void engine_record_waiters(struct intel_engine_cs *engine,
> waiter->seqno = w->seqno;
> waiter++;
>
> - if (++ering->num_waiters == count)
> + if (++ee->num_waiters == count)
> break;
> }
> spin_unlock(&b->lock);
> }
>
> -static void i915_record_ring_state(struct drm_i915_private *dev_priv,
> - struct drm_i915_error_state *error,
> - struct intel_engine_cs *engine,
> - struct drm_i915_error_ring *ering)
> +static void error_record_engine_registers(struct drm_i915_error_state *error,
> + struct intel_engine_cs *engine,
> + struct drm_i915_error_engine *ee)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> +
> if (INTEL_GEN(dev_priv) >= 6) {
> - ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
> - ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
> + ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
> + ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
> if (INTEL_GEN(dev_priv) >= 8)
> - gen8_record_semaphore_state(dev_priv, error, engine,
> - ering);
> + gen8_record_semaphore_state(error, engine, ee);
> else
> - gen6_record_semaphore_state(dev_priv, engine, ering);
> + gen6_record_semaphore_state(engine, ee);
> }
>
> if (INTEL_GEN(dev_priv) >= 4) {
> - ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
> - ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
> - ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
> - ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
> - ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
> - ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
> + ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
> + ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
> + ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
> + ee->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
> + ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
> + ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
> if (INTEL_GEN(dev_priv) >= 8) {
> - ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
> - ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
> + ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
> + ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
> }
> - ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
> + ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
> } else {
> - ering->faddr = I915_READ(DMA_FADD_I8XX);
> - ering->ipeir = I915_READ(IPEIR);
> - ering->ipehr = I915_READ(IPEHR);
> - ering->instdone = I915_READ(GEN2_INSTDONE);
> + ee->faddr = I915_READ(DMA_FADD_I8XX);
> + ee->ipeir = I915_READ(IPEIR);
> + ee->ipehr = I915_READ(IPEHR);
> + ee->instdone = I915_READ(GEN2_INSTDONE);
> }
>
> - ering->waiting = intel_engine_has_waiter(engine);
> - ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
> - ering->acthd = intel_ring_get_active_head(engine);
> - ering->seqno = intel_engine_get_seqno(engine);
> - ering->last_seqno = engine->last_submitted_seqno;
> - ering->start = I915_READ_START(engine);
> - ering->head = I915_READ_HEAD(engine);
> - ering->tail = I915_READ_TAIL(engine);
> - ering->ctl = I915_READ_CTL(engine);
> + ee->waiting = intel_engine_has_waiter(engine);
> + ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
> + ee->acthd = intel_ring_get_active_head(engine);
> + ee->seqno = intel_engine_get_seqno(engine);
> + ee->last_seqno = engine->last_submitted_seqno;
> + ee->start = I915_READ_START(engine);
> + ee->head = I915_READ_HEAD(engine);
> + ee->tail = I915_READ_TAIL(engine);
> + ee->ctl = I915_READ_CTL(engine);
>
> if (I915_NEED_GFX_HWS(dev_priv)) {
> i915_reg_t mmio;
> @@ -1017,29 +1015,29 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
> mmio = RING_HWS_PGA(engine->mmio_base);
> }
>
> - ering->hws = I915_READ(mmio);
> + ee->hws = I915_READ(mmio);
> }
>
> - ering->hangcheck_score = engine->hangcheck.score;
> - ering->hangcheck_action = engine->hangcheck.action;
> + ee->hangcheck_score = engine->hangcheck.score;
> + ee->hangcheck_action = engine->hangcheck.action;
>
> if (USES_PPGTT(dev_priv)) {
> int i;
>
> - ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
> + ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
>
> if (IS_GEN6(dev_priv))
> - ering->vm_info.pp_dir_base =
> + ee->vm_info.pp_dir_base =
> I915_READ(RING_PP_DIR_BASE_READ(engine));
> else if (IS_GEN7(dev_priv))
> - ering->vm_info.pp_dir_base =
> + ee->vm_info.pp_dir_base =
> I915_READ(RING_PP_DIR_BASE(engine));
> else if (INTEL_GEN(dev_priv) >= 8)
> for (i = 0; i < 4; i++) {
> - ering->vm_info.pdp[i] =
> + ee->vm_info.pdp[i] =
> I915_READ(GEN8_RING_PDP_UDW(engine, i));
> - ering->vm_info.pdp[i] <<= 32;
> - ering->vm_info.pdp[i] |=
> + ee->vm_info.pdp[i] <<= 32;
> + ee->vm_info.pdp[i] |=
> I915_READ(GEN8_RING_PDP_LDW(engine, i));
> }
> }
> @@ -1048,7 +1046,7 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
>
> static void i915_gem_record_active_context(struct intel_engine_cs *engine,
> struct drm_i915_error_state *error,
> - struct drm_i915_error_ring *ering)
> + struct drm_i915_error_engine *ee)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> struct drm_i915_gem_object *obj;
> @@ -1062,7 +1060,7 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
> continue;
>
> if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
> - ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
> + ee->ctx = i915_error_ggtt_object_create(dev_priv, obj);
> break;
> }
> }
> @@ -1075,18 +1073,26 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> struct drm_i915_gem_request *request;
> int i, count;
>
> + if (dev_priv->semaphore_obj) {
> + error->semaphore_obj =
> + i915_error_ggtt_object_create(dev_priv,
> + dev_priv->semaphore_obj);
> + }
> +
> for (i = 0; i < I915_NUM_ENGINES; i++) {
> struct intel_engine_cs *engine = &dev_priv->engine[i];
> + struct drm_i915_error_engine *ee = &error->engine[i];
>
> - error->ring[i].pid = -1;
> + ee->pid = -1;
> + ee->engine_id = -1;
>
> if (!intel_engine_initialized(engine))
> continue;
>
> - error->ring[i].valid = true;
> + ee->engine_id = i;
>
> - i915_record_ring_state(dev_priv, error, engine, &error->ring[i]);
> - engine_record_waiters(engine, &error->ring[i]);
> + error_record_engine_registers(error, engine, ee);
> + error_record_engine_waiters(engine, ee);
>
> request = i915_gem_find_active_request(engine);
> if (request) {
> @@ -1100,13 +1106,13 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> * as the simplest method to avoid being overwritten
> * by userspace.
> */
> - error->ring[i].batchbuffer =
> + ee->batchbuffer =
> i915_error_object_create(dev_priv,
> request->batch_obj,
> vm);
>
> if (HAS_BROKEN_CS_TLB(dev_priv))
> - error->ring[i].wa_batchbuffer =
> + ee->wa_batchbuffer =
> i915_error_ggtt_object_create(dev_priv,
> engine->scratch.obj);
>
> @@ -1116,8 +1122,8 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> rcu_read_lock();
> task = pid_task(request->pid, PIDTYPE_PID);
> if (task) {
> - strcpy(error->ring[i].comm, task->comm);
> - error->ring[i].pid = task->pid;
> + strcpy(ee->comm, task->comm);
> + ee->pid = task->pid;
> }
> rcu_read_unlock();
> }
> @@ -1126,35 +1132,34 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
>
> rb = request->ringbuf;
> - error->ring[i].cpu_ring_head = rb->head;
> - error->ring[i].cpu_ring_tail = rb->tail;
> - error->ring[i].ringbuffer =
> + ee->cpu_ring_head = rb->head;
> + ee->cpu_ring_tail = rb->tail;
> + ee->ringbuffer =
> i915_error_ggtt_object_create(dev_priv,
> rb->obj);
> }
>
> - error->ring[i].hws_page =
> + ee->hws_page =
> i915_error_ggtt_object_create(dev_priv,
> engine->status_page.obj);
>
> if (engine->wa_ctx.obj) {
> - error->ring[i].wa_ctx =
> + ee->wa_ctx =
> i915_error_ggtt_object_create(dev_priv,
> engine->wa_ctx.obj);
> }
>
> - i915_gem_record_active_context(engine, error, &error->ring[i]);
> + i915_gem_record_active_context(engine, error, ee);
>
> count = 0;
> list_for_each_entry(request, &engine->request_list, list)
> count++;
>
> - error->ring[i].num_requests = count;
> - error->ring[i].requests =
> - kcalloc(count, sizeof(*error->ring[i].requests),
> - GFP_ATOMIC);
> - if (error->ring[i].requests == NULL) {
> - error->ring[i].num_requests = 0;
> + ee->num_requests = count;
> + ee->requests =
> + kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
> + if (!ee->requests) {
> + ee->num_requests = 0;
> continue;
> }
>
> @@ -1162,7 +1167,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> list_for_each_entry(request, &engine->request_list, list) {
> struct drm_i915_error_request *erq;
>
> - if (count >= error->ring[i].num_requests) {
> + if (count >= ee->num_requests) {
> /*
> * If the ring request list was changed in
> * between the point where the error request
> @@ -1181,7 +1186,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> break;
> }
>
> - erq = &error->ring[i].requests[count++];
> + erq = &ee->requests[count++];
> erq->seqno = request->fence.seqno;
> erq->jiffies = request->emitted_jiffies;
> erq->tail = request->postfix;
> @@ -1352,20 +1357,20 @@ static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
> const char *error_msg)
> {
> u32 ecode;
> - int ring_id = -1, len;
> + int engine_id = -1, len;
>
> - ecode = i915_error_generate_code(dev_priv, error, &ring_id);
> + ecode = i915_error_generate_code(dev_priv, error, &engine_id);
>
> len = scnprintf(error->error_msg, sizeof(error->error_msg),
> "GPU HANG: ecode %d:%d:0x%08x",
> - INTEL_GEN(dev_priv), ring_id, ecode);
> + INTEL_GEN(dev_priv), engine_id, ecode);
>
> - if (ring_id != -1 && error->ring[ring_id].pid != -1)
> + if (engine_id != -1 && error->engine[engine_id].pid != -1)
> len += scnprintf(error->error_msg + len,
> sizeof(error->error_msg) - len,
> ", in %s [%d]",
> - error->ring[ring_id].comm,
> - error->ring[ring_id].pid);
> + error->engine[engine_id].comm,
> + error->engine[engine_id].pid);
>
> scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
> ", reason: %s, action: %s",
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 46/55] drm/i915: Move the special case wait-request handling to its one caller
2016-07-25 17:32 ` [PATCH 46/55] drm/i915: Move the special case wait-request handling to its one caller Chris Wilson
@ 2016-07-26 12:39 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 12:39 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_request.c | 25 -------------------------
> drivers/gpu/drm/i915/i915_gem_request.h | 4 ----
> drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++++++-----
> 3 files changed, 13 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index f1c37b7891cb..2c0c6a37f46a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -716,28 +716,3 @@ complete:
>
> return ret;
> }
> -
> -/**
> - * Waits for a request to be signaled, and cleans up the
> - * request and object lists appropriately for that event.
> - */
> -int i915_wait_request(struct drm_i915_gem_request *req)
> -{
> - int ret;
> -
> - lockdep_assert_held(&req->i915->drm.struct_mutex);
> - GEM_BUG_ON(list_empty(&req->link));
> -
> - ret = __i915_wait_request(req,
> - req->i915->mm.interruptible,
> - NULL,
> - NULL);
> - if (ret)
> - return ret;
> -
> - /* If the GPU hung, we want to keep the requests to find the guilty. */
> - if (!i915_reset_in_progress(&req->i915->gpu_error))
> - i915_gem_request_retire_upto(req);
> -
> - return 0;
> -}
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
> index b1ee37896feb..f4aab8e60c9e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.h
> +++ b/drivers/gpu/drm/i915/i915_gem_request.h
> @@ -220,10 +220,6 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> struct intel_rps_client *rps)
> __attribute__((nonnull(1)));
>
> -int __must_check
> -i915_wait_request(struct drm_i915_gem_request *req)
> - __attribute__((nonnull));
> -
> static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
>
> /**
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index af76869c8db2..507576ef8077 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2284,6 +2284,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> {
> struct intel_ring *ring = req->ring;
> struct drm_i915_gem_request *target;
> + int ret;
>
> intel_ring_update_space(ring);
> if (ring->space >= bytes)
> @@ -2313,7 +2314,18 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> if (WARN_ON(&target->ring_link == &ring->request_list))
> return -ENOSPC;
>
> - return i915_wait_request(target);
> + ret = __i915_wait_request(target, true, NULL, NULL);
> + if (ret)
> + return ret;
> +
> + if (i915_reset_in_progress(&target->i915->gpu_error))
> + return -EAGAIN;
> +
> + i915_gem_request_retire_upto(target);
> +
> + intel_ring_update_space(ring);
> + GEM_BUG_ON(ring->space < bytes);
> + return 0;
> }
>
> int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
> @@ -2351,10 +2363,6 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
> int ret = wait_for_space(req, wait_bytes);
> if (unlikely(ret))
> return ret;
> -
> - intel_ring_update_space(ring);
> - if (unlikely(ring->space < wait_bytes))
> - return -EAGAIN;
> }
>
> if (unlikely(need_wrap)) {
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine
2016-07-25 17:32 ` [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine Chris Wilson
@ 2016-07-26 12:40 ` Joonas Lahtinen
2016-07-26 13:11 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 12:40 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> If the user floods the GPU with so many requests that the engine stalls
> waiting for free space, don't automatically promote the GPU to maximum
> frequencies. If the GPU really is saturated with work, it will migrate
> to high clocks by itself, otherwise it is merely a user flooding us with
> busy-work.
>
Should this even come with Fixes: ?
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 507576ef8077..90e46d1b04e2 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2314,7 +2314,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> if (WARN_ON(&target->ring_link == &ring->request_list))
> return -ENOSPC;
>
> - ret = __i915_wait_request(target, true, NULL, NULL);
> + ret = __i915_wait_request(target, true, NULL, NO_WAITBOOST);
> if (ret)
> return ret;
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 48/55] drm/i915: s/__i915_wait_request/i915_wait_request/
2016-07-25 17:32 ` [PATCH 48/55] drm/i915: s/__i915_wait_request/i915_wait_request/ Chris Wilson
@ 2016-07-26 12:42 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 12:42 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> There is onl one wait on request function now, so drop the "expert"
> indication of leading __.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Simple rename.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 18 +++++++++---------
> drivers/gpu/drm/i915/i915_gem_request.c | 16 ++++++++--------
> drivers/gpu/drm/i915/i915_gem_request.h | 12 ++++++------
> drivers/gpu/drm/i915/i915_gem_userptr.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 14 +++++++-------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
> 6 files changed, 35 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b9874a99ae04..cc84f00cf883 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1420,7 +1420,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
> mutex_unlock(&dev->struct_mutex);
> ret = 0;
> for (i = 0; ret == 0 && i < n; i++)
> - ret = __i915_wait_request(requests[i], true, NULL, rps);
> + ret = i915_wait_request(requests[i], true, NULL, rps);
> mutex_lock(&dev->struct_mutex);
>
> for (i = 0; i < n; i++)
> @@ -2733,9 +2733,9 @@ out:
>
> for (i = 0; i < n; i++) {
> if (ret == 0)
> - ret = __i915_wait_request(requests[i], true,
> - args->timeout_ns > 0 ? &args->timeout_ns : NULL,
> - to_rps_client(file));
> + ret = i915_wait_request(requests[i], true,
> + args->timeout_ns > 0 ? &args->timeout_ns : NULL,
> + to_rps_client(file));
> i915_gem_request_put(requests[i]);
> }
> return ret;
> @@ -2751,10 +2751,10 @@ __i915_gem_object_sync(struct drm_i915_gem_request *to,
> return 0;
>
> if (!i915.semaphores) {
> - ret = __i915_wait_request(from,
> - from->i915->mm.interruptible,
> - NULL,
> - NO_WAITBOOST);
> + ret = i915_wait_request(from,
> + from->i915->mm.interruptible,
> + NULL,
> + NO_WAITBOOST);
> if (ret)
> return ret;
> } else {
> @@ -3723,7 +3723,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
> if (target == NULL)
> return 0;
>
> - ret = __i915_wait_request(target, true, NULL, NULL);
> + ret = i915_wait_request(target, true, NULL, NULL);
> i915_gem_request_put(target);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 2c0c6a37f46a..1935591a98c1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -70,9 +70,9 @@ static signed long i915_fence_wait(struct fence *fence,
> timeout = NULL;
> }
>
> - ret = __i915_wait_request(to_request(fence),
> - interruptible, timeout,
> - NO_WAITBOOST);
> + ret = i915_wait_request(to_request(fence),
> + interruptible, timeout,
> + NO_WAITBOOST);
> if (ret == -ETIME)
> return 0;
>
> @@ -564,7 +564,7 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req,
> }
>
> /**
> - * __i915_wait_request - wait until execution of request has finished
> + * i915_wait_request - wait until execution of request has finished
> * @req: duh!
> * @interruptible: do an interruptible wait (normally yes)
> * @timeout: in - how long to wait (NULL forever); out - how much time remaining
> @@ -580,10 +580,10 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req,
> * Returns 0 if the request was found within the alloted time. Else returns the
> * errno with remaining time filled in timeout argument.
> */
> -int __i915_wait_request(struct drm_i915_gem_request *req,
> - bool interruptible,
> - s64 *timeout,
> - struct intel_rps_client *rps)
> +int i915_wait_request(struct drm_i915_gem_request *req,
> + bool interruptible,
> + s64 *timeout,
> + struct intel_rps_client *rps)
> {
> int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
> DEFINE_WAIT(reset);
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
> index f4aab8e60c9e..828e304b2f11 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.h
> +++ b/drivers/gpu/drm/i915/i915_gem_request.h
> @@ -214,10 +214,10 @@ struct intel_rps_client;
> #define IS_RPS_CLIENT(p) (!IS_ERR(p))
> #define IS_RPS_USER(p) (!IS_ERR_OR_NULL(p))
>
> -int __i915_wait_request(struct drm_i915_gem_request *req,
> - bool interruptible,
> - s64 *timeout,
> - struct intel_rps_client *rps)
> +int i915_wait_request(struct drm_i915_gem_request *req,
> + bool interruptible,
> + s64 *timeout,
> + struct intel_rps_client *rps)
> __attribute__((nonnull(1)));
>
> static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
> @@ -411,7 +411,7 @@ i915_gem_active_wait(const struct i915_gem_active *active, struct mutex *mutex)
> if (!request)
> return 0;
>
> - return __i915_wait_request(request, true, NULL, NULL);
> + return i915_wait_request(request, true, NULL, NULL);
> }
>
> /**
> @@ -434,7 +434,7 @@ i915_gem_active_retire(struct i915_gem_active *active,
> if (!request)
> return 0;
>
> - ret = __i915_wait_request(request, true, NULL, NULL);
> + ret = i915_wait_request(request, true, NULL, NULL);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
> index e57521dbddc6..651a84ba840c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
> @@ -83,7 +83,7 @@ static void wait_rendering(struct drm_i915_gem_object *obj)
> mutex_unlock(&dev->struct_mutex);
>
> for (i = 0; i < n; i++)
> - __i915_wait_request(requests[i], false, NULL, NULL);
> + i915_wait_request(requests[i], false, NULL, NULL);
>
> mutex_lock(&dev->struct_mutex);
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8ea9d5a301d4..ed2069c56036 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11471,9 +11471,9 @@ static void intel_mmio_flip_work_func(struct work_struct *w)
> struct reservation_object *resv;
>
> if (work->flip_queued_req)
> - WARN_ON(__i915_wait_request(work->flip_queued_req,
> - false, NULL,
> - NO_WAITBOOST));
> + WARN_ON(i915_wait_request(work->flip_queued_req,
> + false, NULL,
> + NO_WAITBOOST));
>
> /* For framebuffer backed by dmabuf, wait for fence */
> resv = i915_gem_object_get_dmabuf_resv(obj);
> @@ -13516,8 +13516,8 @@ static int intel_atomic_prepare_commit(struct drm_device *dev,
> if (!intel_plane_state->wait_req)
> continue;
>
> - ret = __i915_wait_request(intel_plane_state->wait_req,
> - true, NULL, NULL);
> + ret = i915_wait_request(intel_plane_state->wait_req,
> + true, NULL, NULL);
> if (ret) {
> /* Any hang should be swallowed by the wait */
> WARN_ON(ret == -EIO);
> @@ -13629,8 +13629,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
> if (!intel_plane_state->wait_req)
> continue;
>
> - ret = __i915_wait_request(intel_plane_state->wait_req,
> - true, NULL, NULL);
> + ret = i915_wait_request(intel_plane_state->wait_req,
> + true, NULL, NULL);
> /* EIO should be eaten, and we can't get interrupted in the
> * worker, and blocking commits have waited already. */
> WARN_ON(ret);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 90e46d1b04e2..924aba1db22d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2255,9 +2255,9 @@ int intel_engine_idle(struct intel_engine_cs *engine)
> link);
>
> /* Make sure we do not trigger any retires */
> - return __i915_wait_request(req,
> - req->i915->mm.interruptible,
> - NULL, NULL);
> + return i915_wait_request(req,
> + req->i915->mm.interruptible,
> + NULL, NULL);
> }
>
> int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
> @@ -2314,7 +2314,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> if (WARN_ON(&target->ring_link == &ring->request_list))
> return -ENOSPC;
>
> - ret = __i915_wait_request(target, true, NULL, NO_WAITBOOST);
> + ret = i915_wait_request(target, true, NULL, NO_WAITBOOST);
> if (ret)
> return ret;
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 49/55] drm/i915: Double check activity before relocations
2016-07-25 17:32 ` [PATCH 49/55] drm/i915: Double check activity before relocations Chris Wilson
@ 2016-07-26 12:45 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 12:45 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> If the object is active and we need to perform a relocation upon it, we
> need to take the slow relocation path. Before we do, double check the
> active requests to see if they have completed.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index e1dfdbd8fc2e..9778b1bc6336 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -441,6 +441,20 @@ relocate_entry_clflush(struct drm_i915_gem_object *obj,
> return 0;
> }
>
> +static bool object_is_idle(struct drm_i915_gem_object *obj)
> +{
> + unsigned long active = obj->active;
> + int idx;
> +
> + for_each_active(active, idx) {
> + if (!i915_gem_active_is_idle(&obj->last_read[idx],
> + &obj->base.dev->struct_mutex))
> + return false;
> + }
> +
> + return true;
> +}
> +
> static int
> i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
> struct eb_vmas *eb,
> @@ -524,7 +538,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
> }
>
> /* We can't wait for rendering with pagefaults disabled */
> - if (obj->active && pagefault_disabled())
> + if (pagefault_disabled() && !object_is_idle(obj))
> return -EFAULT;
>
> if (use_cpu_reloc(obj))
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c
2016-07-25 17:32 ` [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c Chris Wilson
@ 2016-07-26 12:48 ` Joonas Lahtinen
2016-07-26 13:39 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 12:48 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> As the list retirement is now clean of implementation details, we can
> move it closer to the request management.
>
This is again a combined motion + simplification, which should be split
motion first then changes...
Not splitting makes even simple patches slow to review.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 44 ---------------------------------
> drivers/gpu/drm/i915/i915_gem_request.c | 35 ++++++++++++++++++++++++++
> 2 files changed, 35 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index cc84f00cf883..c572c80a6604 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2541,50 +2541,6 @@ void i915_gem_reset(struct drm_device *dev)
> i915_gem_restore_fences(dev);
> }
>
> -/**
> - * This function clears the request list as sequence numbers are passed.
> - * @engine: engine to retire requests on
> - */
> -void
> -i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
> -{
> - while (!list_empty(&engine->request_list)) {
> - struct drm_i915_gem_request *request;
> -
> - request = list_first_entry(&engine->request_list,
> - struct drm_i915_gem_request,
> - link);
> -
> - if (!i915_gem_request_completed(request))
> - break;
> -
> - i915_gem_request_retire_upto(request);
> - }
> -}
> -
> -void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
> -{
> - struct intel_engine_cs *engine;
> -
> - lockdep_assert_held(&dev_priv->drm.struct_mutex);
> -
> - if (dev_priv->gt.active_engines == 0)
> - return;
> -
> - GEM_BUG_ON(!dev_priv->gt.awake);
> -
> - for_each_engine(engine, dev_priv) {
> - i915_gem_retire_requests_ring(engine);
> - if (list_empty(&engine->request_list))
> - dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
> - }
> -
> - if (dev_priv->gt.active_engines == 0)
> - queue_delayed_work(dev_priv->wq,
> - &dev_priv->gt.idle_work,
> - msecs_to_jiffies(100));
> -}
> -
> static void
> i915_gem_retire_work_handler(struct work_struct *work)
> {
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 1935591a98c1..f41572aa53d4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -716,3 +716,38 @@ complete:
>
> return ret;
> }
> +
> +void i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
_engine?
> +{
> + struct drm_i915_gem_request *request, *next;
> +
> + list_for_each_entry_safe(request, next, &engine->request_list, link) {
> + if (!i915_gem_request_completed(request))
> + break;
> +
> + i915_gem_request_retire(request);
> + }
> +}
> +
> +void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
> +{
> + struct intel_engine_cs *engine;
> +
> + lockdep_assert_held(&dev_priv->drm.struct_mutex);
> +
> + if (dev_priv->gt.active_engines == 0)
> + return;
> +
> + GEM_BUG_ON(!dev_priv->gt.awake);
> +
> + for_each_engine(engine, dev_priv) {
> + i915_gem_retire_requests_ring(engine);
> + if (list_empty(&engine->request_list))
> + dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
> + }
> +
> + if (dev_priv->gt.active_engines == 0)
> + queue_delayed_work(dev_priv->wq,
> + &dev_priv->gt.idle_work,
> + msecs_to_jiffies(100));
> +}
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 51/55] drm/i915: i915_vma_move_to_active prep patch
2016-07-25 17:32 ` [PATCH 51/55] drm/i915: i915_vma_move_to_active prep patch Chris Wilson
@ 2016-07-26 12:53 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-26 12:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> This patch is broken out of the next just to remove the code motion from
> that patch and make it more readable. What we do here is move the
> i915_vma_move_to_active() to i915_gem_execbuffer.c and put the three
> stages (read, write, fenced) together so that future modifications to
> active handling are all located in the same spot. The importance of this
> is so that we can more simply control the order in which the requests
> are place in the retirement list (i.e. control the order at which we
> retire and so control the lifetimes to avoid having to hold onto
> references).
>
This is much better. So,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/i915_gem.c | 18 --------
> drivers/gpu/drm/i915/i915_gem_context.c | 9 ++--
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 65 ++++++++++++++++++----------
> drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
> 5 files changed, 51 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 03f12304308a..4876d2a6c2c4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3153,7 +3153,8 @@ int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
> int i915_gem_object_sync(struct drm_i915_gem_object *obj,
> struct drm_i915_gem_request *to);
> void i915_vma_move_to_active(struct i915_vma *vma,
> - struct drm_i915_gem_request *req);
> + struct drm_i915_gem_request *req,
> + unsigned int flags);
> int i915_gem_dumb_create(struct drm_file *file_priv,
> struct drm_device *dev,
> struct drm_mode_create_dumb *args);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index c572c80a6604..2e0b54fa03f9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2330,24 +2330,6 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
> return obj->mapping;
> }
>
> -void i915_vma_move_to_active(struct i915_vma *vma,
> - struct drm_i915_gem_request *req)
> -{
> - struct drm_i915_gem_object *obj = vma->obj;
> - struct intel_engine_cs *engine;
> -
> - engine = i915_gem_request_get_engine(req);
> -
> - /* Add a reference if we're newly entering the active list. */
> - if (obj->active == 0)
> - i915_gem_object_get(obj);
> - obj->active |= intel_engine_flag(engine);
> -
> - i915_gem_active_set(&obj->last_read[engine->id], req);
> -
> - list_move_tail(&vma->vm_link, &vma->vm->active_list);
> -}
> -
> static void
> i915_gem_object_retire__fence(struct i915_gem_active *active,
> struct drm_i915_gem_request *req)
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 60861f616f24..29b2547a2b4c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -816,8 +816,8 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
> * MI_SET_CONTEXT instead of when the next seqno has completed.
> */
> if (from != NULL) {
> - from->engine[RCS].state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> - i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req);
> + struct drm_i915_gem_object *obj = from->engine[RCS].state;
> +
> /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
> * whole damn pipeline, we don't need to explicitly mark the
> * object dirty. The only exception is that the context must be
> @@ -825,10 +825,11 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
> * able to defer doing this until we know the object would be
> * swapped, but there is no way to do that yet.
> */
> - from->engine[RCS].state->dirty = 1;
> + obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> + i915_vma_move_to_active(i915_gem_obj_to_ggtt(obj), req, 0);
>
> /* obj is kept alive until the next request by its active ref */
> - i915_gem_object_ggtt_unpin(from->engine[RCS].state);
> + i915_gem_object_ggtt_unpin(obj);
> i915_gem_context_put(from);
> }
> engine->last_context = i915_gem_context_get(to);
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 9778b1bc6336..d0f1da2863e4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1143,43 +1143,64 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
> return ctx;
> }
>
> +void i915_vma_move_to_active(struct i915_vma *vma,
> + struct drm_i915_gem_request *req,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj = vma->obj;
> + const unsigned int idx = req->engine->id;
> +
> + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> +
> + obj->dirty = 1; /* be paranoid */
> +
> + /* Add a reference if we're newly entering the active list. */
> + if (obj->active == 0)
> + i915_gem_object_get(obj);
> + obj->active |= 1 << idx;
> + i915_gem_active_set(&obj->last_read[idx], req);
> +
> + if (flags & EXEC_OBJECT_WRITE) {
> + i915_gem_active_set(&obj->last_write, req);
> +
> + intel_fb_obj_invalidate(obj, ORIGIN_CS);
> +
> + /* update for the implicit flush after a batch */
> + obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
> + }
> +
> + if (flags & EXEC_OBJECT_NEEDS_FENCE) {
> + i915_gem_active_set(&obj->last_fence, req);
> + if (flags & __EXEC_OBJECT_HAS_FENCE) {
> + struct drm_i915_private *dev_priv = req->i915;
> +
> + list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
> + &dev_priv->mm.fence_list);
> + }
> + }
> +
> + list_move_tail(&vma->vm_link, &vma->vm->active_list);
> +}
> +
> static void
> i915_gem_execbuffer_move_to_active(struct list_head *vmas,
> struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
> struct i915_vma *vma;
>
> list_for_each_entry(vma, vmas, exec_list) {
> - struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
> struct drm_i915_gem_object *obj = vma->obj;
> u32 old_read = obj->base.read_domains;
> u32 old_write = obj->base.write_domain;
>
> - obj->dirty = 1; /* be paranoid */
> obj->base.write_domain = obj->base.pending_write_domain;
> - if (obj->base.write_domain == 0)
> + if (obj->base.write_domain)
> + vma->exec_entry->flags |= EXEC_OBJECT_WRITE;
> + else
> obj->base.pending_read_domains |= obj->base.read_domains;
> obj->base.read_domains = obj->base.pending_read_domains;
>
> - i915_vma_move_to_active(vma, req);
> - if (obj->base.write_domain) {
> - i915_gem_active_set(&obj->last_write, req);
> -
> - intel_fb_obj_invalidate(obj, ORIGIN_CS);
> -
> - /* update for the implicit flush after a batch */
> - obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
> - }
> - if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
> - i915_gem_active_set(&obj->last_fence, req);
> - if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
> - struct drm_i915_private *dev_priv = engine->i915;
> - list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
> - &dev_priv->mm.fence_list);
> - }
> - }
> -
> + i915_vma_move_to_active(vma, req, vma->exec_entry->flags);
> trace_i915_gem_object_change_domain(obj, old_read, old_write);
> }
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index f85c5505bce2..90236672ac1e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -217,7 +217,7 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
> goto err_unpin;
> }
>
> - i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
> + i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req, 0);
> err_unpin:
> i915_gem_object_ggtt_unpin(so.obj);
> err_obj:
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine
2016-07-26 12:40 ` Joonas Lahtinen
@ 2016-07-26 13:11 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 13:11 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 03:40:28PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > If the user floods the GPU with so many requests that the engine stalls
> > waiting for free space, don't automatically promote the GPU to maximum
> > frequencies. If the GPU really is saturated with work, it will migrate
> > to high clocks by itself, otherwise it is merely a user flooding us with
> > busy-work.
> >
>
> Should this even come with Fixes: ?
A fixes patch would need dev_priv->rps.semaphores as the client. In
practice (outside of igt), I don't expect anyone to notice the difference
as you have both to fill the ring and keep the GPU (mostly) idle.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c
2016-07-26 12:48 ` Joonas Lahtinen
@ 2016-07-26 13:39 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-26 13:39 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jul 26, 2016 at 03:48:44PM +0300, Joonas Lahtinen wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> > index 1935591a98c1..f41572aa53d4 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_request.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> > @@ -716,3 +716,38 @@ complete:
> >
> > return ret;
> > }
> > +
> > +void i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
>
> _engine?
In about another 10 patches, this function is made static.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-25 17:32 ` [PATCH 40/55] drm/i915: Refactor blocking waits Chris Wilson
@ 2016-07-27 6:04 ` Joonas Lahtinen
2016-07-27 7:04 ` Chris Wilson
2016-07-27 7:07 ` Chris Wilson
0 siblings, 2 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 6:04 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> Tidy up the for loops that handle waiting for read/write vs read-only
> access.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 158 +++++++++++++++++++---------------------
> 1 file changed, 75 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 3f6b69dcaccb..2d86a0c3f295 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1339,6 +1339,23 @@ put_rpm:
> return ret;
> }
>
> +static void
> +i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> + struct drm_i915_gem_request *req)
> +{
> + int idx = req->engine->id;
> +
> + if (i915_gem_active_peek(&obj->last_read[idx],
> + &obj->base.dev->struct_mutex) == req)
> + i915_gem_object_retire__read(obj, idx);
> + else if (i915_gem_active_peek(&obj->last_write,
> + &obj->base.dev->struct_mutex) == req)
> + i915_gem_object_retire__write(obj);
If these functions will use same mutex (be it different than
struct_mutex) in all invocations, I'd make an alias for it.
> +
> + if (!i915_reset_in_progress(&req->i915->gpu_error))
> + i915_gem_request_retire_upto(req);
> +}
> +
> /**
> * Ensures that all rendering to the object has completed and the object is
> * safe to unbind from the GTT or access from the CPU.
> @@ -1349,39 +1366,34 @@ int
> i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
> bool readonly)
> {
> - struct drm_i915_gem_request *request;
> struct reservation_object *resv;
> - int ret, i;
> + struct i915_gem_active *active;
> + unsigned long active_mask;
> + int idx, ret;
>
We could do early exit here based on the active_mask, like with the
nonblocking version.
> - if (readonly) {
> - request = i915_gem_active_peek(&obj->last_write,
> - &obj->base.dev->struct_mutex);
> - if (request) {
> - ret = i915_wait_request(request);
> - if (ret)
> - return ret;
> + lockdep_assert_held(&obj->base.dev->struct_mutex);
>
> - i = request->engine->id;
> - if (i915_gem_active_peek(&obj->last_read[i],
> - &obj->base.dev->struct_mutex) == request)
> - i915_gem_object_retire__read(obj, i);
> - else
> - i915_gem_object_retire__write(obj);
> - }
> + if (!readonly) {
Not sure why not just swap and keep this if (readonly)...
> + active = obj->last_read;
> + active_mask = obj->active;
> } else {
> - for (i = 0; i < I915_NUM_ENGINES; i++) {
> - request = i915_gem_active_peek(&obj->last_read[i],
> - &obj->base.dev->struct_mutex);
> - if (!request)
> - continue;
> + active_mask = 1;
Wouldn't we have RENDER_RING define for this and other instances?
With above addressed,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
2016-07-26 8:12 ` Chris Wilson
@ 2016-07-27 6:12 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 6:12 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ti, 2016-07-26 at 09:12 +0100, Chris Wilson wrote:
> On Tue, Jul 26, 2016 at 08:02:25AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> > >
> > > A few places we use ring when referring to the struct intel_engine_cs. An
> > > anachronism we are pruning out.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-9-git-send-email-chris@chris-wilson.co.uk
> > > ---
> > > drivers/gpu/drm/i915/i915_gem.c | 24 ++++++++++++------------
> > > 1 file changed, 12 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > index e155e8dd28ed..7bfce1d5c61b 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -46,7 +46,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
> > > static void
> > > i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
> > > static void
> > > -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
> > > +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
> > I vote for engine_idx variable name, that much I dislike differing
> > naming in signature and implementation.
> I think engine_idx is pretty repugnant. I'll wait until you get to
> "Refactor activity tracking for requests" so you see how this function
> looks closer to its final form (in this series at least).
Ok, the parameter completely changes (into request), so no need to
debate really. So have my;
Reviewed-by: Joonas Lahtien <joonas.lahtinen@linux.intel.com>
CC'ing Dave here too.
Regards, Joonas
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-27 6:04 ` Joonas Lahtinen
@ 2016-07-27 7:04 ` Chris Wilson
2016-07-27 10:40 ` Joonas Lahtinen
2016-07-27 7:07 ` Chris Wilson
1 sibling, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 7:04 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 09:04:03AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > Tidy up the for loops that handle waiting for read/write vs read-only
> > access.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 158 +++++++++++++++++++---------------------
> > 1 file changed, 75 insertions(+), 83 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 3f6b69dcaccb..2d86a0c3f295 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -1339,6 +1339,23 @@ put_rpm:
> > return ret;
> > }
> >
> > +static void
> > +i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> > + struct drm_i915_gem_request *req)
> > +{
> > + int idx = req->engine->id;
> > +
> > + if (i915_gem_active_peek(&obj->last_read[idx],
> > + &obj->base.dev->struct_mutex) == req)
> > + i915_gem_object_retire__read(obj, idx);
> > + else if (i915_gem_active_peek(&obj->last_write,
> > + &obj->base.dev->struct_mutex) == req)
> > + i915_gem_object_retire__write(obj);
>
> If these functions will use same mutex (be it different than
> struct_mutex) in all invocations, I'd make an alias for it.
Why? It is written like this to prevent the compiler doing anything when
not debugging.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-27 6:04 ` Joonas Lahtinen
2016-07-27 7:04 ` Chris Wilson
@ 2016-07-27 7:07 ` Chris Wilson
2016-07-27 10:42 ` Joonas Lahtinen
1 sibling, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 7:07 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 09:04:03AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > Tidy up the for loops that handle waiting for read/write vs read-only
> > access.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 158 +++++++++++++++++++---------------------
> > 1 file changed, 75 insertions(+), 83 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 3f6b69dcaccb..2d86a0c3f295 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -1339,6 +1339,23 @@ put_rpm:
> > return ret;
> > }
> >
> > +static void
> > +i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> > + struct drm_i915_gem_request *req)
> > +{
> > + int idx = req->engine->id;
> > +
> > + if (i915_gem_active_peek(&obj->last_read[idx],
> > + &obj->base.dev->struct_mutex) == req)
> > + i915_gem_object_retire__read(obj, idx);
> > + else if (i915_gem_active_peek(&obj->last_write,
> > + &obj->base.dev->struct_mutex) == req)
> > + i915_gem_object_retire__write(obj);
>
> If these functions will use same mutex (be it different than
> struct_mutex) in all invocations, I'd make an alias for it.
>
> > +
> > + if (!i915_reset_in_progress(&req->i915->gpu_error))
> > + i915_gem_request_retire_upto(req);
> > +}
> > +
> > /**
> > * Ensures that all rendering to the object has completed and the object is
> > * safe to unbind from the GTT or access from the CPU.
> > @@ -1349,39 +1366,34 @@ int
> > i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
> > bool readonly)
> > {
> > - struct drm_i915_gem_request *request;
> > struct reservation_object *resv;
> > - int ret, i;
> > + struct i915_gem_active *active;
> > + unsigned long active_mask;
> > + int idx, ret;
> >
>
> We could do early exit here based on the active_mask, like with the
> nonblocking version.
Nope. Because here we have to worry about third parties, we can't exit
early.
> > - if (readonly) {
> > - request = i915_gem_active_peek(&obj->last_write,
> > - &obj->base.dev->struct_mutex);
> > - if (request) {
> > - ret = i915_wait_request(request);
> > - if (ret)
> > - return ret;
> > + lockdep_assert_held(&obj->base.dev->struct_mutex);
> >
> > - i = request->engine->id;
> > - if (i915_gem_active_peek(&obj->last_read[i],
> > - &obj->base.dev->struct_mutex) == request)
> > - i915_gem_object_retire__read(obj, i);
> > - else
> > - i915_gem_object_retire__write(obj);
> > - }
> > + if (!readonly) {
>
> Not sure why not just swap and keep this if (readonly)...
Consistency. The others did !readonly, and this was the odd one out.
>
> > + active = obj->last_read;
> > + active_mask = obj->active;
> > } else {
> > - for (i = 0; i < I915_NUM_ENGINES; i++) {
> > - request = i915_gem_active_peek(&obj->last_read[i],
> > - &obj->base.dev->struct_mutex);
> > - if (!request)
> > - continue;
> > + active_mask = 1;
>
> Wouldn't we have RENDER_RING define for this and other instances?
?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 43/55] drm/i915: Refactor activity tracking for requests
2016-07-25 17:32 ` [PATCH 43/55] drm/i915: Refactor activity tracking for requests Chris Wilson
@ 2016-07-27 7:40 ` Joonas Lahtinen
2016-07-27 7:57 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 7:40 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> static void
> -i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> +i915_gem_object_retire__fence(struct i915_gem_active *active,
> + struct drm_i915_gem_request *req)
> {
> - GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_write));
> - GEM_BUG_ON(!(obj->active &
> - intel_engine_flag(i915_gem_active_get_engine(&obj->last_write,
> - &obj->base.dev->struct_mutex))));
> +}
>
An empty function? Could have at least a comment why currently empty.
> - i915_gem_active_set(&obj->last_write, NULL);
> - intel_fb_obj_flush(obj, true, ORIGIN_CS);
> +static void
> +i915_gem_object_retire__write(struct i915_gem_active *active,
> + struct drm_i915_gem_request *request)
> +{
> + intel_fb_obj_flush(container_of(active,
> + struct drm_i915_gem_object,
> + last_write),
Add a function, manual container_of are horrible. And do it in the
beginning of a function as a separate line, too.
> + true,
> + ORIGIN_CS);
> }
>
> static void
> -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> +i915_gem_object_retire__read(struct i915_gem_active *active,
> + struct drm_i915_gem_request *request)
> {
> - struct intel_engine_cs *engine;
> + int idx = request->engine->id;
> + struct drm_i915_gem_object *obj =
> + container_of(active, struct drm_i915_gem_object, last_read[idx]);
Ditto.
> struct i915_vma *vma;
>
> - GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_read[idx]));
> - GEM_BUG_ON(!(obj->active & (1 << idx)));
> -
> - list_del_init(&obj->engine_list[idx]);
> - i915_gem_active_set(&obj->last_read[idx], NULL);
> -
> - engine = i915_gem_active_get_engine(&obj->last_write,
> - &obj->base.dev->struct_mutex);
> - if (engine && engine->id == idx)
> - i915_gem_object_retire__write(obj);
> + GEM_BUG_ON((obj->active & (1 << idx)) == 0);
BIT() or maybe even ENGINE_MASK() when we have such a beauty. Or do you
intend to make this about something else but engines eventually?
>
> obj->active &= ~(1 << idx);
> if (obj->active)
> @@ -2419,15 +2384,13 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> * so that we don't steal from recently used but inactive objects
> * (unless we are forced to ofc!)
> */
> - list_move_tail(&obj->global_list,
> - &to_i915(obj->base.dev)->mm.bound_list);
> + list_move_tail(&obj->global_list, &request->i915->mm.bound_list);
As a follow-up s/global_list/global_link/?
> void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
> @@ -2818,8 +2742,7 @@ out:
> }
>
> static int
> -__i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *to,
> +__i915_gem_object_sync(struct drm_i915_gem_request *to,
> struct drm_i915_gem_request *from)
> {
> int ret;
> @@ -2827,9 +2750,6 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> if (to->engine == from->engine)
> return 0;
>
> - if (i915_gem_request_completed(from))
> - return 0;
> -
Why remove the early exit?
> @@ -172,6 +176,24 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> */
> request->ring->last_retired_head = request->postfix;
>
> + /* Walk through the active list, calling retire on each. This allows
> + * objects to track their GPU activity and mark themselves as idle
> + * when their *last* active request is completed (updating state
> + * tracking lists for eviction, active references for GEM, etc).
> + *
> + * As the ->retire() may free the node, we decouple it first and
> + * pass along the auxiliary information (to avoid dereferencing
> + * the node after the callback).
> + */
> + list_for_each_entry_safe(active, next, &request->active_list, link) {
> + prefetchw(next);
Would not this be an improvement to go to list_for_each_entry{,_safe}
rather?
> +
> + INIT_LIST_HEAD(&active->link);
> + active->__request = NULL;
> +
> + active->retire(active, request);
> + }
> +
> i915_gem_request_remove_from_client(request);
>
> if (request->previous_context) {
>
> @@ -705,10 +723,13 @@ int i915_wait_request(struct drm_i915_gem_request *req)
> {
> int ret;
>
> - GEM_BUG_ON(!req);
> lockdep_assert_held(&req->i915->drm.struct_mutex);
> + GEM_BUG_ON(list_empty(&req->link));
Humm, why no waiting on requests without the tracker object? Or then
need to use __i915_wait_request? Kerneldoc might be useful.
> i915_gem_active_peek(const struct i915_gem_active *active, struct mutex *mutex)
> {
> - return active->__request;
> + struct drm_i915_gem_request *request;
> +
> + request = active->__request;
> + if (!request || i915_gem_request_completed(request))
> + return NULL;
I see early exit was kinda migrated here.
> +
> + return request;
> }
>
> /**
> @@ -326,13 +360,7 @@ i915_gem_active_peek(const struct i915_gem_active *active, struct mutex *mutex)
> static inline struct drm_i915_gem_request *
> i915_gem_active_get(const struct i915_gem_active *active, struct mutex *mutex)
> {
> - struct drm_i915_gem_request *request;
> -
> - request = i915_gem_active_peek(active, mutex);
> - if (!request || i915_gem_request_completed(request))
> - return NULL;
> -
> - return i915_gem_request_get(request);
> + return i915_gem_request_get(i915_gem_active_peek(active, mutex));
On average looks better with a variable in between and not all
functions chained.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 43/55] drm/i915: Refactor activity tracking for requests
2016-07-27 7:40 ` Joonas Lahtinen
@ 2016-07-27 7:57 ` Chris Wilson
2016-07-27 10:55 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 7:57 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 10:40:14AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > static void
> > -i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> > +i915_gem_object_retire__fence(struct i915_gem_active *active,
> > + struct drm_i915_gem_request *req)
> > {
> > - GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_write));
> > - GEM_BUG_ON(!(obj->active &
> > - intel_engine_flag(i915_gem_active_get_engine(&obj->last_write,
> > - &obj->base.dev->struct_mutex))));
> > +}
> >
>
> An empty function? Could have at least a comment why currently empty.
To avoid the branch inside the retirement loop for an infrequent call.
>
> > - i915_gem_active_set(&obj->last_write, NULL);
> > - intel_fb_obj_flush(obj, true, ORIGIN_CS);
> > +static void
> > +i915_gem_object_retire__write(struct i915_gem_active *active,
> > + struct drm_i915_gem_request *request)
> > +{
> > + intel_fb_obj_flush(container_of(active,
> > + struct drm_i915_gem_object,
> > + last_write),
>
> Add a function, manual container_of are horrible. And do it in the
> beginning of a function as a separate line, too.
>
> > + true,
> > + ORIGIN_CS);
> > }
> >
> > static void
> > -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> > +i915_gem_object_retire__read(struct i915_gem_active *active,
> > + struct drm_i915_gem_request *request)
> > {
> > - struct intel_engine_cs *engine;
> > + int idx = request->engine->id;
> > + struct drm_i915_gem_object *obj =
> > + container_of(active, struct drm_i915_gem_object, last_read[idx]);
>
> Ditto.
No.
>
> > struct i915_vma *vma;
> >
> > - GEM_BUG_ON(!__i915_gem_active_is_busy(&obj->last_read[idx]));
> > - GEM_BUG_ON(!(obj->active & (1 << idx)));
> > -
> > - list_del_init(&obj->engine_list[idx]);
> > - i915_gem_active_set(&obj->last_read[idx], NULL);
> > -
> > - engine = i915_gem_active_get_engine(&obj->last_write,
> > - &obj->base.dev->struct_mutex);
> > - if (engine && engine->id == idx)
> > - i915_gem_object_retire__write(obj);
> > + GEM_BUG_ON((obj->active & (1 << idx)) == 0);
>
> BIT() or maybe even ENGINE_MASK() when we have such a beauty. Or do you
> intend to make this about something else but engines eventually?
Yes. You will get to those patches eventually.
>
> >
> > obj->active &= ~(1 << idx);
> > if (obj->active)
> > @@ -2419,15 +2384,13 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> > * so that we don't steal from recently used but inactive objects
> > * (unless we are forced to ofc!)
> > */
> > - list_move_tail(&obj->global_list,
> > - &to_i915(obj->base.dev)->mm.bound_list);
> > + list_move_tail(&obj->global_list, &request->i915->mm.bound_list);
>
> As a follow-up s/global_list/global_link/?
>
> > void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
> > @@ -2818,8 +2742,7 @@ out:
> > }
> >
> > static int
> > -__i915_gem_object_sync(struct drm_i915_gem_object *obj,
> > - struct drm_i915_gem_request *to,
> > +__i915_gem_object_sync(struct drm_i915_gem_request *to,
> > struct drm_i915_gem_request *from)
> > {
> > int ret;
> > @@ -2827,9 +2750,6 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> > if (to->engine == from->engine)
> > return 0;
> >
> > - if (i915_gem_request_completed(from))
> > - return 0;
> > -
>
> Why remove the early exit?
I made it redundant. There is also a small improvement by using the
sema-seqno tracking (which actually applies equally to the bdw
!semaphore path, more on that later).
> > @@ -172,6 +176,24 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> > */
> > request->ring->last_retired_head = request->postfix;
> >
> > + /* Walk through the active list, calling retire on each. This allows
> > + * objects to track their GPU activity and mark themselves as idle
> > + * when their *last* active request is completed (updating state
> > + * tracking lists for eviction, active references for GEM, etc).
> > + *
> > + * As the ->retire() may free the node, we decouple it first and
> > + * pass along the auxiliary information (to avoid dereferencing
> > + * the node after the callback).
> > + */
> > + list_for_each_entry_safe(active, next, &request->active_list, link) {
> > + prefetchw(next);
>
> Would not this be an improvement to go to list_for_each_entry{,_safe}
> rather?
It's been tried before. It's not a universal improvement. This loop is
one of the top functions in the profiles when handling large request
objects, with perf implying that the memory loads are where our time
goes..
> > +
> > + INIT_LIST_HEAD(&active->link);
> > + active->__request = NULL;
> > +
> > + active->retire(active, request);
> > + }
> > +
> > i915_gem_request_remove_from_client(request);
> >
> > if (request->previous_context) {
> >
> > @@ -705,10 +723,13 @@ int i915_wait_request(struct drm_i915_gem_request *req)
> > {
> > int ret;
> >
> > - GEM_BUG_ON(!req);
> > lockdep_assert_held(&req->i915->drm.struct_mutex);
> > + GEM_BUG_ON(list_empty(&req->link));
>
> Humm, why no waiting on requests without the tracker object? Or then
> need to use __i915_wait_request? Kerneldoc might be useful.
?
-BUG_ON(!req) we declare it as non-null and a NULL pointer dereference
oops isn't much harder than a BUG to pinpoint.
+list_empty() is an assertion against waiting on a retired request.
> > i915_gem_active_peek(const struct i915_gem_active *active, struct mutex *mutex)
> > {
> > - return active->__request;
> > + struct drm_i915_gem_request *request;
> > +
> > + request = active->__request;
> > + if (!request || i915_gem_request_completed(request))
> > + return NULL;
>
> I see early exit was kinda migrated here.
Kinda, but this is also a big difference in behaviour.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking
2016-07-25 17:32 ` [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking Chris Wilson
@ 2016-07-27 8:12 ` Joonas Lahtinen
2016-07-27 8:22 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 8:12 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
>
> -static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
> +static void intel_overlay_submit_request(struct intel_overlay *overlay,
> struct drm_i915_gem_request *req,
> - void (*tail)(struct intel_overlay *))
> + void (*retire)(struct i915_gem_active *,
> + struct drm_i915_gem_request *))
Ugh, not such a beauty. We do not do callback typedefs?
> -static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
> +static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
> + struct drm_i915_gem_request *req)
> {
> + struct intel_overlay *overlay =
> + container_of(active, typeof(*overlay), last_flip);
> struct drm_i915_gem_object *obj = overlay->old_vid_bo;
>
> + i915_gem_track_fb(obj, NULL,
> + INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
> +
Previously this call was after the below calls and old_vid_bo was
always NULL, does this fix a bug?
> i915_gem_object_ggtt_unpin(obj);
> i915_gem_object_put(obj);
>
> overlay->old_vid_bo = NULL;
> }
>
>
> /* Wait for pending overlay flip and release old frame.
> @@ -452,13 +450,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> intel_overlay_release_old_vid_tail);
> if (ret)
> return ret;
> - }
> + } else
> + intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
Why you added else?
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking
2016-07-27 8:12 ` Joonas Lahtinen
@ 2016-07-27 8:22 ` Chris Wilson
2016-07-27 8:34 ` Chris Wilson
2016-07-27 10:59 ` Joonas Lahtinen
0 siblings, 2 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 8:22 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 11:12:32AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> >
> > -static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
> > +static void intel_overlay_submit_request(struct intel_overlay *overlay,
> > struct drm_i915_gem_request *req,
> > - void (*tail)(struct intel_overlay *))
> > + void (*retire)(struct i915_gem_active *,
> > + struct drm_i915_gem_request *))
>
> Ugh, not such a beauty. We do not do callback typedefs?
Not often that we actually pass around function pointers.
> > -static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
> > +static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
> > + struct drm_i915_gem_request *req)
> > {
> > + struct intel_overlay *overlay =
> > + container_of(active, typeof(*overlay), last_flip);
> > struct drm_i915_gem_object *obj = overlay->old_vid_bo;
> >
> > + i915_gem_track_fb(obj, NULL,
> > + INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
> > +
>
> Previously this call was after the below calls and old_vid_bo was
> always NULL, does this fix a bug?
Yes.
https://bugs.freedesktop.org/show_bug.cgi?id=93730
and a recent one.
> > i915_gem_object_ggtt_unpin(obj);
> > i915_gem_object_put(obj);
> >
> > overlay->old_vid_bo = NULL;
> > }
> >
> >
> > /* Wait for pending overlay flip and release old frame.
> > @@ -452,13 +450,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> > intel_overlay_release_old_vid_tail);
> > if (ret)
> > return ret;
> > - }
> > + } else
> > + intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
>
> Why you added else?
Habit?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking
2016-07-27 8:22 ` Chris Wilson
@ 2016-07-27 8:34 ` Chris Wilson
2016-07-27 10:59 ` Joonas Lahtinen
1 sibling, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 8:34 UTC (permalink / raw)
To: Joonas Lahtinen, intel-gfx
On Wed, Jul 27, 2016 at 09:22:33AM +0100, Chris Wilson wrote:
> On Wed, Jul 27, 2016 at 11:12:32AM +0300, Joonas Lahtinen wrote:
> > > @@ -452,13 +450,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> > > intel_overlay_release_old_vid_tail);
> > > if (ret)
> > > return ret;
> > > - }
> > > + } else
> > > + intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
> >
> > Why you added else?
>
> Habit?
Ah, no. Because on the true branch the release is deferred. On the else
brnach the release is immediate.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 52/55] drm/i915: Track active vma requests
2016-07-25 17:32 ` [PATCH 52/55] drm/i915: Track active vma requests Chris Wilson
@ 2016-07-27 9:47 ` Joonas Lahtinen
2016-07-27 10:15 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 9:47 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 529fb483afc8..d2206f40f7b2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
>
> +static inline bool i915_vma_is_active(const struct i915_vma *vma)
> +{
> + return vma->active;
> +}
> +
> +static inline void i915_vma_set_active(struct i915_vma *vma,
> + unsigned int engine)
> +{
> + vma->active |= BIT(engine);
> +}
> +
> +static inline void i915_vma_unset_active(struct i915_vma *vma,
> + unsigned int engine)
> +{
> + vma->active &= ~BIT(engine);
> +}
> +
> +static inline bool i915_vma_has_active_engine(const struct i915_vma *vma,
> + unsigned int engine)
> +{
> + return vma->active & BIT(engine);
> +}
> +
Are these going to grow more complex? Otherwise looks fine,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 53/55] drm/i915: Release vma when the handle is closed
2016-07-25 17:32 ` [PATCH 53/55] drm/i915: Release vma when the handle is closed Chris Wilson
@ 2016-07-27 10:00 ` Joonas Lahtinen
2016-07-27 10:13 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:00 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> /**
> * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
> * @dev: drm device pointer
> @@ -2810,26 +2823,32 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
> if (active && wait) {
> int idx;
>
> + /* When a closed VMA is retired, it is unbound - eek.
> + * In order to prevent it from being recursively closed,
> + * take a pin on the vma so that the second unbind is
> + * aborted.
> + */
> + vma->pin_count++;
Always smells fishy. But an extra variable probably not worthy.
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ef0dc7131808..bfac2448ba04 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3339,6 +3339,31 @@ i915_vma_retire(struct i915_gem_active *active,
> return;
>
> list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
> + if (unlikely(vma->closed && !vma->pin_count))
> + WARN_ON(i915_vma_unbind(vma));
So this is just an optimization to get rid of the VMA ASAP if we're
lucky?
> +
> +void i915_vma_close(struct i915_vma *vma)
> +{
> + GEM_BUG_ON(vma->closed);
> + vma->closed = true;
> +
> + list_del_init(&vma->obj_link);
> + if (!i915_vma_is_active(vma) && !vma->pin_count)
> + WARN_ON(__i915_vma_unbind_no_wait(vma));
Same here, an optimization?
Somebody from the original CC list probably should give it a look too.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 53/55] drm/i915: Release vma when the handle is closed
2016-07-27 10:00 ` Joonas Lahtinen
@ 2016-07-27 10:13 ` Chris Wilson
2016-07-28 7:16 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 10:13 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 01:00:59PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > /**
> > * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
> > * @dev: drm device pointer
> > @@ -2810,26 +2823,32 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
> > if (active && wait) {
> > int idx;
> >
> > + /* When a closed VMA is retired, it is unbound - eek.
> > + * In order to prevent it from being recursively closed,
> > + * take a pin on the vma so that the second unbind is
> > + * aborted.
> > + */
> > + vma->pin_count++;
>
> Always smells fishy. But an extra variable probably not worthy.
>
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index ef0dc7131808..bfac2448ba04 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -3339,6 +3339,31 @@ i915_vma_retire(struct i915_gem_active *active,
> > return;
> >
> > list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
> > + if (unlikely(vma->closed && !vma->pin_count))
> > + WARN_ON(i915_vma_unbind(vma));
>
> So this is just an optimization to get rid of the VMA ASAP if we're
> lucky?
Not quite. Think of this as the active reference, this may be the last
point at which we see the closed vma. If we don't free it now, we leak
the VMA until the object is closed - where if we meet it we BUG.
> > +void i915_vma_close(struct i915_vma *vma)
> > +{
> > + GEM_BUG_ON(vma->closed);
> > + vma->closed = true;
> > +
> > + list_del_init(&vma->obj_link);
> > + if (!i915_vma_is_active(vma) && !vma->pin_count)
> > + WARN_ON(__i915_vma_unbind_no_wait(vma));
>
> Same here, an optimization?
Same as above. This time we know the vma is inactive, so no outstanding
reference.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 54/55] drm/i915: Mark the context and address space as closed
2016-07-25 17:32 ` [PATCH 54/55] drm/i915: Mark the context and address space as closed Chris Wilson
@ 2016-07-27 10:13 ` Joonas Lahtinen
2016-07-27 10:27 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:13 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -907,6 +907,7 @@ struct i915_gem_context {
> struct list_head link;
>
> u8 remap_slice;
> + bool closed:1;
Not a whole bool? I think it could be.
>
> +static void i915_ppgtt_close(struct i915_address_space *vm)
> +{
> + struct list_head *phases[] = {
> + &vm->active_list,
> + &vm->inactive_list,
> + &vm->unbound_list,
> + NULL,
> + }, **phase;
> +
> + GEM_BUG_ON(vm->closed);
> + vm->closed = true;
> +
> + for (phase = phases; *phase; phase++) {
> + struct i915_vma *vma, *vn;
> +
> + list_for_each_entry_safe(vma, vn, *phase, vm_link)
> + if (!vma->closed)
> + i915_vma_close(vma);
> + }
Pretty sure rather listing three three function calls here would be
nicer;
i915_ppgtt_do_close(vm->active_list);
i915_ppgtt_do_close(vm->inactive_list);
...
Patch really makes the tracking easier to follow, there also seems to
be a hint of paranoia, but it's with GEM_BUG_ON() so should not hurt.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 52/55] drm/i915: Track active vma requests
2016-07-27 9:47 ` Joonas Lahtinen
@ 2016-07-27 10:15 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 10:15 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 12:47:46PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
>
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > index 529fb483afc8..d2206f40f7b2 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> >
> > +static inline bool i915_vma_is_active(const struct i915_vma *vma)
> > +{
> > + return vma->active;
> > +}
> > +
> > +static inline void i915_vma_set_active(struct i915_vma *vma,
> > + unsigned int engine)
> > +{
> > + vma->active |= BIT(engine);
> > +}
> > +
> > +static inline void i915_vma_unset_active(struct i915_vma *vma,
> > + unsigned int engine)
> > +{
> > + vma->active &= ~BIT(engine);
> > +}
> > +
> > +static inline bool i915_vma_has_active_engine(const struct i915_vma *vma,
> > + unsigned int engine)
> > +{
> > + return vma->active & BIT(engine);
> > +}
> > +
>
> Are these going to grow more complex? Otherwise looks fine,
No. These were just because I was using similar inlines elsewhere and
wanted a bit of consistency when introducing manual bit operations for
READ_ONCE().
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 55/55] Revert "drm/i915: Clean up associated VMAs on context destruction"
2016-07-25 17:32 ` [PATCH 55/55] Revert "drm/i915: Clean up associated VMAs on context destruction" Chris Wilson
@ 2016-07-27 10:18 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:18 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> This reverts commit e9f24d5fb7cf3628b195b18ff3ac4e37937ceeae.
>
> The patch was only a stop-gap measure that fixed half the problem - the
> leak of the fbcon when restarting X. A complete solution required
> releasing the VMA when the object itself was closed rather than rely on
> file/process exit. The previous patches add the VMA tracking necessary
> to do close them along with the object, context or file, and so the time
> has come to remove the partial fix.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
With the improvements in tracking, makes sense.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 -----
> drivers/gpu/drm/i915/i915_gem.c | 14 ++------------
> drivers/gpu/drm/i915/i915_gem_context.c | 22 ----------------------
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> 4 files changed, 3 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c6c64003504f..40033ca30e55 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3044,11 +3044,6 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
> u32 flags);
> void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
> int __must_check i915_vma_unbind(struct i915_vma *vma);
> -/*
> - * BEWARE: Do not use the function below unless you can _absolutely_
> - * _guarantee_ VMA in question is _not in use_ anywhere.
> - */
> -int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
> void i915_vma_close(struct i915_vma *vma);
> void i915_vma_destroy(struct i915_vma *vma);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 0d9a80b41101..e3278f4e1ad2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2810,7 +2810,7 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
> vma->iomap = NULL;
> }
>
> -static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
> +int i915_vma_unbind(struct i915_vma *vma)
> {
> struct drm_i915_gem_object *obj = vma->obj;
> unsigned long active;
> @@ -2820,7 +2820,7 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
> * have side-effects such as unpinning or even unbinding this vma.
> */
> active = vma->active;
> - if (active && wait) {
> + if (active) {
> int idx;
>
> /* When a closed VMA is retired, it is unbound - eek.
> @@ -2902,16 +2902,6 @@ destroy:
> return 0;
> }
>
> -int i915_vma_unbind(struct i915_vma *vma)
> -{
> - return __i915_vma_unbind(vma, true);
> -}
> -
> -int __i915_vma_unbind_no_wait(struct i915_vma *vma)
> -{
> - return __i915_vma_unbind(vma, false);
> -}
> -
> int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
> {
> struct intel_engine_cs *engine;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 1ba6c0bb856a..e9da8aaaa41d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -134,21 +134,6 @@ static int get_context_size(struct drm_i915_private *dev_priv)
> return ret;
> }
>
> -static void i915_gem_context_clean(struct i915_gem_context *ctx)
> -{
> - struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
> - struct i915_vma *vma, *next;
> -
> - if (!ppgtt)
> - return;
> -
> - list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
> - vm_link) {
> - if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
> - break;
> - }
> -}
> -
> void i915_gem_context_free(struct kref *ctx_ref)
> {
> struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
> @@ -158,13 +143,6 @@ void i915_gem_context_free(struct kref *ctx_ref)
> trace_i915_context_free(ctx);
> GEM_BUG_ON(!ctx->closed);
>
> - /*
> - * This context is going away and we need to remove all VMAs still
> - * around. This is to handle imported shared objects for which
> - * destructor did not run when their handles were closed.
> - */
> - i915_gem_context_clean(ctx);
> -
> i915_ppgtt_put(ctx->ppgtt);
>
> for (i = 0; i < I915_NUM_ENGINES; i++) {
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d2130da3de9d..e19a5fd5f15f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3365,7 +3365,7 @@ void i915_vma_close(struct i915_vma *vma)
>
> list_del_init(&vma->obj_link);
> if (!i915_vma_is_active(vma) && !vma->pin_count)
> - WARN_ON(__i915_vma_unbind_no_wait(vma));
> + WARN_ON(i915_vma_unbind(vma));
> }
>
> static struct i915_vma *
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 32/55] drm/i915: Split early global GTT initialisation
2016-07-26 7:42 ` Chris Wilson
@ 2016-07-27 10:20 ` Joonas Lahtinen
2016-07-27 10:34 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ti, 2016-07-26 at 08:42 +0100, Chris Wilson wrote:
> On Tue, Jul 26, 2016 at 10:08:32AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > >
> > > -/**
> > > - * i915_gem_init_ggtt - Initialize GEM for Global GTT
> > > - * @dev: DRM device
> > > - */
> > > -void i915_gem_init_ggtt(struct drm_device *dev)
> > >
> > > +static void init_global_gtt(struct drm_i915_private *dev_priv)
> > Why not s/global_gtt/ggtt/ for easier grepping.
> init_global_vm() so that you don't think it is just about the ggtt.
Agreed.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 54/55] drm/i915: Mark the context and address space as closed
2016-07-27 10:13 ` Joonas Lahtinen
@ 2016-07-27 10:27 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 10:27 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 01:13:54PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -907,6 +907,7 @@ struct i915_gem_context {
> > struct list_head link;
> >
> > u8 remap_slice;
> > + bool closed:1;
>
> Not a whole bool? I think it could be.
Why? It's read mostly. So a bitfield is not going to adverse affect code
size or add rmw.
> > +static void i915_ppgtt_close(struct i915_address_space *vm)
> > +{
> > + struct list_head *phases[] = {
> > + &vm->active_list,
> > + &vm->inactive_list,
> > + &vm->unbound_list,
> > + NULL,
> > + }, **phase;
> > +
> > + GEM_BUG_ON(vm->closed);
> > + vm->closed = true;
> > +
> > + for (phase = phases; *phase; phase++) {
> > + struct i915_vma *vma, *vn;
> > +
> > + list_for_each_entry_safe(vma, vn, *phase, vm_link)
> > + if (!vma->closed)
> > + i915_vma_close(vma);
> > + }
>
> Pretty sure rather listing three three function calls here would be
> nicer;
>
> i915_ppgtt_do_close(vm->active_list);
> i915_ppgtt_do_close(vm->inactive_list);
But with the above loop structure the compiler generates reasonable code.
That's relevant for improving code generation for eviction later.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 32/55] drm/i915: Split early global GTT initialisation
2016-07-27 10:20 ` Joonas Lahtinen
@ 2016-07-27 10:34 ` Chris Wilson
2016-07-27 11:09 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 10:34 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 01:20:42PM +0300, Joonas Lahtinen wrote:
> On ti, 2016-07-26 at 08:42 +0100, Chris Wilson wrote:
> > On Tue, Jul 26, 2016 at 10:08:32AM +0300, Joonas Lahtinen wrote:
> > >
> > > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > > >
> > > > -/**
> > > > - * i915_gem_init_ggtt - Initialize GEM for Global GTT
> > > > - * @dev: DRM device
> > > > - */
> > > > -void i915_gem_init_ggtt(struct drm_device *dev)
> > > >
> > > > +static void init_global_gtt(struct drm_i915_private *dev_priv)
> > > Why not s/global_gtt/ggtt/ for easier grepping.
> > init_global_vm() so that you don't think it is just about the ggtt.
>
> Agreed.
I ended up inlining it :|
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-27 7:04 ` Chris Wilson
@ 2016-07-27 10:40 ` Joonas Lahtinen
2016-07-27 10:48 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:40 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-07-27 at 08:04 +0100, Chris Wilson wrote:
> On Wed, Jul 27, 2016 at 09:04:03AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > >
> > > Tidy up the for loops that handle waiting for read/write vs read-only
> > > access.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > ---
> > > drivers/gpu/drm/i915/i915_gem.c | 158 +++++++++++++++++++---------------------
> > > 1 file changed, 75 insertions(+), 83 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > index 3f6b69dcaccb..2d86a0c3f295 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -1339,6 +1339,23 @@ put_rpm:
> > > return ret;
> > > }
> > >
> > > +static void
> > > +i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> > > + struct drm_i915_gem_request *req)
> > > +{
> > > + int idx = req->engine->id;
> > > +
> > > + if (i915_gem_active_peek(&obj->last_read[idx],
> > > + &obj->base.dev->struct_mutex) == req)
> > > + i915_gem_object_retire__read(obj, idx);
> > > + else if (i915_gem_active_peek(&obj->last_write,
> > > + &obj->base.dev->struct_mutex) == req)
> > > + i915_gem_object_retire__write(obj);
> > If these functions will use same mutex (be it different than
> > struct_mutex) in all invocations, I'd make an alias for it.
> Why? It is written like this to prevent the compiler doing anything when
> not debugging.
What debuggin related is there, could you elborate? (PS. A branch would
help having the big picture clearer).
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-27 7:07 ` Chris Wilson
@ 2016-07-27 10:42 ` Joonas Lahtinen
2016-07-27 17:34 ` Chris Wilson
0 siblings, 1 reply; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:42 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-07-27 at 08:07 +0100, Chris Wilson wrote:
> >
> > > + active = obj->last_read;
> > > + active_mask = obj->active;
> > > } else {
> > > - for (i = 0; i < I915_NUM_ENGINES; i++) {
> > > - request = i915_gem_active_peek(&obj->last_read[i],
> > > - &obj->base.dev->struct_mutex);
> > > - if (!request)
> > > - continue;
> > > + active_mask = 1;
> >
> > Wouldn't we have RENDER_RING define for this and other instances?
>
> ?
Defining a mask with first bit set is not very informative, is it?
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-27 10:40 ` Joonas Lahtinen
@ 2016-07-27 10:48 ` Chris Wilson
0 siblings, 0 replies; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 10:48 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 01:40:06PM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-27 at 08:04 +0100, Chris Wilson wrote:
> > On Wed, Jul 27, 2016 at 09:04:03AM +0300, Joonas Lahtinen wrote:
> > >
> > > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > > >
> > > > Tidy up the for loops that handle waiting for read/write vs read-only
> > > > access.
> > > >
> > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_gem.c | 158 +++++++++++++++++++---------------------
> > > > 1 file changed, 75 insertions(+), 83 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > > index 3f6b69dcaccb..2d86a0c3f295 100644
> > > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > > @@ -1339,6 +1339,23 @@ put_rpm:
> > > > return ret;
> > > > }
> > > >
> > > > +static void
> > > > +i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> > > > + struct drm_i915_gem_request *req)
> > > > +{
> > > > + int idx = req->engine->id;
> > > > +
> > > > + if (i915_gem_active_peek(&obj->last_read[idx],
> > > > + &obj->base.dev->struct_mutex) == req)
> > > > + i915_gem_object_retire__read(obj, idx);
> > > > + else if (i915_gem_active_peek(&obj->last_write,
> > > > + &obj->base.dev->struct_mutex) == req)
> > > > + i915_gem_object_retire__write(obj);
> > > If these functions will use same mutex (be it different than
> > > struct_mutex) in all invocations, I'd make an alias for it.
> > Why? It is written like this to prevent the compiler doing anything when
> > not debugging.
>
> What debuggin related is there, could you elborate? (PS. A branch would
> help having the big picture clearer).
The mutex is only used for debug annotations.
See https://cgit.freedesktop.org/~ickle/linux-2.6/log/?h=tasklet
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 43/55] drm/i915: Refactor activity tracking for requests
2016-07-27 7:57 ` Chris Wilson
@ 2016-07-27 10:55 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-07-27 at 08:57 +0100, Chris Wilson wrote:
> On Wed, Jul 27, 2016 at 10:40:14AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > >
> > > @@ -172,6 +176,24 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> > > */
> > > request->ring->last_retired_head = request->postfix;
> > >
> > > + /* Walk through the active list, calling retire on each. This allows
> > > + * objects to track their GPU activity and mark themselves as idle
> > > + * when their *last* active request is completed (updating state
> > > + * tracking lists for eviction, active references for GEM, etc).
> > > + *
> > > + * As the ->retire() may free the node, we decouple it first and
> > > + * pass along the auxiliary information (to avoid dereferencing
> > > + * the node after the callback).
> > > + */
> > > + list_for_each_entry_safe(active, next, &request->active_list, link) {
> > > + prefetchw(next);
> > Would not this be an improvement to go to list_for_each_entry{,_safe}
> > rather?
> It's been tried before. It's not a universal improvement. This loop is
> one of the top functions in the profiles when handling large request
> objects, with perf implying that the memory loads are where our time
> goes..
This maybe worth a comment on top of the prefetchw.
> > > @@ -705,10 +723,13 @@ int i915_wait_request(struct drm_i915_gem_request *req)
> > > {
> > > int ret;
> > >
> > > - GEM_BUG_ON(!req);
> > > lockdep_assert_held(&req->i915->drm.struct_mutex);
> > > + GEM_BUG_ON(list_empty(&req->link));
> > Humm, why no waiting on requests without the tracker object? Or then
> > need to use __i915_wait_request? Kerneldoc might be useful.
> ?
>
>
Ok, question was maybe irrelevant reading another round.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking
2016-07-27 8:22 ` Chris Wilson
2016-07-27 8:34 ` Chris Wilson
@ 2016-07-27 10:59 ` Joonas Lahtinen
1 sibling, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 10:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-07-27 at 09:22 +0100, Chris Wilson wrote:
> On Wed, Jul 27, 2016 at 11:12:32AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > >
> > > -static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
> > > +static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
> > > + struct drm_i915_gem_request *req)
> > > {
> > > + struct intel_overlay *overlay =
> > > + container_of(active, typeof(*overlay), last_flip);
> > > struct drm_i915_gem_object *obj = overlay->old_vid_bo;
> > >
> > > + i915_gem_track_fb(obj, NULL,
> > > + INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
> > > +
> > Previously this call was after the below calls and old_vid_bo was
> > always NULL, does this fix a bug?
> Yes.
> https://bugs.freedesktop.org/show_bug.cgi?id=93730
> and a recent one.
>
Maybe link it in headers?
Noticed your another e-mail too,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
2016-07-26 8:19 ` Chris Wilson
@ 2016-07-27 11:08 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 11:08 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ti, 2016-07-26 at 09:19 +0100, Chris Wilson wrote:
> On Tue, Jul 26, 2016 at 07:59:29AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> >
> > >
> > > Inside the error capture itself, we refer to not only the hardware
> > > engine, its ringbuffer but also the capture state. Finding clear names
> > > for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
> > > compromise we keep using ering for the error capture.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-chris@chris-wilson.co.uk
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 6 +-
> > > drivers/gpu/drm/i915/i915_gpu_error.c | 255 +++++++++++++++++-----------------
> > > 2 files changed, 134 insertions(+), 127 deletions(-)
> > >
> >
> >
> > >
> > > @@ -240,69 +240,71 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
> > > }
> > >
> > > static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
> > > - struct drm_device *dev,
> > > - struct drm_i915_error_state *error,
> > > - int ring_idx)
> > > + struct drm_device *dev,
> > > + struct drm_i915_error_state *error,
> > > + int engine_idx)
> > > {
> > > - struct drm_i915_error_ring *ring = &error->ring[ring_idx];
> > > + struct drm_i915_error_engine *ering = &error->engine[engine_idx];
> > >
> > I'd be inclined keeping the struct and variable names close, so rather
> > eengine. Even though the error state is a mashup. We fill the ring
> > state to the engine error state. Function could be
> > i915_engine_error_ring_state() or so, to "reduce" confusion?
> i915_error_print_engine()
>
Fine.
> (We may eventually get to the point where the capture/error functions
> are clearly and distinctly labelled!)
>
> >
> >
> > >
> > > @@ -414,7 +416,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> > > if (IS_GEN7(dev))
> > > err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
> > >
> > > - for (i = 0; i < ARRAY_SIZE(error->ring); i++)
> > > + for (i = 0; i < ARRAY_SIZE(error->engine); i++)
> > > i915_ring_error_state(m, dev, error, i);
> > >
> > This captures the engine related ring state, I think it's even worth a
> > comment when there is engine vs. error disparity.
> This becomes
>
> for (i = 0; i < ARRAY_SIZE(error->engine); i++)
> i915_error_print_engine(m, &error->engine[i]);
>
> >
> > And how about the messages? Should we update them more agressively
> > where necessary.
> Ignoring the tautology in engine->name, in the actual error print the
> only times we explicitly refer to ring we do mean the ring.
Ack, Joonas
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 32/55] drm/i915: Split early global GTT initialisation
2016-07-27 10:34 ` Chris Wilson
@ 2016-07-27 11:09 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-27 11:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-07-27 at 11:34 +0100, Chris Wilson wrote:
> On Wed, Jul 27, 2016 at 01:20:42PM +0300, Joonas Lahtinen wrote:
> >
> > On ti, 2016-07-26 at 08:42 +0100, Chris Wilson wrote:
> > >
> > > On Tue, Jul 26, 2016 at 10:08:32AM +0300, Joonas Lahtinen wrote:
> > > >
> > > >
> > > > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > > > >
> > > > >
> > > > > -/**
> > > > > - * i915_gem_init_ggtt - Initialize GEM for Global GTT
> > > > > - * @dev: DRM device
> > > > > - */
> > > > > -void i915_gem_init_ggtt(struct drm_device *dev)
> > > > >
> > > > > +static void init_global_gtt(struct drm_i915_private *dev_priv)
> > > > Why not s/global_gtt/ggtt/ for easier grepping.
> > > init_global_vm() so that you don't think it is just about the ggtt.
> > Agreed.
> I ended up inlining it :|
Well, we'll live with that, too.
Regards, Joonas
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-27 10:42 ` Joonas Lahtinen
@ 2016-07-27 17:34 ` Chris Wilson
2016-07-28 6:40 ` Joonas Lahtinen
0 siblings, 1 reply; 124+ messages in thread
From: Chris Wilson @ 2016-07-27 17:34 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Wed, Jul 27, 2016 at 01:42:13PM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-27 at 08:07 +0100, Chris Wilson wrote:
> > >
> > > > + active = obj->last_read;
> > > > + active_mask = obj->active;
> > > > } else {
> > > > - for (i = 0; i < I915_NUM_ENGINES; i++) {
> > > > - request = i915_gem_active_peek(&obj->last_read[i],
> > > > - &obj->base.dev->struct_mutex);
> > > > - if (!request)
> > > > - continue;
> > > > + active_mask = 1;
> > >
> > > Wouldn't we have RENDER_RING define for this and other instances?
> >
> > ?
>
> Defining a mask with first bit set is not very informative, is it?
Just for clarification to the list:
This doesn't correspond to any engine, but that the array of active[] is
only of size 1. The first branch iterates over
last_read[I915_NUM_ENGINES] for which we track the current active_mask.
The second branch iterates over last_write[1] for which we have no
shortcut, and so assign the mask the value 1.
-Chris
--
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^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 40/55] drm/i915: Refactor blocking waits
2016-07-27 17:34 ` Chris Wilson
@ 2016-07-28 6:40 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-28 6:40 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-07-27 at 18:34 +0100, Chris Wilson wrote:
> On Wed, Jul 27, 2016 at 01:42:13PM +0300, Joonas Lahtinen wrote:
> >
> > On ke, 2016-07-27 at 08:07 +0100, Chris Wilson wrote:
> > >
> > > >
> > > >
> > > > >
> > > > > + active = obj->last_read;
> > > > > + active_mask = obj->active;
> > > > > } else {
> > > > > - for (i = 0; i < I915_NUM_ENGINES; i++) {
> > > > > - request = i915_gem_active_peek(&obj->last_read[i],
> > > > > - &obj->base.dev->struct_mutex);
> > > > > - if (!request)
> > > > > - continue;
> > > > > + active_mask = 1;
> > > >
> > > > Wouldn't we have RENDER_RING define for this and other instances?
> > > ?
> > Defining a mask with first bit set is not very informative, is it?
> Just for clarification to the list:
>
> This doesn't correspond to any engine, but that the array of active[] is
> only of size 1. The first branch iterates over
> last_read[I915_NUM_ENGINES] for which we track the current active_mask.
> The second branch iterates over last_write[1] for which we have no
> shortcut, and so assign the mask the value 1.
Right, now got it.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 53/55] drm/i915: Release vma when the handle is closed
2016-07-27 10:13 ` Chris Wilson
@ 2016-07-28 7:16 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-28 7:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-07-27 at 11:13 +0100, Chris Wilson wrote:
> On Wed, Jul 27, 2016 at 01:00:59PM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > >
> > > /**
> > > * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
> > > * @dev: drm device pointer
> > > @@ -2810,26 +2823,32 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
> > > if (active && wait) {
> > > int idx;
> > >
> > > + /* When a closed VMA is retired, it is unbound - eek.
> > > + * In order to prevent it from being recursively closed,
> > > + * take a pin on the vma so that the second unbind is
> > > + * aborted.
> > > + */
> > > + vma->pin_count++;
> > Always smells fishy. But an extra variable probably not worthy.
> >
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index ef0dc7131808..bfac2448ba04 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -3339,6 +3339,31 @@ i915_vma_retire(struct i915_gem_active *active,
> > > return;
> > >
> > > list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
> > > + if (unlikely(vma->closed && !vma->pin_count))
> > > + WARN_ON(i915_vma_unbind(vma));
> > So this is just an optimization to get rid of the VMA ASAP if we're
> > lucky?
> Not quite. Think of this as the active reference, this may be the last
> point at which we see the closed vma. If we don't free it now, we leak
> the VMA until the object is closed - where if we meet it we BUG.
>
> >
> > >
> > > +void i915_vma_close(struct i915_vma *vma)
> > > +{
> > > + GEM_BUG_ON(vma->closed);
> > > + vma->closed = true;
> > > +
> > > + list_del_init(&vma->obj_link);
> > > + if (!i915_vma_is_active(vma) && !vma->pin_count)
> > > + WARN_ON(__i915_vma_unbind_no_wait(vma));
> > Same here, an optimization?
> Same as above. This time we know the vma is inactive, so no outstanding
> reference.
Ok,
We have the BUG in place if something slips through the cracks, so
should be good.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking
2016-07-26 8:28 ` Chris Wilson
@ 2016-07-28 7:21 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-28 7:21 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ti, 2016-07-26 at 09:28 +0100, Chris Wilson wrote:
> On Tue, Jul 26, 2016 at 11:23:44AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > >
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -155,10 +155,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> > > obj->base.write_domain);
> > > for_each_engine_id(engine, dev_priv, id)
> > > seq_printf(m, "%x ",
> > > - i915_gem_request_get_seqno(obj->last_read_req[id]));
> > > + i915_gem_request_get_seqno(obj->last_read[id].request));
> > I hate i915_gem_request_get_seqno already, it's just NULL protection,
> > but subject to different patch. Although, I see you got rid
> > of i915_gem_request_get_engine already.
> >
> > >
> > > @@ -2383,10 +2383,10 @@ void i915_vma_move_to_active(struct i915_vma *vma,
> > > static void
> > > i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> > > {
> > > - GEM_BUG_ON(obj->last_write_req == NULL);
> > > - GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
> > > + GEM_BUG_ON(!obj->last_write.request);
> > > + GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write.request->engine)));
> > Over 80 ch line.
> Don't care in this patch.
>
> >
> > intel_engine_flag seems rather dull, there's also this thing called
> > BIT(), but again subject to another series.
> >
> > >
> > > @@ -2395,13 +2395,13 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> > > {
> > > struct i915_vma *vma;
> > >
> > > - GEM_BUG_ON(obj->last_read_req[idx] == NULL);
> > > + GEM_BUG_ON(!obj->last_read[idx].request);
> > > GEM_BUG_ON(!(obj->active & (1 << idx)));
> > BIT(idx)?
> Not in this patch.
> >
> >
> > >
> > > +/* We treat requests as fences. This is not be to confused with our
> > > + * "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
> > > + * We use the fences to synchronize access from the CPU with activity on the
> > > + * GPU, for example, we should not rewrite an object's PTE whilst the GPU
> > > + * is reading them. We also track fences at a higher level to provide
> > > + * implicit synchronisation around GEM objects, e.g. set-domain will wait
> > > + * for outstanding GPU rendering before marking the object ready for CPU
> > > + * access, or a pageflip will wait until the GPU is complete before showing
> > > + * the frame on the scanout.
> > > + *
> > > + * In order to use a fence, the object must track the fence it needs to
> > > + * serialise with. For example, GEM objects want to track both read and
> > > + * write access so that we can perform concurrent read operations between
> > > + * the CPU and GPU engines, as well as waiting for all rendering to
> > > + * complete, or waiting for the last GPU user of a "fence register". The
> > > + * object then embeds a @i915_gem_active to track the most recent (in
> > > + * retirment order) request relevant for the desired mode of access.
> > > + * The @i915_gem_active is updated with i915_gem_request_mark_active() to
> > > + * track the most recent fence request, typically this is done as part of
> > > + * i915_vma_move_to_active().
> > > + *
> > > + * When the @i915_gem_active completes (is retired), it will
> > > + * signal its completion to the owner through a callback as well as mark
> > > + * itself as idle (i915_gem_active.request == NULL). The owner
> > > + * can then perform any action, such as delayed freeing of an active
> > > + * resource including itself.
> > > + */
> > > +struct i915_gem_active {
> > Not sure if this is a good descriptive struct name. Would not this be
> > in the sync terminology a fence? active.request reads nicely though.
> No. The active.request is the fence, this keeps track of the most recent
> fence we are interested in.
>
> >
> > >
> > > + struct drm_i915_gem_request *request;
> > > +};
> > > +
> > > +static inline void
> > > +i915_gem_active_set(struct i915_gem_active *active,
> > > + struct drm_i915_gem_request *request)
> > > +{
> > > + i915_gem_request_assign(&active->request, request);
> > > +}
> > > +
> > > +#define for_each_active(mask, idx) \
> > > + for (; mask ? idx = ffs(mask) - 1, 1 : 0; mask &= ~(1 << idx))
> > BIT()
> >
> > >
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -11378,7 +11378,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
> > > if (resv && !reservation_object_test_signaled_rcu(resv, false))
> > > return true;
> > >
> > > - return engine != i915_gem_request_get_engine(obj->last_write_req);
> > > + return engine != i915_gem_request_get_engine(obj->last_write.request);
> > What's been the obsession with NULL protecting simple accessor
> > functions? Makes the code look overly complicated. One more function to
> > nuke.
> That was against my wishes. This patch was only to introduce the new
> struct, actually making use of it comes later.
As noticed already in later patch the lines get removed,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
* Re: [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation
2016-07-26 9:06 ` Chris Wilson
@ 2016-07-28 7:26 ` Joonas Lahtinen
0 siblings, 0 replies; 124+ messages in thread
From: Joonas Lahtinen @ 2016-07-28 7:26 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ti, 2016-07-26 at 10:06 +0100, Chris Wilson wrote:
> On Tue, Jul 26, 2016 at 11:54:16AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> > >
> > > The future annotations will track the locking used for access to ensure
> > > that it is always sufficient. We make the preparations now to present
> > > the API ahead and to make sure that GCC can eliminate the unused
> > > parameter.
> > >
> > Is it at some point going to be other than struct_mutex?
> Yes.
>
> >
> > I do not feel
> > the API change intuitive at all as it is.
> The API change here is solely for RCU markup later, i.e. we can access
> the active.request lockless but have to be very careful when we do.
>
> >
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index b41561bdfb85..16fa1f527ef5 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -155,10 +155,13 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> > > obj->base.write_domain);
> > > for_each_engine_id(engine, dev_priv, id)
> > > seq_printf(m, "%x ",
> > > - i915_gem_active_get_seqno(&obj->last_read[id]));
> > > + i915_gem_active_get_seqno(&obj->last_read[id],
> > > + &obj->base.dev->struct_mutex));
> > In functions where you use plenty of this, maybe make struct_mutex
> > alias. But before that, what's wrong with passing dev_priv?
> What dev_priv? See earlier answer about this should not be struct_mutex
> in the long run.
Ok, then it's acceptable intermediary state.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 124+ messages in thread
end of thread, other threads:[~2016-07-28 7:26 UTC | newest]
Thread overview: 124+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-25 17:31 Fix the vma leak Chris Wilson
2016-07-25 17:31 ` [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Chris Wilson
2016-07-26 5:07 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 02/55] drm/i915: Prefer list_first_entry_or_null Chris Wilson
2016-07-25 17:31 ` [PATCH 03/55] drm/i915: Only clear the client pointer when tearing down the file Chris Wilson
2016-07-25 17:31 ` [PATCH 04/55] drm/i915: Only drop the batch-pool's object reference Chris Wilson
2016-07-25 17:31 ` [PATCH 05/55] drm/i915/cmdparser: Remove stray intel_engine_cs *ring Chris Wilson
2016-07-25 17:31 ` [PATCH 06/55] drm/i915: Use engine to refer to the user's BSD intel_engine_cs Chris Wilson
2016-07-25 17:31 ` [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture Chris Wilson
2016-07-26 4:59 ` Joonas Lahtinen
2016-07-26 8:19 ` Chris Wilson
2016-07-27 11:08 ` Joonas Lahtinen
2016-07-26 10:21 ` [PATCH v2] " Chris Wilson
2016-07-26 12:35 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c Chris Wilson
2016-07-26 5:02 ` Joonas Lahtinen
2016-07-26 8:12 ` Chris Wilson
2016-07-27 6:12 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 09/55] drm/i915: Update a couple of hangcheck comments to talk about engines Chris Wilson
2016-07-25 17:31 ` [PATCH 10/55] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit Chris Wilson
2016-07-25 17:31 ` [PATCH 11/55] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
2016-07-25 17:31 ` [PATCH 12/55] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
2016-07-25 17:31 ` [PATCH 13/55] drm/i915: Rename struct intel_ringbuffer to struct intel_ring Chris Wilson
2016-07-25 17:31 ` [PATCH 14/55] drm/i915: Rename residual ringbuf parameters Chris Wilson
2016-07-25 17:31 ` [PATCH 15/55] drm/i915: Rename intel_pin_and_map_ring() Chris Wilson
2016-07-25 17:31 ` [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty Chris Wilson
2016-07-26 5:06 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request Chris Wilson
2016-07-26 5:09 ` Joonas Lahtinen
2016-07-25 17:31 ` [PATCH 18/55] drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START Chris Wilson
2016-07-25 17:31 ` [PATCH 19/55] drm/i915: Remove intel_ring_get_tail() Chris Wilson
2016-07-25 17:31 ` [PATCH 20/55] drm/i915: Convert engine->write_tail to operate on a request Chris Wilson
2016-07-25 17:32 ` [PATCH 21/55] drm/i915: Unify request submission Chris Wilson
2016-07-25 17:32 ` [PATCH 22/55] drm/i915/lrc: Update function names to match request flow Chris Wilson
2016-07-25 17:32 ` [PATCH 23/55] drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal() Chris Wilson
2016-07-25 17:32 ` [PATCH 24/55] drm/i915: Reuse legacy breadcrumbs + tail emission Chris Wilson
2016-07-25 17:32 ` [PATCH 25/55] drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores Chris Wilson
2016-07-25 17:32 ` [PATCH 26/55] drm/i915: Remove duplicate golden render state init from execlists Chris Wilson
2016-07-25 17:32 ` [PATCH 27/55] drm/i915: Refactor golden render state emission to unconfuse gcc Chris Wilson
2016-07-25 17:32 ` [PATCH 28/55] drm/i915: Unify legacy/execlists submit_execbuf callbacks Chris Wilson
2016-07-25 17:32 ` [PATCH 29/55] drm/i915: Simplify calling engine->sync_to Chris Wilson
2016-07-25 17:32 ` [PATCH 30/55] drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals Chris Wilson
2016-07-25 17:32 ` [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers Chris Wilson
2016-07-26 5:15 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 32/55] drm/i915: Split early global GTT initialisation Chris Wilson
2016-07-26 7:08 ` Joonas Lahtinen
2016-07-26 7:42 ` Chris Wilson
2016-07-27 10:20 ` Joonas Lahtinen
2016-07-27 10:34 ` Chris Wilson
2016-07-27 11:09 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 33/55] drm/i915: Store owning file on the i915_address_space Chris Wilson
2016-07-26 7:15 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 34/55] drm/i915: Count how many VMA are bound for an object Chris Wilson
2016-07-26 7:44 ` Joonas Lahtinen
2016-07-26 8:02 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 35/55] drm/i915: Be more careful when unbinding vma Chris Wilson
2016-07-26 7:59 ` Joonas Lahtinen
2016-07-26 8:08 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 36/55] drm/i915: Kill drop_pages() Chris Wilson
2016-07-25 17:32 ` [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking Chris Wilson
2016-07-26 8:23 ` Joonas Lahtinen
2016-07-26 8:28 ` Chris Wilson
2016-07-28 7:21 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations Chris Wilson
2016-07-26 8:50 ` Joonas Lahtinen
2016-07-26 9:03 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation Chris Wilson
2016-07-26 8:54 ` Joonas Lahtinen
2016-07-26 9:06 ` Chris Wilson
2016-07-28 7:26 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 40/55] drm/i915: Refactor blocking waits Chris Wilson
2016-07-27 6:04 ` Joonas Lahtinen
2016-07-27 7:04 ` Chris Wilson
2016-07-27 10:40 ` Joonas Lahtinen
2016-07-27 10:48 ` Chris Wilson
2016-07-27 7:07 ` Chris Wilson
2016-07-27 10:42 ` Joonas Lahtinen
2016-07-27 17:34 ` Chris Wilson
2016-07-28 6:40 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 41/55] drm/i915: Rename request->list to link for consistency Chris Wilson
2016-07-26 9:26 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active() Chris Wilson
2016-07-26 9:31 ` Joonas Lahtinen
2016-07-26 9:47 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 43/55] drm/i915: Refactor activity tracking for requests Chris Wilson
2016-07-27 7:40 ` Joonas Lahtinen
2016-07-27 7:57 ` Chris Wilson
2016-07-27 10:55 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 44/55] drm/i915: Track requests inside each intel_ring Chris Wilson
2016-07-26 10:10 ` Joonas Lahtinen
2016-07-26 10:15 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking Chris Wilson
2016-07-27 8:12 ` Joonas Lahtinen
2016-07-27 8:22 ` Chris Wilson
2016-07-27 8:34 ` Chris Wilson
2016-07-27 10:59 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 46/55] drm/i915: Move the special case wait-request handling to its one caller Chris Wilson
2016-07-26 12:39 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine Chris Wilson
2016-07-26 12:40 ` Joonas Lahtinen
2016-07-26 13:11 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 48/55] drm/i915: s/__i915_wait_request/i915_wait_request/ Chris Wilson
2016-07-26 12:42 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 49/55] drm/i915: Double check activity before relocations Chris Wilson
2016-07-26 12:45 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c Chris Wilson
2016-07-26 12:48 ` Joonas Lahtinen
2016-07-26 13:39 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 51/55] drm/i915: i915_vma_move_to_active prep patch Chris Wilson
2016-07-26 12:53 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 52/55] drm/i915: Track active vma requests Chris Wilson
2016-07-27 9:47 ` Joonas Lahtinen
2016-07-27 10:15 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 53/55] drm/i915: Release vma when the handle is closed Chris Wilson
2016-07-27 10:00 ` Joonas Lahtinen
2016-07-27 10:13 ` Chris Wilson
2016-07-28 7:16 ` Joonas Lahtinen
2016-07-25 17:32 ` [PATCH 54/55] drm/i915: Mark the context and address space as closed Chris Wilson
2016-07-27 10:13 ` Joonas Lahtinen
2016-07-27 10:27 ` Chris Wilson
2016-07-25 17:32 ` [PATCH 55/55] Revert "drm/i915: Clean up associated VMAs on context destruction" Chris Wilson
2016-07-27 10:18 ` Joonas Lahtinen
2016-07-26 5:18 ` ✗ Ro.CI.BAT: warning for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() Patchwork
2016-07-26 10:48 ` ✗ Ro.CI.BAT: failure for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() (rev2) Patchwork
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