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* [PATCH 1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM
@ 2016-07-29 14:57 ville.syrjala
  2016-07-29 14:57 ` [PATCH 2/2] drm/i915: Program FW_BLC_SELF on 915G as well ville.syrjala
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: ville.syrjala @ 2016-07-29 14:57 UTC (permalink / raw)
  To: intel-gfx; +Cc: Daniel Vetter

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bspec says:
"FW_BLC_SELF
 ...
 Programming Note [DevALV] and [DevCST]: When calculating watermark
 values for 15/16bpp, assume 32bpp for purposes of calculation using
 the high priority bandwidth analysis spreadsheet."

Let's do that.

Perhaps this might even help with the problem that resulted in
commit 2ab1bc9df01d ("drm/i915: Disable self-refresh for untiled fbs on i915gm")

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1ac32428d4db..8cfef7683088 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1604,6 +1604,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 		unsigned long line_time_us;
 		int entries;
 
+		if (IS_I915GM(dev) || IS_I945GM(dev))
+			cpp = 4;
+
 		line_time_us = max(htotal * 1000 / clock, 1);
 
 		/* Use ns/us then divide to preserve precision */
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: Program FW_BLC_SELF on 915G as well
  2016-07-29 14:57 [PATCH 1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM ville.syrjala
@ 2016-07-29 14:57 ` ville.syrjala
  2016-07-29 16:40   ` Chris Wilson
  2016-07-29 15:21 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM Patchwork
  2016-07-29 16:32 ` [PATCH 1/2] " Chris Wilson
  2 siblings, 1 reply; 7+ messages in thread
From: ville.syrjala @ 2016-07-29 14:57 UTC (permalink / raw)
  To: intel-gfx; +Cc: Daniel Vetter

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

According to Bspec FW_BLC_SELF exists on 915G also. Let's program it.
The only open question is whether there's is a memory self-refresh
enable bit somewhere as well. For 945G/GM it's in FW_BLC_SELF, for
915GM it's in INSTPM. For 915G I can't find one in the docs. Let's drop
a FIXME about this, in case someone with the hardware is ever bored
enough to look for it.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8cfef7683088..eb1f9ba52180 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -340,6 +340,11 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 		I915_WRITE(FW_BLC_SELF, val);
 		POSTING_READ(FW_BLC_SELF);
 	} else if (IS_I915GM(dev)) {
+		/*
+		 * FIXME can't find a bit like this for 915G, and
+		 * and yet it does have the related watermark in
+		 * FW_BLC_SELF. What's going on?
+		 */
 		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 		I915_WRITE(INSTPM, val);
@@ -1621,7 +1626,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 		if (IS_I945G(dev) || IS_I945GM(dev))
 			I915_WRITE(FW_BLC_SELF,
 				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
-		else if (IS_I915GM(dev))
+		else
 			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
 	}
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM
  2016-07-29 14:57 [PATCH 1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM ville.syrjala
  2016-07-29 14:57 ` [PATCH 2/2] drm/i915: Program FW_BLC_SELF on 915G as well ville.syrjala
@ 2016-07-29 15:21 ` Patchwork
  2016-08-02 13:19   ` Ville Syrjälä
  2016-07-29 16:32 ` [PATCH 1/2] " Chris Wilson
  2 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2016-07-29 15:21 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM
URL   : https://patchwork.freedesktop.org/series/10392/
State : failure

== Summary ==

Series 10392v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/10392/revisions/1/mbox

Test drv_module_reload_basic:
                skip       -> PASS       (ro-ivb-i7-3770)
                skip       -> PASS       (ro-skl3-i5-6260u)
Test kms_cursor_legacy:
        Subgroup basic-cursor-vs-flip-legacy:
                fail       -> PASS       (ro-ilk1-i5-650)
        Subgroup basic-cursor-vs-flip-varying-size:
                pass       -> FAIL       (ro-ilk1-i5-650)
        Subgroup basic-flip-vs-cursor-legacy:
                pass       -> FAIL       (ro-bdw-i5-5250u)
        Subgroup basic-flip-vs-cursor-varying-size:
                fail       -> PASS       (ro-skl3-i5-6260u)

fi-kbl-qkkr      total:239  pass:181  dwarn:29  dfail:0   fail:3   skip:26 
fi-skl-i5-6260u  total:239  pass:223  dwarn:0   dfail:0   fail:2   skip:14 
fi-snb-i7-2600   total:239  pass:197  dwarn:0   dfail:0   fail:0   skip:42 
ro-bdw-i5-5250u  total:239  pass:218  dwarn:4   dfail:0   fail:1   skip:16 
ro-bdw-i7-5600u  total:239  pass:206  dwarn:0   dfail:0   fail:1   skip:32 
ro-bsw-n3050     total:239  pass:193  dwarn:0   dfail:0   fail:4   skip:42 
ro-hsw-i3-4010u  total:239  pass:213  dwarn:0   dfail:0   fail:0   skip:26 
ro-hsw-i7-4770r  total:239  pass:213  dwarn:0   dfail:0   fail:0   skip:26 
ro-ilk-i7-620lm  total:239  pass:171  dwarn:1   dfail:0   fail:2   skip:65 
ro-ilk1-i5-650   total:234  pass:172  dwarn:0   dfail:0   fail:2   skip:60 
ro-ivb-i7-3770   total:239  pass:204  dwarn:0   dfail:0   fail:0   skip:35 
ro-ivb2-i7-3770  total:239  pass:208  dwarn:0   dfail:0   fail:0   skip:31 
ro-skl3-i5-6260u total:239  pass:222  dwarn:0   dfail:0   fail:3   skip:14 
ro-snb-i7-2620M  total:239  pass:196  dwarn:0   dfail:0   fail:2   skip:41 
fi-hsw-i7-4770k failed to connect after reboot
fi-skl-i7-6700k failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1644/

cb7629d drm-intel-nightly: 2016y-07m-28d-11h-02m-33s UTC integration manifest
c06a5d8 drm/i915: Program FW_BLC_SELF on 915G as well
99ec8e7 drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM
  2016-07-29 14:57 [PATCH 1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM ville.syrjala
  2016-07-29 14:57 ` [PATCH 2/2] drm/i915: Program FW_BLC_SELF on 915G as well ville.syrjala
  2016-07-29 15:21 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM Patchwork
@ 2016-07-29 16:32 ` Chris Wilson
  2016-08-02 13:42   ` Ville Syrjälä
  2 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2016-07-29 16:32 UTC (permalink / raw)
  To: ville.syrjala; +Cc: Daniel Vetter, intel-gfx

On Fri, Jul 29, 2016 at 05:57:01PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Bspec says:
> "FW_BLC_SELF
>  ...
>  Programming Note [DevALV] and [DevCST]: When calculating watermark
>  values for 15/16bpp, assume 32bpp for purposes of calculation using
>  the high priority bandwidth analysis spreadsheet."

It does indeed.

> Let's do that.
> 
> Perhaps this might even help with the problem that resulted in
> commit 2ab1bc9df01d ("drm/i915: Disable self-refresh for untiled fbs on i915gm")
> 
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1ac32428d4db..8cfef7683088 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1604,6 +1604,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>  		unsigned long line_time_us;
>  		int entries;
>  
> +		if (IS_I915GM(dev) || IS_I945GM(dev))
> +			cpp = 4;
> +

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: Program FW_BLC_SELF on 915G as well
  2016-07-29 14:57 ` [PATCH 2/2] drm/i915: Program FW_BLC_SELF on 915G as well ville.syrjala
@ 2016-07-29 16:40   ` Chris Wilson
  0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2016-07-29 16:40 UTC (permalink / raw)
  To: ville.syrjala; +Cc: Daniel Vetter, intel-gfx

On Fri, Jul 29, 2016 at 05:57:02PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> According to Bspec FW_BLC_SELF exists on 915G also. Let's program it.

Indeed, it is there, and looks mostly the same as 915gm.

> The only open question is whether there's is a memory self-refresh
> enable bit somewhere as well. For 945G/GM it's in FW_BLC_SELF, for
> 915GM it's in INSTPM. For 915G I can't find one in the docs. Let's drop
> a FIXME about this, in case someone with the hardware is ever bored
> enough to look for it.

It looks like a 915/945 split, so my bet would be on INSTPM as well.
> 
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM
  2016-07-29 15:21 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM Patchwork
@ 2016-08-02 13:19   ` Ville Syrjälä
  0 siblings, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2016-08-02 13:19 UTC (permalink / raw)
  To: intel-gfx

On Fri, Jul 29, 2016 at 03:21:00PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM
> URL   : https://patchwork.freedesktop.org/series/10392/
> State : failure
> 
> == Summary ==
> 
> Series 10392v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/10392/revisions/1/mbox
> 
> Test drv_module_reload_basic:
>                 skip       -> PASS       (ro-ivb-i7-3770)
>                 skip       -> PASS       (ro-skl3-i5-6260u)
> Test kms_cursor_legacy:
>         Subgroup basic-cursor-vs-flip-legacy:
>                 fail       -> PASS       (ro-ilk1-i5-650)
>         Subgroup basic-cursor-vs-flip-varying-size:
>                 pass       -> FAIL       (ro-ilk1-i5-650)

(kms_cursor_legacy:8194) DEBUG: Using a target of 32 cursor updates per half-vblank
(kms_cursor_legacy:8194) WARNING: page flip 42 was delayed, missed 2 frames
(kms_cursor_legacy:8194) WARNING: page flip 44 was delayed, missed 1 frames
(kms_cursor_legacy:8194) WARNING: page flip 45 was delayed, missed 1 frames
(kms_cursor_legacy:8194) WARNING: page flip 47 was delayed, missed 2 frames
(kms_cursor_legacy:8194) WARNING: page flip 52 was delayed, missed 3 frames
(kms_cursor_legacy:8194) CRITICAL: Test assertion failure function basic_cursor_vs_flip, file kms_cursor_legacy.c:670:
(kms_cursor_legacy:8194) CRITICAL: Failed assertion: vbl.sequence == vblank_start + 60
(kms_cursor_legacy:8194) CRITICAL: error: 11522 != 11513

https://bugs.freedesktop.org/show_bug.cgi?id=96701

>         Subgroup basic-flip-vs-cursor-legacy:
>                 pass       -> FAIL       (ro-bdw-i5-5250u)

(kms_cursor_legacy:8712) DEBUG: Test requirement passed: target > 1
(kms_cursor_legacy:8712) DEBUG: Using a target of 64 cursor updates per half-vblank
(kms_cursor_legacy:8712) CRITICAL: Test assertion failure function basic_flip_vs_cursor, file kms_cursor_legacy.c:514:
(kms_cursor_legacy:8712) CRITICAL: Failed assertion: get_vblank(display->drm_fd, pipe, 0) == vblank_start
(kms_cursor_legacy:8712) CRITICAL: error: 11091 != 11090

This subtests seems to be a bit different, so potentially a different problem,
and it happens on a lot of machines. Filed a new bug:
https://bugs.freedesktop.org/show_bug.cgi?id=97188

>         Subgroup basic-flip-vs-cursor-varying-size:
>                 fail       -> PASS       (ro-skl3-i5-6260u)
> 
> fi-kbl-qkkr      total:239  pass:181  dwarn:29  dfail:0   fail:3   skip:26 
> fi-skl-i5-6260u  total:239  pass:223  dwarn:0   dfail:0   fail:2   skip:14 
> fi-snb-i7-2600   total:239  pass:197  dwarn:0   dfail:0   fail:0   skip:42 
> ro-bdw-i5-5250u  total:239  pass:218  dwarn:4   dfail:0   fail:1   skip:16 
> ro-bdw-i7-5600u  total:239  pass:206  dwarn:0   dfail:0   fail:1   skip:32 
> ro-bsw-n3050     total:239  pass:193  dwarn:0   dfail:0   fail:4   skip:42 
> ro-hsw-i3-4010u  total:239  pass:213  dwarn:0   dfail:0   fail:0   skip:26 
> ro-hsw-i7-4770r  total:239  pass:213  dwarn:0   dfail:0   fail:0   skip:26 
> ro-ilk-i7-620lm  total:239  pass:171  dwarn:1   dfail:0   fail:2   skip:65 
> ro-ilk1-i5-650   total:234  pass:172  dwarn:0   dfail:0   fail:2   skip:60 
> ro-ivb-i7-3770   total:239  pass:204  dwarn:0   dfail:0   fail:0   skip:35 
> ro-ivb2-i7-3770  total:239  pass:208  dwarn:0   dfail:0   fail:0   skip:31 
> ro-skl3-i5-6260u total:239  pass:222  dwarn:0   dfail:0   fail:3   skip:14 
> ro-snb-i7-2620M  total:239  pass:196  dwarn:0   dfail:0   fail:2   skip:41 
> fi-hsw-i7-4770k failed to connect after reboot
> fi-skl-i7-6700k failed to connect after reboot
> ro-bdw-i7-5557U failed to connect after reboot
> 
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1644/
> 
> cb7629d drm-intel-nightly: 2016y-07m-28d-11h-02m-33s UTC integration manifest
> c06a5d8 drm/i915: Program FW_BLC_SELF on 915G as well
> 99ec8e7 drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM
  2016-07-29 16:32 ` [PATCH 1/2] " Chris Wilson
@ 2016-08-02 13:42   ` Ville Syrjälä
  0 siblings, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2016-08-02 13:42 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx, Daniel Vetter

On Fri, Jul 29, 2016 at 05:32:32PM +0100, Chris Wilson wrote:
> On Fri, Jul 29, 2016 at 05:57:01PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Bspec says:
> > "FW_BLC_SELF
> >  ...
> >  Programming Note [DevALV] and [DevCST]: When calculating watermark
> >  values for 15/16bpp, assume 32bpp for purposes of calculation using
> >  the high priority bandwidth analysis spreadsheet."
> 
> It does indeed.
> 
> > Let's do that.
> > 
> > Perhaps this might even help with the problem that resulted in
> > commit 2ab1bc9df01d ("drm/i915: Disable self-refresh for untiled fbs on i915gm")
> > 
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 1ac32428d4db..8cfef7683088 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1604,6 +1604,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> >  		unsigned long line_time_us;
> >  		int entries;
> >  
> > +		if (IS_I915GM(dev) || IS_I945GM(dev))
> > +			cpp = 4;
> > +
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Series pushed to dinq. Thanks for the reviews.

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-08-02 13:42 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-29 14:57 [PATCH 1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM ville.syrjala
2016-07-29 14:57 ` [PATCH 2/2] drm/i915: Program FW_BLC_SELF on 915G as well ville.syrjala
2016-07-29 16:40   ` Chris Wilson
2016-07-29 15:21 ` ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF on 915GM/945GM Patchwork
2016-08-02 13:19   ` Ville Syrjälä
2016-07-29 16:32 ` [PATCH 1/2] " Chris Wilson
2016-08-02 13:42   ` Ville Syrjälä

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