* [Qemu-devel] [RFC v5 0/7] vITS support
@ 2016-08-02 18:07 Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class Eric Auger
` (6 more replies)
0 siblings, 7 replies; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
This series introduces support for in-kernel GICv3 ITS emulation.
It is based on a kernel API which is not yet released.
Tested on Cavium ThunderX with virtio-net-pci and vhost-net with both dt
and ACPI guests
Host Kernel dependencies:
- [PATCH v10 00/17] KVM: arm64: GICv3 ITS emulation
http://www.spinics.net/lists/kvm/msg135687.html
- [RFC v9 0/6] KVM: arm/arm64: gsi routing support
http://www.spinics.net/lists/kvm/msg136083.html
Guest Kernel dependencies for resp. ACPI ITS and PCIe support:
- [PATCH V7 0/8] Introduce ACPI world to ITS,
https://lkml.org/lkml/2016/6/20/321
- Support for ARM64 ACPI based PCI host controller,
https://lwn.net/Articles/690995/
Host kernel series can be found at:
https://github.com/eauger/linux/tree/v4.7-its-emul-v10-gsi-routing-v9
This QEMU series can be found at:
v5: https://github.com/eauger/qemu/tree/v2.6.0-vITS-v5
Previous versions are available at:
v4: https://github.com/eauger/qemu/tree/v2.6.0-vITS-v4
v3: https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg05197.html
History:
v4 => v5:
- fix compilation issue with arm-softmmu target
- rebase on target-arm: Fix unreachable code in gicv3_class_name()
- add ACPI support
- kernel ITS init sequence is not yet similar to GICv2/V3 ones. This will
be addressed in a subsequent respin.
v3 => v4:
- Took into account Peter's comments (at the exception of sub-class
operation changes)
- rebase on Andre's kernel ITS emulation series v8
- rework KVM init sequence and KVM device creation/settings overall.
I do not use kvm_arm_register_device due to the way the kernel
API is devises (see discussion on the kernel ML)
- change the computation of the GITS_TRANSLATER base address
- fix compilation issues
- new "arget-arm: move gicv3_class_name from machine to kvm_arm.h"
v2 => v3:
- Really added unmigratable flag, was overlooked in v2
- Fixed checkpatch issue with initializing static variable to zero
/bin/bash: indent : commande introuvabledded registers and reset method
- Added unmigratable flag
- Rebased on top of current master, use kvm_arch_fixup_msi_route() now
Pavel Fedin (5):
hw/intc: Implement ITS base class
kernel: Add vGICv3 ITS definitions
kvm_arm: Pass requester ID to MSI routing functions
kvm_arm: Implement support for ITS emulation by KVM
arm/virt: Add ITS to the virt board
Eric Auger (2):
target-arm: move gicv3_class_name from machine to kvm_arm.h
hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table
Pavel Fedin (5):
hw/intc/arm_gicv3_its: Implement ITS base class
linux-headers: update to 4.7-rc6 + ITS emulation and GSI routing
target-arm/kvm: Pass requester ID to MSI routing functions
hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
arm/virt: Add ITS to the virt board
hw/arm/virt-acpi-build.c | 7 +
hw/arm/virt.c | 47 ++++++-
hw/intc/Makefile.objs | 2 +
hw/intc/arm_gicv3_its_common.c | 155 +++++++++++++++++++++
hw/intc/arm_gicv3_its_kvm.c | 145 +++++++++++++++++++
include/hw/acpi/acpi-defs.h | 13 +-
include/hw/intc/arm_gicv3_its_common.h | 75 ++++++++++
include/standard-headers/linux/input-event-codes.h | 31 +++++
include/standard-headers/linux/input.h | 1 +
linux-headers/asm-arm64/kvm.h | 2 +
linux-headers/linux/kvm.h | 12 +-
target-arm/kvm.c | 6 +
target-arm/kvm_arm.h | 38 ++++-
target-arm/machine.c | 15 --
14 files changed, 524 insertions(+), 25 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its_common.c
create mode 100644 hw/intc/arm_gicv3_its_kvm.c
create mode 100644 include/hw/intc/arm_gicv3_its_common.h
--
2.5.5
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
@ 2016-08-02 18:07 ` Eric Auger
2016-08-12 14:12 ` Peter Maydell
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 2/7] target-arm: move gicv3_class_name from machine to kvm_arm.h Eric Auger
` (5 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
From: Pavel Fedin <p.fedin@samsung.com>
This is the basic skeleton for both KVM and software-emulated ITS.
Since we already prepare status structure, we also introduce complete
VMState description. But, because we currently have no migratable
implementations, we also set unmigratable flag.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- send_msi can return 0 meaning the MSI was rejected by guest. Handle this
value as an error
v3 -> v4:
- fix compilation error
- msi_supported -> msi_nonbroken
- streamid -> requester_id
- use PRIx64
- read ops uses _with_attrs form
- 16/32b write access allowed to GITS_TRANSLATER
- move its_class_name in kvm_arm.h and remove #ifdef TARGET_AARCH64
- add new kvm device dev_fd field
- add new gits_translater_gpa field in GICv3ITSState
---
hw/intc/Makefile.objs | 1 +
hw/intc/arm_gicv3_its_common.c | 155 +++++++++++++++++++++++++++++++++
include/hw/intc/arm_gicv3_its_common.h | 75 ++++++++++++++++
target-arm/kvm_arm.h | 19 ++++
4 files changed, 250 insertions(+)
create mode 100644 hw/intc/arm_gicv3_its_common.c
create mode 100644 include/hw/intc/arm_gicv3_its_common.h
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 05ec21b..23a39f7 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -16,6 +16,7 @@ common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
+common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
common-obj-$(CONFIG_OPENPIC) += openpic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
new file mode 100644
index 0000000..0d08ff2
--- /dev/null
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -0,0 +1,155 @@
+/*
+ * ITS base class for a GICv3-based system
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Written by Pavel Fedin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci/msi.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "qemu/log.h"
+
+static void gicv3_its_pre_save(void *opaque)
+{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
+ GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
+
+ if (c->pre_save) {
+ c->pre_save(s);
+ }
+}
+
+static int gicv3_its_post_load(void *opaque, int version_id)
+{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
+ GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
+
+ if (c->post_load) {
+ c->post_load(s);
+ }
+ return 0;
+}
+
+static const VMStateDescription vmstate_its = {
+ .name = "arm_gicv3_its",
+ .pre_save = gicv3_its_pre_save,
+ .post_load = gicv3_its_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(ctlr, GICv3ITSState),
+ VMSTATE_UINT64(cbaser, GICv3ITSState),
+ VMSTATE_UINT64(cwriter, GICv3ITSState),
+ VMSTATE_UINT64(creadr, GICv3ITSState),
+ VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
+ VMSTATE_END_OF_LIST()
+ },
+ .unmigratable = true,
+};
+
+static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
+ return MEMTX_ERROR;
+}
+
+static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ if (offset == 0x0040 && ((size == 2) || (size == 4))) {
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
+ GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
+ int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
+
+ if (ret <= 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS: Error sending MSI: %s\n", strerror(-ret));
+ return MEMTX_DECODE_ERROR;
+ }
+
+ return MEMTX_OK;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS write at bad offset 0x%jX\n", offset);
+ return MEMTX_DECODE_ERROR;
+ }
+}
+
+static const MemoryRegionOps gicv3_its_trans_ops = {
+ .read_with_attrs = gicv3_its_trans_read,
+ .write_with_attrs = gicv3_its_trans_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(s);
+
+ memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
+ "control", ITS_CONTROL_SIZE);
+ memory_region_init_io(&s->iomem_its, OBJECT(s), &gicv3_its_trans_ops, s,
+ "translation", ITS_TRANS_SIZE);
+
+ /* Our two regions are always adjacent, therefore we now combine them
+ * into a single one in order to make our users' life easier.
+ */
+ memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
+ memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
+ memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
+ &s->iomem_its);
+ sysbus_init_mmio(sbd, &s->iomem_main);
+
+ msi_nonbroken = true;
+}
+
+static void gicv3_its_common_reset(DeviceState *dev)
+{
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+
+ s->ctlr = 0;
+ s->cbaser = 0;
+ s->cwriter = 0;
+ s->creadr = 0;
+ memset(&s->baser, 0, sizeof(s->baser));
+
+ gicv3_its_post_load(s, 0);
+}
+
+static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = gicv3_its_common_reset;
+ dc->vmsd = &vmstate_its;
+}
+
+static const TypeInfo gicv3_its_common_info = {
+ .name = TYPE_ARM_GICV3_ITS_COMMON,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(GICv3ITSState),
+ .class_size = sizeof(GICv3ITSCommonClass),
+ .class_init = gicv3_its_common_class_init,
+ .abstract = true,
+};
+
+static void gicv3_its_common_register_types(void)
+{
+ type_register_static(&gicv3_its_common_info);
+}
+
+type_init(gicv3_its_common_register_types)
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
new file mode 100644
index 0000000..b590f90
--- /dev/null
+++ b/include/hw/intc/arm_gicv3_its_common.h
@@ -0,0 +1,75 @@
+/*
+ * ITS support for ARM GICv3
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Written by Pavel Fedin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_ARM_GICV3_ITS_COMMON_H
+#define QEMU_ARM_GICV3_ITS_COMMON_H
+
+#include "hw/sysbus.h"
+#include "hw/intc/arm_gicv3_common.h"
+
+#define ITS_CONTROL_SIZE 0x10000
+#define ITS_TRANS_SIZE 0x10000
+#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
+
+struct GICv3ITSState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem_main;
+ MemoryRegion iomem_its_cntrl;
+ MemoryRegion iomem_its;
+
+ GICv3State *gicv3;
+
+ int dev_fd; /* kvm device fd if backed by kvm vgic support */
+ uint64_t gits_translater_gpa;
+
+ /* Registers */
+ uint32_t ctlr;
+ uint64_t cbaser;
+ uint64_t cwriter;
+ uint64_t creadr;
+ uint64_t baser[8];
+};
+
+typedef struct GICv3ITSState GICv3ITSState;
+
+void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
+
+#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
+#define ARM_GICV3_ITS_COMMON(obj) \
+ OBJECT_CHECK(GICv3ITSState, (obj), TYPE_ARM_GICV3_ITS_COMMON)
+#define ARM_GICV3_ITS_COMMON_CLASS(klass) \
+ OBJECT_CLASS_CHECK(GICv3ITSCommonClass, (klass), TYPE_ARM_GICV3_ITS_COMMON)
+#define ARM_GICV3_ITS_COMMON_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(GICv3ITSCommonClass, (obj), TYPE_ARM_GICV3_ITS_COMMON)
+
+struct GICv3ITSCommonClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ int (*send_msi)(GICv3ITSState *s, uint32_t data, uint16_t devid);
+ void (*pre_save)(GICv3ITSState *s);
+ void (*post_load)(GICv3ITSState *s);
+};
+
+typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
+
+#endif
diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
index a419368..544e404 100644
--- a/target-arm/kvm_arm.h
+++ b/target-arm/kvm_arm.h
@@ -255,4 +255,23 @@ struct kvm_guest_debug_arch;
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
+/**
+ * its_class_name
+ *
+ * Return the ITS class name to use depending on whether KVM acceleration
+ * and KVM CAP_SIGNAL_MSI are supported
+ *
+ * Returns: class name to use or NULL
+ */
+static inline const char *its_class_name(void)
+{
+ if (kvm_irqchip_in_kernel()) {
+ /* KVM implementation requires this capability */
+ return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
+ } else {
+ /* Software emulation is not implemented yet */
+ return NULL;
+ }
+}
+
#endif
--
2.5.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [RFC v5 2/7] target-arm: move gicv3_class_name from machine to kvm_arm.h
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class Eric Auger
@ 2016-08-02 18:07 ` Eric Auger
2016-08-12 14:01 ` Peter Maydell
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 3/7] linux-headers: update to 4.7-rc6 + ITS emulation and GSI routing Eric Auger
` (4 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
Machine.c contains code related to migration. Let's move
gicv3_class_name to kvm_arm.h instead.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
---
v4 -> v5:
- add #include "qemu/error-report.h"
- rebased on target-arm: Fix unreachable code in gicv3_class_name()
v4: creation
Conflicts:
target-arm/machine.c
---
target-arm/kvm_arm.h | 16 +++++++++++++++-
target-arm/machine.c | 15 ---------------
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
index 544e404..633d088 100644
--- a/target-arm/kvm_arm.h
+++ b/target-arm/kvm_arm.h
@@ -13,6 +13,7 @@
#include "sysemu/kvm.h"
#include "exec/memory.h"
+#include "qemu/error-report.h"
/**
* kvm_arm_vcpu_init:
@@ -223,7 +224,20 @@ static inline const char *gic_class_name(void)
*
* Returns: class name to use
*/
-const char *gicv3_class_name(void);
+static inline const char *gicv3_class_name(void)
+{
+ if (kvm_irqchip_in_kernel()) {
+#ifdef TARGET_AARCH64
+ return "kvm-arm-gicv3";
+#else
+ error_report("KVM GICv3 acceleration is not supported on this "
+ "platform");
+ exit(1);
+#endif
+ } else {
+ return "arm-gicv3";
+ }
+}
/**
* kvm_arm_handle_debug:
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 7a6ca31..d90943b 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -331,18 +331,3 @@ const VMStateDescription vmstate_arm_cpu = {
NULL
}
};
-
-const char *gicv3_class_name(void)
-{
- if (kvm_irqchip_in_kernel()) {
-#ifdef TARGET_AARCH64
- return "kvm-arm-gicv3";
-#else
- error_report("KVM GICv3 acceleration is not supported on this "
- "platform");
- exit(1);
-#endif
- } else {
- return "arm-gicv3";
- }
-}
--
2.5.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [RFC v5 3/7] linux-headers: update to 4.7-rc6 + ITS emulation and GSI routing
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 2/7] target-arm: move gicv3_class_name from machine to kvm_arm.h Eric Auger
@ 2016-08-02 18:07 ` Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 4/7] target-arm/kvm: Pass requester ID to MSI routing functions Eric Auger
` (3 subsequent siblings)
6 siblings, 0 replies; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
From: Pavel Fedin <p.fedin@samsung.com>
Linux header update for in-kernel ITS emulation and KVM MSI routing.
The kernel can be found at
https://github.com/eauger/linux/tree/v4.7-rc6-its-emul-v7-gsi-routing-v5
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- upgrade
---
include/standard-headers/linux/input-event-codes.h | 31 ++++++++++++++++++++++
include/standard-headers/linux/input.h | 1 +
| 2 ++
| 12 +++++++--
4 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
index 354f0de..1f33521 100644
--- a/include/standard-headers/linux/input-event-codes.h
+++ b/include/standard-headers/linux/input-event-codes.h
@@ -611,6 +611,37 @@
#define KEY_KBDINPUTASSIST_ACCEPT 0x264
#define KEY_KBDINPUTASSIST_CANCEL 0x265
+/* Diagonal movement keys */
+#define KEY_RIGHT_UP 0x266
+#define KEY_RIGHT_DOWN 0x267
+#define KEY_LEFT_UP 0x268
+#define KEY_LEFT_DOWN 0x269
+
+#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */
+/* Show Top Menu of the Media (e.g. DVD) */
+#define KEY_MEDIA_TOP_MENU 0x26b
+#define KEY_NUMERIC_11 0x26c
+#define KEY_NUMERIC_12 0x26d
+/*
+ * Toggle Audio Description: refers to an audio service that helps blind and
+ * visually impaired consumers understand the action in a program. Note: in
+ * some countries this is referred to as "Video Description".
+ */
+#define KEY_AUDIO_DESC 0x26e
+#define KEY_3D_MODE 0x26f
+#define KEY_NEXT_FAVORITE 0x270
+#define KEY_STOP_RECORD 0x271
+#define KEY_PAUSE_RECORD 0x272
+#define KEY_VOD 0x273 /* Video on Demand */
+#define KEY_UNMUTE 0x274
+#define KEY_FASTREVERSE 0x275
+#define KEY_SLOWREVERSE 0x276
+/*
+ * Control a data application associated with the currently viewed channel,
+ * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
+ */
+#define KEY_DATA 0x275
+
#define BTN_TRIGGER_HAPPY 0x2c0
#define BTN_TRIGGER_HAPPY1 0x2c0
#define BTN_TRIGGER_HAPPY2 0x2c1
diff --git a/include/standard-headers/linux/input.h b/include/standard-headers/linux/input.h
index a52b202..7361a16 100644
--- a/include/standard-headers/linux/input.h
+++ b/include/standard-headers/linux/input.h
@@ -244,6 +244,7 @@ struct input_mask {
#define BUS_ATARI 0x1B
#define BUS_SPI 0x1C
#define BUS_RMI 0x1D
+#define BUS_CEC 0x1E
/*
* MT_TOOL types
--git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
index 7d82d1f..dc6f750 100644
--- a/linux-headers/asm-arm64/kvm.h
+++ b/linux-headers/asm-arm64/kvm.h
@@ -87,9 +87,11 @@ struct kvm_regs {
/* Supported VGICv3 address types */
#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
+#define KVM_VGIC_ITS_ADDR_TYPE 4
#define KVM_VGIC_V3_DIST_SIZE SZ_64K
#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
+#define KVM_VGIC_V3_ITS_SIZE SZ_64K
#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index e60e21b..37c05e2 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -866,6 +866,7 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_ARM_PMU_V3 126
#define KVM_CAP_VCPU_ATTRIBUTES 127
#define KVM_CAP_MAX_VCPU_ID 128
+#define KVM_CAP_MSI_DEVID 129
#ifdef KVM_CAP_IRQ_ROUTING
@@ -878,7 +879,10 @@ struct kvm_irq_routing_msi {
__u32 address_lo;
__u32 address_hi;
__u32 data;
- __u32 pad;
+ union {
+ __u32 pad;
+ __u32 devid;
+ };
};
struct kvm_irq_routing_s390_adapter {
@@ -1024,12 +1028,14 @@ struct kvm_one_reg {
__u64 addr;
};
+#define KVM_MSI_VALID_DEVID (1U << 0)
struct kvm_msi {
__u32 address_lo;
__u32 address_hi;
__u32 data;
__u32 flags;
- __u8 pad[16];
+ __u32 devid;
+ __u8 pad[12];
};
struct kvm_arm_device_addr {
@@ -1074,6 +1080,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_FLIC
KVM_DEV_TYPE_ARM_VGIC_V3,
#define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
+ KVM_DEV_TYPE_ARM_VGIC_ITS,
+#define KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_ARM_VGIC_ITS
KVM_DEV_TYPE_MAX,
};
--
2.5.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [RFC v5 4/7] target-arm/kvm: Pass requester ID to MSI routing functions
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
` (2 preceding siblings ...)
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 3/7] linux-headers: update to 4.7-rc6 + ITS emulation and GSI routing Eric Auger
@ 2016-08-02 18:07 ` Eric Auger
2016-08-12 14:19 ` Peter Maydell
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 5/7] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Eric Auger
` (2 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
From: Pavel Fedin <p.fedin@samsung.com>
Introduce global kvm_arm_msi_use_devid flag and pass device IDs in
kvm_arch_fixup_msi_route(). Device IDs are required by the ITS.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v3 -> v4:
- OR route->flags with KVM_MSI_VALID_DEVID
---
target-arm/kvm.c | 6 ++++++
target-arm/kvm_arm.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index dbe393c..4675aa3 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "internals.h"
#include "hw/arm/arm.h"
+#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "hw/boards.h"
#include "qemu/log.h"
@@ -31,6 +32,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
};
static bool cap_has_mp_state;
+bool kvm_arm_msi_use_devid;
int kvm_arm_vcpu_init(CPUState *cs)
{
@@ -619,6 +621,10 @@ int kvm_arm_vgic_probe(void)
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
uint64_t address, uint32_t data, PCIDevice *dev)
{
+ if (kvm_arm_msi_use_devid) {
+ route->flags |= KVM_MSI_VALID_DEVID;
+ route->u.msi.devid = pci_requester_id(dev);
+ }
return 0;
}
diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
index 633d088..befcfd1 100644
--- a/target-arm/kvm_arm.h
+++ b/target-arm/kvm_arm.h
@@ -121,6 +121,9 @@ bool write_kvmstate_to_list(ARMCPU *cpu);
void kvm_arm_reset_vcpu(ARMCPU *cpu);
#ifdef CONFIG_KVM
+
+extern bool kvm_arm_msi_use_devid;
+
/**
* kvm_arm_create_scratch_host_vcpu:
* @cpus_to_try: array of QEMU_KVM_ARM_TARGET_* values (terminated with
--
2.5.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [RFC v5 5/7] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
` (3 preceding siblings ...)
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 4/7] target-arm/kvm: Pass requester ID to MSI routing functions Eric Auger
@ 2016-08-02 18:07 ` Eric Auger
2016-08-12 14:03 ` Peter Maydell
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 6/7] arm/virt: Add ITS to the virt board Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table Eric Auger
6 siblings, 1 reply; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
From: Pavel Fedin <p.fedin@samsung.com>
The ITS control frame is in-kernel emulated while accesses to the
GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
direct MSI injection advertised by the CAP_SIGNAL_MSI capability)
the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
difference with GICv2M. Direct mapping cannot work with ITS since
the content of the MSI data is not the target interrupt ID but an
eventd id.
GSI routing is advertised (kvm_gsi_routing_allowed) as well as
msi/irqfd signaling (kvm_msi_via_irqfd_allowed).
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v3 -> v4:
- include "qemu/osdep.h" and "qapi/error.h"
- rename KVM_VGIC_V3_ADDR_TYPE_ITS into KVM_VGIC_ITS_ADDR_TYPE
- reword commit message
- change kvm_msi_via_irqfd_allowed definition (attached to irqfd dynamic
availability + MSI controller availability)
- create the ITS KVM device (previously abstracted by the GICv3 KVM device)
- init sequence changed
- absolute GITS_TRANSLATER GPA stored
---
hw/intc/Makefile.objs | 1 +
hw/intc/arm_gicv3_its_kvm.c | 145 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 146 insertions(+)
create mode 100644 hw/intc/arm_gicv3_its_kvm.c
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 23a39f7..9cca280 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -22,6 +22,7 @@ common-obj-$(CONFIG_OPENPIC) += openpic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
+obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
new file mode 100644
index 0000000..b6d92aa
--- /dev/null
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -0,0 +1,145 @@
+/*
+ * KVM-based ITS implementation for a GICv3-based system
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Written by Pavel Fedin <p.fedin@samsung.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "kvm_arm.h"
+
+#define TYPE_KVM_ARM_ITS "arm-its-kvm"
+#define KVM_ARM_ITS(obj) OBJECT_CHECK(GICv3ITSState, (obj), TYPE_KVM_ARM_ITS)
+
+static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
+{
+ struct kvm_msi msi;
+
+ msi.address_lo = s->gits_translater_gpa & 0xFFFFFFFFULL;
+ msi.address_hi = s->gits_translater_gpa >> 32;
+ msi.data = value;
+ msi.flags = KVM_MSI_VALID_DEVID;
+ msi.devid = devid;
+ memset(msi.pad, 0, sizeof(msi.pad));
+
+ return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
+}
+
+typedef struct ItsInitNotifierParams {
+ Notifier notifier;
+ GICv3ITSState *s;
+} ItsInitNotifierParams;
+
+/**
+ *
+ * We currently do not use kvm_arm_register_device to provide
+ * the kernel with the vITS control frame base address since the
+ * KVM_DEV_ARM_VGIC_CTRL_INIT init MUST be called after the
+ * KVM_ARM_SET_DEVICE_ADDR and the kvm_arm_register_device
+ * infra does not allow this.
+ */
+static void its_notify(Notifier *notifier, void *data)
+{
+ ItsInitNotifierParams *p = DO_UPCAST(ItsInitNotifierParams,
+ notifier, notifier);
+ GICv3ITSState *s = p->s;
+ MemoryRegion *mr = &s->iomem_its_cntrl;
+ MemoryRegionSection mrs;
+ struct kvm_device_attr attr;
+ uint64_t addr;
+ int ret;
+
+ mrs = memory_region_find(mr, 0, 1);
+ addr = mrs.offset_within_address_space;
+
+ attr.flags = 0;
+ attr.group = KVM_DEV_ARM_VGIC_GRP_ADDR;
+ attr.attr = KVM_VGIC_ITS_ADDR_TYPE;
+ attr.addr = (uintptr_t)&addr;
+
+ s->gits_translater_gpa = addr + ITS_CONTROL_SIZE + 0x40;
+
+ ret = kvm_device_ioctl(s->dev_fd, KVM_SET_DEVICE_ATTR, attr);
+ if (ret) {
+ error_setg_errno(&error_fatal, -ret,
+ "not able to set base address for vITS ctrl frame");
+ }
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
+}
+
+static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
+{
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+ ItsInitNotifierParams *p = g_new(ItsInitNotifierParams, 1);
+
+ s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
+ if (s->dev_fd < 0) {
+ error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
+ return;
+ }
+
+ gicv3_its_init_mmio(s, NULL);
+
+ p->notifier.notify = its_notify;
+ p->s = s;
+ qemu_add_machine_init_done_notifier(&p->notifier);
+
+ kvm_arm_msi_use_devid = true;
+ kvm_gsi_routing_allowed = kvm_has_gsi_routing();
+ kvm_gsi_direct_mapping = false;
+ kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
+}
+
+static void kvm_arm_its_init(Object *obj)
+{
+ GICv3ITSState *s = KVM_ARM_ITS(obj);
+
+ object_property_add_link(obj, "parent-gicv3",
+ "kvm-arm-gicv3", (Object **)&s->gicv3,
+ object_property_allow_set_link,
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
+ &error_abort);
+}
+
+static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
+
+ dc->realize = kvm_arm_its_realize;
+ icc->send_msi = kvm_its_send_msi;
+}
+
+static const TypeInfo kvm_arm_its_info = {
+ .name = TYPE_KVM_ARM_ITS,
+ .parent = TYPE_ARM_GICV3_ITS_COMMON,
+ .instance_size = sizeof(GICv3ITSState),
+ .instance_init = kvm_arm_its_init,
+ .class_init = kvm_arm_its_class_init,
+};
+
+static void kvm_arm_its_register_types(void)
+{
+ type_register_static(&kvm_arm_its_info);
+}
+
+type_init(kvm_arm_its_register_types)
--
2.5.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [RFC v5 6/7] arm/virt: Add ITS to the virt board
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
` (4 preceding siblings ...)
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 5/7] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Eric Auger
@ 2016-08-02 18:07 ` Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table Eric Auger
6 siblings, 0 replies; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
From: Pavel Fedin <p.fedin@samsung.com>
If supported by the configuration, ITS will be added automatically.
This patch also renames v2m_phandle to msi_phandle because it's now used
by both MSI implementations.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
--
v3 -> v4:
- added Peter's R-b
---
hw/arm/virt.c | 47 +++++++++++++++++++++++++++++++++++++++++------
1 file changed, 41 insertions(+), 6 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a193b5a..c5f65dd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -76,7 +76,7 @@ typedef struct VirtBoardInfo {
int fdt_size;
uint32_t clock_phandle;
uint32_t gic_phandle;
- uint32_t v2m_phandle;
+ uint32_t msi_phandle;
bool using_psci;
} VirtBoardInfo;
@@ -423,9 +423,22 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
}
}
+static void fdt_add_its_gic_node(VirtBoardInfo *vbi)
+{
+ vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
+ qemu_fdt_add_subnode(vbi->fdt, "/intc/its");
+ qemu_fdt_setprop_string(vbi->fdt, "/intc/its", "compatible",
+ "arm,gic-v3-its");
+ qemu_fdt_setprop(vbi->fdt, "/intc/its", "msi-controller", NULL, 0);
+ qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/its", "reg",
+ 2, vbi->memmap[VIRT_GIC_ITS].base,
+ 2, vbi->memmap[VIRT_GIC_ITS].size);
+ qemu_fdt_setprop_cell(vbi->fdt, "/intc/its", "phandle", vbi->msi_phandle);
+}
+
static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
{
- vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
+ vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m");
qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible",
"arm,gic-v2m-frame");
@@ -433,7 +446,7 @@ static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg",
2, vbi->memmap[VIRT_GIC_V2M].base,
2, vbi->memmap[VIRT_GIC_V2M].size);
- qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle);
+ qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->msi_phandle);
}
static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
@@ -500,6 +513,26 @@ static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype)
}
}
+static void create_its(VirtBoardInfo *vbi, DeviceState *gicdev)
+{
+ const char *itsclass = its_class_name();
+ DeviceState *dev;
+
+ if (!itsclass) {
+ /* Do nothing if not supported */
+ return;
+ }
+
+ dev = qdev_create(NULL, itsclass);
+
+ object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
+ &error_abort);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_ITS].base);
+
+ fdt_add_its_gic_node(vbi);
+}
+
static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
{
int i;
@@ -583,7 +616,9 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure)
fdt_add_gic_node(vbi, type);
- if (type == 2) {
+ if (type == 3) {
+ create_its(vbi, gicdev);
+ } else {
create_v2m(vbi, pic);
}
}
@@ -1025,9 +1060,9 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
nr_pcie_buses - 1);
qemu_fdt_setprop(vbi->fdt, nodename, "dma-coherent", NULL, 0);
- if (vbi->v2m_phandle) {
+ if (vbi->msi_phandle) {
qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent",
- vbi->v2m_phandle);
+ vbi->msi_phandle);
}
qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
--
2.5.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
` (5 preceding siblings ...)
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 6/7] arm/virt: Add ITS to the virt board Eric Auger
@ 2016-08-02 18:07 ` Eric Auger
2016-08-03 0:56 ` Shannon Zhao
6 siblings, 1 reply; 19+ messages in thread
From: Eric Auger @ 2016-08-02 18:07 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: shlomopongratz, diana.craciun, tn, shannon.zhao,
christoffer.dall, drjones
This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
is added to the MADT table.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v5: new
Tested with Tomasz' kernel series on guest side:
- [PATCH V7 0/8] Introduce ACPI world to ITS,
https://lkml.org/lkml/2016/6/20/321
- for running PCIe on the guest (virtio-pci-net or vhost-net)
the following series is also needed, although not directly ITS:
Support for ARM64 ACPI based PCI host controller,
https://lwn.net/Articles/690995/
---
hw/arm/virt-acpi-build.c | 7 +++++++
include/hw/acpi/acpi-defs.h | 13 ++++++++++++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 28fc59c..6cfedff 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -546,6 +546,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
}
if (guest_info->gic_version == 3) {
+ AcpiMadtGicIts *gic_its;
AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
sizeof *gicr);
@@ -553,6 +554,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
gicr->length = sizeof(*gicr);
gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
+
+ gic_its = acpi_data_push(table_data, sizeof *gic_its);
+ gic_its->type = ACPI_APIC_ITS_STRUCTURE;
+ gic_its->length = sizeof(*gic_its);
+ gic_its->gic_its_id = 0;
+ gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
} else {
gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 41c1d95..ba3be1e 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -294,7 +294,8 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
#define ACPI_APIC_GENERIC_MSI_FRAME 13
#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
-#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
+#define ACPI_APIC_ITS_STRUCTURE 15
+#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
/*
* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
@@ -386,6 +387,16 @@ struct AcpiMadtGenericMsiFrame {
typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
+struct AcpiMadtGicIts {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t gic_its_id;
+ uint64_t base_address;
+ uint32_t reserved2;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGicIts AcpiMadtGicIts;
+
struct AcpiMadtGenericRedistributor {
ACPI_SUB_HEADER_DEF
uint16_t reserved;
--
2.5.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table Eric Auger
@ 2016-08-03 0:56 ` Shannon Zhao
2016-08-03 7:22 ` Auger Eric
0 siblings, 1 reply; 19+ messages in thread
From: Shannon Zhao @ 2016-08-03 0:56 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: drjones, tn, shlomopongratz, shannon.zhao, diana.craciun,
christoffer.dall
Hi Eric,
On 2016/8/3 2:07, Eric Auger wrote:
> This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
> is added to the MADT table.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
>
> v5: new
>
> Tested with Tomasz' kernel series on guest side:
> - [PATCH V7 0/8] Introduce ACPI world to ITS,
> https://lkml.org/lkml/2016/6/20/321
> - for running PCIe on the guest (virtio-pci-net or vhost-net)
> the following series is also needed, although not directly ITS:
> Support for ARM64 ACPI based PCI host controller,
> https://lwn.net/Articles/690995/
> ---
> hw/arm/virt-acpi-build.c | 7 +++++++
> include/hw/acpi/acpi-defs.h | 13 ++++++++++++-
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 28fc59c..6cfedff 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -546,6 +546,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
> }
>
> if (guest_info->gic_version == 3) {
> + AcpiMadtGicIts *gic_its;
> AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
> sizeof *gicr);
>
> @@ -553,6 +554,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
> gicr->length = sizeof(*gicr);
> gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
> gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
> +
> + gic_its = acpi_data_push(table_data, sizeof *gic_its);
> + gic_its->type = ACPI_APIC_ITS_STRUCTURE;
> + gic_its->length = sizeof(*gic_its);
> + gic_its->gic_its_id = 0;
> + gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
Since for TCG it doesn't support ITS yet, it should check here using
its_class_name().
> } else {
> gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
> gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index 41c1d95..ba3be1e 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -294,7 +294,8 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
> #define ACPI_APIC_GENERIC_DISTRIBUTOR 12
> #define ACPI_APIC_GENERIC_MSI_FRAME 13
> #define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
> -#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
> +#define ACPI_APIC_ITS_STRUCTURE 15
use ACPI_APIC_GENERIC_TRANSLATOR instead.
> +#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
>
> /*
> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
> @@ -386,6 +387,16 @@ struct AcpiMadtGenericMsiFrame {
>
> typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
>
> +struct AcpiMadtGicIts {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t gic_its_id;
> + uint64_t base_address;
> + uint32_t reserved2;
> +} QEMU_PACKED;
> +
> +typedef struct AcpiMadtGicIts AcpiMadtGicIts;
> +
Define it like below to respect the name in linux kernel and also keep
consistent with other structures.
+struct AcpiMadtGenericTranslator {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t translation_id;
+ uint64_t base_address;
+ uint32_t reserved2;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
BTW, you could have a look at [1] which I sent before.
[1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg06282.html
Thanks,
--
Shannon
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table
2016-08-03 0:56 ` Shannon Zhao
@ 2016-08-03 7:22 ` Auger Eric
2016-08-03 8:50 ` Shannon Zhao
0 siblings, 1 reply; 19+ messages in thread
From: Auger Eric @ 2016-08-03 7:22 UTC (permalink / raw)
To: Shannon Zhao, eric.auger.pro, peter.maydell, qemu-arm,
qemu-devel, p.fedin
Cc: drjones, tn, shlomopongratz, shannon.zhao, diana.craciun,
christoffer.dall
Hi Shannon,
On 03/08/2016 02:56, Shannon Zhao wrote:
> Hi Eric,
>
> On 2016/8/3 2:07, Eric Auger wrote:
>> This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
>> is added to the MADT table.
>>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>
>> ---
>>
>> v5: new
>>
>> Tested with Tomasz' kernel series on guest side:
>> - [PATCH V7 0/8] Introduce ACPI world to ITS,
>> https://lkml.org/lkml/2016/6/20/321
>> - for running PCIe on the guest (virtio-pci-net or vhost-net)
>> the following series is also needed, although not directly ITS:
>> Support for ARM64 ACPI based PCI host controller,
>> https://lwn.net/Articles/690995/
>> ---
>> hw/arm/virt-acpi-build.c | 7 +++++++
>> include/hw/acpi/acpi-defs.h | 13 ++++++++++++-
>> 2 files changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index 28fc59c..6cfedff 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -546,6 +546,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
>> }
>>
>> if (guest_info->gic_version == 3) {
>> + AcpiMadtGicIts *gic_its;
>> AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
>> sizeof *gicr);
>>
>> @@ -553,6 +554,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
>> gicr->length = sizeof(*gicr);
>> gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
>> gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
>> +
>> + gic_its = acpi_data_push(table_data, sizeof *gic_its);
>> + gic_its->type = ACPI_APIC_ITS_STRUCTURE;
>> + gic_its->length = sizeof(*gic_its);
>> + gic_its->gic_its_id = 0;
>> + gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
> Since for TCG it doesn't support ITS yet, it should check here using
> its_class_name().
>
>> } else {
>> gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
>> gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
>> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>> index 41c1d95..ba3be1e 100644
>> --- a/include/hw/acpi/acpi-defs.h
>> +++ b/include/hw/acpi/acpi-defs.h
>> @@ -294,7 +294,8 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
>> #define ACPI_APIC_GENERIC_DISTRIBUTOR 12
>> #define ACPI_APIC_GENERIC_MSI_FRAME 13
>> #define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
>> -#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>> +#define ACPI_APIC_ITS_STRUCTURE 15
> use ACPI_APIC_GENERIC_TRANSLATOR instead.
>
>> +#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
>>
>> /*
>> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
>> @@ -386,6 +387,16 @@ struct AcpiMadtGenericMsiFrame {
>>
>> typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
>>
>> +struct AcpiMadtGicIts {
>> + ACPI_SUB_HEADER_DEF
>> + uint16_t reserved;
>> + uint32_t gic_its_id;
>> + uint64_t base_address;
>> + uint32_t reserved2;
>> +} QEMU_PACKED;
>> +
>> +typedef struct AcpiMadtGicIts AcpiMadtGicIts;
>> +
> Define it like below to respect the name in linux kernel and also keep
> consistent with other structures.
>
> +struct AcpiMadtGenericTranslator {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t translation_id;
> + uint64_t base_address;
> + uint32_t reserved2;
> +} QEMU_PACKED;
> +
> +typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
>
> BTW, you could have a look at [1] which I sent before.
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg06282.html
Hum sorry, please apologize. I was not aware of those. Do you want to
respin or shall I respin mine taking into account your comments and
changing the author. Besides, thanks for the review.
Thanks
Eric
>
> Thanks,
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table
2016-08-03 7:22 ` Auger Eric
@ 2016-08-03 8:50 ` Shannon Zhao
2016-08-03 9:02 ` Auger Eric
0 siblings, 1 reply; 19+ messages in thread
From: Shannon Zhao @ 2016-08-03 8:50 UTC (permalink / raw)
To: Auger Eric, eric.auger.pro, peter.maydell, qemu-arm, qemu-devel, p.fedin
Cc: drjones, tn, shlomopongratz, shannon.zhao, diana.craciun,
christoffer.dall
On 2016/8/3 15:22, Auger Eric wrote:
> Hi Shannon,
>
> On 03/08/2016 02:56, Shannon Zhao wrote:
>> > Hi Eric,
>> >
>> > On 2016/8/3 2:07, Eric Auger wrote:
>>> >> This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
>>> >> is added to the MADT table.
>>> >>
>>> >> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>> >>
>>> >> ---
>>> >>
>>> >> v5: new
>>> >>
>>> >> Tested with Tomasz' kernel series on guest side:
>>> >> - [PATCH V7 0/8] Introduce ACPI world to ITS,
>>> >> https://lkml.org/lkml/2016/6/20/321
>>> >> - for running PCIe on the guest (virtio-pci-net or vhost-net)
>>> >> the following series is also needed, although not directly ITS:
>>> >> Support for ARM64 ACPI based PCI host controller,
>>> >> https://lwn.net/Articles/690995/
>>> >> ---
>>> >> hw/arm/virt-acpi-build.c | 7 +++++++
>>> >> include/hw/acpi/acpi-defs.h | 13 ++++++++++++-
>>> >> 2 files changed, 19 insertions(+), 1 deletion(-)
>>> >>
>>> >> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>>> >> index 28fc59c..6cfedff 100644
>>> >> --- a/hw/arm/virt-acpi-build.c
>>> >> +++ b/hw/arm/virt-acpi-build.c
>>> >> @@ -546,6 +546,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
>>> >> }
>>> >>
>>> >> if (guest_info->gic_version == 3) {
>>> >> + AcpiMadtGicIts *gic_its;
>>> >> AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
>>> >> sizeof *gicr);
>>> >>
>>> >> @@ -553,6 +554,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
>>> >> gicr->length = sizeof(*gicr);
>>> >> gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
>>> >> gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
>>> >> +
>>> >> + gic_its = acpi_data_push(table_data, sizeof *gic_its);
>>> >> + gic_its->type = ACPI_APIC_ITS_STRUCTURE;
>>> >> + gic_its->length = sizeof(*gic_its);
>>> >> + gic_its->gic_its_id = 0;
>>> >> + gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
>> > Since for TCG it doesn't support ITS yet, it should check here using
>> > its_class_name().
>> >
>>> >> } else {
>>> >> gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
>>> >> gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
>>> >> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>>> >> index 41c1d95..ba3be1e 100644
>>> >> --- a/include/hw/acpi/acpi-defs.h
>>> >> +++ b/include/hw/acpi/acpi-defs.h
>>> >> @@ -294,7 +294,8 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
>>> >> #define ACPI_APIC_GENERIC_DISTRIBUTOR 12
>>> >> #define ACPI_APIC_GENERIC_MSI_FRAME 13
>>> >> #define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
>>> >> -#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>>> >> +#define ACPI_APIC_ITS_STRUCTURE 15
>> > use ACPI_APIC_GENERIC_TRANSLATOR instead.
>> >
>>> >> +#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
>>> >>
>>> >> /*
>>> >> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
>>> >> @@ -386,6 +387,16 @@ struct AcpiMadtGenericMsiFrame {
>>> >>
>>> >> typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
>>> >>
>>> >> +struct AcpiMadtGicIts {
>>> >> + ACPI_SUB_HEADER_DEF
>>> >> + uint16_t reserved;
>>> >> + uint32_t gic_its_id;
>>> >> + uint64_t base_address;
>>> >> + uint32_t reserved2;
>>> >> +} QEMU_PACKED;
>>> >> +
>>> >> +typedef struct AcpiMadtGicIts AcpiMadtGicIts;
>>> >> +
>> > Define it like below to respect the name in linux kernel and also keep
>> > consistent with other structures.
>> >
>> > +struct AcpiMadtGenericTranslator {
>> > + ACPI_SUB_HEADER_DEF
>> > + uint16_t reserved;
>> > + uint32_t translation_id;
>> > + uint64_t base_address;
>> > + uint32_t reserved2;
>> > +} QEMU_PACKED;
>> > +
>> > +typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
>> >
>> > BTW, you could have a look at [1] which I sent before.
>> >
>> > [1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg06282.html
> Hum sorry, please apologize. I was not aware of those. Do you want to
> respin or shall I respin mine taking into account your comments and
> changing the author. Besides, thanks for the review.
Never mind. I think you can respin yours.
Thanks,
--
Shannon
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table
2016-08-03 8:50 ` Shannon Zhao
@ 2016-08-03 9:02 ` Auger Eric
0 siblings, 0 replies; 19+ messages in thread
From: Auger Eric @ 2016-08-03 9:02 UTC (permalink / raw)
To: Shannon Zhao, eric.auger.pro, peter.maydell, qemu-arm,
qemu-devel, p.fedin
Cc: drjones, tn, shlomopongratz, shannon.zhao, diana.craciun,
christoffer.dall
Hi Shannon,
On 03/08/2016 10:50, Shannon Zhao wrote:
>
>
> On 2016/8/3 15:22, Auger Eric wrote:
>> Hi Shannon,
>>
>> On 03/08/2016 02:56, Shannon Zhao wrote:
>>>> Hi Eric,
>>>>
>>>> On 2016/8/3 2:07, Eric Auger wrote:
>>>>>> This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
>>>>>> is added to the MADT table.
>>>>>>
>>>>>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>>>>>
>>>>>> ---
>>>>>>
>>>>>> v5: new
>>>>>>
>>>>>> Tested with Tomasz' kernel series on guest side:
>>>>>> - [PATCH V7 0/8] Introduce ACPI world to ITS,
>>>>>> https://lkml.org/lkml/2016/6/20/321
>>>>>> - for running PCIe on the guest (virtio-pci-net or vhost-net)
>>>>>> the following series is also needed, although not directly ITS:
>>>>>> Support for ARM64 ACPI based PCI host controller,
>>>>>> https://lwn.net/Articles/690995/
>>>>>> ---
>>>>>> hw/arm/virt-acpi-build.c | 7 +++++++
>>>>>> include/hw/acpi/acpi-defs.h | 13 ++++++++++++-
>>>>>> 2 files changed, 19 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>>>>>> index 28fc59c..6cfedff 100644
>>>>>> --- a/hw/arm/virt-acpi-build.c
>>>>>> +++ b/hw/arm/virt-acpi-build.c
>>>>>> @@ -546,6 +546,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
>>>>>> }
>>>>>>
>>>>>> if (guest_info->gic_version == 3) {
>>>>>> + AcpiMadtGicIts *gic_its;
>>>>>> AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
>>>>>> sizeof *gicr);
>>>>>>
>>>>>> @@ -553,6 +554,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
>>>>>> gicr->length = sizeof(*gicr);
>>>>>> gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
>>>>>> gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
>>>>>> +
>>>>>> + gic_its = acpi_data_push(table_data, sizeof *gic_its);
>>>>>> + gic_its->type = ACPI_APIC_ITS_STRUCTURE;
>>>>>> + gic_its->length = sizeof(*gic_its);
>>>>>> + gic_its->gic_its_id = 0;
>>>>>> + gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
>>>> Since for TCG it doesn't support ITS yet, it should check here using
>>>> its_class_name().
>>>>
>>>>>> } else {
>>>>>> gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
>>>>>> gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
>>>>>> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>>>>>> index 41c1d95..ba3be1e 100644
>>>>>> --- a/include/hw/acpi/acpi-defs.h
>>>>>> +++ b/include/hw/acpi/acpi-defs.h
>>>>>> @@ -294,7 +294,8 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
>>>>>> #define ACPI_APIC_GENERIC_DISTRIBUTOR 12
>>>>>> #define ACPI_APIC_GENERIC_MSI_FRAME 13
>>>>>> #define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
>>>>>> -#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>>>>>> +#define ACPI_APIC_ITS_STRUCTURE 15
>>>> use ACPI_APIC_GENERIC_TRANSLATOR instead.
>>>>
>>>>>> +#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
>>>>>>
>>>>>> /*
>>>>>> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
>>>>>> @@ -386,6 +387,16 @@ struct AcpiMadtGenericMsiFrame {
>>>>>>
>>>>>> typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
>>>>>>
>>>>>> +struct AcpiMadtGicIts {
>>>>>> + ACPI_SUB_HEADER_DEF
>>>>>> + uint16_t reserved;
>>>>>> + uint32_t gic_its_id;
>>>>>> + uint64_t base_address;
>>>>>> + uint32_t reserved2;
>>>>>> +} QEMU_PACKED;
>>>>>> +
>>>>>> +typedef struct AcpiMadtGicIts AcpiMadtGicIts;
>>>>>> +
>>>> Define it like below to respect the name in linux kernel and also keep
>>>> consistent with other structures.
>>>>
>>>> +struct AcpiMadtGenericTranslator {
>>>> + ACPI_SUB_HEADER_DEF
>>>> + uint16_t reserved;
>>>> + uint32_t translation_id;
>>>> + uint64_t base_address;
>>>> + uint32_t reserved2;
>>>> +} QEMU_PACKED;
>>>> +
>>>> +typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
>>>>
>>>> BTW, you could have a look at [1] which I sent before.
>>>>
>>>> [1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg06282.html
>> Hum sorry, please apologize. I was not aware of those. Do you want to
>> respin or shall I respin mine taking into account your comments and
>> changing the author. Besides, thanks for the review.
> Never mind. I think you can respin yours.
OK thanks.
Eric
>
> Thanks,
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 2/7] target-arm: move gicv3_class_name from machine to kvm_arm.h
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 2/7] target-arm: move gicv3_class_name from machine to kvm_arm.h Eric Auger
@ 2016-08-12 14:01 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2016-08-12 14:01 UTC (permalink / raw)
To: Eric Auger
Cc: eric.auger.pro, qemu-arm, QEMU Developers, Pavel Fedin,
Shlomo Pongratz, Diana Craciun, Tomasz Nowicki, Shannon Zhao,
Christoffer Dall, Andrew Jones
On 2 August 2016 at 19:07, Eric Auger <eric.auger@redhat.com> wrote:
> Machine.c contains code related to migration. Let's move
> gicv3_class_name to kvm_arm.h instead.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 5/7] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 5/7] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Eric Auger
@ 2016-08-12 14:03 ` Peter Maydell
2016-08-17 15:59 ` Auger Eric
0 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2016-08-12 14:03 UTC (permalink / raw)
To: Eric Auger
Cc: eric.auger.pro, qemu-arm, QEMU Developers, Pavel Fedin,
Shlomo Pongratz, Diana Craciun, Tomasz Nowicki, Shannon Zhao,
Christoffer Dall, Andrew Jones
On 2 August 2016 at 19:07, Eric Auger <eric.auger@redhat.com> wrote:
> From: Pavel Fedin <p.fedin@samsung.com>
>
> The ITS control frame is in-kernel emulated while accesses to the
> GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
> direct MSI injection advertised by the CAP_SIGNAL_MSI capability)
>
> the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
> difference with GICv2M. Direct mapping cannot work with ITS since
> the content of the MSI data is not the target interrupt ID but an
> eventd id.
>
> GSI routing is advertised (kvm_gsi_routing_allowed) as well as
> msi/irqfd signaling (kvm_msi_via_irqfd_allowed).
>
> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
>
> v3 -> v4:
> - include "qemu/osdep.h" and "qapi/error.h"
> - rename KVM_VGIC_V3_ADDR_TYPE_ITS into KVM_VGIC_ITS_ADDR_TYPE
> - reword commit message
> - change kvm_msi_via_irqfd_allowed definition (attached to irqfd dynamic
> availability + MSI controller availability)
> - create the ITS KVM device (previously abstracted by the GICv3 KVM device)
> - init sequence changed
> - absolute GITS_TRANSLATER GPA stored
> ---
> hw/intc/Makefile.objs | 1 +
> hw/intc/arm_gicv3_its_kvm.c | 145 ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 146 insertions(+)
> create mode 100644 hw/intc/arm_gicv3_its_kvm.c
>
> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> index 23a39f7..9cca280 100644
> --- a/hw/intc/Makefile.objs
> +++ b/hw/intc/Makefile.objs
> @@ -22,6 +22,7 @@ common-obj-$(CONFIG_OPENPIC) += openpic.o
> obj-$(CONFIG_APIC) += apic.o apic_common.o
> obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
> obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
> +obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
> obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
> obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
> obj-$(CONFIG_GRLIB) += grlib_irqmp.o
> diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
> new file mode 100644
> index 0000000..b6d92aa
> --- /dev/null
> +++ b/hw/intc/arm_gicv3_its_kvm.c
> @@ -0,0 +1,145 @@
> +/*
> + * KVM-based ITS implementation for a GICv3-based system
> + *
> + * Copyright (c) 2015 Samsung Electronics Co., Ltd.
> + * Written by Pavel Fedin <p.fedin@samsung.com>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/intc/arm_gicv3_its_common.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/kvm.h"
> +#include "kvm_arm.h"
> +
> +#define TYPE_KVM_ARM_ITS "arm-its-kvm"
> +#define KVM_ARM_ITS(obj) OBJECT_CHECK(GICv3ITSState, (obj), TYPE_KVM_ARM_ITS)
> +
> +static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
> +{
> + struct kvm_msi msi;
> +
> + msi.address_lo = s->gits_translater_gpa & 0xFFFFFFFFULL;
> + msi.address_hi = s->gits_translater_gpa >> 32;
extract64() might be preferable?
> + msi.data = value;
> + msi.flags = KVM_MSI_VALID_DEVID;
> + msi.devid = devid;
> + memset(msi.pad, 0, sizeof(msi.pad));
> +
> + return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
> +}
> +
> +typedef struct ItsInitNotifierParams {
> + Notifier notifier;
> + GICv3ITSState *s;
> +} ItsInitNotifierParams;
> +
> +/**
> + *
> + * We currently do not use kvm_arm_register_device to provide
> + * the kernel with the vITS control frame base address since the
> + * KVM_DEV_ARM_VGIC_CTRL_INIT init MUST be called after the
> + * KVM_ARM_SET_DEVICE_ADDR and the kvm_arm_register_device
> + * infra does not allow this.
> + */
I thought we'd fixed the kernel API so we didn't need to
have this workaround?
> +static void its_notify(Notifier *notifier, void *data)
> +{
> + ItsInitNotifierParams *p = DO_UPCAST(ItsInitNotifierParams,
> + notifier, notifier);
> + GICv3ITSState *s = p->s;
> + MemoryRegion *mr = &s->iomem_its_cntrl;
> + MemoryRegionSection mrs;
> + struct kvm_device_attr attr;
> + uint64_t addr;
> + int ret;
> +
> + mrs = memory_region_find(mr, 0, 1);
> + addr = mrs.offset_within_address_space;
> +
> + attr.flags = 0;
> + attr.group = KVM_DEV_ARM_VGIC_GRP_ADDR;
> + attr.attr = KVM_VGIC_ITS_ADDR_TYPE;
> + attr.addr = (uintptr_t)&addr;
> +
> + s->gits_translater_gpa = addr + ITS_CONTROL_SIZE + 0x40;
> +
> + ret = kvm_device_ioctl(s->dev_fd, KVM_SET_DEVICE_ATTR, attr);
> + if (ret) {
> + error_setg_errno(&error_fatal, -ret,
> + "not able to set base address for vITS ctrl frame");
> + }
> +
> + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
> + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class Eric Auger
@ 2016-08-12 14:12 ` Peter Maydell
2016-08-17 16:03 ` Auger Eric
0 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2016-08-12 14:12 UTC (permalink / raw)
To: Eric Auger
Cc: eric.auger.pro, qemu-arm, QEMU Developers, Pavel Fedin,
Shlomo Pongratz, Diana Craciun, Tomasz Nowicki, Shannon Zhao,
Christoffer Dall, Andrew Jones
On 2 August 2016 at 19:07, Eric Auger <eric.auger@redhat.com> wrote:
> From: Pavel Fedin <p.fedin@samsung.com>
>
> This is the basic skeleton for both KVM and software-emulated ITS.
> Since we already prepare status structure, we also introduce complete
> VMState description. But, because we currently have no migratable
> implementations, we also set unmigratable flag.
>
> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
> v4 -> v5:
> - send_msi can return 0 meaning the MSI was rejected by guest. Handle this
> value as an error
>
> v3 -> v4:
> - fix compilation error
> - msi_supported -> msi_nonbroken
> - streamid -> requester_id
> - use PRIx64
> - read ops uses _with_attrs form
> - 16/32b write access allowed to GITS_TRANSLATER
> - move its_class_name in kvm_arm.h and remove #ifdef TARGET_AARCH64
> - add new kvm device dev_fd field
> - add new gits_translater_gpa field in GICv3ITSState
> ---
> hw/intc/Makefile.objs | 1 +
> hw/intc/arm_gicv3_its_common.c | 155 +++++++++++++++++++++++++++++++++
> include/hw/intc/arm_gicv3_its_common.h | 75 ++++++++++++++++
> target-arm/kvm_arm.h | 19 ++++
> 4 files changed, 250 insertions(+)
> create mode 100644 hw/intc/arm_gicv3_its_common.c
> create mode 100644 include/hw/intc/arm_gicv3_its_common.h
>
> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> index 05ec21b..23a39f7 100644
> --- a/hw/intc/Makefile.objs
> +++ b/hw/intc/Makefile.objs
> @@ -16,6 +16,7 @@ common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
> common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
> common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
> common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
> +common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
> common-obj-$(CONFIG_OPENPIC) += openpic.o
>
> obj-$(CONFIG_APIC) += apic.o apic_common.o
> diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
> new file mode 100644
> index 0000000..0d08ff2
> --- /dev/null
> +++ b/hw/intc/arm_gicv3_its_common.c
> @@ -0,0 +1,155 @@
> +/*
> + * ITS base class for a GICv3-based system
> + *
> + * Copyright (c) 2015 Samsung Electronics Co., Ltd.
> + * Written by Pavel Fedin
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/pci/msi.h"
> +#include "hw/intc/arm_gicv3_its_common.h"
> +#include "qemu/log.h"
> +
> +static void gicv3_its_pre_save(void *opaque)
> +{
> + GICv3ITSState *s = (GICv3ITSState *)opaque;
> + GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
> +
> + if (c->pre_save) {
> + c->pre_save(s);
> + }
> +}
> +
> +static int gicv3_its_post_load(void *opaque, int version_id)
> +{
> + GICv3ITSState *s = (GICv3ITSState *)opaque;
> + GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
> +
> + if (c->post_load) {
> + c->post_load(s);
> + }
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_its = {
> + .name = "arm_gicv3_its",
> + .pre_save = gicv3_its_pre_save,
> + .post_load = gicv3_its_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(ctlr, GICv3ITSState),
> + VMSTATE_UINT64(cbaser, GICv3ITSState),
> + VMSTATE_UINT64(cwriter, GICv3ITSState),
> + VMSTATE_UINT64(creadr, GICv3ITSState),
> + VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
> + VMSTATE_END_OF_LIST()
> + },
> + .unmigratable = true,
Why define the fields and also mark it unmigratable?
A comment saying why the device is unmigratable would be good.
> +};
> +
> +static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
> + return MEMTX_ERROR;
> +}
> +
> +static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + if (offset == 0x0040 && ((size == 2) || (size == 4))) {
> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
> + GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
> + int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
> +
> + if (ret <= 0) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "ITS: Error sending MSI: %s\n", strerror(-ret));
> + return MEMTX_DECODE_ERROR;
> + }
> +
> + return MEMTX_OK;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "ITS write at bad offset 0x%jX\n", offset);
Can we be consistent about the format string used for printing hwaddrs?
I suspect this one won't build on 32-bit.
> + return MEMTX_DECODE_ERROR;
> + }
> +}
> +
> +static const MemoryRegionOps gicv3_its_trans_ops = {
> + .read_with_attrs = gicv3_its_trans_read,
> + .write_with_attrs = gicv3_its_trans_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(s);
> +
> + memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
> + "control", ITS_CONTROL_SIZE);
> + memory_region_init_io(&s->iomem_its, OBJECT(s), &gicv3_its_trans_ops, s,
> + "translation", ITS_TRANS_SIZE);
> +
> + /* Our two regions are always adjacent, therefore we now combine them
> + * into a single one in order to make our users' life easier.
> + */
> + memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
> + memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
> + memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
> + &s->iomem_its);
> + sysbus_init_mmio(sbd, &s->iomem_main);
> +
> + msi_nonbroken = true;
> +}
> +
> +static void gicv3_its_common_reset(DeviceState *dev)
> +{
> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> +
> + s->ctlr = 0;
> + s->cbaser = 0;
> + s->cwriter = 0;
> + s->creadr = 0;
> + memset(&s->baser, 0, sizeof(s->baser));
> +
> + gicv3_its_post_load(s, 0);
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 4/7] target-arm/kvm: Pass requester ID to MSI routing functions
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 4/7] target-arm/kvm: Pass requester ID to MSI routing functions Eric Auger
@ 2016-08-12 14:19 ` Peter Maydell
2016-08-17 16:05 ` Auger Eric
0 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2016-08-12 14:19 UTC (permalink / raw)
To: Eric Auger
Cc: eric.auger.pro, qemu-arm, QEMU Developers, Pavel Fedin,
Shlomo Pongratz, Diana Craciun, Tomasz Nowicki, Shannon Zhao,
Christoffer Dall, Andrew Jones
On 2 August 2016 at 19:07, Eric Auger <eric.auger@redhat.com> wrote:
> From: Pavel Fedin <p.fedin@samsung.com>
>
> Introduce global kvm_arm_msi_use_devid flag and pass device IDs in
> kvm_arch_fixup_msi_route(). Device IDs are required by the ITS.
>
> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
>
> v3 -> v4:
> - OR route->flags with KVM_MSI_VALID_DEVID
> ---
> target-arm/kvm.c | 6 ++++++
> target-arm/kvm_arm.h | 3 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/target-arm/kvm.c b/target-arm/kvm.c
> index dbe393c..4675aa3 100644
> --- a/target-arm/kvm.c
> +++ b/target-arm/kvm.c
> @@ -22,6 +22,7 @@
> #include "cpu.h"
> #include "internals.h"
> #include "hw/arm/arm.h"
> +#include "hw/pci/pci.h"
> #include "exec/memattrs.h"
> #include "hw/boards.h"
> #include "qemu/log.h"
> @@ -31,6 +32,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> };
>
> static bool cap_has_mp_state;
> +bool kvm_arm_msi_use_devid;
>
> int kvm_arm_vcpu_init(CPUState *cs)
> {
> @@ -619,6 +621,10 @@ int kvm_arm_vgic_probe(void)
> int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
> uint64_t address, uint32_t data, PCIDevice *dev)
> {
> + if (kvm_arm_msi_use_devid) {
> + route->flags |= KVM_MSI_VALID_DEVID;
> + route->u.msi.devid = pci_requester_id(dev);
> + }
> return 0;
> }
>
> diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
> index 633d088..befcfd1 100644
> --- a/target-arm/kvm_arm.h
> +++ b/target-arm/kvm_arm.h
> @@ -121,6 +121,9 @@ bool write_kvmstate_to_list(ARMCPU *cpu);
> void kvm_arm_reset_vcpu(ARMCPU *cpu);
>
> #ifdef CONFIG_KVM
> +
> +extern bool kvm_arm_msi_use_devid;
> +
The kernel documentation and most of the code for this flag
isn't ARM specific, which suggests to me that we should put
the QEMU support into the non-architecture-specific files too.
That is, a flag and wrapper function like all the existing
ones in include/sysemu/kvm.h, and then put the
if (kvm_msi_use_devid()) {
...
}
in the functions in kvm-all.c that need it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 5/7] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
2016-08-12 14:03 ` Peter Maydell
@ 2016-08-17 15:59 ` Auger Eric
0 siblings, 0 replies; 19+ messages in thread
From: Auger Eric @ 2016-08-17 15:59 UTC (permalink / raw)
To: Peter Maydell
Cc: eric.auger.pro, qemu-arm, QEMU Developers, Pavel Fedin,
Shlomo Pongratz, Diana Craciun, Tomasz Nowicki, Shannon Zhao,
Christoffer Dall, Andrew Jones
Hi Peter,
On 12/08/2016 16:03, Peter Maydell wrote:
> On 2 August 2016 at 19:07, Eric Auger <eric.auger@redhat.com> wrote:
>> From: Pavel Fedin <p.fedin@samsung.com>
>>
>> The ITS control frame is in-kernel emulated while accesses to the
>> GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
>> direct MSI injection advertised by the CAP_SIGNAL_MSI capability)
>>
>> the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
>> difference with GICv2M. Direct mapping cannot work with ITS since
>> the content of the MSI data is not the target interrupt ID but an
>> eventd id.
>>
>> GSI routing is advertised (kvm_gsi_routing_allowed) as well as
>> msi/irqfd signaling (kvm_msi_via_irqfd_allowed).
>>
>> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>
>> ---
>>
>> v3 -> v4:
>> - include "qemu/osdep.h" and "qapi/error.h"
>> - rename KVM_VGIC_V3_ADDR_TYPE_ITS into KVM_VGIC_ITS_ADDR_TYPE
>> - reword commit message
>> - change kvm_msi_via_irqfd_allowed definition (attached to irqfd dynamic
>> availability + MSI controller availability)
>> - create the ITS KVM device (previously abstracted by the GICv3 KVM device)
>> - init sequence changed
>> - absolute GITS_TRANSLATER GPA stored
>> ---
>> hw/intc/Makefile.objs | 1 +
>> hw/intc/arm_gicv3_its_kvm.c | 145 ++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 146 insertions(+)
>> create mode 100644 hw/intc/arm_gicv3_its_kvm.c
>>
>> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
>> index 23a39f7..9cca280 100644
>> --- a/hw/intc/Makefile.objs
>> +++ b/hw/intc/Makefile.objs
>> @@ -22,6 +22,7 @@ common-obj-$(CONFIG_OPENPIC) += openpic.o
>> obj-$(CONFIG_APIC) += apic.o apic_common.o
>> obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
>> obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
>> +obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
>> obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
>> obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
>> obj-$(CONFIG_GRLIB) += grlib_irqmp.o
>> diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
>> new file mode 100644
>> index 0000000..b6d92aa
>> --- /dev/null
>> +++ b/hw/intc/arm_gicv3_its_kvm.c
>> @@ -0,0 +1,145 @@
>> +/*
>> + * KVM-based ITS implementation for a GICv3-based system
>> + *
>> + * Copyright (c) 2015 Samsung Electronics Co., Ltd.
>> + * Written by Pavel Fedin <p.fedin@samsung.com>
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "hw/intc/arm_gicv3_its_common.h"
>> +#include "sysemu/sysemu.h"
>> +#include "sysemu/kvm.h"
>> +#include "kvm_arm.h"
>> +
>> +#define TYPE_KVM_ARM_ITS "arm-its-kvm"
>> +#define KVM_ARM_ITS(obj) OBJECT_CHECK(GICv3ITSState, (obj), TYPE_KVM_ARM_ITS)
>> +
>> +static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
>> +{
>> + struct kvm_msi msi;
>> +
>> + msi.address_lo = s->gits_translater_gpa & 0xFFFFFFFFULL;
>> + msi.address_hi = s->gits_translater_gpa >> 32;
>
> extract64() might be preferable?
>
>> + msi.data = value;
>> + msi.flags = KVM_MSI_VALID_DEVID;
>> + msi.devid = devid;
>> + memset(msi.pad, 0, sizeof(msi.pad));
>> +
>> + return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
>> +}
>> +
>> +typedef struct ItsInitNotifierParams {
>> + Notifier notifier;
>> + GICv3ITSState *s;
>> +} ItsInitNotifierParams;
>> +
>> +/**
>> + *
>> + * We currently do not use kvm_arm_register_device to provide
>> + * the kernel with the vITS control frame base address since the
>> + * KVM_DEV_ARM_VGIC_CTRL_INIT init MUST be called after the
>> + * KVM_ARM_SET_DEVICE_ADDR and the kvm_arm_register_device
>> + * infra does not allow this.
>> + */
>
> I thought we'd fixed the kernel API so we didn't need to
> have this workaround?
The kernel fixes landed in kvmarm/master so I will respin the series
accordingly.
Thanks
Eric
>
>> +static void its_notify(Notifier *notifier, void *data)
>> +{
>> + ItsInitNotifierParams *p = DO_UPCAST(ItsInitNotifierParams,
>> + notifier, notifier);
>> + GICv3ITSState *s = p->s;
>> + MemoryRegion *mr = &s->iomem_its_cntrl;
>> + MemoryRegionSection mrs;
>> + struct kvm_device_attr attr;
>> + uint64_t addr;
>> + int ret;
>> +
>> + mrs = memory_region_find(mr, 0, 1);
>> + addr = mrs.offset_within_address_space;
>> +
>> + attr.flags = 0;
>> + attr.group = KVM_DEV_ARM_VGIC_GRP_ADDR;
>> + attr.attr = KVM_VGIC_ITS_ADDR_TYPE;
>> + attr.addr = (uintptr_t)&addr;
>> +
>> + s->gits_translater_gpa = addr + ITS_CONTROL_SIZE + 0x40;
>> +
>> + ret = kvm_device_ioctl(s->dev_fd, KVM_SET_DEVICE_ATTR, attr);
>> + if (ret) {
>> + error_setg_errno(&error_fatal, -ret,
>> + "not able to set base address for vITS ctrl frame");
>> + }
>> +
>> + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
>> + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
>> +}
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class
2016-08-12 14:12 ` Peter Maydell
@ 2016-08-17 16:03 ` Auger Eric
0 siblings, 0 replies; 19+ messages in thread
From: Auger Eric @ 2016-08-17 16:03 UTC (permalink / raw)
To: Peter Maydell
Cc: eric.auger.pro, qemu-arm, QEMU Developers, Pavel Fedin,
Shlomo Pongratz, Diana Craciun, Tomasz Nowicki, Shannon Zhao,
Christoffer Dall, Andrew Jones
Hi Peter,
On 12/08/2016 16:12, Peter Maydell wrote:
> On 2 August 2016 at 19:07, Eric Auger <eric.auger@redhat.com> wrote:
>> From: Pavel Fedin <p.fedin@samsung.com>
>>
>> This is the basic skeleton for both KVM and software-emulated ITS.
>> Since we already prepare status structure, we also introduce complete
>> VMState description. But, because we currently have no migratable
>> implementations, we also set unmigratable flag.
>>
>> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>
>> ---
>> v4 -> v5:
>> - send_msi can return 0 meaning the MSI was rejected by guest. Handle this
>> value as an error
>>
>> v3 -> v4:
>> - fix compilation error
>> - msi_supported -> msi_nonbroken
>> - streamid -> requester_id
>> - use PRIx64
>> - read ops uses _with_attrs form
>> - 16/32b write access allowed to GITS_TRANSLATER
>> - move its_class_name in kvm_arm.h and remove #ifdef TARGET_AARCH64
>> - add new kvm device dev_fd field
>> - add new gits_translater_gpa field in GICv3ITSState
>> ---
>> hw/intc/Makefile.objs | 1 +
>> hw/intc/arm_gicv3_its_common.c | 155 +++++++++++++++++++++++++++++++++
>> include/hw/intc/arm_gicv3_its_common.h | 75 ++++++++++++++++
>> target-arm/kvm_arm.h | 19 ++++
>> 4 files changed, 250 insertions(+)
>> create mode 100644 hw/intc/arm_gicv3_its_common.c
>> create mode 100644 include/hw/intc/arm_gicv3_its_common.h
>>
>> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
>> index 05ec21b..23a39f7 100644
>> --- a/hw/intc/Makefile.objs
>> +++ b/hw/intc/Makefile.objs
>> @@ -16,6 +16,7 @@ common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
>> common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
>> common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
>> common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
>> +common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
>> common-obj-$(CONFIG_OPENPIC) += openpic.o
>>
>> obj-$(CONFIG_APIC) += apic.o apic_common.o
>> diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
>> new file mode 100644
>> index 0000000..0d08ff2
>> --- /dev/null
>> +++ b/hw/intc/arm_gicv3_its_common.c
>> @@ -0,0 +1,155 @@
>> +/*
>> + * ITS base class for a GICv3-based system
>> + *
>> + * Copyright (c) 2015 Samsung Electronics Co., Ltd.
>> + * Written by Pavel Fedin
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/pci/msi.h"
>> +#include "hw/intc/arm_gicv3_its_common.h"
>> +#include "qemu/log.h"
>> +
>> +static void gicv3_its_pre_save(void *opaque)
>> +{
>> + GICv3ITSState *s = (GICv3ITSState *)opaque;
>> + GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
>> +
>> + if (c->pre_save) {
>> + c->pre_save(s);
>> + }
>> +}
>> +
>> +static int gicv3_its_post_load(void *opaque, int version_id)
>> +{
>> + GICv3ITSState *s = (GICv3ITSState *)opaque;
>> + GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
>> +
>> + if (c->post_load) {
>> + c->post_load(s);
>> + }
>> + return 0;
>> +}
>> +
>> +static const VMStateDescription vmstate_its = {
>> + .name = "arm_gicv3_its",
>> + .pre_save = gicv3_its_pre_save,
>> + .post_load = gicv3_its_post_load,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32(ctlr, GICv3ITSState),
>> + VMSTATE_UINT64(cbaser, GICv3ITSState),
>> + VMSTATE_UINT64(cwriter, GICv3ITSState),
>> + VMSTATE_UINT64(creadr, GICv3ITSState),
>> + VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
>> + VMSTATE_END_OF_LIST()
>> + },
>> + .unmigratable = true,
>
> Why define the fields and also mark it unmigratable?
> A comment saying why the device is unmigratable would be good.
Yes sure I will remove the fields and add a comment on the migration status.
>
>> +};
>> +
>> +static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
>> + uint64_t *data, unsigned size,
>> + MemTxAttrs attrs)
>> +{
>> + qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
>> + return MEMTX_ERROR;
>> +}
>> +
>> +static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
>> + uint64_t value, unsigned size,
>> + MemTxAttrs attrs)
>> +{
>> + if (offset == 0x0040 && ((size == 2) || (size == 4))) {
>> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
>> + GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
>> + int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
>> +
>> + if (ret <= 0) {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "ITS: Error sending MSI: %s\n", strerror(-ret));
>> + return MEMTX_DECODE_ERROR;
>> + }
>> +
>> + return MEMTX_OK;
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "ITS write at bad offset 0x%jX\n", offset);
>
> Can we be consistent about the format string used for printing hwaddrs?
> I suspect this one won't build on 32-bit.
I will use PRIx64 instead.
Thanks
Eric
>
>> + return MEMTX_DECODE_ERROR;
>> + }
>> +}
>> +
>> +static const MemoryRegionOps gicv3_its_trans_ops = {
>> + .read_with_attrs = gicv3_its_trans_read,
>> + .write_with_attrs = gicv3_its_trans_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
>> +{
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(s);
>> +
>> + memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
>> + "control", ITS_CONTROL_SIZE);
>> + memory_region_init_io(&s->iomem_its, OBJECT(s), &gicv3_its_trans_ops, s,
>> + "translation", ITS_TRANS_SIZE);
>> +
>> + /* Our two regions are always adjacent, therefore we now combine them
>> + * into a single one in order to make our users' life easier.
>> + */
>> + memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
>> + memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
>> + memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
>> + &s->iomem_its);
>> + sysbus_init_mmio(sbd, &s->iomem_main);
>> +
>> + msi_nonbroken = true;
>> +}
>> +
>> +static void gicv3_its_common_reset(DeviceState *dev)
>> +{
>> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
>> +
>> + s->ctlr = 0;
>> + s->cbaser = 0;
>> + s->cwriter = 0;
>> + s->creadr = 0;
>> + memset(&s->baser, 0, sizeof(s->baser));
>> +
>> + gicv3_its_post_load(s, 0);
>> +}
>
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [RFC v5 4/7] target-arm/kvm: Pass requester ID to MSI routing functions
2016-08-12 14:19 ` Peter Maydell
@ 2016-08-17 16:05 ` Auger Eric
0 siblings, 0 replies; 19+ messages in thread
From: Auger Eric @ 2016-08-17 16:05 UTC (permalink / raw)
To: Peter Maydell
Cc: eric.auger.pro, qemu-arm, QEMU Developers, Pavel Fedin,
Shlomo Pongratz, Diana Craciun, Tomasz Nowicki, Shannon Zhao,
Christoffer Dall, Andrew Jones
Hi Peter,
On 12/08/2016 16:19, Peter Maydell wrote:
> On 2 August 2016 at 19:07, Eric Auger <eric.auger@redhat.com> wrote:
>> From: Pavel Fedin <p.fedin@samsung.com>
>>
>> Introduce global kvm_arm_msi_use_devid flag and pass device IDs in
>> kvm_arch_fixup_msi_route(). Device IDs are required by the ITS.
>>
>> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>
>> ---
>>
>> v3 -> v4:
>> - OR route->flags with KVM_MSI_VALID_DEVID
>> ---
>> target-arm/kvm.c | 6 ++++++
>> target-arm/kvm_arm.h | 3 +++
>> 2 files changed, 9 insertions(+)
>>
>> diff --git a/target-arm/kvm.c b/target-arm/kvm.c
>> index dbe393c..4675aa3 100644
>> --- a/target-arm/kvm.c
>> +++ b/target-arm/kvm.c
>> @@ -22,6 +22,7 @@
>> #include "cpu.h"
>> #include "internals.h"
>> #include "hw/arm/arm.h"
>> +#include "hw/pci/pci.h"
>> #include "exec/memattrs.h"
>> #include "hw/boards.h"
>> #include "qemu/log.h"
>> @@ -31,6 +32,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
>> };
>>
>> static bool cap_has_mp_state;
>> +bool kvm_arm_msi_use_devid;
>>
>> int kvm_arm_vcpu_init(CPUState *cs)
>> {
>> @@ -619,6 +621,10 @@ int kvm_arm_vgic_probe(void)
>> int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
>> uint64_t address, uint32_t data, PCIDevice *dev)
>> {
>> + if (kvm_arm_msi_use_devid) {
>> + route->flags |= KVM_MSI_VALID_DEVID;
>> + route->u.msi.devid = pci_requester_id(dev);
>> + }
>> return 0;
>> }
>>
>> diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
>> index 633d088..befcfd1 100644
>> --- a/target-arm/kvm_arm.h
>> +++ b/target-arm/kvm_arm.h
>> @@ -121,6 +121,9 @@ bool write_kvmstate_to_list(ARMCPU *cpu);
>> void kvm_arm_reset_vcpu(ARMCPU *cpu);
>>
>> #ifdef CONFIG_KVM
>> +
>> +extern bool kvm_arm_msi_use_devid;
>> +
>
> The kernel documentation and most of the code for this flag
> isn't ARM specific, which suggests to me that we should put
> the QEMU support into the non-architecture-specific files too.
> That is, a flag and wrapper function like all the existing
> ones in include/sysemu/kvm.h, and then put the
> if (kvm_msi_use_devid()) {
> ...
> }
> in the functions in kvm-all.c that need it.
OK this makes sense to me too
Thank you for your time
Best Regards
Eric
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2016-08-17 16:05 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-02 18:07 [Qemu-devel] [RFC v5 0/7] vITS support Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 1/7] hw/intc/arm_gicv3_its: Implement ITS base class Eric Auger
2016-08-12 14:12 ` Peter Maydell
2016-08-17 16:03 ` Auger Eric
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 2/7] target-arm: move gicv3_class_name from machine to kvm_arm.h Eric Auger
2016-08-12 14:01 ` Peter Maydell
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 3/7] linux-headers: update to 4.7-rc6 + ITS emulation and GSI routing Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 4/7] target-arm/kvm: Pass requester ID to MSI routing functions Eric Auger
2016-08-12 14:19 ` Peter Maydell
2016-08-17 16:05 ` Auger Eric
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 5/7] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Eric Auger
2016-08-12 14:03 ` Peter Maydell
2016-08-17 15:59 ` Auger Eric
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 6/7] arm/virt: Add ITS to the virt board Eric Auger
2016-08-02 18:07 ` [Qemu-devel] [RFC v5 7/7] hw/arm/virt-acpi-build: Add ITS description in ACPI MADT table Eric Auger
2016-08-03 0:56 ` Shannon Zhao
2016-08-03 7:22 ` Auger Eric
2016-08-03 8:50 ` Shannon Zhao
2016-08-03 9:02 ` Auger Eric
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