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* [PATCH] drm/i915/bxt: Bring MIPI out of reset
@ 2016-08-04 18:16 Bob Paauwe
  2016-08-05  5:24 ` ✗ Ro.CI.BAT: failure for " Patchwork
  2016-08-05 22:23 ` [isg-gms] [PATCH] " Xiong, James
  0 siblings, 2 replies; 6+ messages in thread
From: Bob Paauwe @ 2016-08-04 18:16 UTC (permalink / raw)
  To: isg-gms, intel-gfx

and power up the DSI regulator when initializing a MIPI display.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  8 ++++++++
 drivers/gpu/drm/i915/intel_dsi.c | 13 +++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6607aaf..da29d74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1262,11 +1262,19 @@ enum skl_disp_power_wells {
 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
 #define   DPIO_UPAR_SHIFT		30
 
+/* BXT DSI Regulator registers */
+#define BXT_DSI_CFG                    _MMIO(0x160020)
+#define   STRAP_SELECT                 (1 << 0)
+
+#define BXT_DSI_TXCNTRL                _MMIO(0x160054)
+#define   HS_IO_CONTROL_SELECT         0x0
+
 /* BXT PHY registers */
 #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
 
 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
 #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
+#define   MIPIO_RST_CTRL                (1 << 2)
 
 #define _PHY_CTL_FAMILY_EDP		0x64C80
 #define _PHY_CTL_FAMILY_DDI		0x64C90
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b2d2cba..c2aa9e1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -549,6 +549,19 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 		I915_WRITE(DSPCLK_GATE_D, tmp);
 	}
 
+	if (IS_BROXTON(dev)) {
+		/*
+		 * Bring the MIPI IO out of reset and power up
+		 * the DSI regulator.
+		 */
+		tmp = I915_READ(BXT_P_CR_GT_DISP_PWRON);
+		tmp |= MIPIO_RST_CTRL;
+		I915_WRITE(BXT_P_CR_GT_DISP_PWRON, tmp);
+
+		I915_WRITE(BXT_DSI_CFG, STRAP_SELECT);
+		I915_WRITE(BXT_DSI_TXCNTRL, HS_IO_CONTROL_SELECT);
+	}
+
 	/* put device in ready state */
 	intel_dsi_device_ready(encoder);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* ✗ Ro.CI.BAT: failure for drm/i915/bxt: Bring MIPI out of reset
  2016-08-04 18:16 [PATCH] drm/i915/bxt: Bring MIPI out of reset Bob Paauwe
@ 2016-08-05  5:24 ` Patchwork
  2016-08-05 22:23 ` [isg-gms] [PATCH] " Xiong, James
  1 sibling, 0 replies; 6+ messages in thread
From: Patchwork @ 2016-08-05  5:24 UTC (permalink / raw)
  To: Bob Paauwe; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/bxt: Bring MIPI out of reset
URL   : https://patchwork.freedesktop.org/series/10682/
State : failure

== Summary ==

Applying: drm/i915/bxt: Bring MIPI out of reset
fatal: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_reg.h).
error: could not build fake ancestor
Patch failed at 0001 drm/i915/bxt: Bring MIPI out of reset
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
  2016-08-04 18:16 [PATCH] drm/i915/bxt: Bring MIPI out of reset Bob Paauwe
  2016-08-05  5:24 ` ✗ Ro.CI.BAT: failure for " Patchwork
@ 2016-08-05 22:23 ` Xiong, James
  2016-08-05 23:15   ` Bob Paauwe
  1 sibling, 1 reply; 6+ messages in thread
From: Xiong, James @ 2016-08-05 22:23 UTC (permalink / raw)
  To: Paauwe, Bob J, isg-gms, intel-gfx

Reviewed-by James Xiong <james.xiong@intel.com>

-----Original Message-----
From: isg-gms-request@eclists.intel.com [mailto:isg-gms-request@eclists.intel.com] On Behalf Of Paauwe, Bob J
Sent: Thursday, August 4, 2016 11:16 AM
To: isg-gms <isg-gms@eclists.intel.com>; intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Paauwe, Bob J <bob.j.paauwe@intel.com>
Subject: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset

and power up the DSI regulator when initializing a MIPI display.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  8 ++++++++  drivers/gpu/drm/i915/intel_dsi.c | 13 +++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6607aaf..da29d74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1262,11 +1262,19 @@ enum skl_disp_power_wells {  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
 #define   DPIO_UPAR_SHIFT		30
 
+/* BXT DSI Regulator registers */
+#define BXT_DSI_CFG                    _MMIO(0x160020)
+#define   STRAP_SELECT                 (1 << 0)
+
+#define BXT_DSI_TXCNTRL                _MMIO(0x160054)
+#define   HS_IO_CONTROL_SELECT         0x0
+
 /* BXT PHY registers */
 #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
 
 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
 #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
+#define   MIPIO_RST_CTRL                (1 << 2)
 
 #define _PHY_CTL_FAMILY_EDP		0x64C80
 #define _PHY_CTL_FAMILY_DDI		0x64C90
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b2d2cba..c2aa9e1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -549,6 +549,19 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 		I915_WRITE(DSPCLK_GATE_D, tmp);
 	}
 
+	if (IS_BROXTON(dev)) {
+		/*
+		 * Bring the MIPI IO out of reset and power up
+		 * the DSI regulator.
+		 */
+		tmp = I915_READ(BXT_P_CR_GT_DISP_PWRON);
+		tmp |= MIPIO_RST_CTRL;
+		I915_WRITE(BXT_P_CR_GT_DISP_PWRON, tmp);
+
+		I915_WRITE(BXT_DSI_CFG, STRAP_SELECT);
+		I915_WRITE(BXT_DSI_TXCNTRL, HS_IO_CONTROL_SELECT);
+	}
+
 	/* put device in ready state */
 	intel_dsi_device_ready(encoder);
 
--
2.7.4

-------------------------------------
isg-gms@eclists.intel.com
https://eclists.intel.com/sympa/info/isg-gms
Unsubscribe by sending email to sympa@eclists.intel.com with subject "Unsubscribe isg-gms"
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
  2016-08-05 22:23 ` [isg-gms] [PATCH] " Xiong, James
@ 2016-08-05 23:15   ` Bob Paauwe
  2016-08-19 10:04     ` Jani Nikula
  0 siblings, 1 reply; 6+ messages in thread
From: Bob Paauwe @ 2016-08-05 23:15 UTC (permalink / raw)
  To: Xiong, James; +Cc: isg-gms, intel-gfx

On Fri, 5 Aug 2016 15:23:23 -0700
"Xiong, James" <james.xiong@intel.com> wrote:

> Reviewed-by James Xiong <james.xiong@intel.com>

Merged to gold.  Thanks for the review.

Bob
> 
> -----Original Message-----
> From: isg-gms-request@eclists.intel.com [mailto:isg-gms-request@eclists.intel.com] On Behalf Of Paauwe, Bob J
> Sent: Thursday, August 4, 2016 11:16 AM
> To: isg-gms <isg-gms@eclists.intel.com>; intel-gfx <intel-gfx@lists.freedesktop.org>
> Cc: Paauwe, Bob J <bob.j.paauwe@intel.com>
> Subject: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
> 
> and power up the DSI regulator when initializing a MIPI display.
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  8 ++++++++  drivers/gpu/drm/i915/intel_dsi.c | 13 +++++++++++++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6607aaf..da29d74 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1262,11 +1262,19 @@ enum skl_disp_power_wells {  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
>  #define   DPIO_UPAR_SHIFT		30
>  
> +/* BXT DSI Regulator registers */
> +#define BXT_DSI_CFG                    _MMIO(0x160020)
> +#define   STRAP_SELECT                 (1 << 0)
> +
> +#define BXT_DSI_TXCNTRL                _MMIO(0x160054)
> +#define   HS_IO_CONTROL_SELECT         0x0
> +
>  /* BXT PHY registers */
>  #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
>  
>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
>  #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
> +#define   MIPIO_RST_CTRL                (1 << 2)
>  
>  #define _PHY_CTL_FAMILY_EDP		0x64C80
>  #define _PHY_CTL_FAMILY_DDI		0x64C90
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index b2d2cba..c2aa9e1 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -549,6 +549,19 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  		I915_WRITE(DSPCLK_GATE_D, tmp);
>  	}
>  
> +	if (IS_BROXTON(dev)) {
> +		/*
> +		 * Bring the MIPI IO out of reset and power up
> +		 * the DSI regulator.
> +		 */
> +		tmp = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> +		tmp |= MIPIO_RST_CTRL;
> +		I915_WRITE(BXT_P_CR_GT_DISP_PWRON, tmp);
> +
> +		I915_WRITE(BXT_DSI_CFG, STRAP_SELECT);
> +		I915_WRITE(BXT_DSI_TXCNTRL, HS_IO_CONTROL_SELECT);
> +	}
> +
>  	/* put device in ready state */
>  	intel_dsi_device_ready(encoder);
>  
> --
> 2.7.4
> 
> -------------------------------------
> isg-gms@eclists.intel.com
> https://eclists.intel.com/sympa/info/isg-gms
> Unsubscribe by sending email to sympa@eclists.intel.com with subject "Unsubscribe isg-gms"



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
  2016-08-05 23:15   ` Bob Paauwe
@ 2016-08-19 10:04     ` Jani Nikula
  2016-08-19 15:59       ` Bob Paauwe
  0 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2016-08-19 10:04 UTC (permalink / raw)
  To: Bob Paauwe, Xiong, James; +Cc: isg-gms, intel-gfx

On Sat, 06 Aug 2016, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> On Fri, 5 Aug 2016 15:23:23 -0700
> "Xiong, James" <james.xiong@intel.com> wrote:
>
>> Reviewed-by James Xiong <james.xiong@intel.com>
>
> Merged to gold.  Thanks for the review.

What does this mean? Why do you Cc both internal and external lists?

BR,
Jani.


>
> Bob
>> 
>> -----Original Message-----
>> From: isg-gms-request@eclists.intel.com [mailto:isg-gms-request@eclists.intel.com] On Behalf Of Paauwe, Bob J
>> Sent: Thursday, August 4, 2016 11:16 AM
>> To: isg-gms <isg-gms@eclists.intel.com>; intel-gfx <intel-gfx@lists.freedesktop.org>
>> Cc: Paauwe, Bob J <bob.j.paauwe@intel.com>
>> Subject: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
>> 
>> and power up the DSI regulator when initializing a MIPI display.
>> 
>> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h  |  8 ++++++++  drivers/gpu/drm/i915/intel_dsi.c | 13 +++++++++++++
>>  2 files changed, 21 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6607aaf..da29d74 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1262,11 +1262,19 @@ enum skl_disp_power_wells {  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
>>  #define   DPIO_UPAR_SHIFT		30
>>  
>> +/* BXT DSI Regulator registers */
>> +#define BXT_DSI_CFG                    _MMIO(0x160020)
>> +#define   STRAP_SELECT                 (1 << 0)
>> +
>> +#define BXT_DSI_TXCNTRL                _MMIO(0x160054)
>> +#define   HS_IO_CONTROL_SELECT         0x0
>> +
>>  /* BXT PHY registers */
>>  #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
>>  
>>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
>>  #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
>> +#define   MIPIO_RST_CTRL                (1 << 2)
>>  
>>  #define _PHY_CTL_FAMILY_EDP		0x64C80
>>  #define _PHY_CTL_FAMILY_DDI		0x64C90
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index b2d2cba..c2aa9e1 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -549,6 +549,19 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>>  		I915_WRITE(DSPCLK_GATE_D, tmp);
>>  	}
>>  
>> +	if (IS_BROXTON(dev)) {
>> +		/*
>> +		 * Bring the MIPI IO out of reset and power up
>> +		 * the DSI regulator.
>> +		 */
>> +		tmp = I915_READ(BXT_P_CR_GT_DISP_PWRON);
>> +		tmp |= MIPIO_RST_CTRL;
>> +		I915_WRITE(BXT_P_CR_GT_DISP_PWRON, tmp);
>> +
>> +		I915_WRITE(BXT_DSI_CFG, STRAP_SELECT);
>> +		I915_WRITE(BXT_DSI_TXCNTRL, HS_IO_CONTROL_SELECT);
>> +	}
>> +
>>  	/* put device in ready state */
>>  	intel_dsi_device_ready(encoder);
>>  
>> --
>> 2.7.4
>> 
>> -------------------------------------
>> isg-gms@eclists.intel.com
>> https://eclists.intel.com/sympa/info/isg-gms
>> Unsubscribe by sending email to sympa@eclists.intel.com with subject "Unsubscribe isg-gms"

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
  2016-08-19 10:04     ` Jani Nikula
@ 2016-08-19 15:59       ` Bob Paauwe
  0 siblings, 0 replies; 6+ messages in thread
From: Bob Paauwe @ 2016-08-19 15:59 UTC (permalink / raw)
  To: Jani Nikula; +Cc: isg-gms, Xiong, James, intel-gfx

On Fri, 19 Aug 2016 13:04:54 +0300
Jani Nikula <jani.nikula@linux.intel.com> wrote:

> On Sat, 06 Aug 2016, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> > On Fri, 5 Aug 2016 15:23:23 -0700
> > "Xiong, James" <james.xiong@intel.com> wrote:
> >  
> >> Reviewed-by James Xiong <james.xiong@intel.com>  
> >
> > Merged to gold.  Thanks for the review.  
> 
> What does this mean? Why do you Cc both internal and external lists?
> 
> BR,
> Jani.
> 

Hi Jani,

The patch was sent to both the upstream list for review and to our IOTG
internal list.  Since we're freezing our code for release and this is
needed to fully enable MIPI functionality on our platform, it was
merged into our release branch.

I should have been more careful about where the reply went. It didn't
need to go the public list.  Sorry for the confusion.

Bob

> 
> >
> > Bob  
> >> 
> >> -----Original Message-----
> >> From: isg-gms-request@eclists.intel.com [mailto:isg-gms-request@eclists.intel.com] On Behalf Of Paauwe, Bob J
> >> Sent: Thursday, August 4, 2016 11:16 AM
> >> To: isg-gms <isg-gms@eclists.intel.com>; intel-gfx <intel-gfx@lists.freedesktop.org>
> >> Cc: Paauwe, Bob J <bob.j.paauwe@intel.com>
> >> Subject: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
> >> 
> >> and power up the DSI regulator when initializing a MIPI display.
> >> 
> >> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h  |  8 ++++++++  drivers/gpu/drm/i915/intel_dsi.c | 13 +++++++++++++
> >>  2 files changed, 21 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6607aaf..da29d74 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -1262,11 +1262,19 @@ enum skl_disp_power_wells {  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
> >>  #define   DPIO_UPAR_SHIFT		30
> >>  
> >> +/* BXT DSI Regulator registers */
> >> +#define BXT_DSI_CFG                    _MMIO(0x160020)
> >> +#define   STRAP_SELECT                 (1 << 0)
> >> +
> >> +#define BXT_DSI_TXCNTRL                _MMIO(0x160054)
> >> +#define   HS_IO_CONTROL_SELECT         0x0
> >> +
> >>  /* BXT PHY registers */
> >>  #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
> >>  
> >>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
> >>  #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
> >> +#define   MIPIO_RST_CTRL                (1 << 2)
> >>  
> >>  #define _PHY_CTL_FAMILY_EDP		0x64C80
> >>  #define _PHY_CTL_FAMILY_DDI		0x64C90
> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> >> index b2d2cba..c2aa9e1 100644
> >> --- a/drivers/gpu/drm/i915/intel_dsi.c
> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> >> @@ -549,6 +549,19 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> >>  		I915_WRITE(DSPCLK_GATE_D, tmp);
> >>  	}
> >>  
> >> +	if (IS_BROXTON(dev)) {
> >> +		/*
> >> +		 * Bring the MIPI IO out of reset and power up
> >> +		 * the DSI regulator.
> >> +		 */
> >> +		tmp = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> >> +		tmp |= MIPIO_RST_CTRL;
> >> +		I915_WRITE(BXT_P_CR_GT_DISP_PWRON, tmp);
> >> +
> >> +		I915_WRITE(BXT_DSI_CFG, STRAP_SELECT);
> >> +		I915_WRITE(BXT_DSI_TXCNTRL, HS_IO_CONTROL_SELECT);
> >> +	}
> >> +
> >>  	/* put device in ready state */
> >>  	intel_dsi_device_ready(encoder);
> >>  
> >> --
> >> 2.7.4
> >> 
> >> -------------------------------------
> >> isg-gms@eclists.intel.com
> >> https://eclists.intel.com/sympa/info/isg-gms
> >> Unsubscribe by sending email to sympa@eclists.intel.com with subject "Unsubscribe isg-gms"  
> 



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-08-19 15:58 UTC | newest]

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2016-08-04 18:16 [PATCH] drm/i915/bxt: Bring MIPI out of reset Bob Paauwe
2016-08-05  5:24 ` ✗ Ro.CI.BAT: failure for " Patchwork
2016-08-05 22:23 ` [isg-gms] [PATCH] " Xiong, James
2016-08-05 23:15   ` Bob Paauwe
2016-08-19 10:04     ` Jani Nikula
2016-08-19 15:59       ` Bob Paauwe

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