* [U-Boot] [PATCH 0/4] Amlogic Meson pinctrl driver for u-boot
@ 2016-08-16 9:49 ` Beniamino Galvani
0 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: u-boot
Hi,
these patches add a pinctrl driver for Meson GXBB and enable
Ethernet support through the device tree.
Beniamino Galvani (4):
pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
arm: dts: update DTS files for meson-gxbb and odroid-c2
pinctrl: add driver for meson-gxbb pin controller
meson: odroid-c2: enable Ethernet support through the device tree
arch/arm/dts/meson-gxbb-odroidc2.dts | 19 +
arch/arm/dts/meson-gxbb.dtsi | 170 +++++++-
arch/arm/include/asm/arch-meson/gxbb.h | 3 -
board/amlogic/odroid-c2/odroid-c2.c | 13 -
configs/odroid-c2_defconfig | 3 +
drivers/net/designware.c | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/meson/Kconfig | 11 +
drivers/pinctrl/meson/Makefile | 6 +
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 432 +++++++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 179 +++++++++
drivers/pinctrl/meson/pinctrl-meson.h | 74 ++++
drivers/pinctrl/pinctrl-generic.c | 6 +-
include/dt-bindings/gpio/meson-gxbb-gpio.h | 154 ++++++++
.../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 210 ++++++++++
16 files changed, 1264 insertions(+), 19 deletions(-)
create mode 100644 drivers/pinctrl/meson/Kconfig
create mode 100644 drivers/pinctrl/meson/Makefile
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxbb.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
create mode 100644 include/dt-bindings/gpio/meson-gxbb-gpio.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
--
2.7.4
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 0/4] Amlogic Meson pinctrl driver for u-boot
@ 2016-08-16 9:49 ` Beniamino Galvani
0 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: linus-amlogic
Hi,
these patches add a pinctrl driver for Meson GXBB and enable
Ethernet support through the device tree.
Beniamino Galvani (4):
pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
arm: dts: update DTS files for meson-gxbb and odroid-c2
pinctrl: add driver for meson-gxbb pin controller
meson: odroid-c2: enable Ethernet support through the device tree
arch/arm/dts/meson-gxbb-odroidc2.dts | 19 +
arch/arm/dts/meson-gxbb.dtsi | 170 +++++++-
arch/arm/include/asm/arch-meson/gxbb.h | 3 -
board/amlogic/odroid-c2/odroid-c2.c | 13 -
configs/odroid-c2_defconfig | 3 +
drivers/net/designware.c | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/meson/Kconfig | 11 +
drivers/pinctrl/meson/Makefile | 6 +
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 432 +++++++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 179 +++++++++
drivers/pinctrl/meson/pinctrl-meson.h | 74 ++++
drivers/pinctrl/pinctrl-generic.c | 6 +-
include/dt-bindings/gpio/meson-gxbb-gpio.h | 154 ++++++++
.../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 210 ++++++++++
16 files changed, 1264 insertions(+), 19 deletions(-)
create mode 100644 drivers/pinctrl/meson/Kconfig
create mode 100644 drivers/pinctrl/meson/Makefile
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxbb.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
create mode 100644 include/dt-bindings/gpio/meson-gxbb-gpio.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
--
2.7.4
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-16 9:49 ` Beniamino Galvani
-1 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: u-boot
In cases where the pins and groups definitions are in a sub-node, as:
uart_a {
mux {
groups = "uart_tx_a", "uart_rx_a";
function = "uart_a";
};
};
pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
drivers/pinctrl/pinctrl-generic.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
index e86b72a..baff40f 100644
--- a/drivers/pinctrl/pinctrl-generic.c
+++ b/drivers/pinctrl/pinctrl-generic.c
@@ -312,8 +312,10 @@ static int pinctrl_generic_set_state_subnode(struct udevice *dev,
is_group = true;
strings_count = fdt_count_strings(fdt, node,
subnode_target_type);
- if (strings_count < 0)
- return -EINVAL;
+ if (strings_count < 0) {
+ /* skip this node; may contain config child nodes */
+ return 0;
+ }
}
for (i = 0; i < strings_count; i++) {
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
@ 2016-08-16 9:49 ` Beniamino Galvani
0 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: linus-amlogic
In cases where the pins and groups definitions are in a sub-node, as:
uart_a {
mux {
groups = "uart_tx_a", "uart_rx_a";
function = "uart_a";
};
};
pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
drivers/pinctrl/pinctrl-generic.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
index e86b72a..baff40f 100644
--- a/drivers/pinctrl/pinctrl-generic.c
+++ b/drivers/pinctrl/pinctrl-generic.c
@@ -312,8 +312,10 @@ static int pinctrl_generic_set_state_subnode(struct udevice *dev,
is_group = true;
strings_count = fdt_count_strings(fdt, node,
subnode_target_type);
- if (strings_count < 0)
- return -EINVAL;
+ if (strings_count < 0) {
+ /* skip this node; may contain config child nodes */
+ return 0;
+ }
}
for (i = 0; i < strings_count; i++) {
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 2/4] arm: dts: update DTS files for meson-gxbb and odroid-c2
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-16 9:49 ` Beniamino Galvani
-1 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: u-boot
Import DTS files and dt-bindings includes from Linux 4.8-rc1.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
arch/arm/dts/meson-gxbb-odroidc2.dts | 19 ++
arch/arm/dts/meson-gxbb.dtsi | 170 ++++++++++++++++-
include/dt-bindings/gpio/meson-gxbb-gpio.h | 154 +++++++++++++++
.../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 210 +++++++++++++++++++++
4 files changed, 552 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/gpio/meson-gxbb-gpio.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 653c2fa..79bee64 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -45,6 +45,7 @@
/dts-v1/;
#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
@@ -62,8 +63,26 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ blue {
+ label = "c2:blue:alive";
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
};
&uart_AO {
status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_pins>;
+ pinctrl-names = "default";
};
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
index 832815d..e502c24 100644
--- a/arch/arm/dts/meson-gxbb.dtsi
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -43,6 +43,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/meson-gxbb-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
/ {
compatible = "amlogic,meson-gxbb";
@@ -129,13 +131,35 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+ reset: reset-controller at 4404 {
+ compatible = "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x04404 0x0 0x20>;
+ #reset-cells = <1>;
+ };
+
uart_A: serial at 84c0 {
compatible = "amlogic,meson-uart";
- reg = <0x0 0x084c0 0x0 0x14>;
+ reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
+
+ uart_B: serial at 84dc {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x84dc 0x0 0x14>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ uart_C: serial at 8700 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x8700 0x0 0x14>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
};
gic: interrupt-controller at c4301000 {
@@ -158,6 +182,29 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+ pinctrl_aobus: pinctrl at 14 {
+ compatible = "amlogic,meson-gxbb-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio_ao: bank at 14 {
+ reg = <0x0 0x00014 0x0 0x8>,
+ <0x0 0x0002c 0x0 0x4>,
+ <0x0 0x00024 0x0 0x8>;
+ reg-names = "mux", "pull", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ uart_ao_a_pins: uart_ao_a {
+ mux {
+ groups = "uart_tx_ao_a", "uart_rx_ao_a";
+ function = "uart_ao";
+ };
+ };
+ };
+
uart_AO: serial at 4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
@@ -167,6 +214,115 @@
};
};
+ periphs: periphs at c8834000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc8834000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
+
+ rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+
+ pinctrl_periphs: pinctrl at 4b0 {
+ compatible = "amlogic,meson-gxbb-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank at 4b0 {
+ reg = <0x0 0x004b0 0x0 0x28>,
+ <0x0 0x004e8 0x0 0x14>,
+ <0x0 0x00120 0x0 0x14>,
+ <0x0 0x00430 0x0 0x40>;
+ reg-names = "mux", "pull", "pull-enable", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d07",
+ "emmc_cmd",
+ "emmc_clk";
+ function = "emmc";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0",
+ "sdcard_d1",
+ "sdcard_d2",
+ "sdcard_d3",
+ "sdcard_cmd",
+ "sdcard_clk";
+ function = "sdcard";
+ };
+ };
+
+ uart_a_pins: uart_a {
+ mux {
+ groups = "uart_tx_a",
+ "uart_rx_a";
+ function = "uart_a";
+ };
+ };
+
+ uart_b_pins: uart_b {
+ mux {
+ groups = "uart_tx_b",
+ "uart_rx_b";
+ function = "uart_b";
+ };
+ };
+
+ uart_c_pins: uart_c {
+ mux {
+ groups = "uart_tx_c",
+ "uart_rx_c";
+ function = "uart_c";
+ };
+ };
+
+ eth_pins: eth_c {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_clk_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_rxd2",
+ "eth_rxd3",
+ "eth_rgmii_tx_clk",
+ "eth_tx_en",
+ "eth_txd0",
+ "eth_txd1",
+ "eth_txd2",
+ "eth_txd3";
+ function = "eth";
+ };
+ };
+ };
+ };
+
+ hiubus: hiubus at c883c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc883c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+
+ clkc: clock-controller at 0 {
+ compatible = "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x3db>;
+ };
+ };
+
apb: apb at d0000000 {
compatible = "simple-bus";
reg = <0x0 0xd0000000 0x0 0x200000>;
@@ -174,5 +330,17 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
};
+
+ ethmac: ethernet at c9410000 {
+ compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+ reg = <0x0 0xc9410000 0x0 0x10000
+ 0x0 0xc8834540 0x0 0x4>;
+ interrupts = <0 8 1>;
+ interrupt-names = "macirq";
+ clocks = <&xtal>;
+ clock-names = "stmmaceth";
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
};
};
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
new file mode 100644
index 0000000..58654fd
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-gxbb-gpio.h
@@ -0,0 +1,154 @@
+/*
+ * GPIO definitions for Amlogic Meson GXBB SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
+#define _DT_BINDINGS_MESON_GXBB_GPIO_H
+
+#define GPIOAO_0 0
+#define GPIOAO_1 1
+#define GPIOAO_2 2
+#define GPIOAO_3 3
+#define GPIOAO_4 4
+#define GPIOAO_5 5
+#define GPIOAO_6 6
+#define GPIOAO_7 7
+#define GPIOAO_8 8
+#define GPIOAO_9 9
+#define GPIOAO_10 10
+#define GPIOAO_11 11
+#define GPIOAO_12 12
+#define GPIOAO_13 13
+
+#define GPIOZ_0 0
+#define GPIOZ_1 1
+#define GPIOZ_2 2
+#define GPIOZ_3 3
+#define GPIOZ_4 4
+#define GPIOZ_5 5
+#define GPIOZ_6 6
+#define GPIOZ_7 7
+#define GPIOZ_8 8
+#define GPIOZ_9 9
+#define GPIOZ_10 10
+#define GPIOZ_11 11
+#define GPIOZ_12 12
+#define GPIOZ_13 13
+#define GPIOZ_14 14
+#define GPIOZ_15 15
+#define GPIOH_0 16
+#define GPIOH_1 17
+#define GPIOH_2 18
+#define GPIOH_3 19
+#define BOOT_0 20
+#define BOOT_1 21
+#define BOOT_2 22
+#define BOOT_3 23
+#define BOOT_4 24
+#define BOOT_5 25
+#define BOOT_6 26
+#define BOOT_7 27
+#define BOOT_8 28
+#define BOOT_9 29
+#define BOOT_10 30
+#define BOOT_11 31
+#define BOOT_12 32
+#define BOOT_13 33
+#define BOOT_14 34
+#define BOOT_15 35
+#define BOOT_16 36
+#define BOOT_17 37
+#define CARD_0 38
+#define CARD_1 39
+#define CARD_2 40
+#define CARD_3 41
+#define CARD_4 42
+#define CARD_5 43
+#define CARD_6 44
+#define GPIODV_0 45
+#define GPIODV_1 46
+#define GPIODV_2 47
+#define GPIODV_3 48
+#define GPIODV_4 49
+#define GPIODV_5 50
+#define GPIODV_6 51
+#define GPIODV_7 52
+#define GPIODV_8 53
+#define GPIODV_9 54
+#define GPIODV_10 55
+#define GPIODV_11 56
+#define GPIODV_12 57
+#define GPIODV_13 58
+#define GPIODV_14 59
+#define GPIODV_15 60
+#define GPIODV_16 61
+#define GPIODV_17 62
+#define GPIODV_18 63
+#define GPIODV_19 64
+#define GPIODV_20 65
+#define GPIODV_21 66
+#define GPIODV_22 67
+#define GPIODV_23 68
+#define GPIODV_24 69
+#define GPIODV_25 70
+#define GPIODV_26 71
+#define GPIODV_27 72
+#define GPIODV_28 73
+#define GPIODV_29 74
+#define GPIOY_0 75
+#define GPIOY_1 76
+#define GPIOY_2 77
+#define GPIOY_3 78
+#define GPIOY_4 79
+#define GPIOY_5 80
+#define GPIOY_6 81
+#define GPIOY_7 82
+#define GPIOY_8 83
+#define GPIOY_9 84
+#define GPIOY_10 85
+#define GPIOY_11 86
+#define GPIOY_12 87
+#define GPIOY_13 88
+#define GPIOY_14 89
+#define GPIOY_15 90
+#define GPIOY_16 91
+#define GPIOX_0 92
+#define GPIOX_1 93
+#define GPIOX_2 94
+#define GPIOX_3 95
+#define GPIOX_4 96
+#define GPIOX_5 97
+#define GPIOX_6 98
+#define GPIOX_7 99
+#define GPIOX_8 100
+#define GPIOX_9 101
+#define GPIOX_10 102
+#define GPIOX_11 103
+#define GPIOX_12 104
+#define GPIOX_13 105
+#define GPIOX_14 106
+#define GPIOX_15 107
+#define GPIOX_16 108
+#define GPIOX_17 109
+#define GPIOX_18 110
+#define GPIOX_19 111
+#define GPIOX_20 112
+#define GPIOX_21 113
+#define GPIOX_22 114
+#define GPIOCLK_0 115
+#define GPIOCLK_1 116
+#define GPIOCLK_2 117
+#define GPIOCLK_3 118
+#define GPIO_TEST_N 119
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
new file mode 100644
index 0000000..524d607
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
@@ -0,0 +1,210 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
+
+/* RESET0 */
+#define RESET_HIU 0
+/* 1 */
+#define RESET_DOS_RESET 2
+#define RESET_DDR_TOP 3
+#define RESET_DCU_RESET 4
+#define RESET_VIU 5
+#define RESET_AIU 6
+#define RESET_VID_PLL_DIV 7
+/* 8 */
+#define RESET_PMUX 9
+#define RESET_VENC 10
+#define RESET_ASSIST 11
+#define RESET_AFIFO2 12
+#define RESET_VCBUS 13
+/* 14 */
+/* 15 */
+#define RESET_GIC 16
+#define RESET_CAPB3_DECODE 17
+#define RESET_NAND_CAPB3 18
+#define RESET_HDMITX_CAPB3 19
+#define RESET_MALI_CAPB3 20
+#define RESET_DOS_CAPB3 21
+#define RESET_SYS_CPU_CAPB3 22
+#define RESET_CBUS_CAPB3 23
+#define RESET_AHB_CNTL 24
+#define RESET_AHB_DATA 25
+#define RESET_VCBUS_CLK81 26
+#define RESET_MMC 27
+#define RESET_MIPI_0 28
+#define RESET_MIPI_1 29
+#define RESET_MIPI_2 30
+#define RESET_MIPI_3 31
+/* RESET1 */
+#define RESET_CPPM 32
+#define RESET_DEMUX 33
+#define RESET_USB_OTG 34
+#define RESET_DDR 35
+#define RESET_AO_RESET 36
+#define RESET_BT656 37
+#define RESET_AHB_SRAM 38
+/* 39 */
+#define RESET_PARSER 40
+#define RESET_BLKMV 41
+#define RESET_ISA 42
+#define RESET_ETHERNET 43
+#define RESET_SD_EMMC_A 44
+#define RESET_SD_EMMC_B 45
+#define RESET_SD_EMMC_C 46
+#define RESET_ROM_BOOT 47
+#define RESET_SYS_CPU_0 48
+#define RESET_SYS_CPU_1 49
+#define RESET_SYS_CPU_2 50
+#define RESET_SYS_CPU_3 51
+#define RESET_SYS_CPU_CORE_0 52
+#define RESET_SYS_CPU_CORE_1 53
+#define RESET_SYS_CPU_CORE_2 54
+#define RESET_SYS_CPU_CORE_3 55
+#define RESET_SYS_PLL_DIV 56
+#define RESET_SYS_CPU_AXI 57
+#define RESET_SYS_CPU_L2 58
+#define RESET_SYS_CPU_P 59
+#define RESET_SYS_CPU_MBIST 60
+/* 61 */
+/* 62 */
+/* 63 */
+/* RESET2 */
+#define RESET_VD_RMEM 64
+#define RESET_AUDIN 65
+#define RESET_HDMI_TX 66
+/* 67 */
+/* 68 */
+/* 69 */
+#define RESET_GE2D 70
+#define RESET_PARSER_REG 71
+#define RESET_PARSER_FETCH 72
+#define RESET_PARSER_CTL 73
+#define RESET_PARSER_TOP 74
+/* 75 */
+/* 76 */
+#define RESET_AO_CPU_RESET 77
+#define RESET_MALI 78
+#define RESET_HDMI_SYSTEM_RESET 79
+/* 80-95 */
+/* RESET3 */
+#define RESET_RING_OSCILLATOR 96
+#define RESET_SYS_CPU 97
+#define RESET_EFUSE 98
+#define RESET_SYS_CPU_BVCI 99
+#define RESET_AIFIFO 100
+#define RESET_TVFE 101
+#define RESET_AHB_BRIDGE_CNTL 102
+/* 103 */
+#define RESET_AUDIO_DAC 104
+#define RESET_DEMUX_TOP 105
+#define RESET_DEMUX_DES 106
+#define RESET_DEMUX_S2P_0 107
+#define RESET_DEMUX_S2P_1 108
+#define RESET_DEMUX_RESET_0 109
+#define RESET_DEMUX_RESET_1 110
+#define RESET_DEMUX_RESET_2 111
+/* 112-127 */
+/* RESET4 */
+/* 128 */
+/* 129 */
+/* 130 */
+/* 131 */
+#define RESET_DVIN_RESET 132
+#define RESET_RDMA 133
+#define RESET_VENCI 134
+#define RESET_VENCP 135
+/* 136 */
+#define RESET_VDAC 137
+#define RESET_RTC 138
+/* 139 */
+#define RESET_VDI6 140
+#define RESET_VENCL 141
+#define RESET_I2C_MASTER_2 142
+#define RESET_I2C_MASTER_1 143
+/* 144-159 */
+/* RESET5 */
+/* 160-191 */
+/* RESET6 */
+#define RESET_PERIPHS_GENERAL 192
+#define RESET_PERIPHS_SPICC 193
+#define RESET_PERIPHS_SMART_CARD 194
+#define RESET_PERIPHS_SAR_ADC 195
+#define RESET_PERIPHS_I2C_MASTER_0 196
+#define RESET_SANA 197
+/* 198 */
+#define RESET_PERIPHS_STREAM_INTERFACE 199
+#define RESET_PERIPHS_SDIO 200
+#define RESET_PERIPHS_UART_0 201
+#define RESET_PERIPHS_UART_1_2 202
+#define RESET_PERIPHS_ASYNC_0 203
+#define RESET_PERIPHS_ASYNC_1 204
+#define RESET_PERIPHS_SPI_0 205
+#define RESET_PERIPHS_SDHC 206
+#define RESET_UART_SLIP 207
+/* 208-223 */
+/* RESET7 */
+#define RESET_USB_DDR_0 224
+#define RESET_USB_DDR_1 225
+#define RESET_USB_DDR_2 226
+#define RESET_USB_DDR_3 227
+/* 228 */
+#define RESET_DEVICE_MMC_ARB 229
+/* 230 */
+#define RESET_VID_LOCK 231
+#define RESET_A9_DMC_PIPEL 232
+/* 233-255 */
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/4] arm: dts: update DTS files for meson-gxbb and odroid-c2
@ 2016-08-16 9:49 ` Beniamino Galvani
0 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: linus-amlogic
Import DTS files and dt-bindings includes from Linux 4.8-rc1.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
arch/arm/dts/meson-gxbb-odroidc2.dts | 19 ++
arch/arm/dts/meson-gxbb.dtsi | 170 ++++++++++++++++-
include/dt-bindings/gpio/meson-gxbb-gpio.h | 154 +++++++++++++++
.../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 210 +++++++++++++++++++++
4 files changed, 552 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/gpio/meson-gxbb-gpio.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 653c2fa..79bee64 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -45,6 +45,7 @@
/dts-v1/;
#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
@@ -62,8 +63,26 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ blue {
+ label = "c2:blue:alive";
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
};
&uart_AO {
status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_pins>;
+ pinctrl-names = "default";
};
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
index 832815d..e502c24 100644
--- a/arch/arm/dts/meson-gxbb.dtsi
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -43,6 +43,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/meson-gxbb-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
/ {
compatible = "amlogic,meson-gxbb";
@@ -129,13 +131,35 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+ reset: reset-controller at 4404 {
+ compatible = "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x04404 0x0 0x20>;
+ #reset-cells = <1>;
+ };
+
uart_A: serial at 84c0 {
compatible = "amlogic,meson-uart";
- reg = <0x0 0x084c0 0x0 0x14>;
+ reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
+
+ uart_B: serial at 84dc {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x84dc 0x0 0x14>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ uart_C: serial at 8700 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x8700 0x0 0x14>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
};
gic: interrupt-controller at c4301000 {
@@ -158,6 +182,29 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+ pinctrl_aobus: pinctrl at 14 {
+ compatible = "amlogic,meson-gxbb-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio_ao: bank at 14 {
+ reg = <0x0 0x00014 0x0 0x8>,
+ <0x0 0x0002c 0x0 0x4>,
+ <0x0 0x00024 0x0 0x8>;
+ reg-names = "mux", "pull", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ uart_ao_a_pins: uart_ao_a {
+ mux {
+ groups = "uart_tx_ao_a", "uart_rx_ao_a";
+ function = "uart_ao";
+ };
+ };
+ };
+
uart_AO: serial at 4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
@@ -167,6 +214,115 @@
};
};
+ periphs: periphs at c8834000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc8834000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
+
+ rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+
+ pinctrl_periphs: pinctrl at 4b0 {
+ compatible = "amlogic,meson-gxbb-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank at 4b0 {
+ reg = <0x0 0x004b0 0x0 0x28>,
+ <0x0 0x004e8 0x0 0x14>,
+ <0x0 0x00120 0x0 0x14>,
+ <0x0 0x00430 0x0 0x40>;
+ reg-names = "mux", "pull", "pull-enable", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d07",
+ "emmc_cmd",
+ "emmc_clk";
+ function = "emmc";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0",
+ "sdcard_d1",
+ "sdcard_d2",
+ "sdcard_d3",
+ "sdcard_cmd",
+ "sdcard_clk";
+ function = "sdcard";
+ };
+ };
+
+ uart_a_pins: uart_a {
+ mux {
+ groups = "uart_tx_a",
+ "uart_rx_a";
+ function = "uart_a";
+ };
+ };
+
+ uart_b_pins: uart_b {
+ mux {
+ groups = "uart_tx_b",
+ "uart_rx_b";
+ function = "uart_b";
+ };
+ };
+
+ uart_c_pins: uart_c {
+ mux {
+ groups = "uart_tx_c",
+ "uart_rx_c";
+ function = "uart_c";
+ };
+ };
+
+ eth_pins: eth_c {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_clk_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_rxd2",
+ "eth_rxd3",
+ "eth_rgmii_tx_clk",
+ "eth_tx_en",
+ "eth_txd0",
+ "eth_txd1",
+ "eth_txd2",
+ "eth_txd3";
+ function = "eth";
+ };
+ };
+ };
+ };
+
+ hiubus: hiubus at c883c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc883c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+
+ clkc: clock-controller at 0 {
+ compatible = "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x3db>;
+ };
+ };
+
apb: apb at d0000000 {
compatible = "simple-bus";
reg = <0x0 0xd0000000 0x0 0x200000>;
@@ -174,5 +330,17 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
};
+
+ ethmac: ethernet at c9410000 {
+ compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+ reg = <0x0 0xc9410000 0x0 0x10000
+ 0x0 0xc8834540 0x0 0x4>;
+ interrupts = <0 8 1>;
+ interrupt-names = "macirq";
+ clocks = <&xtal>;
+ clock-names = "stmmaceth";
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
};
};
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
new file mode 100644
index 0000000..58654fd
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-gxbb-gpio.h
@@ -0,0 +1,154 @@
+/*
+ * GPIO definitions for Amlogic Meson GXBB SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
+#define _DT_BINDINGS_MESON_GXBB_GPIO_H
+
+#define GPIOAO_0 0
+#define GPIOAO_1 1
+#define GPIOAO_2 2
+#define GPIOAO_3 3
+#define GPIOAO_4 4
+#define GPIOAO_5 5
+#define GPIOAO_6 6
+#define GPIOAO_7 7
+#define GPIOAO_8 8
+#define GPIOAO_9 9
+#define GPIOAO_10 10
+#define GPIOAO_11 11
+#define GPIOAO_12 12
+#define GPIOAO_13 13
+
+#define GPIOZ_0 0
+#define GPIOZ_1 1
+#define GPIOZ_2 2
+#define GPIOZ_3 3
+#define GPIOZ_4 4
+#define GPIOZ_5 5
+#define GPIOZ_6 6
+#define GPIOZ_7 7
+#define GPIOZ_8 8
+#define GPIOZ_9 9
+#define GPIOZ_10 10
+#define GPIOZ_11 11
+#define GPIOZ_12 12
+#define GPIOZ_13 13
+#define GPIOZ_14 14
+#define GPIOZ_15 15
+#define GPIOH_0 16
+#define GPIOH_1 17
+#define GPIOH_2 18
+#define GPIOH_3 19
+#define BOOT_0 20
+#define BOOT_1 21
+#define BOOT_2 22
+#define BOOT_3 23
+#define BOOT_4 24
+#define BOOT_5 25
+#define BOOT_6 26
+#define BOOT_7 27
+#define BOOT_8 28
+#define BOOT_9 29
+#define BOOT_10 30
+#define BOOT_11 31
+#define BOOT_12 32
+#define BOOT_13 33
+#define BOOT_14 34
+#define BOOT_15 35
+#define BOOT_16 36
+#define BOOT_17 37
+#define CARD_0 38
+#define CARD_1 39
+#define CARD_2 40
+#define CARD_3 41
+#define CARD_4 42
+#define CARD_5 43
+#define CARD_6 44
+#define GPIODV_0 45
+#define GPIODV_1 46
+#define GPIODV_2 47
+#define GPIODV_3 48
+#define GPIODV_4 49
+#define GPIODV_5 50
+#define GPIODV_6 51
+#define GPIODV_7 52
+#define GPIODV_8 53
+#define GPIODV_9 54
+#define GPIODV_10 55
+#define GPIODV_11 56
+#define GPIODV_12 57
+#define GPIODV_13 58
+#define GPIODV_14 59
+#define GPIODV_15 60
+#define GPIODV_16 61
+#define GPIODV_17 62
+#define GPIODV_18 63
+#define GPIODV_19 64
+#define GPIODV_20 65
+#define GPIODV_21 66
+#define GPIODV_22 67
+#define GPIODV_23 68
+#define GPIODV_24 69
+#define GPIODV_25 70
+#define GPIODV_26 71
+#define GPIODV_27 72
+#define GPIODV_28 73
+#define GPIODV_29 74
+#define GPIOY_0 75
+#define GPIOY_1 76
+#define GPIOY_2 77
+#define GPIOY_3 78
+#define GPIOY_4 79
+#define GPIOY_5 80
+#define GPIOY_6 81
+#define GPIOY_7 82
+#define GPIOY_8 83
+#define GPIOY_9 84
+#define GPIOY_10 85
+#define GPIOY_11 86
+#define GPIOY_12 87
+#define GPIOY_13 88
+#define GPIOY_14 89
+#define GPIOY_15 90
+#define GPIOY_16 91
+#define GPIOX_0 92
+#define GPIOX_1 93
+#define GPIOX_2 94
+#define GPIOX_3 95
+#define GPIOX_4 96
+#define GPIOX_5 97
+#define GPIOX_6 98
+#define GPIOX_7 99
+#define GPIOX_8 100
+#define GPIOX_9 101
+#define GPIOX_10 102
+#define GPIOX_11 103
+#define GPIOX_12 104
+#define GPIOX_13 105
+#define GPIOX_14 106
+#define GPIOX_15 107
+#define GPIOX_16 108
+#define GPIOX_17 109
+#define GPIOX_18 110
+#define GPIOX_19 111
+#define GPIOX_20 112
+#define GPIOX_21 113
+#define GPIOX_22 114
+#define GPIOCLK_0 115
+#define GPIOCLK_1 116
+#define GPIOCLK_2 117
+#define GPIOCLK_3 118
+#define GPIO_TEST_N 119
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
new file mode 100644
index 0000000..524d607
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
@@ -0,0 +1,210 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
+
+/* RESET0 */
+#define RESET_HIU 0
+/* 1 */
+#define RESET_DOS_RESET 2
+#define RESET_DDR_TOP 3
+#define RESET_DCU_RESET 4
+#define RESET_VIU 5
+#define RESET_AIU 6
+#define RESET_VID_PLL_DIV 7
+/* 8 */
+#define RESET_PMUX 9
+#define RESET_VENC 10
+#define RESET_ASSIST 11
+#define RESET_AFIFO2 12
+#define RESET_VCBUS 13
+/* 14 */
+/* 15 */
+#define RESET_GIC 16
+#define RESET_CAPB3_DECODE 17
+#define RESET_NAND_CAPB3 18
+#define RESET_HDMITX_CAPB3 19
+#define RESET_MALI_CAPB3 20
+#define RESET_DOS_CAPB3 21
+#define RESET_SYS_CPU_CAPB3 22
+#define RESET_CBUS_CAPB3 23
+#define RESET_AHB_CNTL 24
+#define RESET_AHB_DATA 25
+#define RESET_VCBUS_CLK81 26
+#define RESET_MMC 27
+#define RESET_MIPI_0 28
+#define RESET_MIPI_1 29
+#define RESET_MIPI_2 30
+#define RESET_MIPI_3 31
+/* RESET1 */
+#define RESET_CPPM 32
+#define RESET_DEMUX 33
+#define RESET_USB_OTG 34
+#define RESET_DDR 35
+#define RESET_AO_RESET 36
+#define RESET_BT656 37
+#define RESET_AHB_SRAM 38
+/* 39 */
+#define RESET_PARSER 40
+#define RESET_BLKMV 41
+#define RESET_ISA 42
+#define RESET_ETHERNET 43
+#define RESET_SD_EMMC_A 44
+#define RESET_SD_EMMC_B 45
+#define RESET_SD_EMMC_C 46
+#define RESET_ROM_BOOT 47
+#define RESET_SYS_CPU_0 48
+#define RESET_SYS_CPU_1 49
+#define RESET_SYS_CPU_2 50
+#define RESET_SYS_CPU_3 51
+#define RESET_SYS_CPU_CORE_0 52
+#define RESET_SYS_CPU_CORE_1 53
+#define RESET_SYS_CPU_CORE_2 54
+#define RESET_SYS_CPU_CORE_3 55
+#define RESET_SYS_PLL_DIV 56
+#define RESET_SYS_CPU_AXI 57
+#define RESET_SYS_CPU_L2 58
+#define RESET_SYS_CPU_P 59
+#define RESET_SYS_CPU_MBIST 60
+/* 61 */
+/* 62 */
+/* 63 */
+/* RESET2 */
+#define RESET_VD_RMEM 64
+#define RESET_AUDIN 65
+#define RESET_HDMI_TX 66
+/* 67 */
+/* 68 */
+/* 69 */
+#define RESET_GE2D 70
+#define RESET_PARSER_REG 71
+#define RESET_PARSER_FETCH 72
+#define RESET_PARSER_CTL 73
+#define RESET_PARSER_TOP 74
+/* 75 */
+/* 76 */
+#define RESET_AO_CPU_RESET 77
+#define RESET_MALI 78
+#define RESET_HDMI_SYSTEM_RESET 79
+/* 80-95 */
+/* RESET3 */
+#define RESET_RING_OSCILLATOR 96
+#define RESET_SYS_CPU 97
+#define RESET_EFUSE 98
+#define RESET_SYS_CPU_BVCI 99
+#define RESET_AIFIFO 100
+#define RESET_TVFE 101
+#define RESET_AHB_BRIDGE_CNTL 102
+/* 103 */
+#define RESET_AUDIO_DAC 104
+#define RESET_DEMUX_TOP 105
+#define RESET_DEMUX_DES 106
+#define RESET_DEMUX_S2P_0 107
+#define RESET_DEMUX_S2P_1 108
+#define RESET_DEMUX_RESET_0 109
+#define RESET_DEMUX_RESET_1 110
+#define RESET_DEMUX_RESET_2 111
+/* 112-127 */
+/* RESET4 */
+/* 128 */
+/* 129 */
+/* 130 */
+/* 131 */
+#define RESET_DVIN_RESET 132
+#define RESET_RDMA 133
+#define RESET_VENCI 134
+#define RESET_VENCP 135
+/* 136 */
+#define RESET_VDAC 137
+#define RESET_RTC 138
+/* 139 */
+#define RESET_VDI6 140
+#define RESET_VENCL 141
+#define RESET_I2C_MASTER_2 142
+#define RESET_I2C_MASTER_1 143
+/* 144-159 */
+/* RESET5 */
+/* 160-191 */
+/* RESET6 */
+#define RESET_PERIPHS_GENERAL 192
+#define RESET_PERIPHS_SPICC 193
+#define RESET_PERIPHS_SMART_CARD 194
+#define RESET_PERIPHS_SAR_ADC 195
+#define RESET_PERIPHS_I2C_MASTER_0 196
+#define RESET_SANA 197
+/* 198 */
+#define RESET_PERIPHS_STREAM_INTERFACE 199
+#define RESET_PERIPHS_SDIO 200
+#define RESET_PERIPHS_UART_0 201
+#define RESET_PERIPHS_UART_1_2 202
+#define RESET_PERIPHS_ASYNC_0 203
+#define RESET_PERIPHS_ASYNC_1 204
+#define RESET_PERIPHS_SPI_0 205
+#define RESET_PERIPHS_SDHC 206
+#define RESET_UART_SLIP 207
+/* 208-223 */
+/* RESET7 */
+#define RESET_USB_DDR_0 224
+#define RESET_USB_DDR_1 225
+#define RESET_USB_DDR_2 226
+#define RESET_USB_DDR_3 227
+/* 228 */
+#define RESET_DEVICE_MMC_ARB 229
+/* 230 */
+#define RESET_VID_LOCK 231
+#define RESET_A9_DMC_PIPEL 232
+/* 233-255 */
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 3/4] pinctrl: add driver for meson-gxbb pin controller
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-16 9:49 ` Beniamino Galvani
-1 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: u-boot
Add a pin controller driver for Meson GXBB adapted from Linux kernel.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/meson/Kconfig | 11 +
drivers/pinctrl/meson/Makefile | 6 +
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 432 +++++++++++++++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 179 ++++++++++++
drivers/pinctrl/meson/pinctrl-meson.h | 74 +++++
7 files changed, 704 insertions(+)
create mode 100644 drivers/pinctrl/meson/Kconfig
create mode 100644 drivers/pinctrl/meson/Makefile
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxbb.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2972dba..c0c7153 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -161,6 +161,7 @@ config PIC32_PINCTRL
endif
+source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 7f94681..62340f5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
+obj-$(CONFIG_PINCTRL_MESON) += meson/
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
new file mode 100644
index 0000000..c3e6901
--- /dev/null
+++ b/drivers/pinctrl/meson/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MESON
+
+config PINCTRL_MESON
+ depends on PINCTRL_GENERIC
+ bool
+
+config PINCTRL_MESON_GXBB
+ bool "Amlogic Meson GXBB SoC pinctrl driver"
+ select PINCTRL_MESON
+
+endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 0000000..6dde4bc
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pinctrl-meson.o
+obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
new file mode 100644
index 0000000..a0a7de5
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * Based on code from Linux kernel:
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-gxbb-gpio.h>
+
+#include "pinctrl-meson.h"
+
+#define EE_OFF 14
+
+static const unsigned int emmc_nand_d07_pins[] = {
+ PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
+ PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
+ PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
+};
+static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
+
+static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
+static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
+static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
+static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
+static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
+static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
+
+static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) };
+
+static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) };
+static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) };
+static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
+static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
+
+static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_13, EE_OFF) };
+static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_14, EE_OFF) };
+static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_12, EE_OFF) };
+
+static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
+static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) };
+static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) };
+
+static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) };
+static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
+static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_1, 0),
+ PIN(GPIOAO_5, 0) };
+static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
+
+static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
+static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
+
+static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
+ GPIO_GROUP(GPIOZ_0, EE_OFF),
+ GPIO_GROUP(GPIOZ_1, EE_OFF),
+ GPIO_GROUP(GPIOZ_2, EE_OFF),
+ GPIO_GROUP(GPIOZ_3, EE_OFF),
+ GPIO_GROUP(GPIOZ_4, EE_OFF),
+ GPIO_GROUP(GPIOZ_5, EE_OFF),
+ GPIO_GROUP(GPIOZ_6, EE_OFF),
+ GPIO_GROUP(GPIOZ_7, EE_OFF),
+ GPIO_GROUP(GPIOZ_8, EE_OFF),
+ GPIO_GROUP(GPIOZ_9, EE_OFF),
+ GPIO_GROUP(GPIOZ_10, EE_OFF),
+ GPIO_GROUP(GPIOZ_11, EE_OFF),
+ GPIO_GROUP(GPIOZ_12, EE_OFF),
+ GPIO_GROUP(GPIOZ_13, EE_OFF),
+ GPIO_GROUP(GPIOZ_14, EE_OFF),
+ GPIO_GROUP(GPIOZ_15, EE_OFF),
+
+ GPIO_GROUP(GPIOH_0, EE_OFF),
+ GPIO_GROUP(GPIOH_1, EE_OFF),
+ GPIO_GROUP(GPIOH_2, EE_OFF),
+ GPIO_GROUP(GPIOH_3, EE_OFF),
+
+ GPIO_GROUP(BOOT_0, EE_OFF),
+ GPIO_GROUP(BOOT_1, EE_OFF),
+ GPIO_GROUP(BOOT_2, EE_OFF),
+ GPIO_GROUP(BOOT_3, EE_OFF),
+ GPIO_GROUP(BOOT_4, EE_OFF),
+ GPIO_GROUP(BOOT_5, EE_OFF),
+ GPIO_GROUP(BOOT_6, EE_OFF),
+ GPIO_GROUP(BOOT_7, EE_OFF),
+ GPIO_GROUP(BOOT_8, EE_OFF),
+ GPIO_GROUP(BOOT_9, EE_OFF),
+ GPIO_GROUP(BOOT_10, EE_OFF),
+ GPIO_GROUP(BOOT_11, EE_OFF),
+ GPIO_GROUP(BOOT_12, EE_OFF),
+ GPIO_GROUP(BOOT_13, EE_OFF),
+ GPIO_GROUP(BOOT_14, EE_OFF),
+ GPIO_GROUP(BOOT_15, EE_OFF),
+ GPIO_GROUP(BOOT_16, EE_OFF),
+ GPIO_GROUP(BOOT_17, EE_OFF),
+
+ GPIO_GROUP(CARD_0, EE_OFF),
+ GPIO_GROUP(CARD_1, EE_OFF),
+ GPIO_GROUP(CARD_2, EE_OFF),
+ GPIO_GROUP(CARD_3, EE_OFF),
+ GPIO_GROUP(CARD_4, EE_OFF),
+ GPIO_GROUP(CARD_5, EE_OFF),
+ GPIO_GROUP(CARD_6, EE_OFF),
+
+ GPIO_GROUP(GPIODV_0, EE_OFF),
+ GPIO_GROUP(GPIODV_1, EE_OFF),
+ GPIO_GROUP(GPIODV_2, EE_OFF),
+ GPIO_GROUP(GPIODV_3, EE_OFF),
+ GPIO_GROUP(GPIODV_4, EE_OFF),
+ GPIO_GROUP(GPIODV_5, EE_OFF),
+ GPIO_GROUP(GPIODV_6, EE_OFF),
+ GPIO_GROUP(GPIODV_7, EE_OFF),
+ GPIO_GROUP(GPIODV_8, EE_OFF),
+ GPIO_GROUP(GPIODV_9, EE_OFF),
+ GPIO_GROUP(GPIODV_10, EE_OFF),
+ GPIO_GROUP(GPIODV_11, EE_OFF),
+ GPIO_GROUP(GPIODV_12, EE_OFF),
+ GPIO_GROUP(GPIODV_13, EE_OFF),
+ GPIO_GROUP(GPIODV_14, EE_OFF),
+ GPIO_GROUP(GPIODV_15, EE_OFF),
+ GPIO_GROUP(GPIODV_16, EE_OFF),
+ GPIO_GROUP(GPIODV_17, EE_OFF),
+ GPIO_GROUP(GPIODV_19, EE_OFF),
+ GPIO_GROUP(GPIODV_20, EE_OFF),
+ GPIO_GROUP(GPIODV_21, EE_OFF),
+ GPIO_GROUP(GPIODV_22, EE_OFF),
+ GPIO_GROUP(GPIODV_23, EE_OFF),
+ GPIO_GROUP(GPIODV_24, EE_OFF),
+ GPIO_GROUP(GPIODV_25, EE_OFF),
+ GPIO_GROUP(GPIODV_26, EE_OFF),
+ GPIO_GROUP(GPIODV_27, EE_OFF),
+ GPIO_GROUP(GPIODV_28, EE_OFF),
+ GPIO_GROUP(GPIODV_29, EE_OFF),
+
+ GPIO_GROUP(GPIOY_0, EE_OFF),
+ GPIO_GROUP(GPIOY_1, EE_OFF),
+ GPIO_GROUP(GPIOY_2, EE_OFF),
+ GPIO_GROUP(GPIOY_3, EE_OFF),
+ GPIO_GROUP(GPIOY_4, EE_OFF),
+ GPIO_GROUP(GPIOY_5, EE_OFF),
+ GPIO_GROUP(GPIOY_6, EE_OFF),
+ GPIO_GROUP(GPIOY_7, EE_OFF),
+ GPIO_GROUP(GPIOY_8, EE_OFF),
+ GPIO_GROUP(GPIOY_9, EE_OFF),
+ GPIO_GROUP(GPIOY_10, EE_OFF),
+ GPIO_GROUP(GPIOY_11, EE_OFF),
+ GPIO_GROUP(GPIOY_12, EE_OFF),
+ GPIO_GROUP(GPIOY_13, EE_OFF),
+ GPIO_GROUP(GPIOY_14, EE_OFF),
+ GPIO_GROUP(GPIOY_15, EE_OFF),
+ GPIO_GROUP(GPIOY_16, EE_OFF),
+
+ GPIO_GROUP(GPIOX_0, EE_OFF),
+ GPIO_GROUP(GPIOX_1, EE_OFF),
+ GPIO_GROUP(GPIOX_2, EE_OFF),
+ GPIO_GROUP(GPIOX_3, EE_OFF),
+ GPIO_GROUP(GPIOX_4, EE_OFF),
+ GPIO_GROUP(GPIOX_5, EE_OFF),
+ GPIO_GROUP(GPIOX_6, EE_OFF),
+ GPIO_GROUP(GPIOX_7, EE_OFF),
+ GPIO_GROUP(GPIOX_8, EE_OFF),
+ GPIO_GROUP(GPIOX_9, EE_OFF),
+ GPIO_GROUP(GPIOX_10, EE_OFF),
+ GPIO_GROUP(GPIOX_11, EE_OFF),
+ GPIO_GROUP(GPIOX_12, EE_OFF),
+ GPIO_GROUP(GPIOX_13, EE_OFF),
+ GPIO_GROUP(GPIOX_14, EE_OFF),
+ GPIO_GROUP(GPIOX_15, EE_OFF),
+ GPIO_GROUP(GPIOX_16, EE_OFF),
+ GPIO_GROUP(GPIOX_17, EE_OFF),
+ GPIO_GROUP(GPIOX_18, EE_OFF),
+ GPIO_GROUP(GPIOX_19, EE_OFF),
+ GPIO_GROUP(GPIOX_20, EE_OFF),
+ GPIO_GROUP(GPIOX_21, EE_OFF),
+ GPIO_GROUP(GPIOX_22, EE_OFF),
+
+ GPIO_GROUP(GPIOCLK_0, EE_OFF),
+ GPIO_GROUP(GPIOCLK_1, EE_OFF),
+ GPIO_GROUP(GPIOCLK_2, EE_OFF),
+ GPIO_GROUP(GPIOCLK_3, EE_OFF),
+
+ GPIO_GROUP(GPIO_TEST_N, EE_OFF),
+
+ /* Bank X */
+ GROUP(uart_tx_a, 4, 13),
+ GROUP(uart_rx_a, 4, 12),
+ GROUP(uart_cts_a, 4, 11),
+ GROUP(uart_rts_a, 4, 10),
+
+ /* Bank Y */
+ GROUP(uart_cts_c, 1, 19),
+ GROUP(uart_rts_c, 1, 18),
+ GROUP(uart_tx_c, 1, 17),
+ GROUP(uart_rx_c, 1, 16),
+
+ /* Bank Z */
+ GROUP(eth_mdio, 6, 1),
+ GROUP(eth_mdc, 6, 0),
+ GROUP(eth_clk_rx_clk, 6, 13),
+ GROUP(eth_rx_dv, 6, 12),
+ GROUP(eth_rxd0, 6, 11),
+ GROUP(eth_rxd1, 6, 10),
+ GROUP(eth_rxd2, 6, 9),
+ GROUP(eth_rxd3, 6, 8),
+ GROUP(eth_rgmii_tx_clk, 6, 7),
+ GROUP(eth_tx_en, 6, 6),
+ GROUP(eth_txd0, 6, 5),
+ GROUP(eth_txd1, 6, 4),
+ GROUP(eth_txd2, 6, 3),
+ GROUP(eth_txd3, 6, 2),
+
+ /* Bank DV */
+ GROUP(uart_tx_b, 2, 29),
+ GROUP(uart_rx_b, 2, 28),
+ GROUP(uart_cts_b, 2, 27),
+ GROUP(uart_rts_b, 2, 26),
+
+ /* Bank BOOT */
+ GROUP(emmc_nand_d07, 4, 30),
+ GROUP(emmc_clk, 4, 18),
+ GROUP(emmc_cmd, 4, 19),
+ GROUP(emmc_ds, 4, 31),
+
+ /* Bank CARD */
+ GROUP(sdcard_d1, 2, 14),
+ GROUP(sdcard_d0, 2, 15),
+ GROUP(sdcard_d3, 2, 12),
+ GROUP(sdcard_d2, 2, 13),
+ GROUP(sdcard_cmd, 2, 10),
+ GROUP(sdcard_clk, 2, 11),
+};
+
+static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
+ GPIO_GROUP(GPIOAO_0, 0),
+ GPIO_GROUP(GPIOAO_1, 0),
+ GPIO_GROUP(GPIOAO_2, 0),
+ GPIO_GROUP(GPIOAO_3, 0),
+ GPIO_GROUP(GPIOAO_4, 0),
+ GPIO_GROUP(GPIOAO_5, 0),
+ GPIO_GROUP(GPIOAO_6, 0),
+ GPIO_GROUP(GPIOAO_7, 0),
+ GPIO_GROUP(GPIOAO_8, 0),
+ GPIO_GROUP(GPIOAO_9, 0),
+ GPIO_GROUP(GPIOAO_10, 0),
+ GPIO_GROUP(GPIOAO_11, 0),
+ GPIO_GROUP(GPIOAO_12, 0),
+ GPIO_GROUP(GPIOAO_13, 0),
+
+ /* bank AO */
+ GROUP(uart_tx_ao_b, 0, 26),
+ GROUP(uart_rx_ao_b, 0, 25),
+ GROUP(uart_tx_ao_a, 0, 12),
+ GROUP(uart_rx_ao_a, 0, 11),
+ GROUP(uart_cts_ao_a, 0, 10),
+ GROUP(uart_rts_ao_a, 0, 9),
+ GROUP(uart_cts_ao_b, 0, 8),
+ GROUP(uart_rts_ao_b, 0, 7),
+ GROUP(i2c_sck_ao, 0, 6),
+ GROUP(i2c_sda_ao, 0, 5),
+ GROUP(i2c_slave_sck_ao, 0, 2),
+ GROUP(i2c_slave_sda_ao, 0, 1),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
+ "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
+ "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
+ "GPIOZ_15",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3",
+
+ "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
+ "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
+ "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
+ "BOOT_15", "BOOT_16", "BOOT_17",
+
+ "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
+ "CARD_5", "CARD_6",
+
+ "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
+ "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
+ "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
+ "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
+ "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
+ "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
+
+ "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
+ "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
+ "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
+ "GPIOY_15", "GPIOY_16",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+ "GPIOX_20", "GPIOX_21", "GPIOX_22",
+
+ "GPIO_TEST_N",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
+ "sdcard_cmd", "sdcard_clk",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
+ "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
+ "eth_rgmii_tx_clk", "eth_tx_en",
+ "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
+};
+
+static const char * const gpio_aobus_groups[] = {
+ "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
+ "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
+ "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
+};
+
+static const char * const uart_ao_groups[] = {
+ "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
+};
+
+static const char * const i2c_ao_groups[] = {
+ "i2c_sdk_ao", "i2c_sda_ao",
+};
+
+static const char * const i2c_slave_ao_groups[] = {
+ "i2c_slave_sdk_ao", "i2c_slave_sda_ao",
+};
+
+static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(emmc),
+ FUNCTION(sdcard),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(eth),
+};
+
+static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
+ FUNCTION(gpio_aobus),
+ FUNCTION(uart_ao),
+ FUNCTION(uart_ao_b),
+ FUNCTION(i2c_ao),
+ FUNCTION(i2c_slave_ao),
+};
+
+struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .pin_base = 14,
+ .groups = meson_gxbb_periphs_groups,
+ .funcs = meson_gxbb_periphs_functions,
+ .num_pins = 120,
+ .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
+};
+
+struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
+ .name = "aobus-banks",
+ .pin_base = 0,
+ .groups = meson_gxbb_aobus_groups,
+ .funcs = meson_gxbb_aobus_functions,
+ .num_pins = 14,
+ .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
+ .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
+};
+
+static const struct udevice_id meson_gxbb_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-periphs-pinctrl",
+ .data = (ulong)&meson_gxbb_periphs_pinctrl_data,
+ },
+ {
+ .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
+ .data = (ulong)&meson_gxbb_aobus_pinctrl_data,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(meson_gxbb_pinctrl) = {
+ .name = "meson-gxbb-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_gxbb_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 0000000..d21a3dd
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <fdt_support.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "pinctrl-meson.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *meson_pinctrl_dummy_name = "_dummy";
+
+static int meson_pinctrl_get_groups_count(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ return priv->data->num_groups;
+}
+
+static const char *meson_pinctrl_get_group_name(struct udevice *dev,
+ unsigned selector)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ if (!priv->data->groups[selector].name)
+ return meson_pinctrl_dummy_name;
+
+ return priv->data->groups[selector].name;
+}
+
+static int meson_pinmux_get_functions_count(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ return priv->data->num_funcs;
+}
+
+static const char *meson_pinmux_get_function_name(struct udevice *dev,
+ unsigned selector)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ return priv->data->funcs[selector].name;
+}
+
+static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv,
+ unsigned int pin, int sel_group)
+{
+ struct meson_pmx_group *group;
+ void __iomem *addr;
+ int i, j;
+
+ for (i = 0; i < priv->data->num_groups; i++) {
+ group = &priv->data->groups[i];
+ if (group->is_gpio || i == sel_group)
+ continue;
+
+ for (j = 0; j < group->num_pins; j++) {
+ if (group->pins[j] == pin) {
+ /* We have found a group using the pin */
+ debug("pinmux: disabling %s\n", group->name);
+ addr = priv->reg_mux + group->reg * 4;
+ writel(readl(addr) & ~BIT(group->bit), addr);
+ }
+ }
+ }
+}
+
+static int meson_pinmux_group_set(struct udevice *dev,
+ unsigned group_selector,
+ unsigned func_selector)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+ const struct meson_pmx_group *group;
+ const struct meson_pmx_func *func;
+ void __iomem *addr;
+ int i;
+
+ group = &priv->data->groups[group_selector];
+ func = &priv->data->funcs[func_selector];
+
+ debug("pinmux: set group %s func %s\n", group->name, func->name);
+
+ /*
+ * Disable groups using the same pins.
+ * The selected group is not disabled to avoid glitches.
+ */
+ for (i = 0; i < group->num_pins; i++) {
+ meson_pinmux_disable_other_groups(priv,
+ group->pins[i],
+ group_selector);
+ }
+
+ /* Function 0 (GPIO) doesn't need any additional setting */
+ if (func_selector) {
+ addr = priv->reg_mux + group->reg * 4;
+ writel(readl(addr) | BIT(group->bit), addr);
+ }
+
+ return 0;
+}
+
+const struct pinctrl_ops meson_pinctrl_ops = {
+ .get_groups_count = meson_pinctrl_get_groups_count,
+ .get_group_name = meson_pinctrl_get_group_name,
+ .get_functions_count = meson_pinmux_get_functions_count,
+ .get_function_name = meson_pinmux_get_function_name,
+ .pinmux_group_set = meson_pinmux_group_set,
+ .set_state = pinctrl_generic_set_state,
+};
+
+static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
+{
+ int index, len = 0;
+ const fdt32_t *reg;
+
+ index = fdt_find_string(gd->fdt_blob, offset, "reg-names", name);
+ if (index < 0)
+ return FDT_ADDR_T_NONE;
+
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+ if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
+ return FDT_ADDR_T_NONE;
+
+ reg += index * (na + ns);
+
+ return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
+}
+
+int meson_pinctrl_probe(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ int node, gpio = -1, len;
+ int na, ns;
+
+ na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (na < 1) {
+ debug("bad #address-cells\n");
+ return -EINVAL;
+ }
+
+ ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (ns < 1) {
+ debug("bad #size-cells\n");
+ return -EINVAL;
+ }
+
+ fdt_for_each_subnode(gd->fdt_blob, node, dev->of_offset) {
+ if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
+ gpio = node;
+ break;
+ }
+ }
+
+ if (!gpio) {
+ debug("gpio node not found\n");
+ return -EINVAL;
+ }
+
+ addr = parse_address(gpio, "mux", na, ns);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("mux not found\n");
+ return -EINVAL;
+ }
+
+ priv->reg_mux = (void __iomem *)addr;
+ priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
+
+ return 0;
+}
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
new file mode 100644
index 0000000..4127a60
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PINCTRL_MESON_H__
+#define __PINCTRL_MESON_H__
+
+#include <linux/types.h>
+
+struct meson_pmx_group {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int num_pins;
+ bool is_gpio;
+ unsigned int reg;
+ unsigned int bit;
+};
+
+struct meson_pmx_func {
+ const char *name;
+ const char * const *groups;
+ unsigned int num_groups;
+};
+
+struct meson_pinctrl_data {
+ const char *name;
+ struct meson_pmx_group *groups;
+ struct meson_pmx_func *funcs;
+ unsigned int pin_base;
+ unsigned int num_pins;
+ unsigned int num_groups;
+ unsigned int num_funcs;
+};
+
+struct meson_pinctrl {
+ struct meson_pinctrl_data *data;
+ void __iomem *reg_mux;
+};
+
+#define PIN(x, b) (b + x)
+
+#define GROUP(grp, r, b) \
+ { \
+ .name = #grp, \
+ .pins = grp ## _pins, \
+ .num_pins = ARRAY_SIZE(grp ## _pins), \
+ .reg = r, \
+ .bit = b, \
+ }
+
+#define GPIO_GROUP(gpio, b) \
+ { \
+ .name = #gpio, \
+ .pins = (const unsigned int[]){ PIN(gpio, b) }, \
+ .num_pins = 1, \
+ .is_gpio = true, \
+ }
+
+#define FUNCTION(fn) \
+ { \
+ .name = #fn, \
+ .groups = fn ## _groups, \
+ .num_groups = ARRAY_SIZE(fn ## _groups), \
+ }
+
+#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
+
+extern const struct pinctrl_ops meson_pinctrl_ops;
+
+int meson_pinctrl_probe(struct udevice *dev);
+
+#endif /* __PINCTRL_MESON_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/4] pinctrl: add driver for meson-gxbb pin controller
@ 2016-08-16 9:49 ` Beniamino Galvani
0 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: linus-amlogic
Add a pin controller driver for Meson GXBB adapted from Linux kernel.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/meson/Kconfig | 11 +
drivers/pinctrl/meson/Makefile | 6 +
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 432 +++++++++++++++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 179 ++++++++++++
drivers/pinctrl/meson/pinctrl-meson.h | 74 +++++
7 files changed, 704 insertions(+)
create mode 100644 drivers/pinctrl/meson/Kconfig
create mode 100644 drivers/pinctrl/meson/Makefile
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxbb.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2972dba..c0c7153 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -161,6 +161,7 @@ config PIC32_PINCTRL
endif
+source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 7f94681..62340f5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
+obj-$(CONFIG_PINCTRL_MESON) += meson/
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
new file mode 100644
index 0000000..c3e6901
--- /dev/null
+++ b/drivers/pinctrl/meson/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MESON
+
+config PINCTRL_MESON
+ depends on PINCTRL_GENERIC
+ bool
+
+config PINCTRL_MESON_GXBB
+ bool "Amlogic Meson GXBB SoC pinctrl driver"
+ select PINCTRL_MESON
+
+endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 0000000..6dde4bc
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pinctrl-meson.o
+obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
new file mode 100644
index 0000000..a0a7de5
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * Based on code from Linux kernel:
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-gxbb-gpio.h>
+
+#include "pinctrl-meson.h"
+
+#define EE_OFF 14
+
+static const unsigned int emmc_nand_d07_pins[] = {
+ PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
+ PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
+ PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
+};
+static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
+
+static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
+static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
+static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
+static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
+static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
+static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
+
+static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) };
+
+static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) };
+static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) };
+static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
+static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
+
+static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_13, EE_OFF) };
+static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_14, EE_OFF) };
+static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_12, EE_OFF) };
+
+static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
+static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) };
+static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) };
+
+static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) };
+static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
+static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_1, 0),
+ PIN(GPIOAO_5, 0) };
+static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
+
+static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
+static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
+
+static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
+ GPIO_GROUP(GPIOZ_0, EE_OFF),
+ GPIO_GROUP(GPIOZ_1, EE_OFF),
+ GPIO_GROUP(GPIOZ_2, EE_OFF),
+ GPIO_GROUP(GPIOZ_3, EE_OFF),
+ GPIO_GROUP(GPIOZ_4, EE_OFF),
+ GPIO_GROUP(GPIOZ_5, EE_OFF),
+ GPIO_GROUP(GPIOZ_6, EE_OFF),
+ GPIO_GROUP(GPIOZ_7, EE_OFF),
+ GPIO_GROUP(GPIOZ_8, EE_OFF),
+ GPIO_GROUP(GPIOZ_9, EE_OFF),
+ GPIO_GROUP(GPIOZ_10, EE_OFF),
+ GPIO_GROUP(GPIOZ_11, EE_OFF),
+ GPIO_GROUP(GPIOZ_12, EE_OFF),
+ GPIO_GROUP(GPIOZ_13, EE_OFF),
+ GPIO_GROUP(GPIOZ_14, EE_OFF),
+ GPIO_GROUP(GPIOZ_15, EE_OFF),
+
+ GPIO_GROUP(GPIOH_0, EE_OFF),
+ GPIO_GROUP(GPIOH_1, EE_OFF),
+ GPIO_GROUP(GPIOH_2, EE_OFF),
+ GPIO_GROUP(GPIOH_3, EE_OFF),
+
+ GPIO_GROUP(BOOT_0, EE_OFF),
+ GPIO_GROUP(BOOT_1, EE_OFF),
+ GPIO_GROUP(BOOT_2, EE_OFF),
+ GPIO_GROUP(BOOT_3, EE_OFF),
+ GPIO_GROUP(BOOT_4, EE_OFF),
+ GPIO_GROUP(BOOT_5, EE_OFF),
+ GPIO_GROUP(BOOT_6, EE_OFF),
+ GPIO_GROUP(BOOT_7, EE_OFF),
+ GPIO_GROUP(BOOT_8, EE_OFF),
+ GPIO_GROUP(BOOT_9, EE_OFF),
+ GPIO_GROUP(BOOT_10, EE_OFF),
+ GPIO_GROUP(BOOT_11, EE_OFF),
+ GPIO_GROUP(BOOT_12, EE_OFF),
+ GPIO_GROUP(BOOT_13, EE_OFF),
+ GPIO_GROUP(BOOT_14, EE_OFF),
+ GPIO_GROUP(BOOT_15, EE_OFF),
+ GPIO_GROUP(BOOT_16, EE_OFF),
+ GPIO_GROUP(BOOT_17, EE_OFF),
+
+ GPIO_GROUP(CARD_0, EE_OFF),
+ GPIO_GROUP(CARD_1, EE_OFF),
+ GPIO_GROUP(CARD_2, EE_OFF),
+ GPIO_GROUP(CARD_3, EE_OFF),
+ GPIO_GROUP(CARD_4, EE_OFF),
+ GPIO_GROUP(CARD_5, EE_OFF),
+ GPIO_GROUP(CARD_6, EE_OFF),
+
+ GPIO_GROUP(GPIODV_0, EE_OFF),
+ GPIO_GROUP(GPIODV_1, EE_OFF),
+ GPIO_GROUP(GPIODV_2, EE_OFF),
+ GPIO_GROUP(GPIODV_3, EE_OFF),
+ GPIO_GROUP(GPIODV_4, EE_OFF),
+ GPIO_GROUP(GPIODV_5, EE_OFF),
+ GPIO_GROUP(GPIODV_6, EE_OFF),
+ GPIO_GROUP(GPIODV_7, EE_OFF),
+ GPIO_GROUP(GPIODV_8, EE_OFF),
+ GPIO_GROUP(GPIODV_9, EE_OFF),
+ GPIO_GROUP(GPIODV_10, EE_OFF),
+ GPIO_GROUP(GPIODV_11, EE_OFF),
+ GPIO_GROUP(GPIODV_12, EE_OFF),
+ GPIO_GROUP(GPIODV_13, EE_OFF),
+ GPIO_GROUP(GPIODV_14, EE_OFF),
+ GPIO_GROUP(GPIODV_15, EE_OFF),
+ GPIO_GROUP(GPIODV_16, EE_OFF),
+ GPIO_GROUP(GPIODV_17, EE_OFF),
+ GPIO_GROUP(GPIODV_19, EE_OFF),
+ GPIO_GROUP(GPIODV_20, EE_OFF),
+ GPIO_GROUP(GPIODV_21, EE_OFF),
+ GPIO_GROUP(GPIODV_22, EE_OFF),
+ GPIO_GROUP(GPIODV_23, EE_OFF),
+ GPIO_GROUP(GPIODV_24, EE_OFF),
+ GPIO_GROUP(GPIODV_25, EE_OFF),
+ GPIO_GROUP(GPIODV_26, EE_OFF),
+ GPIO_GROUP(GPIODV_27, EE_OFF),
+ GPIO_GROUP(GPIODV_28, EE_OFF),
+ GPIO_GROUP(GPIODV_29, EE_OFF),
+
+ GPIO_GROUP(GPIOY_0, EE_OFF),
+ GPIO_GROUP(GPIOY_1, EE_OFF),
+ GPIO_GROUP(GPIOY_2, EE_OFF),
+ GPIO_GROUP(GPIOY_3, EE_OFF),
+ GPIO_GROUP(GPIOY_4, EE_OFF),
+ GPIO_GROUP(GPIOY_5, EE_OFF),
+ GPIO_GROUP(GPIOY_6, EE_OFF),
+ GPIO_GROUP(GPIOY_7, EE_OFF),
+ GPIO_GROUP(GPIOY_8, EE_OFF),
+ GPIO_GROUP(GPIOY_9, EE_OFF),
+ GPIO_GROUP(GPIOY_10, EE_OFF),
+ GPIO_GROUP(GPIOY_11, EE_OFF),
+ GPIO_GROUP(GPIOY_12, EE_OFF),
+ GPIO_GROUP(GPIOY_13, EE_OFF),
+ GPIO_GROUP(GPIOY_14, EE_OFF),
+ GPIO_GROUP(GPIOY_15, EE_OFF),
+ GPIO_GROUP(GPIOY_16, EE_OFF),
+
+ GPIO_GROUP(GPIOX_0, EE_OFF),
+ GPIO_GROUP(GPIOX_1, EE_OFF),
+ GPIO_GROUP(GPIOX_2, EE_OFF),
+ GPIO_GROUP(GPIOX_3, EE_OFF),
+ GPIO_GROUP(GPIOX_4, EE_OFF),
+ GPIO_GROUP(GPIOX_5, EE_OFF),
+ GPIO_GROUP(GPIOX_6, EE_OFF),
+ GPIO_GROUP(GPIOX_7, EE_OFF),
+ GPIO_GROUP(GPIOX_8, EE_OFF),
+ GPIO_GROUP(GPIOX_9, EE_OFF),
+ GPIO_GROUP(GPIOX_10, EE_OFF),
+ GPIO_GROUP(GPIOX_11, EE_OFF),
+ GPIO_GROUP(GPIOX_12, EE_OFF),
+ GPIO_GROUP(GPIOX_13, EE_OFF),
+ GPIO_GROUP(GPIOX_14, EE_OFF),
+ GPIO_GROUP(GPIOX_15, EE_OFF),
+ GPIO_GROUP(GPIOX_16, EE_OFF),
+ GPIO_GROUP(GPIOX_17, EE_OFF),
+ GPIO_GROUP(GPIOX_18, EE_OFF),
+ GPIO_GROUP(GPIOX_19, EE_OFF),
+ GPIO_GROUP(GPIOX_20, EE_OFF),
+ GPIO_GROUP(GPIOX_21, EE_OFF),
+ GPIO_GROUP(GPIOX_22, EE_OFF),
+
+ GPIO_GROUP(GPIOCLK_0, EE_OFF),
+ GPIO_GROUP(GPIOCLK_1, EE_OFF),
+ GPIO_GROUP(GPIOCLK_2, EE_OFF),
+ GPIO_GROUP(GPIOCLK_3, EE_OFF),
+
+ GPIO_GROUP(GPIO_TEST_N, EE_OFF),
+
+ /* Bank X */
+ GROUP(uart_tx_a, 4, 13),
+ GROUP(uart_rx_a, 4, 12),
+ GROUP(uart_cts_a, 4, 11),
+ GROUP(uart_rts_a, 4, 10),
+
+ /* Bank Y */
+ GROUP(uart_cts_c, 1, 19),
+ GROUP(uart_rts_c, 1, 18),
+ GROUP(uart_tx_c, 1, 17),
+ GROUP(uart_rx_c, 1, 16),
+
+ /* Bank Z */
+ GROUP(eth_mdio, 6, 1),
+ GROUP(eth_mdc, 6, 0),
+ GROUP(eth_clk_rx_clk, 6, 13),
+ GROUP(eth_rx_dv, 6, 12),
+ GROUP(eth_rxd0, 6, 11),
+ GROUP(eth_rxd1, 6, 10),
+ GROUP(eth_rxd2, 6, 9),
+ GROUP(eth_rxd3, 6, 8),
+ GROUP(eth_rgmii_tx_clk, 6, 7),
+ GROUP(eth_tx_en, 6, 6),
+ GROUP(eth_txd0, 6, 5),
+ GROUP(eth_txd1, 6, 4),
+ GROUP(eth_txd2, 6, 3),
+ GROUP(eth_txd3, 6, 2),
+
+ /* Bank DV */
+ GROUP(uart_tx_b, 2, 29),
+ GROUP(uart_rx_b, 2, 28),
+ GROUP(uart_cts_b, 2, 27),
+ GROUP(uart_rts_b, 2, 26),
+
+ /* Bank BOOT */
+ GROUP(emmc_nand_d07, 4, 30),
+ GROUP(emmc_clk, 4, 18),
+ GROUP(emmc_cmd, 4, 19),
+ GROUP(emmc_ds, 4, 31),
+
+ /* Bank CARD */
+ GROUP(sdcard_d1, 2, 14),
+ GROUP(sdcard_d0, 2, 15),
+ GROUP(sdcard_d3, 2, 12),
+ GROUP(sdcard_d2, 2, 13),
+ GROUP(sdcard_cmd, 2, 10),
+ GROUP(sdcard_clk, 2, 11),
+};
+
+static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
+ GPIO_GROUP(GPIOAO_0, 0),
+ GPIO_GROUP(GPIOAO_1, 0),
+ GPIO_GROUP(GPIOAO_2, 0),
+ GPIO_GROUP(GPIOAO_3, 0),
+ GPIO_GROUP(GPIOAO_4, 0),
+ GPIO_GROUP(GPIOAO_5, 0),
+ GPIO_GROUP(GPIOAO_6, 0),
+ GPIO_GROUP(GPIOAO_7, 0),
+ GPIO_GROUP(GPIOAO_8, 0),
+ GPIO_GROUP(GPIOAO_9, 0),
+ GPIO_GROUP(GPIOAO_10, 0),
+ GPIO_GROUP(GPIOAO_11, 0),
+ GPIO_GROUP(GPIOAO_12, 0),
+ GPIO_GROUP(GPIOAO_13, 0),
+
+ /* bank AO */
+ GROUP(uart_tx_ao_b, 0, 26),
+ GROUP(uart_rx_ao_b, 0, 25),
+ GROUP(uart_tx_ao_a, 0, 12),
+ GROUP(uart_rx_ao_a, 0, 11),
+ GROUP(uart_cts_ao_a, 0, 10),
+ GROUP(uart_rts_ao_a, 0, 9),
+ GROUP(uart_cts_ao_b, 0, 8),
+ GROUP(uart_rts_ao_b, 0, 7),
+ GROUP(i2c_sck_ao, 0, 6),
+ GROUP(i2c_sda_ao, 0, 5),
+ GROUP(i2c_slave_sck_ao, 0, 2),
+ GROUP(i2c_slave_sda_ao, 0, 1),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
+ "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
+ "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
+ "GPIOZ_15",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3",
+
+ "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
+ "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
+ "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
+ "BOOT_15", "BOOT_16", "BOOT_17",
+
+ "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
+ "CARD_5", "CARD_6",
+
+ "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
+ "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
+ "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
+ "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
+ "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
+ "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
+
+ "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
+ "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
+ "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
+ "GPIOY_15", "GPIOY_16",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+ "GPIOX_20", "GPIOX_21", "GPIOX_22",
+
+ "GPIO_TEST_N",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
+ "sdcard_cmd", "sdcard_clk",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
+ "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
+ "eth_rgmii_tx_clk", "eth_tx_en",
+ "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
+};
+
+static const char * const gpio_aobus_groups[] = {
+ "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
+ "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
+ "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
+};
+
+static const char * const uart_ao_groups[] = {
+ "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
+};
+
+static const char * const i2c_ao_groups[] = {
+ "i2c_sdk_ao", "i2c_sda_ao",
+};
+
+static const char * const i2c_slave_ao_groups[] = {
+ "i2c_slave_sdk_ao", "i2c_slave_sda_ao",
+};
+
+static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(emmc),
+ FUNCTION(sdcard),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(eth),
+};
+
+static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
+ FUNCTION(gpio_aobus),
+ FUNCTION(uart_ao),
+ FUNCTION(uart_ao_b),
+ FUNCTION(i2c_ao),
+ FUNCTION(i2c_slave_ao),
+};
+
+struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .pin_base = 14,
+ .groups = meson_gxbb_periphs_groups,
+ .funcs = meson_gxbb_periphs_functions,
+ .num_pins = 120,
+ .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
+};
+
+struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
+ .name = "aobus-banks",
+ .pin_base = 0,
+ .groups = meson_gxbb_aobus_groups,
+ .funcs = meson_gxbb_aobus_functions,
+ .num_pins = 14,
+ .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
+ .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
+};
+
+static const struct udevice_id meson_gxbb_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-periphs-pinctrl",
+ .data = (ulong)&meson_gxbb_periphs_pinctrl_data,
+ },
+ {
+ .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
+ .data = (ulong)&meson_gxbb_aobus_pinctrl_data,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(meson_gxbb_pinctrl) = {
+ .name = "meson-gxbb-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_gxbb_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 0000000..d21a3dd
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <fdt_support.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "pinctrl-meson.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *meson_pinctrl_dummy_name = "_dummy";
+
+static int meson_pinctrl_get_groups_count(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ return priv->data->num_groups;
+}
+
+static const char *meson_pinctrl_get_group_name(struct udevice *dev,
+ unsigned selector)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ if (!priv->data->groups[selector].name)
+ return meson_pinctrl_dummy_name;
+
+ return priv->data->groups[selector].name;
+}
+
+static int meson_pinmux_get_functions_count(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ return priv->data->num_funcs;
+}
+
+static const char *meson_pinmux_get_function_name(struct udevice *dev,
+ unsigned selector)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ return priv->data->funcs[selector].name;
+}
+
+static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv,
+ unsigned int pin, int sel_group)
+{
+ struct meson_pmx_group *group;
+ void __iomem *addr;
+ int i, j;
+
+ for (i = 0; i < priv->data->num_groups; i++) {
+ group = &priv->data->groups[i];
+ if (group->is_gpio || i == sel_group)
+ continue;
+
+ for (j = 0; j < group->num_pins; j++) {
+ if (group->pins[j] == pin) {
+ /* We have found a group using the pin */
+ debug("pinmux: disabling %s\n", group->name);
+ addr = priv->reg_mux + group->reg * 4;
+ writel(readl(addr) & ~BIT(group->bit), addr);
+ }
+ }
+ }
+}
+
+static int meson_pinmux_group_set(struct udevice *dev,
+ unsigned group_selector,
+ unsigned func_selector)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+ const struct meson_pmx_group *group;
+ const struct meson_pmx_func *func;
+ void __iomem *addr;
+ int i;
+
+ group = &priv->data->groups[group_selector];
+ func = &priv->data->funcs[func_selector];
+
+ debug("pinmux: set group %s func %s\n", group->name, func->name);
+
+ /*
+ * Disable groups using the same pins.
+ * The selected group is not disabled to avoid glitches.
+ */
+ for (i = 0; i < group->num_pins; i++) {
+ meson_pinmux_disable_other_groups(priv,
+ group->pins[i],
+ group_selector);
+ }
+
+ /* Function 0 (GPIO) doesn't need any additional setting */
+ if (func_selector) {
+ addr = priv->reg_mux + group->reg * 4;
+ writel(readl(addr) | BIT(group->bit), addr);
+ }
+
+ return 0;
+}
+
+const struct pinctrl_ops meson_pinctrl_ops = {
+ .get_groups_count = meson_pinctrl_get_groups_count,
+ .get_group_name = meson_pinctrl_get_group_name,
+ .get_functions_count = meson_pinmux_get_functions_count,
+ .get_function_name = meson_pinmux_get_function_name,
+ .pinmux_group_set = meson_pinmux_group_set,
+ .set_state = pinctrl_generic_set_state,
+};
+
+static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
+{
+ int index, len = 0;
+ const fdt32_t *reg;
+
+ index = fdt_find_string(gd->fdt_blob, offset, "reg-names", name);
+ if (index < 0)
+ return FDT_ADDR_T_NONE;
+
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+ if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
+ return FDT_ADDR_T_NONE;
+
+ reg += index * (na + ns);
+
+ return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
+}
+
+int meson_pinctrl_probe(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ int node, gpio = -1, len;
+ int na, ns;
+
+ na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (na < 1) {
+ debug("bad #address-cells\n");
+ return -EINVAL;
+ }
+
+ ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (ns < 1) {
+ debug("bad #size-cells\n");
+ return -EINVAL;
+ }
+
+ fdt_for_each_subnode(gd->fdt_blob, node, dev->of_offset) {
+ if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
+ gpio = node;
+ break;
+ }
+ }
+
+ if (!gpio) {
+ debug("gpio node not found\n");
+ return -EINVAL;
+ }
+
+ addr = parse_address(gpio, "mux", na, ns);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("mux not found\n");
+ return -EINVAL;
+ }
+
+ priv->reg_mux = (void __iomem *)addr;
+ priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
+
+ return 0;
+}
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
new file mode 100644
index 0000000..4127a60
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PINCTRL_MESON_H__
+#define __PINCTRL_MESON_H__
+
+#include <linux/types.h>
+
+struct meson_pmx_group {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int num_pins;
+ bool is_gpio;
+ unsigned int reg;
+ unsigned int bit;
+};
+
+struct meson_pmx_func {
+ const char *name;
+ const char * const *groups;
+ unsigned int num_groups;
+};
+
+struct meson_pinctrl_data {
+ const char *name;
+ struct meson_pmx_group *groups;
+ struct meson_pmx_func *funcs;
+ unsigned int pin_base;
+ unsigned int num_pins;
+ unsigned int num_groups;
+ unsigned int num_funcs;
+};
+
+struct meson_pinctrl {
+ struct meson_pinctrl_data *data;
+ void __iomem *reg_mux;
+};
+
+#define PIN(x, b) (b + x)
+
+#define GROUP(grp, r, b) \
+ { \
+ .name = #grp, \
+ .pins = grp ## _pins, \
+ .num_pins = ARRAY_SIZE(grp ## _pins), \
+ .reg = r, \
+ .bit = b, \
+ }
+
+#define GPIO_GROUP(gpio, b) \
+ { \
+ .name = #gpio, \
+ .pins = (const unsigned int[]){ PIN(gpio, b) }, \
+ .num_pins = 1, \
+ .is_gpio = true, \
+ }
+
+#define FUNCTION(fn) \
+ { \
+ .name = #fn, \
+ .groups = fn ## _groups, \
+ .num_groups = ARRAY_SIZE(fn ## _groups), \
+ }
+
+#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
+
+extern const struct pinctrl_ops meson_pinctrl_ops;
+
+int meson_pinctrl_probe(struct udevice *dev);
+
+#endif /* __PINCTRL_MESON_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 4/4] meson: odroid-c2: enable Ethernet support through the device tree
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-16 9:49 ` Beniamino Galvani
-1 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: u-boot
Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
arch/arm/include/asm/arch-meson/gxbb.h | 3 ---
board/amlogic/odroid-c2/odroid-c2.c | 13 -------------
configs/odroid-c2_defconfig | 3 +++
drivers/net/designware.c | 1 +
4 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
index f90f632..ce41349 100644
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -20,9 +20,6 @@
#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
-/* Pinmux registers 0 to 12 */
-#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n))
-
#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index bd72100..b61daaa 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -21,24 +21,11 @@ int board_init(void)
return 0;
}
-static const struct eth_pdata gxbb_eth_pdata = {
- .iobase = GXBB_ETH_BASE,
- .phy_interface = PHY_INTERFACE_MODE_RGMII,
-};
-
-U_BOOT_DEVICE(meson_eth) = {
- .name = "eth_designware",
- .platdata = &gxbb_eth_pdata,
-};
-
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
ssize_t len;
- /* Select Ethernet function */
- setbits_le32(GXBB_PINMUX(6), 0x3fff);
-
/* Set RGMII mode */
setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
GXBB_ETH_REG_0_TX_PHASE(1) |
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 808bbc2..3e9ef68 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -14,6 +14,9 @@ CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 8ba72e3..9e6d726 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -737,6 +737,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "allwinner,sun7i-a20-gmac" },
{ .compatible = "altr,socfpga-stmmac" },
+ { .compatible = "amlogic,meson6-dwmac" },
{ }
};
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 4/4] meson: odroid-c2: enable Ethernet support through the device tree
@ 2016-08-16 9:49 ` Beniamino Galvani
0 siblings, 0 replies; 30+ messages in thread
From: Beniamino Galvani @ 2016-08-16 9:49 UTC (permalink / raw)
To: linus-amlogic
Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
arch/arm/include/asm/arch-meson/gxbb.h | 3 ---
board/amlogic/odroid-c2/odroid-c2.c | 13 -------------
configs/odroid-c2_defconfig | 3 +++
drivers/net/designware.c | 1 +
4 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
index f90f632..ce41349 100644
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -20,9 +20,6 @@
#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
-/* Pinmux registers 0 to 12 */
-#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n))
-
#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index bd72100..b61daaa 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -21,24 +21,11 @@ int board_init(void)
return 0;
}
-static const struct eth_pdata gxbb_eth_pdata = {
- .iobase = GXBB_ETH_BASE,
- .phy_interface = PHY_INTERFACE_MODE_RGMII,
-};
-
-U_BOOT_DEVICE(meson_eth) = {
- .name = "eth_designware",
- .platdata = &gxbb_eth_pdata,
-};
-
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
ssize_t len;
- /* Select Ethernet function */
- setbits_le32(GXBB_PINMUX(6), 0x3fff);
-
/* Set RGMII mode */
setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
GXBB_ETH_REG_0_TX_PHASE(1) |
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 808bbc2..3e9ef68 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -14,6 +14,9 @@ CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 8ba72e3..9e6d726 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -737,6 +737,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "allwinner,sun7i-a20-gmac" },
{ .compatible = "altr,socfpga-stmmac" },
+ { .compatible = "amlogic,meson6-dwmac" },
{ }
};
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 2/4] arm: dts: update DTS files for meson-gxbb and odroid-c2
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-18 3:44 ` Simon Glass
-1 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: u-boot
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Import DTS files and dt-bindings includes from Linux 4.8-rc1.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> arch/arm/dts/meson-gxbb-odroidc2.dts | 19 ++
> arch/arm/dts/meson-gxbb.dtsi | 170 ++++++++++++++++-
> include/dt-bindings/gpio/meson-gxbb-gpio.h | 154 +++++++++++++++
> .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 210 +++++++++++++++++++++
> 4 files changed, 552 insertions(+), 1 deletion(-)
> create mode 100644 include/dt-bindings/gpio/meson-gxbb-gpio.h
> create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 2/4] arm: dts: update DTS files for meson-gxbb and odroid-c2
@ 2016-08-18 3:44 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: linus-amlogic
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Import DTS files and dt-bindings includes from Linux 4.8-rc1.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> arch/arm/dts/meson-gxbb-odroidc2.dts | 19 ++
> arch/arm/dts/meson-gxbb.dtsi | 170 ++++++++++++++++-
> include/dt-bindings/gpio/meson-gxbb-gpio.h | 154 +++++++++++++++
> .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 210 +++++++++++++++++++++
> 4 files changed, 552 insertions(+), 1 deletion(-)
> create mode 100644 include/dt-bindings/gpio/meson-gxbb-gpio.h
> create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-18 3:44 ` Simon Glass
-1 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: u-boot
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> In cases where the pins and groups definitions are in a sub-node, as:
>
> uart_a {
> mux {
> groups = "uart_tx_a", "uart_rx_a";
> function = "uart_a";
> };
> };
>
> pinctrl_generic_set_state_subnode() returns an error for the top-level
> node and pinctrl_generic_set_state() fails. Instead, return success so
> that the child nodes are tried.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> drivers/pinctrl/pinctrl-generic.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro, are you happy with this change?
We really need some pinctrl tests.
>
> diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
> index e86b72a..baff40f 100644
> --- a/drivers/pinctrl/pinctrl-generic.c
> +++ b/drivers/pinctrl/pinctrl-generic.c
> @@ -312,8 +312,10 @@ static int pinctrl_generic_set_state_subnode(struct udevice *dev,
> is_group = true;
> strings_count = fdt_count_strings(fdt, node,
> subnode_target_type);
> - if (strings_count < 0)
> - return -EINVAL;
> + if (strings_count < 0) {
> + /* skip this node; may contain config child nodes */
> + return 0;
> + }
> }
>
> for (i = 0; i < strings_count; i++) {
> --
> 2.7.4
>
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
@ 2016-08-18 3:44 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: linus-amlogic
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> In cases where the pins and groups definitions are in a sub-node, as:
>
> uart_a {
> mux {
> groups = "uart_tx_a", "uart_rx_a";
> function = "uart_a";
> };
> };
>
> pinctrl_generic_set_state_subnode() returns an error for the top-level
> node and pinctrl_generic_set_state() fails. Instead, return success so
> that the child nodes are tried.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> drivers/pinctrl/pinctrl-generic.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro, are you happy with this change?
We really need some pinctrl tests.
>
> diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
> index e86b72a..baff40f 100644
> --- a/drivers/pinctrl/pinctrl-generic.c
> +++ b/drivers/pinctrl/pinctrl-generic.c
> @@ -312,8 +312,10 @@ static int pinctrl_generic_set_state_subnode(struct udevice *dev,
> is_group = true;
> strings_count = fdt_count_strings(fdt, node,
> subnode_target_type);
> - if (strings_count < 0)
> - return -EINVAL;
> + if (strings_count < 0) {
> + /* skip this node; may contain config child nodes */
> + return 0;
> + }
> }
>
> for (i = 0; i < strings_count; i++) {
> --
> 2.7.4
>
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 3/4] pinctrl: add driver for meson-gxbb pin controller
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-18 3:44 ` Simon Glass
-1 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: u-boot
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Add a pin controller driver for Meson GXBB adapted from Linux kernel.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/meson/Kconfig | 11 +
> drivers/pinctrl/meson/Makefile | 6 +
> drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 432 +++++++++++++++++++++++++++++
> drivers/pinctrl/meson/pinctrl-meson.c | 179 ++++++++++++
> drivers/pinctrl/meson/pinctrl-meson.h | 74 +++++
> 7 files changed, 704 insertions(+)
> create mode 100644 drivers/pinctrl/meson/Kconfig
> create mode 100644 drivers/pinctrl/meson/Makefile
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxbb.c
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 3/4] pinctrl: add driver for meson-gxbb pin controller
@ 2016-08-18 3:44 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: linus-amlogic
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Add a pin controller driver for Meson GXBB adapted from Linux kernel.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/meson/Kconfig | 11 +
> drivers/pinctrl/meson/Makefile | 6 +
> drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 432 +++++++++++++++++++++++++++++
> drivers/pinctrl/meson/pinctrl-meson.c | 179 ++++++++++++
> drivers/pinctrl/meson/pinctrl-meson.h | 74 +++++
> 7 files changed, 704 insertions(+)
> create mode 100644 drivers/pinctrl/meson/Kconfig
> create mode 100644 drivers/pinctrl/meson/Makefile
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxbb.c
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 4/4] meson: odroid-c2: enable Ethernet support through the device tree
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-18 3:44 ` Simon Glass
-1 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: u-boot
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Remove the device definition from board file, update the driver with
> the new compatible property and update config with necessary options.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> arch/arm/include/asm/arch-meson/gxbb.h | 3 ---
> board/amlogic/odroid-c2/odroid-c2.c | 13 -------------
> configs/odroid-c2_defconfig | 3 +++
> drivers/net/designware.c | 1 +
> 4 files changed, 4 insertions(+), 16 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 4/4] meson: odroid-c2: enable Ethernet support through the device tree
@ 2016-08-18 3:44 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2016-08-18 3:44 UTC (permalink / raw)
To: linus-amlogic
On 16 August 2016 at 03:49, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Remove the device definition from board file, update the driver with
> the new compatible property and update config with necessary options.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
> arch/arm/include/asm/arch-meson/gxbb.h | 3 ---
> board/amlogic/odroid-c2/odroid-c2.c | 13 -------------
> configs/odroid-c2_defconfig | 3 +++
> drivers/net/designware.c | 1 +
> 4 files changed, 4 insertions(+), 16 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-08-19 9:19 ` Masahiro Yamada
-1 siblings, 0 replies; 30+ messages in thread
From: Masahiro Yamada @ 2016-08-19 9:19 UTC (permalink / raw)
To: u-boot
2016-08-16 18:49 GMT+09:00 Beniamino Galvani <b.galvani@gmail.com>:
> In cases where the pins and groups definitions are in a sub-node, as:
>
> uart_a {
> mux {
> groups = "uart_tx_a", "uart_rx_a";
> function = "uart_a";
> };
> };
>
> pinctrl_generic_set_state_subnode() returns an error for the top-level
> node and pinctrl_generic_set_state() fails. Instead, return success so
> that the child nodes are tried.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
Looks good to me. Thanks!
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
@ 2016-08-19 9:19 ` Masahiro Yamada
0 siblings, 0 replies; 30+ messages in thread
From: Masahiro Yamada @ 2016-08-19 9:19 UTC (permalink / raw)
To: linus-amlogic
2016-08-16 18:49 GMT+09:00 Beniamino Galvani <b.galvani@gmail.com>:
> In cases where the pins and groups definitions are in a sub-node, as:
>
> uart_a {
> mux {
> groups = "uart_tx_a", "uart_rx_a";
> function = "uart_a";
> };
> };
>
> pinctrl_generic_set_state_subnode() returns an error for the top-level
> node and pinctrl_generic_set_state() fails. Instead, return success so
> that the child nodes are tried.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
Looks good to me. Thanks!
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [U-Boot, 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-09-07 17:57 ` Tom Rini
-1 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: u-boot
On Tue, Aug 16, 2016 at 11:49:47AM +0200, Beniamino Galvani wrote:
> In cases where the pins and groups definitions are in a sub-node, as:
>
> uart_a {
> mux {
> groups = "uart_tx_a", "uart_rx_a";
> function = "uart_a";
> };
> };
>
> pinctrl_generic_set_state_subnode() returns an error for the top-level
> node and pinctrl_generic_set_state() fails. Instead, return success so
> that the child nodes are tried.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot, 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
@ 2016-09-07 17:57 ` Tom Rini
0 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: linus-amlogic
On Tue, Aug 16, 2016 at 11:49:47AM +0200, Beniamino Galvani wrote:
> In cases where the pins and groups definitions are in a sub-node, as:
>
> uart_a {
> mux {
> groups = "uart_tx_a", "uart_rx_a";
> function = "uart_a";
> };
> };
>
> pinctrl_generic_set_state_subnode() returns an error for the top-level
> node and pinctrl_generic_set_state() fails. Instead, return success so
> that the child nodes are tried.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [U-Boot, 2/4] arm: dts: update DTS files for meson-gxbb and odroid-c2
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-09-07 17:57 ` Tom Rini
-1 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: u-boot
On Tue, Aug 16, 2016 at 11:49:48AM +0200, Beniamino Galvani wrote:
> Import DTS files and dt-bindings includes from Linux 4.8-rc1.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot,2/4] arm: dts: update DTS files for meson-gxbb and odroid-c2
@ 2016-09-07 17:57 ` Tom Rini
0 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: linus-amlogic
On Tue, Aug 16, 2016 at 11:49:48AM +0200, Beniamino Galvani wrote:
> Import DTS files and dt-bindings includes from Linux 4.8-rc1.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 3/4] pinctrl: add driver for meson-gxbb pin controller
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-09-07 17:57 ` Tom Rini
-1 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: u-boot
On Tue, Aug 16, 2016 at 11:49:49AM +0200, Beniamino Galvani wrote:
> Add a pin controller driver for Meson GXBB adapted from Linux kernel.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot,3/4] pinctrl: add driver for meson-gxbb pin controller
@ 2016-09-07 17:57 ` Tom Rini
0 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: linus-amlogic
On Tue, Aug 16, 2016 at 11:49:49AM +0200, Beniamino Galvani wrote:
> Add a pin controller driver for Meson GXBB adapted from Linux kernel.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 3/4] pinctrl: add driver for meson-gxbb pin controller
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-09-07 17:57 ` Tom Rini
-1 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: u-boot
On Tue, Aug 16, 2016 at 11:49:49AM +0200, Beniamino Galvani wrote:
> Add a pin controller driver for Meson GXBB adapted from Linux kernel.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot,3/4] pinctrl: add driver for meson-gxbb pin controller
@ 2016-09-07 17:57 ` Tom Rini
0 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: linus-amlogic
On Tue, Aug 16, 2016 at 11:49:49AM +0200, Beniamino Galvani wrote:
> Add a pin controller driver for Meson GXBB adapted from Linux kernel.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 4/4] meson: odroid-c2: enable Ethernet support through the device tree
2016-08-16 9:49 ` Beniamino Galvani
@ 2016-09-07 17:57 ` Tom Rini
-1 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: u-boot
On Tue, Aug 16, 2016 at 11:49:50AM +0200, Beniamino Galvani wrote:
> Remove the device definition from board file, update the driver with
> the new compatible property and update config with necessary options.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot, 4/4] meson: odroid-c2: enable Ethernet support through the device tree
@ 2016-09-07 17:57 ` Tom Rini
0 siblings, 0 replies; 30+ messages in thread
From: Tom Rini @ 2016-09-07 17:57 UTC (permalink / raw)
To: linus-amlogic
On Tue, Aug 16, 2016 at 11:49:50AM +0200, Beniamino Galvani wrote:
> Remove the device definition from board file, update the driver with
> the new compatible property and update config with necessary options.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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end of thread, other threads:[~2016-09-07 17:57 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-16 9:49 [U-Boot] [PATCH 0/4] Amlogic Meson pinctrl driver for u-boot Beniamino Galvani
2016-08-16 9:49 ` Beniamino Galvani
2016-08-16 9:49 ` [U-Boot] [PATCH 1/4] pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes Beniamino Galvani
2016-08-16 9:49 ` Beniamino Galvani
2016-08-18 3:44 ` [U-Boot] " Simon Glass
2016-08-18 3:44 ` Simon Glass
2016-08-19 9:19 ` [U-Boot] " Masahiro Yamada
2016-08-19 9:19 ` Masahiro Yamada
2016-09-07 17:57 ` [U-Boot] [U-Boot, " Tom Rini
2016-09-07 17:57 ` Tom Rini
2016-08-16 9:49 ` [U-Boot] [PATCH 2/4] arm: dts: update DTS files for meson-gxbb and odroid-c2 Beniamino Galvani
2016-08-16 9:49 ` Beniamino Galvani
2016-08-18 3:44 ` [U-Boot] " Simon Glass
2016-08-18 3:44 ` Simon Glass
2016-09-07 17:57 ` [U-Boot] [U-Boot, " Tom Rini
2016-09-07 17:57 ` [U-Boot,2/4] " Tom Rini
2016-08-16 9:49 ` [U-Boot] [PATCH 3/4] pinctrl: add driver for meson-gxbb pin controller Beniamino Galvani
2016-08-16 9:49 ` Beniamino Galvani
2016-08-18 3:44 ` [U-Boot] " Simon Glass
2016-08-18 3:44 ` Simon Glass
2016-09-07 17:57 ` [U-Boot] [U-Boot, " Tom Rini
2016-09-07 17:57 ` [U-Boot,3/4] " Tom Rini
2016-09-07 17:57 ` [U-Boot] [U-Boot, 3/4] " Tom Rini
2016-09-07 17:57 ` [U-Boot,3/4] " Tom Rini
2016-08-16 9:49 ` [U-Boot] [PATCH 4/4] meson: odroid-c2: enable Ethernet support through the device tree Beniamino Galvani
2016-08-16 9:49 ` Beniamino Galvani
2016-08-18 3:44 ` [U-Boot] " Simon Glass
2016-08-18 3:44 ` Simon Glass
2016-09-07 17:57 ` [U-Boot] [U-Boot, " Tom Rini
2016-09-07 17:57 ` Tom Rini
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