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From: Bibby Hsieh <bibby.hsieh@mediatek.com>
To: David Airlie <airlied@linux.ie>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	<dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>
Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Cawa Cheng <cawa.cheng@mediatek.com>,
	Daniel Kurtz <djkurtz@chromium.org>,
	Bibby Hsieh <bibby.hsieh@mediatek.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	YT Shen <yt.shen@mediatek.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	CK Hu <ck.hu@mediatek.com>, Mao Huang <littlecvr@chromium.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Junzhi Zhao <junzhi.zhao@mediatek.com>
Subject: [PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
Date: Wed, 17 Aug 2016 14:58:08 +0800	[thread overview]
Message-ID: <1471417088-2993-4-git-send-email-bibby.hsieh@mediatek.com> (raw)
In-Reply-To: <1471417088-2993-1-git-send-email-bibby.hsieh@mediatek.com>

From: Junzhi Zhao <junzhi.zhao@mediatek.com>

Pixel clock should be 297MHz when resolution is 4K.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0186e50..90fb831 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	unsigned long pll_rate;
 	unsigned int factor;
 
+	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
 	pix_rate = 1000UL * mode->clock;
-	if (mode->clock <= 74000)
+	if (mode->clock <= 27000)
+		factor = 16 * 3;
+	else if (mode->clock <= 84000)
 		factor = 8 * 3;
-	else
+	else if (mode->clock <= 167000)
 		factor = 4 * 3;
+	else
+		factor = 2 * 3;
 	pll_rate = pix_rate * factor;
 
 	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: Bibby Hsieh <bibby.hsieh@mediatek.com>
To: David Airlie <airlied@linux.ie>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org
Cc: Junzhi Zhao <junzhi.zhao@mediatek.com>,
	linux-kernel@vger.kernel.org,
	Cawa Cheng <cawa.cheng@mediatek.com>,
	Mao Huang <littlecvr@chromium.org>,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Sascha Hauer <kernel@pengutronix.de>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
Date: Wed, 17 Aug 2016 14:58:08 +0800	[thread overview]
Message-ID: <1471417088-2993-4-git-send-email-bibby.hsieh@mediatek.com> (raw)
In-Reply-To: <1471417088-2993-1-git-send-email-bibby.hsieh@mediatek.com>

From: Junzhi Zhao <junzhi.zhao@mediatek.com>

Pixel clock should be 297MHz when resolution is 4K.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0186e50..90fb831 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	unsigned long pll_rate;
 	unsigned int factor;
 
+	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
 	pix_rate = 1000UL * mode->clock;
-	if (mode->clock <= 74000)
+	if (mode->clock <= 27000)
+		factor = 16 * 3;
+	else if (mode->clock <= 84000)
 		factor = 8 * 3;
-	else
+	else if (mode->clock <= 167000)
 		factor = 4 * 3;
+	else
+		factor = 2 * 3;
 	pll_rate = pix_rate * factor;
 
 	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
-- 
1.7.9.5

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
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WARNING: multiple messages have this Message-ID (diff)
From: bibby.hsieh@mediatek.com (Bibby Hsieh)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
Date: Wed, 17 Aug 2016 14:58:08 +0800	[thread overview]
Message-ID: <1471417088-2993-4-git-send-email-bibby.hsieh@mediatek.com> (raw)
In-Reply-To: <1471417088-2993-1-git-send-email-bibby.hsieh@mediatek.com>

From: Junzhi Zhao <junzhi.zhao@mediatek.com>

Pixel clock should be 297MHz when resolution is 4K.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0186e50..90fb831 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	unsigned long pll_rate;
 	unsigned int factor;
 
+	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
 	pix_rate = 1000UL * mode->clock;
-	if (mode->clock <= 74000)
+	if (mode->clock <= 27000)
+		factor = 16 * 3;
+	else if (mode->clock <= 84000)
 		factor = 8 * 3;
-	else
+	else if (mode->clock <= 167000)
 		factor = 4 * 3;
+	else
+		factor = 2 * 3;
 	pll_rate = pix_rate * factor;
 
 	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
-- 
1.7.9.5

  parent reply	other threads:[~2016-08-17  6:58 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-17  6:58 [PATCH v4 0/3] MT8173 HDMI 4K support Bibby Hsieh
2016-08-17  6:58 ` Bibby Hsieh
2016-08-17  6:58 ` Bibby Hsieh
2016-08-17  6:58 ` [PATCH v4 1/3] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable Bibby Hsieh
2016-08-17  6:58   ` Bibby Hsieh
2016-08-17  6:58   ` Bibby Hsieh
2016-08-17  6:58 ` [PATCH v4 2/3] drm/mediatek: enhance the HDMI driving current Bibby Hsieh
2016-08-17  6:58   ` Bibby Hsieh
2016-08-17  6:58   ` Bibby Hsieh
2016-08-17  6:58 ` Bibby Hsieh [this message]
2016-08-17  6:58   ` [PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K Bibby Hsieh
2016-08-17  6:58   ` Bibby Hsieh
2016-09-12  3:15   ` CK Hu
2016-09-12  3:15     ` CK Hu
2016-09-12  3:15     ` CK Hu

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