[PATCH 0/1] AMDGPU SI support almost fixed

[PATCH 0/1] AMDGPU SI support almost fixed

[Marek Olšák]

Hi,

This amdgpu patch fixes DCE support. Now only the cursor is broken:

[   37.936022] [drm:dce_v6_0_crtc_cursor_set2 [amdgpu]] *ERROR* bad cursor width or height 128 x 128

Everything else seems to work. I've not tested UVD and VCE.

Now I'm gonna send out all userspace patches that I intend to merge before the kernel support lands. I think that shouldn't be a problem.

Marek
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[PATCH] drm/amdgpu: fix SI display support

[Marek Olšák]

From: Marek Olšák <marek.olsak@amd.com>

The tiling flags use the same amdgpu encoding regardless of the ASIC.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c         | 74 ++++-----------------------
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 32 ------------
 2 files changed, 11 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 07e0475..4444b73 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1476,66 +1476,33 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
 
 	if (enable)
 		WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
 	else
 		WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
 }
 
-
-static void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
-			     unsigned *bankh, unsigned *mtaspect,
-			     unsigned *tile_split)
-{
-	*bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
-	*bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
-	*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
-	*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
-	switch (*bankw) {
-	default:
-	case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
-	case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
-	case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
-	case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
-	}
-	switch (*bankh) {
-	default:
-	case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
-	case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
-	case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
-	case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
-	}
-	switch (*mtaspect) {
-	default:
-	case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
-	case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
-	case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
-	case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
-	}
-}
-
 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
 				     struct drm_framebuffer *fb,
 				     int x, int y, int atomic)
 {
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
 	struct amdgpu_framebuffer *amdgpu_fb;
 	struct drm_framebuffer *target_fb;
 	struct drm_gem_object *obj;
 	struct amdgpu_bo *rbo;
 	uint64_t fb_location, tiling_flags;
-	uint32_t fb_format, fb_pitch_pixels;
-	unsigned bankw, bankh, mtaspect, tile_split;
+	uint32_t fb_format, fb_pitch_pixels, pipe_config;
 	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
 	u32 viewport_w, viewport_h;
 	int r;
 	bool bypass_lut = false;
 
 	/* no fb bound */
 	if (!atomic && !crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
@@ -1634,59 +1601,40 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
 #endif
 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
 		bypass_lut = true;
 		break;
 	default:
 		DRM_ERROR("Unsupported screen format %s\n",
 			  drm_get_format_name(target_fb->pixel_format));
 		return -EINVAL;
 	}
 
-	if (tiling_flags & AMDGPU_TILING_MACRO) {
+	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
+		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
 
-		unsigned index, num_banks;
-		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
-
-		/* Set NUM_BANKS. */
-
-		switch (target_fb->bits_per_pixel) {
-		case 8:
-			index = 10;
-			break;
-		case 16:
-			index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
-			break;
-		default:
-		case 32:
-			index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
-			break;
-		}
-
-		num_banks = (adev->gfx.config.tile_mode_array[index] >> 20) & 0x3;
+		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
+		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
+		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
+		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
+		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
 
 		fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
-
 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
 		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
 		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
 		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
 		fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
-	} else if (tiling_flags & AMDGPU_TILING_MICRO)
+	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 
-
-	if ((adev->asic_type == CHIP_TAHITI) ||
-	    (adev->asic_type == CHIP_PITCAIRN))
-		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
-	else if ((adev->asic_type == CHIP_VERDE) ||
-		 (adev->asic_type == CHIP_OLAND))
-		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
+	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
+	fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
 
 	dce_v6_0_vga_enable(crtc, false);
 
 	/* Make sure surface address is updated at vertical blank rather than
 	 * horizontal blank
 	 */
 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
 
 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 	       upper_32_bits(fb_location));
diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
index f9a0c14..9609199 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
@@ -2003,23 +2003,20 @@
 #       define EVERGREEN_INTERLEAVE_EN                  (1 << 0)
 
 #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
 #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
 
 #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL            (0 << 20)
 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED            (1 << 20)
 #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1            (2 << 20)
 #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1            (4 << 20)
 
-#define AMDGPU_TILING_MACRO				0x1
-#define AMDGPU_TILING_MICRO				0x2
-
 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1a45
 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1845
 
 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1847
 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1a47
 
 #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
@@ -2164,49 +2161,20 @@
 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4  2
 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8  3
 
 #define EVERGREEN_GRPH_SWAP_CONTROL                     0x1a03
 #define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
 #       define EVERGREEN_GRPH_ENDIAN_NONE               0
 #       define EVERGREEN_GRPH_ENDIAN_8IN16              1
 #       define EVERGREEN_GRPH_ENDIAN_8IN32              2
 #       define EVERGREEN_GRPH_ENDIAN_8IN64              3
 
-/* this object requires a surface when mapped - i.e. front buffer */
-#define RADEON_TILING_SURFACE				0x10
-#define RADEON_TILING_MICRO_SQUARE			0x20
-#define RADEON_TILING_EG_BANKW_SHIFT			8
-#define RADEON_TILING_EG_BANKW_MASK			0xf
-#define RADEON_TILING_EG_BANKH_SHIFT			12
-#define RADEON_TILING_EG_BANKH_MASK			0xf
-#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT	16
-#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK		0xf
-#define RADEON_TILING_EG_TILE_SPLIT_SHIFT		24
-#define RADEON_TILING_EG_TILE_SPLIT_MASK		0xf
-#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT	28
-#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK	0xf
-
-#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED	8
-#define SI_TILE_MODE_COLOR_1D			13
-#define SI_TILE_MODE_COLOR_1D_SCANOUT		9
-#define SI_TILE_MODE_COLOR_2D_8BPP		14
-#define SI_TILE_MODE_COLOR_2D_16BPP		15
-#define SI_TILE_MODE_COLOR_2D_32BPP		16
-#define SI_TILE_MODE_COLOR_2D_64BPP		17
-#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP	11
-#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP	12
-#define SI_TILE_MODE_DEPTH_STENCIL_1D		4
-#define SI_TILE_MODE_DEPTH_STENCIL_2D		0
-#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA	3
-#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA	3
-#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA	2
-
 #define EVERGREEN_D3VGA_CONTROL                         0xf8
 #define EVERGREEN_D4VGA_CONTROL                         0xf9
 #define EVERGREEN_D5VGA_CONTROL                         0xfa
 #define EVERGREEN_D6VGA_CONTROL                         0xfb
 
 #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK      0xffffff00
 
 #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL         0x1a02
 #define EVERGREEN_LUT_10BIT_BYPASS_EN            (1 << 8)
 
-- 
2.7.4

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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Michel Dänzer]

On 19/08/16 06:01 PM, Marek Olšák wrote:
> Hi,
> 
> This amdgpu patch fixes DCE support. Now only the cursor is broken:
> 
> [   37.936022] [drm:dce_v6_0_crtc_cursor_set2 [amdgpu]] *ERROR* bad cursor width or height 128 x 128

The DDX driver's AMDGPUPreInit_KMS is hardcoding the >= CIK cursor size.


-- 
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Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Marek Olšák]

I've added this. The dmesg message is gone, but the cursor is still missing.

diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index 9ee48df..d9f15a4 100644
--- a/src/amdgpu_kms.c
+++ b/src/amdgpu_kms.c
@@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
        else
                pAMDGPUEnt->HasCRTC2 = TRUE;

-       info->cursor_w = CURSOR_WIDTH_CIK;
-       info->cursor_h = CURSOR_HEIGHT_CIK;
+       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
+           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
+               info->cursor_w = CURSOR_WIDTH;
+               info->cursor_h = CURSOR_HEIGHT;
+       } else {
+               info->cursor_w = CURSOR_WIDTH_CIK;
+               info->cursor_h = CURSOR_HEIGHT_CIK;
+       }

        amdgpu_query_heap_size(pAMDGPUEnt->pDev, AMDGPU_GEM_DOMAIN_GTT,
                                &heap_size, &max_allocation);

Marek



diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index 9ee48df..d9f15a4 100644
--- a/src/amdgpu_kms.c
+++ b/src/amdgpu_kms.c
@@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
        else
                pAMDGPUEnt->HasCRTC2 = TRUE;

-       info->cursor_w = CURSOR_WIDTH_CIK;
-       info->cursor_h = CURSOR_HEIGHT_CIK;
+       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
+           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
+               info->cursor_w = CURSOR_WIDTH;
+               info->cursor_h = CURSOR_HEIGHT;
+       } else {
+               info->cursor_w = CURSOR_WIDTH_CIK;
+               info->cursor_h = CURSOR_HEIGHT_CIK;
+       }

        amdgpu_query_heap_size(pAMDGPUEnt->pDev, AMDGPU_GEM_DOMAIN_GTT,
                                &heap_size, &max_allocation);

On Fri, Aug 19, 2016 at 11:14 AM, Michel Dänzer <michel@daenzer.net> wrote:
> On 19/08/16 06:01 PM, Marek Olšák wrote:
>> Hi,
>>
>> This amdgpu patch fixes DCE support. Now only the cursor is broken:
>>
>> [   37.936022] [drm:dce_v6_0_crtc_cursor_set2 [amdgpu]] *ERROR* bad cursor width or height 128 x 128
>
> The DDX driver's AMDGPUPreInit_KMS is hardcoding the >= CIK cursor size.
>
>
> --
> Earthling Michel Dänzer               |               http://www.amd.com
> Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Michel Dänzer]

On 19/08/16 06:24 PM, Marek Olšák wrote:
> I've added this. The dmesg message is gone, but the cursor is still missing.
> 
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index 9ee48df..d9f15a4 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
>         else
>                 pAMDGPUEnt->HasCRTC2 = TRUE;
> 
> -       info->cursor_w = CURSOR_WIDTH_CIK;
> -       info->cursor_h = CURSOR_HEIGHT_CIK;
> +       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
> +           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
> +               info->cursor_w = CURSOR_WIDTH;
> +               info->cursor_h = CURSOR_HEIGHT;
> +       } else {
> +               info->cursor_w = CURSOR_WIDTH_CIK;
> +               info->cursor_h = CURSOR_HEIGHT_CIK;
> +       }
> 
>         amdgpu_query_heap_size(pAMDGPUEnt->pDev, AMDGPU_GEM_DOMAIN_GTT,
>                                 &heap_size, &max_allocation);

Looks good; does the HW cursor work with the modesetting driver?


-- 
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Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Marek Olšák]

On Fri, Aug 19, 2016 at 11:45 AM, Michel Dänzer <michel@daenzer.net> wrote:
> On 19/08/16 06:24 PM, Marek Olšák wrote:
>> I've added this. The dmesg message is gone, but the cursor is still missing.
>>
>> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
>> index 9ee48df..d9f15a4 100644
>> --- a/src/amdgpu_kms.c
>> +++ b/src/amdgpu_kms.c
>> @@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
>>         else
>>                 pAMDGPUEnt->HasCRTC2 = TRUE;
>>
>> -       info->cursor_w = CURSOR_WIDTH_CIK;
>> -       info->cursor_h = CURSOR_HEIGHT_CIK;
>> +       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
>> +           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
>> +               info->cursor_w = CURSOR_WIDTH;
>> +               info->cursor_h = CURSOR_HEIGHT;
>> +       } else {
>> +               info->cursor_w = CURSOR_WIDTH_CIK;
>> +               info->cursor_h = CURSOR_HEIGHT_CIK;
>> +       }
>>
>>         amdgpu_query_heap_size(pAMDGPUEnt->pDev, AMDGPU_GEM_DOMAIN_GTT,
>>                                 &heap_size, &max_allocation);
>
> Looks good; does the HW cursor work with the modesetting driver?

No, the cursor doesn't work with modesetting either. There are no
errors in dmesg.

Marek
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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Michel Dänzer]

On 19/08/16 07:00 PM, Marek Olšák wrote:
> On Fri, Aug 19, 2016 at 11:45 AM, Michel Dänzer <michel@daenzer.net> wrote:
>> On 19/08/16 06:24 PM, Marek Olšák wrote:
>>> I've added this. The dmesg message is gone, but the cursor is still missing.
>>>
>>> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
>>> index 9ee48df..d9f15a4 100644
>>> --- a/src/amdgpu_kms.c
>>> +++ b/src/amdgpu_kms.c
>>> @@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
>>>         else
>>>                 pAMDGPUEnt->HasCRTC2 = TRUE;
>>>
>>> -       info->cursor_w = CURSOR_WIDTH_CIK;
>>> -       info->cursor_h = CURSOR_HEIGHT_CIK;
>>> +       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
>>> +           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
>>> +               info->cursor_w = CURSOR_WIDTH;
>>> +               info->cursor_h = CURSOR_HEIGHT;
>>> +       } else {
>>> +               info->cursor_w = CURSOR_WIDTH_CIK;
>>> +               info->cursor_h = CURSOR_HEIGHT_CIK;
>>> +       }
>>>
>>>         amdgpu_query_heap_size(pAMDGPUEnt->pDev, AMDGPU_GEM_DOMAIN_GTT,
>>>                                 &heap_size, &max_allocation);
>>
>> Looks good; does the HW cursor work with the modesetting driver?
> 
> No, the cursor doesn't work with modesetting either. There are no
> errors in dmesg.

Then it's probably a kernel driver issue.


-- 
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Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Marek Olšák]

On Fri, Aug 19, 2016 at 12:04 PM, Michel Dänzer <michel@daenzer.net> wrote:
> On 19/08/16 07:00 PM, Marek Olšák wrote:
>> On Fri, Aug 19, 2016 at 11:45 AM, Michel Dänzer <michel@daenzer.net> wrote:
>>> On 19/08/16 06:24 PM, Marek Olšák wrote:
>>>> I've added this. The dmesg message is gone, but the cursor is still missing.
>>>>
>>>> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
>>>> index 9ee48df..d9f15a4 100644
>>>> --- a/src/amdgpu_kms.c
>>>> +++ b/src/amdgpu_kms.c
>>>> @@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
>>>>         else
>>>>                 pAMDGPUEnt->HasCRTC2 = TRUE;
>>>>
>>>> -       info->cursor_w = CURSOR_WIDTH_CIK;
>>>> -       info->cursor_h = CURSOR_HEIGHT_CIK;
>>>> +       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
>>>> +           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
>>>> +               info->cursor_w = CURSOR_WIDTH;
>>>> +               info->cursor_h = CURSOR_HEIGHT;
>>>> +       } else {
>>>> +               info->cursor_w = CURSOR_WIDTH_CIK;
>>>> +               info->cursor_h = CURSOR_HEIGHT_CIK;
>>>> +       }
>>>>
>>>>         amdgpu_query_heap_size(pAMDGPUEnt->pDev, AMDGPU_GEM_DOMAIN_GTT,
>>>>                                 &heap_size, &max_allocation);
>>>
>>> Looks good; does the HW cursor work with the modesetting driver?
>>
>> No, the cursor doesn't work with modesetting either. There are no
>> errors in dmesg.
>
> Then it's probably a kernel driver issue.

OK. I'll leave that to our DCE experts. ;)

Marek
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RE: [PATCH 0/1] AMDGPU SI support almost fixed

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Marek Olšák
> Sent: Friday, August 19, 2016 5:25 AM
> To: Michel Dänzer
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 0/1] AMDGPU SI support almost fixed
> 
> I've added this. The dmesg message is gone, but the cursor is still missing.
> 
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index 9ee48df..d9f15a4 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int
> flags)
>         else
>                 pAMDGPUEnt->HasCRTC2 = TRUE;
> 
> -       info->cursor_w = CURSOR_WIDTH_CIK;
> -       info->cursor_h = CURSOR_HEIGHT_CIK;
> +       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
> +           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
> +               info->cursor_w = CURSOR_WIDTH;
> +               info->cursor_h = CURSOR_HEIGHT;
> +       } else {
> +               info->cursor_w = CURSOR_WIDTH_CIK;
> +               info->cursor_h = CURSOR_HEIGHT_CIK;
> +       }

At some point I added code to either radeon or modesetting to query the cursor size from the kernel.  That would probably be better than hardcoding it in case it ever changes again.

Alex

> 
>         amdgpu_query_heap_size(pAMDGPUEnt->pDev,
> AMDGPU_GEM_DOMAIN_GTT,
>                                 &heap_size, &max_allocation);
> 
> Marek
> 
> 
> 
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index 9ee48df..d9f15a4 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -929,8 +929,14 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int
> flags)
>         else
>                 pAMDGPUEnt->HasCRTC2 = TRUE;
> 
> -       info->cursor_w = CURSOR_WIDTH_CIK;
> -       info->cursor_h = CURSOR_HEIGHT_CIK;
> +       if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
> +           info->ChipFamily <= CHIP_FAMILY_HAINAN) {
> +               info->cursor_w = CURSOR_WIDTH;
> +               info->cursor_h = CURSOR_HEIGHT;
> +       } else {
> +               info->cursor_w = CURSOR_WIDTH_CIK;
> +               info->cursor_h = CURSOR_HEIGHT_CIK;
> +       }
> 
>         amdgpu_query_heap_size(pAMDGPUEnt->pDev,
> AMDGPU_GEM_DOMAIN_GTT,
>                                 &heap_size, &max_allocation);
> 
> On Fri, Aug 19, 2016 at 11:14 AM, Michel Dänzer <michel@daenzer.net>
> wrote:
> > On 19/08/16 06:01 PM, Marek Olšák wrote:
> >> Hi,
> >>
> >> This amdgpu patch fixes DCE support. Now only the cursor is broken:
> >>
> >> [   37.936022] [drm:dce_v6_0_crtc_cursor_set2 [amdgpu]] *ERROR* bad
> cursor width or height 128 x 128
> >
> > The DDX driver's AMDGPUPreInit_KMS is hardcoding the >= CIK cursor size.
> >
> >
> > --
> > Earthling Michel Dänzer               |               http://www.amd.com
> > Libre software enthusiast             |             Mesa and X developer
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH] drm/amdgpu: fix SI display support

[Alex Deucher]

I've squashed this patch into my si tree and also fixed the cursor.
Updated tree:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.9-si

Alex

On Fri, Aug 19, 2016 at 5:01 AM, Marek Olšák <maraeo@gmail.com> wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> The tiling flags use the same amdgpu encoding regardless of the ASIC.
>
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c         | 74 ++++-----------------------
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 32 ------------
>  2 files changed, 11 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 07e0475..4444b73 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1476,66 +1476,33 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
>         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>         struct drm_device *dev = crtc->dev;
>         struct amdgpu_device *adev = dev->dev_private;
>
>         if (enable)
>                 WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
>         else
>                 WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
>  }
>
> -
> -static void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
> -                            unsigned *bankh, unsigned *mtaspect,
> -                            unsigned *tile_split)
> -{
> -       *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
> -       *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
> -       *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
> -       *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
> -       switch (*bankw) {
> -       default:
> -       case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
> -       case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
> -       case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
> -       case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
> -       }
> -       switch (*bankh) {
> -       default:
> -       case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
> -       case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
> -       case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
> -       case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
> -       }
> -       switch (*mtaspect) {
> -       default:
> -       case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
> -       case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
> -       case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
> -       case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
> -       }
> -}
> -
>  static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
>                                      struct drm_framebuffer *fb,
>                                      int x, int y, int atomic)
>  {
>         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>         struct drm_device *dev = crtc->dev;
>         struct amdgpu_device *adev = dev->dev_private;
>         struct amdgpu_framebuffer *amdgpu_fb;
>         struct drm_framebuffer *target_fb;
>         struct drm_gem_object *obj;
>         struct amdgpu_bo *rbo;
>         uint64_t fb_location, tiling_flags;
> -       uint32_t fb_format, fb_pitch_pixels;
> -       unsigned bankw, bankh, mtaspect, tile_split;
> +       uint32_t fb_format, fb_pitch_pixels, pipe_config;
>         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
>         u32 viewport_w, viewport_h;
>         int r;
>         bool bypass_lut = false;
>
>         /* no fb bound */
>         if (!atomic && !crtc->primary->fb) {
>                 DRM_DEBUG_KMS("No FB bound\n");
>                 return 0;
>         }
> @@ -1634,59 +1601,40 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
>  #endif
>                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
>                 bypass_lut = true;
>                 break;
>         default:
>                 DRM_ERROR("Unsupported screen format %s\n",
>                           drm_get_format_name(target_fb->pixel_format));
>                 return -EINVAL;
>         }
>
> -       if (tiling_flags & AMDGPU_TILING_MACRO) {
> +       if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
> +               unsigned bankw, bankh, mtaspect, tile_split, num_banks;
>
> -               unsigned index, num_banks;
> -               evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
> -
> -               /* Set NUM_BANKS. */
> -
> -               switch (target_fb->bits_per_pixel) {
> -               case 8:
> -                       index = 10;
> -                       break;
> -               case 16:
> -                       index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
> -                       break;
> -               default:
> -               case 32:
> -                       index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
> -                       break;
> -               }
> -
> -               num_banks = (adev->gfx.config.tile_mode_array[index] >> 20) & 0x3;
> +               bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
> +               bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
> +               mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
> +               tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
> +               num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
>
>                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
> -
>                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
>                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
>                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
>                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
>                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
> -       } else if (tiling_flags & AMDGPU_TILING_MICRO)
> +       } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
>                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
>
> -
> -       if ((adev->asic_type == CHIP_TAHITI) ||
> -           (adev->asic_type == CHIP_PITCAIRN))
> -               fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
> -       else if ((adev->asic_type == CHIP_VERDE) ||
> -                (adev->asic_type == CHIP_OLAND))
> -               fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
> +       pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
> +       fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
>
>         dce_v6_0_vga_enable(crtc, false);
>
>         /* Make sure surface address is updated at vertical blank rather than
>          * horizontal blank
>          */
>         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
>
>         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
>                upper_32_bits(fb_location));
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> index f9a0c14..9609199 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> @@ -2003,23 +2003,20 @@
>  #       define EVERGREEN_INTERLEAVE_EN                  (1 << 0)
>
>  #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
>  #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
>
>  #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL            (0 << 20)
>  #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED            (1 << 20)
>  #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1            (2 << 20)
>  #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1            (4 << 20)
>
> -#define AMDGPU_TILING_MACRO                            0x1
> -#define AMDGPU_TILING_MICRO                            0x2
> -
>  #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1a45
>  #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1845
>
>  #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1847
>  #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1a47
>
>  #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
>  #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
>  #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
>  #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
> @@ -2164,49 +2161,20 @@
>  #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4  2
>  #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8  3
>
>  #define EVERGREEN_GRPH_SWAP_CONTROL                     0x1a03
>  #define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
>  #       define EVERGREEN_GRPH_ENDIAN_NONE               0
>  #       define EVERGREEN_GRPH_ENDIAN_8IN16              1
>  #       define EVERGREEN_GRPH_ENDIAN_8IN32              2
>  #       define EVERGREEN_GRPH_ENDIAN_8IN64              3
>
> -/* this object requires a surface when mapped - i.e. front buffer */
> -#define RADEON_TILING_SURFACE                          0x10
> -#define RADEON_TILING_MICRO_SQUARE                     0x20
> -#define RADEON_TILING_EG_BANKW_SHIFT                   8
> -#define RADEON_TILING_EG_BANKW_MASK                    0xf
> -#define RADEON_TILING_EG_BANKH_SHIFT                   12
> -#define RADEON_TILING_EG_BANKH_MASK                    0xf
> -#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT       16
> -#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK                0xf
> -#define RADEON_TILING_EG_TILE_SPLIT_SHIFT              24
> -#define RADEON_TILING_EG_TILE_SPLIT_MASK               0xf
> -#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT      28
> -#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK       0xf
> -
> -#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED      8
> -#define SI_TILE_MODE_COLOR_1D                  13
> -#define SI_TILE_MODE_COLOR_1D_SCANOUT          9
> -#define SI_TILE_MODE_COLOR_2D_8BPP             14
> -#define SI_TILE_MODE_COLOR_2D_16BPP            15
> -#define SI_TILE_MODE_COLOR_2D_32BPP            16
> -#define SI_TILE_MODE_COLOR_2D_64BPP            17
> -#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP    11
> -#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP    12
> -#define SI_TILE_MODE_DEPTH_STENCIL_1D          4
> -#define SI_TILE_MODE_DEPTH_STENCIL_2D          0
> -#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA      3
> -#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA      3
> -#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA      2
> -
>  #define EVERGREEN_D3VGA_CONTROL                         0xf8
>  #define EVERGREEN_D4VGA_CONTROL                         0xf9
>  #define EVERGREEN_D5VGA_CONTROL                         0xfa
>  #define EVERGREEN_D6VGA_CONTROL                         0xfb
>
>  #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK      0xffffff00
>
>  #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL         0x1a02
>  #define EVERGREEN_LUT_10BIT_BYPASS_EN            (1 << 8)
>
> --
> 2.7.4
>
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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Dave Airlie]

On 19 August 2016 at 19:01, Marek Olšák <maraeo@gmail.com> wrote:
> Hi,
>
> This amdgpu patch fixes DCE support. Now only the cursor is broken:
>
> [   37.936022] [drm:dce_v6_0_crtc_cursor_set2 [amdgpu]] *ERROR* bad cursor width or height 128 x 128
>
> Everything else seems to work. I've not tested UVD and VCE.
>
> Now I'm gonna send out all userspace patches that I intend to merge before the kernel support lands. I think that shouldn't be a problem.

Please don't land anything in userspace until kernel side is in
drm-next. At least if it's kernel API related.

Been burned too many times with people shipping libdrm before
something got set in stone in the kernel.

Dave.
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Re: [PATCH 0/1] AMDGPU SI support almost fixed

[Marek Olšák]

On Mon, Aug 22, 2016 at 3:18 AM, Dave Airlie <airlied@gmail.com> wrote:
> On 19 August 2016 at 19:01, Marek Olšák <maraeo@gmail.com> wrote:
>> Hi,
>>
>> This amdgpu patch fixes DCE support. Now only the cursor is broken:
>>
>> [   37.936022] [drm:dce_v6_0_crtc_cursor_set2 [amdgpu]] *ERROR* bad cursor width or height 128 x 128
>>
>> Everything else seems to work. I've not tested UVD and VCE.
>>
>> Now I'm gonna send out all userspace patches that I intend to merge before the kernel support lands. I think that shouldn't be a problem.
>
> Please don't land anything in userspace until kernel side is in
> drm-next. At least if it's kernel API related.
>
> Been burned too many times with people shipping libdrm before
> something got set in stone in the kernel.

There is just a new definition in amdgpu_drm.h: AMDGPU_FAMILY_SI

However, userspace doesn't need it, which means there is practically
no kernel API change from the userspace point of view.

I can delay pushing the AMDGPU_FAMILY_SI definition, but I don't think
anything else needs to be delayed.

Marek
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