* [PATCH v5 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY @ 2016-08-20 2:53 ` Shawn Lin 0 siblings, 0 replies; 7+ messages in thread From: Shawn Lin @ 2016-08-20 2:53 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: linux-kernel, linux-rockchip, Heiko Stuebner, Doug Anderson, Brian Norris, Wenrui Li, Rob Herring, devicetree, Shawn Lin This patch adds a binding that describes the Rockchip PCIe PHY found on Rockchip SoCs PCIe interface. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> --- Changes in v5: - add Rob's ack tag Changes in v4: None Changes in v3: - rename the node to pcie_phy: pcie-phy suggested by Doug Changes in v2: - add clk and reset description - remove unit-address .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file mode 100644 index 0000000..aedca29 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt @@ -0,0 +1,32 @@ +Rockchip PCIE PHY +----------------------- + +Required properties: + - compatible: rockchip,rk3399-pcie-phy + - #phy-cells: must be 0 + - clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must be "refclk" + - resets: Must contain an entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must be "phy" + +Example: + +grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + ... + + pcie_phy: pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <0>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + }; +}; + -- 2.3.7 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY @ 2016-08-20 2:53 ` Shawn Lin 0 siblings, 0 replies; 7+ messages in thread From: Shawn Lin @ 2016-08-20 2:53 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Heiko Stuebner, Doug Anderson, Brian Norris, Wenrui Li, Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA, Shawn Lin This patch adds a binding that describes the Rockchip PCIe PHY found on Rockchip SoCs PCIe interface. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- Changes in v5: - add Rob's ack tag Changes in v4: None Changes in v3: - rename the node to pcie_phy: pcie-phy suggested by Doug Changes in v2: - add clk and reset description - remove unit-address .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file mode 100644 index 0000000..aedca29 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt @@ -0,0 +1,32 @@ +Rockchip PCIE PHY +----------------------- + +Required properties: + - compatible: rockchip,rk3399-pcie-phy + - #phy-cells: must be 0 + - clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must be "refclk" + - resets: Must contain an entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must be "phy" + +Example: + +grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + ... + + pcie_phy: pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <0>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + }; +}; + -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY 2016-08-20 2:53 ` Shawn Lin (?) @ 2016-08-20 2:53 ` Shawn Lin 2016-08-31 14:08 ` Heiko Stübner -1 siblings, 1 reply; 7+ messages in thread From: Shawn Lin @ 2016-08-20 2:53 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: linux-kernel, linux-rockchip, Heiko Stuebner, Doug Anderson, Brian Norris, Wenrui Li, Rob Herring, devicetree, Shawn Lin This patch to add a generic PHY driver for rockchip PCIe PHY. Access the PHY via registers provided by GRF (general register files) module. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v5: - add COMPILE_TEST and select MFD_SYSCON on Kconfig Changes in v4: - remove laneoff symbol as we still fail to get a workable solution except for exporting symbol. But I will be back with some other possible routine once finished. Changes in v3: None Changes in v2: None drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-pcie.c | 357 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 366 insertions(+) create mode 100644 drivers/phy/phy-rockchip-pcie.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index f9bf981..46e5536 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -388,6 +388,14 @@ config PHY_ROCKCHIP_DP help Enable this to support the Rockchip Display Port PHY. +config PHY_ROCKCHIP_PCIE + tristate "Rockchip PCIe PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the Rockchip PCIe PHY. + config PHY_ST_SPEAR1310_MIPHY tristate "ST SPEAR1310-MIPHY driver" select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 74b44ef..ce0e526 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o +obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o diff --git a/drivers/phy/phy-rockchip-pcie.c b/drivers/phy/phy-rockchip-pcie.c new file mode 100644 index 0000000..63cd200 --- /dev/null +++ b/drivers/phy/phy-rockchip-pcie.c @@ -0,0 +1,357 @@ +/* + * Rockchip PCIe PHY driver + * + * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com> + * Copyright (C) 2016 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +/* + * The higher 16-bit of this register is used for write protection + * only if BIT(x + 16) set to 1 the BIT(x) can be written. + */ +#define HIWORD_UPDATE(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +#define PHY_MAX_LANE_NUM 4 +#define PHY_CFG_DATA_SHIFT 7 +#define PHY_CFG_ADDR_SHIFT 1 +#define PHY_CFG_DATA_MASK 0xf +#define PHY_CFG_ADDR_MASK 0x3f +#define PHY_CFG_RD_MASK 0x3ff +#define PHY_CFG_WR_ENABLE 1 +#define PHY_CFG_WR_DISABLE 1 +#define PHY_CFG_WR_SHIFT 0 +#define PHY_CFG_WR_MASK 1 +#define PHY_CFG_PLL_LOCK 0x10 +#define PHY_CFG_CLK_TEST 0x10 +#define PHY_CFG_CLK_SCC 0x12 +#define PHY_CFG_SEPE_RATE BIT(3) +#define PHY_CFG_PLL_100M BIT(3) +#define PHY_PLL_LOCKED BIT(9) +#define PHY_PLL_OUTPUT BIT(10) +#define PHY_LANE_A_STATUS 0x30 +#define PHY_LANE_B_STATUS 0x31 +#define PHY_LANE_C_STATUS 0x32 +#define PHY_LANE_D_STATUS 0x33 +#define PHY_LANE_RX_DET_SHIFT 11 +#define PHY_LANE_RX_DET_TH 0x1 +#define PHY_LANE_IDLE_OFF 0x1 +#define PHY_LANE_IDLE_MASK 0x1 +#define PHY_LANE_IDLE_A_SHIFT 3 +#define PHY_LANE_IDLE_B_SHIFT 4 +#define PHY_LANE_IDLE_C_SHIFT 5 +#define PHY_LANE_IDLE_D_SHIFT 6 + +struct rockchip_pcie_data { + unsigned int pcie_conf; + unsigned int pcie_status; + unsigned int pcie_laneoff; +}; + +struct rockchip_pcie_phy { + struct rockchip_pcie_data *phy_data; + struct regmap *reg_base; + struct reset_control *phy_rst; + struct clk *clk_pciephy_ref; +}; + +static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy, + u32 addr, u32 data) +{ + regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, + HIWORD_UPDATE(data, + PHY_CFG_DATA_MASK, + PHY_CFG_DATA_SHIFT) | + HIWORD_UPDATE(addr, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT)); + udelay(1); + regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, + HIWORD_UPDATE(PHY_CFG_WR_ENABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT)); + udelay(1); + regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, + HIWORD_UPDATE(PHY_CFG_WR_DISABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT)); +} + +static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy, + u32 addr) +{ + u32 val; + + regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, + HIWORD_UPDATE(addr, + PHY_CFG_RD_MASK, + PHY_CFG_ADDR_SHIFT)); + regmap_read(rk_phy->reg_base, + rk_phy->phy_data->pcie_status, + &val); + return val; +} + +static int rockchip_pcie_phy_power_off(struct phy *phy) +{ + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); + int err = 0; + + err = reset_control_assert(rk_phy->phy_rst); + if (err) { + pr_err("assert phy_rst err %d\n", err); + return err; + } + + return 0; +} + +static int rockchip_pcie_phy_power_on(struct phy *phy) +{ + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); + int err = 0; + u32 status; + unsigned long timeout; + + err = reset_control_deassert(rk_phy->phy_rst); + if (err) { + pr_err("deassert phy_rst err %d\n", err); + return err; + } + + regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, + HIWORD_UPDATE(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT)); + + /* + * No documented timeout value for phy operation below, + * so we make it large enough here. And we use loop-break + * method which should not be harmful. + */ + timeout = jiffies + msecs_to_jiffies(1000); + + err = -EINVAL; + while (time_before(jiffies, timeout)) { + regmap_read(rk_phy->reg_base, + rk_phy->phy_data->pcie_status, + &status); + if (status & PHY_PLL_LOCKED) { + pr_debug("pll locked!\n"); + err = 0; + break; + } + msleep(20); + } + + if (err) { + pr_err("pll lock timeout!\n"); + goto err_pll_lock; + } + + phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); + phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); + + err = -ETIMEDOUT; + while (time_before(jiffies, timeout)) { + regmap_read(rk_phy->reg_base, + rk_phy->phy_data->pcie_status, + &status); + if (!(status & PHY_PLL_OUTPUT)) { + pr_debug("pll output enable done!\n"); + err = 0; + break; + } + msleep(20); + } + + if (err) { + pr_err("pll output enable timeout!\n"); + goto err_pll_lock; + } + + regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, + HIWORD_UPDATE(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT)); + err = -EINVAL; + while (time_before(jiffies, timeout)) { + regmap_read(rk_phy->reg_base, + rk_phy->phy_data->pcie_status, + &status); + if (status & PHY_PLL_LOCKED) { + pr_debug("pll relocked!\n"); + err = 0; + break; + } + msleep(20); + } + + if (err) { + pr_err("pll relock timeout!\n"); + goto err_pll_lock; + } + + return 0; + +err_pll_lock: + reset_control_assert(rk_phy->phy_rst); + return err; +} + +static int rockchip_pcie_phy_init(struct phy *phy) +{ + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); + int err = 0; + + err = clk_prepare_enable(rk_phy->clk_pciephy_ref); + if (err) { + pr_err("Fail to enable pcie ref clock.\n"); + goto err_refclk; + } + + err = reset_control_assert(rk_phy->phy_rst); + if (err) { + pr_err("assert phy_rst err %d\n", err); + goto err_reset; + } + + return err; + +err_reset: + clk_disable_unprepare(rk_phy->clk_pciephy_ref); +err_refclk: + return err; +} + +static int rockchip_pcie_phy_exit(struct phy *phy) +{ + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); + int err = 0; + + clk_disable_unprepare(rk_phy->clk_pciephy_ref); + + err = reset_control_deassert(rk_phy->phy_rst); + if (err) { + pr_err("deassert phy_rst err %d\n", err); + goto err_reset; + } + + return err; + +err_reset: + clk_prepare_enable(rk_phy->clk_pciephy_ref); + return err; +} + +static const struct phy_ops ops = { + .init = rockchip_pcie_phy_init, + .exit = rockchip_pcie_phy_exit, + .power_on = rockchip_pcie_phy_power_on, + .power_off = rockchip_pcie_phy_power_off, + .owner = THIS_MODULE, +}; + +static const struct rockchip_pcie_data rk3399_pcie_data = { + .pcie_conf = 0xe220, + .pcie_status = 0xe2a4, + .pcie_laneoff = 0xe214, +}; + +static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { + { + .compatible = "rockchip,rk3399-pcie-phy", + .data = &rk3399_pcie_data, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); + +static int rockchip_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rockchip_pcie_phy *rk_phy; + struct phy *generic_phy; + struct phy_provider *phy_provider; + struct regmap *grf; + const struct of_device_id *of_id; + + grf = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(grf)) { + dev_err(dev, "Missing rockchip,grf property\n"); + return PTR_ERR(grf); + } + + rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); + if (!rk_phy) + return -ENOMEM; + + of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev); + if (!of_id) + return -EINVAL; + + rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data; + rk_phy->reg_base = grf; + + rk_phy->phy_rst = devm_reset_control_get(dev, "phy"); + if (IS_ERR(rk_phy->phy_rst)) { + if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER) + dev_err(dev, + "missing phy property for reset controller\n"); + return PTR_ERR(rk_phy->phy_rst); + } + + rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk"); + if (IS_ERR(rk_phy->clk_pciephy_ref)) { + dev_err(dev, "refclk not found.\n"); + return PTR_ERR(rk_phy->clk_pciephy_ref); + } + + generic_phy = devm_phy_create(dev, dev->of_node, &ops); + if (IS_ERR(generic_phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(generic_phy); + } + + phy_set_drvdata(generic_phy, rk_phy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver rockchip_pcie_driver = { + .probe = rockchip_pcie_phy_probe, + .driver = { + .name = "rockchip-pcie-phy", + .of_match_table = rockchip_pcie_phy_dt_ids, + }, +}; + +module_platform_driver(rockchip_pcie_driver); + +MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); +MODULE_DESCRIPTION("Rockchip PCIe PHY driver"); +MODULE_LICENSE("GPL v2"); -- 2.3.7 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY @ 2016-08-31 14:08 ` Heiko Stübner 0 siblings, 0 replies; 7+ messages in thread From: Heiko Stübner @ 2016-08-31 14:08 UTC (permalink / raw) To: Shawn Lin Cc: Kishon Vijay Abraham I, linux-kernel, linux-rockchip, Doug Anderson, Brian Norris, Wenrui Li, Rob Herring, devicetree Hi, Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin: > This patch to add a generic PHY driver for rockchip PCIe PHY. > Access the PHY via registers provided by GRF (general register > files) module. > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> seems I'm late to the party, but when looking if I can apply the pcie- devicetree patches, I found that the phy is still pending. Apart from some error-message nitpicks below, this looks ok to me. I don't know enough about the actual pci phy part though. Kishon, is this on your radar? [...] > +static int rockchip_pcie_phy_power_off(struct phy *phy) > +{ > + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); > + int err = 0; > + > + err = reset_control_assert(rk_phy->phy_rst); > + if (err) { > + pr_err("assert phy_rst err %d\n", err); dev_err(phy->dev, ...) probably the same for all other pr_err invocations > + return err; > + } > + > + return 0; > +} [...] > +static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { > + { > + .compatible = "rockchip,rk3399-pcie-phy", > + .data = &rk3399_pcie_data, > + }, > + {} > +}; > + > +MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); > + > +static int rockchip_pcie_phy_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rockchip_pcie_phy *rk_phy; > + struct phy *generic_phy; > + struct phy_provider *phy_provider; > + struct regmap *grf; > + const struct of_device_id *of_id; > + > + grf = syscon_node_to_regmap(dev->parent->of_node); > + if (IS_ERR(grf)) { > + dev_err(dev, "Missing rockchip,grf property\n"); dev_err(dev, "Cannot find GRF syscon\n"); Heiko ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY @ 2016-08-31 14:08 ` Heiko Stübner 0 siblings, 0 replies; 7+ messages in thread From: Heiko Stübner @ 2016-08-31 14:08 UTC (permalink / raw) To: Shawn Lin Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Wenrui Li, Brian Norris, Doug Anderson, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Kishon Vijay Abraham I Hi, Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin: > This patch to add a generic PHY driver for rockchip PCIe PHY. > Access the PHY via registers provided by GRF (general register > files) module. > > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> seems I'm late to the party, but when looking if I can apply the pcie- devicetree patches, I found that the phy is still pending. Apart from some error-message nitpicks below, this looks ok to me. I don't know enough about the actual pci phy part though. Kishon, is this on your radar? [...] > +static int rockchip_pcie_phy_power_off(struct phy *phy) > +{ > + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); > + int err = 0; > + > + err = reset_control_assert(rk_phy->phy_rst); > + if (err) { > + pr_err("assert phy_rst err %d\n", err); dev_err(phy->dev, ...) probably the same for all other pr_err invocations > + return err; > + } > + > + return 0; > +} [...] > +static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { > + { > + .compatible = "rockchip,rk3399-pcie-phy", > + .data = &rk3399_pcie_data, > + }, > + {} > +}; > + > +MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); > + > +static int rockchip_pcie_phy_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rockchip_pcie_phy *rk_phy; > + struct phy *generic_phy; > + struct phy_provider *phy_provider; > + struct regmap *grf; > + const struct of_device_id *of_id; > + > + grf = syscon_node_to_regmap(dev->parent->of_node); > + if (IS_ERR(grf)) { > + dev_err(dev, "Missing rockchip,grf property\n"); dev_err(dev, "Cannot find GRF syscon\n"); Heiko ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY 2016-08-31 14:08 ` Heiko Stübner @ 2016-09-01 5:05 ` Kishon Vijay Abraham I -1 siblings, 0 replies; 7+ messages in thread From: Kishon Vijay Abraham I @ 2016-09-01 5:05 UTC (permalink / raw) To: Heiko Stübner, Shawn Lin Cc: linux-kernel, linux-rockchip, Doug Anderson, Brian Norris, Wenrui Li, Rob Herring, devicetree On Wednesday 31 August 2016 07:38 PM, Heiko Stübner wrote: > Hi, > > Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin: >> This patch to add a generic PHY driver for rockchip PCIe PHY. >> Access the PHY via registers provided by GRF (general register >> files) module. >> >> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > seems I'm late to the party, but when looking if I can apply the pcie- > devicetree patches, I found that the phy is still pending. > > Apart from some error-message nitpicks below, this looks ok to me. I don't > know enough about the actual pci phy part though. > > Kishon, is this on your radar? yes.. can the nipicks be fixed and posted asap? Thanks Kishon > > [...] > >> +static int rockchip_pcie_phy_power_off(struct phy *phy) >> +{ >> + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); >> + int err = 0; >> + >> + err = reset_control_assert(rk_phy->phy_rst); >> + if (err) { >> + pr_err("assert phy_rst err %d\n", err); > > dev_err(phy->dev, ...) > > probably the same for all other pr_err invocations > > >> + return err; >> + } >> + >> + return 0; >> +} > > [...] > >> +static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { >> + { >> + .compatible = "rockchip,rk3399-pcie-phy", >> + .data = &rk3399_pcie_data, >> + }, >> + {} >> +}; >> + >> +MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); >> + >> +static int rockchip_pcie_phy_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + struct rockchip_pcie_phy *rk_phy; >> + struct phy *generic_phy; >> + struct phy_provider *phy_provider; >> + struct regmap *grf; >> + const struct of_device_id *of_id; >> + >> + grf = syscon_node_to_regmap(dev->parent->of_node); >> + if (IS_ERR(grf)) { >> + dev_err(dev, "Missing rockchip,grf property\n"); > > dev_err(dev, "Cannot find GRF syscon\n"); > > > Heiko > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY @ 2016-09-01 5:05 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 7+ messages in thread From: Kishon Vijay Abraham I @ 2016-09-01 5:05 UTC (permalink / raw) To: Heiko Stübner, Shawn Lin Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Wenrui Li, Brian Norris, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Doug Anderson, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring On Wednesday 31 August 2016 07:38 PM, Heiko Stübner wrote: > Hi, > > Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin: >> This patch to add a generic PHY driver for rockchip PCIe PHY. >> Access the PHY via registers provided by GRF (general register >> files) module. >> >> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > seems I'm late to the party, but when looking if I can apply the pcie- > devicetree patches, I found that the phy is still pending. > > Apart from some error-message nitpicks below, this looks ok to me. I don't > know enough about the actual pci phy part though. > > Kishon, is this on your radar? yes.. can the nipicks be fixed and posted asap? Thanks Kishon > > [...] > >> +static int rockchip_pcie_phy_power_off(struct phy *phy) >> +{ >> + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); >> + int err = 0; >> + >> + err = reset_control_assert(rk_phy->phy_rst); >> + if (err) { >> + pr_err("assert phy_rst err %d\n", err); > > dev_err(phy->dev, ...) > > probably the same for all other pr_err invocations > > >> + return err; >> + } >> + >> + return 0; >> +} > > [...] > >> +static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { >> + { >> + .compatible = "rockchip,rk3399-pcie-phy", >> + .data = &rk3399_pcie_data, >> + }, >> + {} >> +}; >> + >> +MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); >> + >> +static int rockchip_pcie_phy_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + struct rockchip_pcie_phy *rk_phy; >> + struct phy *generic_phy; >> + struct phy_provider *phy_provider; >> + struct regmap *grf; >> + const struct of_device_id *of_id; >> + >> + grf = syscon_node_to_regmap(dev->parent->of_node); >> + if (IS_ERR(grf)) { >> + dev_err(dev, "Missing rockchip,grf property\n"); > > dev_err(dev, "Cannot find GRF syscon\n"); > > > Heiko > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-09-01 5:05 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-08-20 2:53 [PATCH v5 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Shawn Lin 2016-08-20 2:53 ` Shawn Lin 2016-08-20 2:53 ` [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal " Shawn Lin 2016-08-31 14:08 ` Heiko Stübner 2016-08-31 14:08 ` Heiko Stübner 2016-09-01 5:05 ` Kishon Vijay Abraham I 2016-09-01 5:05 ` Kishon Vijay Abraham I
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