* [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
@ 2016-08-29 3:20 Fabio Estevam
2016-08-29 5:32 ` Peng Fan
2016-08-29 11:58 ` Fabio Estevam
0 siblings, 2 replies; 7+ messages in thread
From: Fabio Estevam @ 2016-08-29 3:20 UTC (permalink / raw)
To: u-boot
From: Fabio Estevam <fabio.estevam@nxp.com>
When running NXP 4.1 kernel with U-Boot mainline we observe a
hang when going into the lowest operational point of cpufreq.
Comparing the DDR calibration values against NXP U-Boot showed
that the values were incorrect.
Adjust the calibration values so that we can avoid such system hang.
Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index c213861..77c561d 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -784,10 +784,10 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00070007,
- .p0_mpdgctrl0 = 0x41490145,
- .p0_mprddlctl = 0x40404546,
- .p0_mpwrdlctl = 0x4040524D,
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x41570155,
+ .p0_mprddlctl = 0x4040474A,
+ .p0_mpwrdlctl = 0x40405550,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
2016-08-29 3:20 [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values Fabio Estevam
@ 2016-08-29 5:32 ` Peng Fan
2016-08-29 11:58 ` Fabio Estevam
1 sibling, 0 replies; 7+ messages in thread
From: Peng Fan @ 2016-08-29 5:32 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On Mon, Aug 29, 2016 at 12:20:12AM -0300, Fabio Estevam wrote:
>From: Fabio Estevam <fabio.estevam@nxp.com>
>
>When running NXP 4.1 kernel with U-Boot mainline we observe a
>hang when going into the lowest operational point of cpufreq.
>
>Comparing the DDR calibration values against NXP U-Boot showed
>that the values were incorrect.
>
>Adjust the calibration values so that we can avoid such system hang.
>
>Reported-by: Eric Nelson <eric@nelint.com>
>Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Thanks,
Peng.
>---
> board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
>diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>index c213861..77c561d 100644
>--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>@@ -784,10 +784,10 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
> };
>
> static struct mx6_mmdc_calibration mx6_mmcd_calib = {
>- .p0_mpwldectrl0 = 0x00070007,
>- .p0_mpdgctrl0 = 0x41490145,
>- .p0_mprddlctl = 0x40404546,
>- .p0_mpwrdlctl = 0x4040524D,
>+ .p0_mpwldectrl0 = 0x00000000,
>+ .p0_mpdgctrl0 = 0x41570155,
>+ .p0_mprddlctl = 0x4040474A,
>+ .p0_mpwrdlctl = 0x40405550,
> };
>
> struct mx6_ddr_sysinfo ddr_sysinfo = {
>--
>2.7.4
>
>_______________________________________________
>U-Boot mailing list
>U-Boot at lists.denx.de
>http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
2016-08-29 3:20 [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values Fabio Estevam
2016-08-29 5:32 ` Peng Fan
@ 2016-08-29 11:58 ` Fabio Estevam
2016-08-29 17:00 ` Eric Nelson
1 sibling, 1 reply; 7+ messages in thread
From: Fabio Estevam @ 2016-08-29 11:58 UTC (permalink / raw)
To: u-boot
Hi Eric,
On Mon, Aug 29, 2016 at 12:20 AM, Fabio Estevam <festevam@gmail.com> wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> When running NXP 4.1 kernel with U-Boot mainline we observe a
> hang when going into the lowest operational point of cpufreq.
>
> Comparing the DDR calibration values against NXP U-Boot showed
> that the values were incorrect.
>
> Adjust the calibration values so that we can avoid such system hang.
>
> Reported-by: Eric Nelson <eric@nelint.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
After running more tests I still get the hang sometimes, so we still
need to review the DDR SPL settings.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
2016-08-29 11:58 ` Fabio Estevam
@ 2016-08-29 17:00 ` Eric Nelson
2016-08-29 17:14 ` Eric Nelson
0 siblings, 1 reply; 7+ messages in thread
From: Eric Nelson @ 2016-08-29 17:00 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On 08/29/2016 04:58 AM, Fabio Estevam wrote:
> Hi Eric,
>
> On Mon, Aug 29, 2016 at 12:20 AM, Fabio Estevam <festevam@gmail.com> wrote:
>> From: Fabio Estevam <fabio.estevam@nxp.com>
>>
>> When running NXP 4.1 kernel with U-Boot mainline we observe a
>> hang when going into the lowest operational point of cpufreq.
>>
>> Comparing the DDR calibration values against NXP U-Boot showed
>> that the values were incorrect.
>>
>> Adjust the calibration values so that we can avoid such system hang.
>>
>> Reported-by: Eric Nelson <eric@nelint.com>
>> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
>
> After running more tests I still get the hang sometimes, so we still
> need to review the DDR SPL settings.
>
> Regards,
>
> Fabio Estevam
>
I just test this patch against imx/master and I'm still seeing the
issue:
root at imx6ulevk:~#
Bus freq set to 24000000 start...
Do you have kernel debug messages enabled so you can see the bus
frequency change?
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
2016-08-29 17:00 ` Eric Nelson
@ 2016-08-29 17:14 ` Eric Nelson
2016-08-29 18:06 ` Fabio Estevam
0 siblings, 1 reply; 7+ messages in thread
From: Eric Nelson @ 2016-08-29 17:14 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On 08/29/2016 10:00 AM, Eric Nelson wrote:
> On 08/29/2016 04:58 AM, Fabio Estevam wrote:
>> On Mon, Aug 29, 2016 at 12:20 AM, Fabio Estevam <festevam@gmail.com> wrote:
>>> From: Fabio Estevam <fabio.estevam@nxp.com>
>>>
>>> When running NXP 4.1 kernel with U-Boot mainline we observe a
>>> hang when going into the lowest operational point of cpufreq.
>>>
>>> Comparing the DDR calibration values against NXP U-Boot showed
>>> that the values were incorrect.
>>>
>>> Adjust the calibration values so that we can avoid such system hang.
>>>
>>> Reported-by: Eric Nelson <eric@nelint.com>
>>> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
>>
>> After running more tests I still get the hang sometimes, so we still
>> need to review the DDR SPL settings.
>>
>> Regards,
>>
>> Fabio Estevam
>>
>
> I just test this patch against imx/master and I'm still seeing the
> issue:
>
> root at imx6ulevk:~#
> Bus freq set to 24000000 start...
>
> Do you have kernel debug messages enabled so you can see the bus
> frequency change?
>
Things are working well using your config patch:
http://pastebin.com/crAe1Yr1
root at imx6ulevk:~#
Bus freq set to 24000000 start...
Bus freq set to 24000000 done!
root at imx6ulevk:~#
root at imx6ulevk:~#
Bus freq set to 400000000 start...
Bus freq set to 400000000 done!
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
2016-08-29 17:14 ` Eric Nelson
@ 2016-08-29 18:06 ` Fabio Estevam
2016-08-29 18:51 ` Eric Nelson
0 siblings, 1 reply; 7+ messages in thread
From: Fabio Estevam @ 2016-08-29 18:06 UTC (permalink / raw)
To: u-boot
Hi Eric,
On Mon, Aug 29, 2016 at 2:14 PM, Eric Nelson <eric@nelint.com> wrote:
> Things are working well using your config patch:
> http://pastebin.com/crAe1Yr1
Please test this one:
http://lists.denx.de/pipermail/u-boot/2016-August/265131.html
Thanks
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
2016-08-29 18:06 ` Fabio Estevam
@ 2016-08-29 18:51 ` Eric Nelson
0 siblings, 0 replies; 7+ messages in thread
From: Eric Nelson @ 2016-08-29 18:51 UTC (permalink / raw)
To: u-boot
Thanks very much for your efforts Fabio,
On 08/29/2016 11:06 AM, Fabio Estevam wrote:
> Hi Eric,
>
> On Mon, Aug 29, 2016 at 2:14 PM, Eric Nelson <eric@nelint.com> wrote:
>
>> Things are working well using your config patch:
>> http://pastebin.com/crAe1Yr1
>
> Please test this one:
> http://lists.denx.de/pipermail/u-boot/2016-August/265131.html
>
I did and it fixes the problem.
I sent a review with some concerns about why and how, but
patch 1/3 confirmed that the problem doesn't stem from calibration.
This is good, because I originally found the problem on a custom
board that had pristine calibration values which survived multiple
overnight stress tests (using the stress tool and Linux).
Regards,
Eric
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-08-29 18:51 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-29 3:20 [U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values Fabio Estevam
2016-08-29 5:32 ` Peng Fan
2016-08-29 11:58 ` Fabio Estevam
2016-08-29 17:00 ` Eric Nelson
2016-08-29 17:14 ` Eric Nelson
2016-08-29 18:06 ` Fabio Estevam
2016-08-29 18:51 ` Eric Nelson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.