[PATCH 00/14] drm/amdgpu/si: Make SI DPM workable

[PATCH 00/14] drm/amdgpu/si: Make SI DPM workable

[Huang Rui]

Hi all,

These patchest resolve the DPM issues of SI.
SI DPM doesn't work since it implemented, the following patches fixes
serival issues to make SI DPM workable now.

Patch 1 -> 3: Add firmware version for checking firmware loading via
sysfs.

Patch 4 -> 5: Refine the codes for si dpm.

Patch 6 -> 13: Fix the issues which impact DPM functionality.

Patch 14: Enable SI DPM by default.

Thanks,
Rui

Huang Rui (14):
  drm/amdgpu: add gfx v6 firmware versions for sysfs dump
  drm/amdgpu: add gmc v6 firmware versions for sysfs dump
  drm/amdgpu/si: add SI smc firmware versions for sysfs dump
  drm/amdgpu: remove useless functions of si dpm
  drm/amdgpu: use DRM print instead of printk
  drm/amdgpu: fix oland and hainan asic specific handle at
    si_program_aspm
  drm/amdgpu/si: fix the dce6 for si macro
  drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
  drm/amdgpu: fix to miss adding thermal controller
  drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag
  drm/amdgpu: fix incorrect index of CG_FFCT_0 register
  drm/amdgpu: introduce pcie port read/write entry
  drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
  drm/amdgpu/si: enable SI DPM by default

 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         |  14 ++++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |   2 +
 drivers/gpu/drm/amd/amdgpu/si.c               | 112 ++++++++++++++------------
 drivers/gpu/drm/amd/amdgpu/si_dpm.c           |  54 +++++++++----
 drivers/gpu/drm/amd/amdgpu/si_smc.c           |   1 +
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   6 +-
 8 files changed, 124 insertions(+), 71 deletions(-)

-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 01/14] drm/amdgpu: add gfx v6 firmware versions for sysfs dump

[Huang Rui]

Change-Id: I4af15bca9b20190803411afcd8711c10ec25ac56
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index f3ad4aa..17a560c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -298,6 +298,8 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	const char *chip_name;
 	char fw_name[30];
 	int err;
+	const struct gfx_firmware_header_v1_0 *cp_hdr;
+	const struct rlc_firmware_header_v1_0 *rlc_hdr;
 
 	DRM_DEBUG("\n");
 
@@ -327,6 +329,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
 	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
@@ -335,6 +340,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
 	snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
@@ -343,12 +351,18 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
 	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 	if (err)
 		goto out;
 	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+	rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
+	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 
 out:
 	if (err) {
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 02/14] drm/amdgpu: add gmc v6 firmware versions for sysfs dump

[Huang Rui]

Change-Id: I33269be5fb6e877e0b85e168aa7e122e9d197721
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index c18a4ef..1d2952b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -149,6 +149,8 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 	hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 
 	amdgpu_ucode_print_mc_hdr(&hdr->header);
+
+	adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 	new_io_mc_regs = (const __le32 *)
 		(adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 03/14] drm/amdgpu/si: add SI smc firmware versions for sysfs dump

[Huang Rui]

Change-Id: I7953f8e2b0722d5ed0209a8171418ca7644de2ee
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_smc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_smc.c b/drivers/gpu/drm/amd/amdgpu/si_smc.c
index 214f37c..c1c2594 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_smc.c
@@ -224,6 +224,7 @@ int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
 
 	amdgpu_ucode_print_smc_hdr(&hdr->header);
 
+	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 	ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
 	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 	src = (const u8 *)
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 04/14] drm/amdgpu: remove useless functions of si dpm

[Huang Rui]

Change-Id: Ie5f078079d6732cb875f31c9eb62a045f3cc40f3
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 076f6cd..b06c583 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -1828,9 +1828,6 @@ struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
 struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
 struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
 
-extern int si_mc_load_microcode(struct amdgpu_device *adev);
-extern void vce_v1_0_enable_mgcg(struct amdgpu_device *adev, bool enable);
-
 static int si_populate_voltage_value(struct amdgpu_device *adev,
 				     const struct atom_voltage_table *table,
 				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 05/14] drm/amdgpu: use DRM print instead of printk

[Huang Rui]

Change-Id: I51756925d16d02a67440787d05742a6877a507d7
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index b06c583..1764c0b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7720,9 +7720,8 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev)
 
 out:
 	if (err) {
-		printk(KERN_ERR
-		       "si_smc: Failed to load firmware. err = %d\"%s\"\n",
-		       err, fw_name);
+		DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
+			  err, fw_name);
 		release_firmware(adev->pm.fw);
 		adev->pm.fw = NULL;
 	}
@@ -7941,15 +7940,15 @@ static void si_dpm_print_power_state(struct amdgpu_device *adev,
                                
         amdgpu_dpm_print_class_info(rps->class, rps->class2);
         amdgpu_dpm_print_cap_info(rps->caps);
-        printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+        DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
         for (i = 0; i < ps->performance_level_count; i++) {
                 pl = &ps->performance_levels[i];
                 if (adev->asic_type >= CHIP_TAHITI)
-                        printk("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
-                               i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
+                        DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
+				 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
                 else
-                        printk("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
-                               i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+                        DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
+				 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
         }
         amdgpu_dpm_print_ps_status(adev, rps);
 }
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 06/14] drm/amdgpu: fix oland and hainan asic specific handle at si_program_aspm

[Huang Rui]

Change-Id: Icaca76072003f99c1789937110161b3ef0feab51
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index d2309b7..d5fc197 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1602,7 +1602,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
 			if (orig != data)
 				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-			{
+			if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
 				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
 				data &= ~PLL_RAMP_UP_TIME_0_MASK;
 				if (orig != data)
@@ -1651,11 +1651,15 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
 			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
+			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
+				data |= LS2_EXIT_TIME(5);
 			if (orig != data)
 				si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
 			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
+			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
+				data |= LS2_EXIT_TIME(5);
 			if (orig != data)
 				si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
 
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro

[Huang Rui]

Change-Id: I3e5f42158c57d1ec722f713b129189bc5f802b11
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
index 9609199..ced0390 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
@@ -1968,7 +1968,11 @@
 #define AMDGPU_MM_INDEX		        0x0000
 #define AMDGPU_MM_DATA		        0x0001
 
-#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE))
+#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE)    || \
+			    (adev->asic_type == CHIP_TAHITI)   || \
+			    (adev->asic_type == CHIP_PITCAIRN) || \
+			    (adev->asic_type == CHIP_OLAND))
+
 #define VERDE_NUM_CRTC 6
 #define	BLACKOUT_MODE_MASK			0x00000007
 #define	VGA_RENDER_CONTROL			0xC0
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 08/14] drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field

[Huang Rui]

Change-Id: Ib5b6146fa712192dec120702831252d9221335bb
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 1764c0b..90842c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4173,7 +4173,13 @@ static void si_program_response_times(struct amdgpu_device *adev)
 static void si_program_ds_registers(struct amdgpu_device *adev)
 {
 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
-	u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
+	u32 tmp;
+
+	/* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
+	if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
+		tmp = 0x10;
+	else
+		tmp = 0x1;
 
 	if (eg_pi->sclk_deep_sleep) {
 		WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 09/14] drm/amdgpu: fix to miss adding thermal controller

[Huang Rui]

Thermal controller isn't inited during si dpm sw_init phase.

Change-Id: Ie9ddcd7026067e19bb0e300cf85c79948e7275a9
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 90842c0..5f1e5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7281,6 +7281,8 @@ static int si_parse_power_table(struct amdgpu_device *adev)
 		return -EINVAL;
 	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
 
+	amdgpu_add_thermal_controller(adev);
+
 	state_array = (struct _StateArray *)
 		(mode_info->atom_context->bios + data_offset +
 		 le16_to_cpu(power_info->pplib.usStateArrayOffset));
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

[Huang Rui]

Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
used on the whole si dpm part.

Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 5f1e5fe..563aeea 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
 	}
 }
 
+void rv770_get_memory_type(struct amdgpu_device *adev)
+{
+	struct rv7xx_power_info *pi = rv770_get_pi(adev);
+	u32 tmp;
+
+	tmp = RREG32(MC_SEQ_MISC0);
+
+	if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
+	    MC_SEQ_MISC0_GDDR5_VALUE)
+		pi->mem_gddr5 = true;
+	else
+		pi->mem_gddr5 = false;
+
+}
+
 static void si_dpm_setup_asic(struct amdgpu_device *adev)
 {
+	rv770_get_memory_type(adev);
 	si_read_clock_registers(adev);
 	si_enable_acpi_power_management(adev);
 }
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 11/14] drm/amdgpu: fix incorrect index of CG_FFCT_0 register

[Huang Rui]

Change-Id: I8b1c7618b3043595c1f6d369dca693d4eaac412e
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 563aeea..ce563cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4281,7 +4281,7 @@ static void si_program_tp(struct amdgpu_device *adev)
 	enum r600_td td = R600_TD_DFLT;
 
 	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
-		WREG32(CG_FFCT_0 + (i * 10), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
+		WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
 
 	if (td == R600_TD_AUTO)
 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 12/14] drm/amdgpu: introduce pcie port read/write entry

[Huang Rui]

This patch adds pcie port read/write entry, because it will be also
used on si dpm part.

Change-Id: Id8a3cf57233ac807c2e5a37fe1d310e2874b0814
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |   4 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/si.c            | 106 +++++++++++++++--------------
 3 files changed, 60 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 19c9a2e..6eb1d3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2043,6 +2043,8 @@ struct amdgpu_device {
 	spinlock_t pcie_idx_lock;
 	amdgpu_rreg_t			pcie_rreg;
 	amdgpu_wreg_t			pcie_wreg;
+	amdgpu_rreg_t			pciep_rreg;
+	amdgpu_wreg_t			pciep_wreg;
 	/* protects concurrent UVD register access */
 	spinlock_t uvd_ctx_idx_lock;
 	amdgpu_rreg_t			uvd_ctx_rreg;
@@ -2183,6 +2185,8 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
+#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
+#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8eb5396..a20a2b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1544,6 +1544,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	adev->smc_wreg = &amdgpu_invalid_wreg;
 	adev->pcie_rreg = &amdgpu_invalid_rreg;
 	adev->pcie_wreg = &amdgpu_invalid_wreg;
+	adev->pciep_rreg = &amdgpu_invalid_rreg;
+	adev->pciep_wreg = &amdgpu_invalid_wreg;
 	adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
 	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
 	adev->didt_rreg = &amdgpu_invalid_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index d5fc197..fee76b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -905,6 +905,31 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 }
 
+u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
+{
+	unsigned long flags;
+	u32 r;
+
+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+	(void)RREG32(PCIE_PORT_INDEX);
+	r = RREG32(PCIE_PORT_DATA);
+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+	return r;
+}
+
+void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+	(void)RREG32(PCIE_PORT_INDEX);
+	WREG32(PCIE_PORT_DATA, (v));
+	(void)RREG32(PCIE_PORT_DATA);
+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 {
 	unsigned long flags;
@@ -1125,6 +1150,8 @@ static int si_common_early_init(void *handle)
 	adev->smc_wreg = &si_smc_wreg;
 	adev->pcie_rreg = &si_pcie_rreg;
 	adev->pcie_wreg = &si_pcie_wreg;
+	adev->pciep_rreg = &si_pciep_rreg;
+	adev->pciep_wreg = &si_pciep_wreg;
 	adev->uvd_ctx_rreg = NULL;
 	adev->uvd_ctx_wreg = NULL;
 	adev->didt_rreg = NULL;
@@ -1316,31 +1343,6 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
 	}
 }
 
-u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
-{
-	unsigned long flags;
-	u32 r;
-
-	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
-	(void)RREG32(PCIE_PORT_INDEX);
-	r = RREG32(PCIE_PORT_DATA);
-	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
-	return r;
-}
-
-void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
-	(void)RREG32(PCIE_PORT_INDEX);
-	WREG32(PCIE_PORT_DATA, (v));
-	(void)RREG32(PCIE_PORT_DATA);
-	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
-}
-
 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 {
 	struct pci_dev *root = adev->pdev->bus->self;
@@ -1365,7 +1367,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
 		return;
 
-	speed_cntl = si_pciep_rreg(adev,PCIE_LC_SPEED_CNTL);
+	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 	current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
 		LC_CURRENT_DATA_RATE_SHIFT;
 	if (mask & DRM_PCIE_SPEED_80) {
@@ -1410,12 +1412,12 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 			current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
 
 			if (current_lw < max_lw) {
-				tmp = si_pciep_rreg(adev, PCIE_LC_LINK_WIDTH_CNTL);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
 				if (tmp & LC_RENEGOTIATION_SUPPORT) {
 					tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
 					tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
 					tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
-					si_pciep_wreg(adev, PCIE_LC_LINK_WIDTH_CNTL, tmp);
+					WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
 				}
 			}
 
@@ -1430,13 +1432,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
 
-				tmp = si_pciep_rreg(adev, PCIE_LC_CNTL4);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
 				tmp |= LC_SET_QUIESCE;
-				si_pciep_wreg(adev,PCIE_LC_CNTL4, tmp);
+				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
 
-				tmp = si_pciep_rreg(adev, PCIE_LC_CNTL4);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
 				tmp |= LC_REDO_EQ;
-				si_pciep_wreg(adev, PCIE_LC_CNTL4, tmp);
+				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
 
 				mdelay(100);
 
@@ -1460,16 +1462,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
-				tmp = si_pciep_rreg(adev, PCIE_LC_CNTL4);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
 				tmp &= ~LC_SET_QUIESCE;
-				si_pciep_wreg(adev, PCIE_LC_CNTL4, tmp);
+				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
 			}
 		}
 	}
 
 	speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
 	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
-	si_pciep_wreg(adev, PCIE_LC_SPEED_CNTL, speed_cntl);
+	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
 	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
 	tmp16 &= ~0xf;
@@ -1481,12 +1483,12 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 		tmp16 |= 1;
 	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
-	speed_cntl = si_pciep_rreg(adev, PCIE_LC_SPEED_CNTL);
+	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
-	si_pciep_wreg(adev, PCIE_LC_SPEED_CNTL, speed_cntl);
+	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
 	for (i = 0; i < adev->usec_timeout; i++) {
-		speed_cntl = si_pciep_rreg(adev, PCIE_LC_SPEED_CNTL);
+		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 		if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
 			break;
 		udelay(1);
@@ -1547,23 +1549,23 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
 	if (adev->flags & AMD_IS_APU)
 		return;
-	orig = data = si_pciep_rreg(adev, PCIE_LC_N_FTS_CNTL);
+	orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
 	data &= ~LC_XMIT_N_FTS_MASK;
 	data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
 	if (orig != data)
-		si_pciep_wreg(adev, PCIE_LC_N_FTS_CNTL, data);
+		WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
 
-	orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL3);
+	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
 	data |= LC_GO_TO_RECOVERY;
 	if (orig != data)
-		si_pciep_wreg(adev, PCIE_LC_CNTL3, data);
+		WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
 
 	orig = data = RREG32_PCIE(PCIE_P_CNTL);
 	data |= P_IGNORE_EDB_ERR;
 	if (orig != data)
 		WREG32_PCIE(PCIE_P_CNTL, data);
 
-	orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL);
+	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
 	data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
 	data |= LC_PMI_TO_L1_DIS;
 	if (!disable_l0s)
@@ -1573,7 +1575,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
 		data |= LC_L1_INACTIVITY(7);
 		data &= ~LC_PMI_TO_L1_DIS;
 		if (orig != data)
-			si_pciep_wreg(adev, PCIE_LC_CNTL, data);
+			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
 
 		if (!disable_plloff_in_l1) {
 			bool clk_req_support;
@@ -1643,11 +1645,11 @@ static void si_program_aspm(struct amdgpu_device *adev)
 				if (orig != data)
 					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
 			}
-			orig = data = si_pciep_rreg(adev, PCIE_LC_LINK_WIDTH_CNTL);
+			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
 			data &= ~LC_DYN_LANES_PWR_STATE_MASK;
 			data |= LC_DYN_LANES_PWR_STATE(3);
 			if (orig != data)
-				si_pciep_wreg(adev, PCIE_LC_LINK_WIDTH_CNTL, data);
+				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
 
 			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
@@ -1677,10 +1679,10 @@ static void si_program_aspm(struct amdgpu_device *adev)
 			}
 
 			if (clk_req_support) {
-				orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL2);
+				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
 				data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
 				if (orig != data)
-					si_pciep_wreg(adev, PCIE_LC_CNTL2, data);
+					WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
 
 				orig = data = RREG32(THM_CLK_CNTL);
 				data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
@@ -1718,7 +1720,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
 		}
 	} else {
 		if (orig != data)
-			si_pciep_wreg(adev, PCIE_LC_CNTL, data);
+			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
 	}
 
 	orig = data = RREG32_PCIE(PCIE_CNTL2);
@@ -1727,14 +1729,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
 		WREG32_PCIE(PCIE_CNTL2, data);
 
 	if (!disable_l0s) {
-		data = si_pciep_rreg(adev, PCIE_LC_N_FTS_CNTL);
+		data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
 		if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
 			data = RREG32_PCIE(PCIE_LC_STATUS1);
 			if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
-				orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL);
+				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
 				data &= ~LC_L0S_INACTIVITY_MASK;
 				if (orig != data)
-					si_pciep_wreg(adev, PCIE_LC_CNTL, data);
+					WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
 			}
 		}
 	}
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 13/14] drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed

[Huang Rui]

Change-Id: I7379d073c0e8123444deed9a91564de17b3fb722
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ce563cb..9b7d4bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -6242,7 +6242,7 @@ static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
 {
 	u32 speed_cntl;
 
-	speed_cntl = RREG32_PCIE(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
+	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
 	speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
 
 	return (u16)speed_cntl;
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 14/14] drm/amdgpu/si: enable SI DPM by default

[Huang Rui]

SI DPM issue is fixed, so enable it by default.

Change-Id: Ib12a81018a5fc43e9ac2920b8d4051dbe463f9df
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 9b7d4bf..9064e98 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7649,7 +7649,7 @@ static int si_dpm_late_init(void *handle)
 	int ret;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (amdgpu_dpm <= 0)
+	if (!amdgpu_dpm)
 		return 0;
 
 	/* init the sysfs and debugfs files late */
@@ -7776,7 +7776,7 @@ static int si_dpm_sw_init(void *handle)
 	adev->pm.current_mclk = adev->clock.default_mclk;
 	adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 
-	if (amdgpu_dpm <= 0)
+	if (!amdgpu_dpm)
 		return 0;
 
 	ret = si_dpm_init_microcode(adev);
@@ -7821,7 +7821,7 @@ static int si_dpm_hw_init(void *handle)
 
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (amdgpu_dpm <= 0)
+	if (!amdgpu_dpm)
 		return 0;
 
 	mutex_lock(&adev->pm.mutex);
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 00/14] drm/amdgpu/si: Make SI DPM workable

[Christian König]

For patch #4:
> drm/amdgpu: remove useless functions of si dpm
Maybe call that "remove unused function forward define".

And in general patches should at least have a commit message and not 
just subject. A simple one liner like "The functions don't exists any 
more." should be sufficient in this case.

Patch #10:

Well we probably shouldn't call those functions rv770_* any more.

Apart from that the patches look good to me, but since I'm clearly not 
the DPM expert they are Acked-by: Christian König 
<christian.koenig@amd.com>.

Regards,
Christian.

Am 30.08.2016 um 13:49 schrieb Huang Rui:
> Hi all,
>
> These patchest resolve the DPM issues of SI.
> SI DPM doesn't work since it implemented, the following patches fixes
> serival issues to make SI DPM workable now.
>
> Patch 1 -> 3: Add firmware version for checking firmware loading via
> sysfs.
>
> Patch 4 -> 5: Refine the codes for si dpm.
>
> Patch 6 -> 13: Fix the issues which impact DPM functionality.
>
> Patch 14: Enable SI DPM by default.
>
> Thanks,
> Rui
>
> Huang Rui (14):
>    drm/amdgpu: add gfx v6 firmware versions for sysfs dump
>    drm/amdgpu: add gmc v6 firmware versions for sysfs dump
>    drm/amdgpu/si: add SI smc firmware versions for sysfs dump
>    drm/amdgpu: remove useless functions of si dpm
>    drm/amdgpu: use DRM print instead of printk
>    drm/amdgpu: fix oland and hainan asic specific handle at
>      si_program_aspm
>    drm/amdgpu/si: fix the dce6 for si macro
>    drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
>    drm/amdgpu: fix to miss adding thermal controller
>    drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag
>    drm/amdgpu: fix incorrect index of CG_FFCT_0 register
>    drm/amdgpu: introduce pcie port read/write entry
>    drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
>    drm/amdgpu/si: enable SI DPM by default
>
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   2 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         |  14 ++++
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |   2 +
>   drivers/gpu/drm/amd/amdgpu/si.c               | 112 ++++++++++++++------------
>   drivers/gpu/drm/amd/amdgpu/si_dpm.c           |  54 +++++++++----
>   drivers/gpu/drm/amd/amdgpu/si_smc.c           |   1 +
>   drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   6 +-
>   8 files changed, 124 insertions(+), 71 deletions(-)
>

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 7:50 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> Subject: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro
> 
> Change-Id: I3e5f42158c57d1ec722f713b129189bc5f802b11
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> index 9609199..ced0390 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> @@ -1968,7 +1968,11 @@
>  #define AMDGPU_MM_INDEX		        0x0000
>  #define AMDGPU_MM_DATA		        0x0001
> 
> -#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE))
> +#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE)    || \
> +			    (adev->asic_type == CHIP_TAHITI)   || \
> +			    (adev->asic_type == CHIP_PITCAIRN) || \
> +			    (adev->asic_type == CHIP_OLAND))
> +

Let's just drop this macro and check the asic types explicitly.

Alex

>  #define VERDE_NUM_CRTC 6
>  #define	BLACKOUT_MODE_MASK			0x00000007
>  #define	VGA_RENDER_CONTROL			0xC0
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 7:50 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set
> the GDDR5 flag
> 
> Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
> used on the whole si dpm part.
> 
> Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> index 5f1e5fe..563aeea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> @@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct
> amdgpu_device *adev,
>  	}
>  }
> 
> +void rv770_get_memory_type(struct amdgpu_device *adev)

adev->mc.vram_type should be set in the gmc module.  Use that instead of pi->mem_gddr5.  See ci_dpm.c for example.

Alex

> +{
> +	struct rv7xx_power_info *pi = rv770_get_pi(adev);
> +	u32 tmp;
> +
> +	tmp = RREG32(MC_SEQ_MISC0);
> +
> +	if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >>
> MC_SEQ_MISC0_GDDR5_SHIFT) ==
> +	    MC_SEQ_MISC0_GDDR5_VALUE)
> +		pi->mem_gddr5 = true;
> +	else
> +		pi->mem_gddr5 = false;
> +
> +}
> +
>  static void si_dpm_setup_asic(struct amdgpu_device *adev)
>  {
> +	rv770_get_memory_type(adev);
>  	si_read_clock_registers(adev);
>  	si_enable_acpi_power_management(adev);
>  }
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 00/14] drm/amdgpu/si: Make SI DPM workable

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 7:50 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> Subject: [PATCH 00/14] drm/amdgpu/si: Make SI DPM workable
> 
> Hi all,
> 
> These patchest resolve the DPM issues of SI.
> SI DPM doesn't work since it implemented, the following patches fixes
> serival issues to make SI DPM workable now.
> 
> Patch 1 -> 3: Add firmware version for checking firmware loading via
> sysfs.
> 
> Patch 4 -> 5: Refine the codes for si dpm.
> 
> Patch 6 -> 13: Fix the issues which impact DPM functionality.
> 
> Patch 14: Enable SI DPM by default.

A few comments on patches 7 and 10.  The rest are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> 
> Thanks,
> Rui
> 
> Huang Rui (14):
>   drm/amdgpu: add gfx v6 firmware versions for sysfs dump
>   drm/amdgpu: add gmc v6 firmware versions for sysfs dump
>   drm/amdgpu/si: add SI smc firmware versions for sysfs dump
>   drm/amdgpu: remove useless functions of si dpm
>   drm/amdgpu: use DRM print instead of printk
>   drm/amdgpu: fix oland and hainan asic specific handle at
>     si_program_aspm
>   drm/amdgpu/si: fix the dce6 for si macro
>   drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
>   drm/amdgpu: fix to miss adding thermal controller
>   drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag
>   drm/amdgpu: fix incorrect index of CG_FFCT_0 register
>   drm/amdgpu: introduce pcie port read/write entry
>   drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
>   drm/amdgpu/si: enable SI DPM by default
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   2 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         |  14 ++++
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |   2 +
>  drivers/gpu/drm/amd/amdgpu/si.c               | 112 ++++++++++++++------------
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c           |  54 +++++++++----
>  drivers/gpu/drm/amd/amdgpu/si_smc.c           |   1 +
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   6 +-
>  8 files changed, 124 insertions(+), 71 deletions(-)
> 
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 00/14] drm/amdgpu/si: Make SI DPM workable

[Huang Rui]

On Tue, Aug 30, 2016 at 08:30:57PM +0800, Christian König wrote:
> For patch #4:
> > drm/amdgpu: remove useless functions of si dpm
> Maybe call that "remove unused function forward define".
> 
> And in general patches should at least have a commit message and not 
> just subject. A simple one liner like "The functions don't exists any 
> more." should be sufficient in this case.
> 

I see, you're right. "unused function" is better, I will update it at V2.

> Patch #10:
> 
> Well we probably shouldn't call those functions rv770_* any more.
> 

Yep, I would like to remove that function. Use "adev->mc.vram_type ==
AMDGPU_VRAM_TYPE_GDDR5" instead of mem_gddr5 flag.

> Apart from that the patches look good to me, but since I'm clearly not 
> the DPM expert they are Acked-by: Christian König 
> <christian.koenig@amd.com>.
> 

Thank you,
Rui
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro

[Huang Rui]

On Tue, Aug 30, 2016 at 10:17:58PM +0800, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of Huang Rui
> > Sent: Tuesday, August 30, 2016 7:50 AM
> > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> > Subject: [PATCH 07/14] drm/amdgpu/si: fix the dce6 for si macro
> > 
> > Change-Id: I3e5f42158c57d1ec722f713b129189bc5f802b11
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > index 9609199..ced0390 100644
> > --- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > +++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
> > @@ -1968,7 +1968,11 @@
> >  #define AMDGPU_MM_INDEX		        0x0000
> >  #define AMDGPU_MM_DATA		        0x0001
> > 
> > -#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE))
> > +#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE)    || \
> > +			    (adev->asic_type == CHIP_TAHITI)   || \
> > +			    (adev->asic_type == CHIP_PITCAIRN) || \
> > +			    (adev->asic_type == CHIP_OLAND))
> > +
> 
> Let's just drop this macro and check the asic types explicitly.
> 

OK, will remove this macro in V2.

Thanks,
Rui
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

[Huang Rui]

On Tue, Aug 30, 2016 at 10:21:21PM +0800, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of Huang Rui
> > Sent: Tuesday, August 30, 2016 7:50 AM
> > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> > Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set
> > the GDDR5 flag
> > 
> > Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
> > used on the whole si dpm part.
> > 
> > Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > index 5f1e5fe..563aeea 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > @@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct
> > amdgpu_device *adev,
> >  	}
> >  }
> > 
> > +void rv770_get_memory_type(struct amdgpu_device *adev)
> 
> adev->mc.vram_type should be set in the gmc module.  Use that instead of pi->mem_gddr5.  See ci_dpm.c for example.
> 

So should I use "adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5" check
instead? I will update it in V2.

Thanks,
Rui
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Tuesday, August 30, 2016 12:07 PM
> To: Deucher, Alexander
> Cc: Huan, Alvin; Wang, Ken; amd-gfx@lists.freedesktop.org; Yu, Hui
> Subject: Re: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to
> set the GDDR5 flag
> 
> On Tue, Aug 30, 2016 at 10:21:21PM +0800, Deucher, Alexander wrote:
> > > -----Original Message-----
> > > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On
> Behalf
> > > Of Huang Rui
> > > Sent: Tuesday, August 30, 2016 7:50 AM
> > > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> > > Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to
> set
> > > the GDDR5 flag
> > >
> > > Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
> > > used on the whole si dpm part.
> > >
> > > Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 ++++++++++++++++
> > >  1 file changed, 16 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > index 5f1e5fe..563aeea 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > @@ -6433,8 +6433,24 @@ static void
> si_set_pcie_lane_width_in_smc(struct
> > > amdgpu_device *adev,
> > >  	}
> > >  }
> > >
> > > +void rv770_get_memory_type(struct amdgpu_device *adev)
> >
> > adev->mc.vram_type should be set in the gmc module.  Use that instead of
> pi->mem_gddr5.  See ci_dpm.c for example.
> >
> 
> So should I use "adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5"
> check
> instead? I will update it in V2.

Sure.  Either that or set pi->mem_gddr5 = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5;

Also, double check that the gmc6 module properly sets vram_type.  See the gmc 7 module for reference.

Alex

> 
> Thanks,
> Rui
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set the GDDR5 flag

[Huang Rui]

On Wed, Aug 31, 2016 at 12:17:27AM +0800, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of Huang Rui
> > Sent: Tuesday, August 30, 2016 12:07 PM
> > To: Deucher, Alexander
> > Cc: Huan, Alvin; Wang, Ken; amd-gfx@lists.freedesktop.org; Yu, Hui
> > Subject: Re: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to
> > set the GDDR5 flag
> > 
> > On Tue, Aug 30, 2016 at 10:21:21PM +0800, Deucher, Alexander wrote:
> > > > -----Original Message-----
> > > > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On
> > Behalf
> > > > Of Huang Rui
> > > > Sent: Tuesday, August 30, 2016 7:50 AM
> > > > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > > > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin
> > > > Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to
> > set
> > > > the GDDR5 flag
> > > >
> > > > Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
> > > > used on the whole si dpm part.
> > > >
> > > > Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
> > > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > > ---
> > > >  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 ++++++++++++++++
> > > >  1 file changed, 16 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > > b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > > index 5f1e5fe..563aeea 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> > > > @@ -6433,8 +6433,24 @@ static void
> > si_set_pcie_lane_width_in_smc(struct
> > > > amdgpu_device *adev,
> > > >  	}
> > > >  }
> > > >
> > > > +void rv770_get_memory_type(struct amdgpu_device *adev)
> > >
> > > adev->mc.vram_type should be set in the gmc module.  Use that instead of
> > pi->mem_gddr5.  See ci_dpm.c for example.
> > >
> > 
> > So should I use "adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5"
> > check
> > instead? I will update it in V2.
> 
> Sure.  Either that or set pi->mem_gddr5 = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5;
> 
> Also, double check that the gmc6 module properly sets vram_type.  See the gmc 7 module for reference.
> 

I see. vram_type is already inited as gmc_v6_0_convert_vram_type(tmp) in
early_init of gmc 6. Good to know, thanks.

Rui
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx