* [PATCH v4 0/3] Add ZTE ZX296718 support
@ 2016-09-06 6:04 Jun Nie
2016-09-06 6:04 ` [PATCH v4 1/3] arm64: add ZTE ZX SoC family Jun Nie
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Jun Nie @ 2016-09-06 6:04 UTC (permalink / raw)
To: linux-arm-kernel
Changes in version4:
- Change dts file name to align with compatible name.
- Reorder dts nodes with reg address sequence.
- Move nodes out of soc, which do not have soc simple
bus address or share soc interrupt.
- Change some nodes name to align with convention.
Changes in version3:
- Remove unnecessary flag of gic in dts.
Changes in version2:
- Use more precise cpu and pmu compatible name in dts.
- fix minor coding style issue.
Jun Nie (3):
arm64: add ZTE ZX SoC family
arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
arm64: defconfig: enable ZTE ZX related config
Documentation/devicetree/bindings/arm/zte.txt | 24 +++
arch/arm64/Kconfig.platforms | 5 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/zte/Makefile | 5 +
arch/arm64/boot/dts/zte/zx296718-evb.dts | 25 +++
arch/arm64/boot/dts/zte/zx296718.dtsi | 254 ++++++++++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
7 files changed, 315 insertions(+)
create mode 100644 arch/arm64/boot/dts/zte/Makefile
create mode 100644 arch/arm64/boot/dts/zte/zx296718-evb.dts
create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/3] arm64: add ZTE ZX SoC family
2016-09-06 6:04 [PATCH v4 0/3] Add ZTE ZX296718 support Jun Nie
@ 2016-09-06 6:04 ` Jun Nie
2016-09-06 6:04 ` [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile Jun Nie
2016-09-06 6:04 ` [PATCH v4 3/3] arm64: defconfig: enable ZTE ZX related config Jun Nie
2 siblings, 0 replies; 9+ messages in thread
From: Jun Nie @ 2016-09-06 6:04 UTC (permalink / raw)
To: linux-arm-kernel
This patch introduces ARCH_ZX to add the support of the ZTE ZX SoC
family for the arm64 architecture.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
arch/arm64/Kconfig.platforms | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index be5d824..bc75fd2 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -204,6 +204,11 @@ config ARCH_XGENE
help
This enables support for AppliedMicro X-Gene SOC Family
+config ARCH_ZX
+ bool "ZTE ZX SoC Family"
+ help
+ This enables support for ZTE ZX SoC Family
+
config ARCH_ZYNQMP
bool "Xilinx ZynqMP Family"
help
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
2016-09-06 6:04 [PATCH v4 0/3] Add ZTE ZX296718 support Jun Nie
2016-09-06 6:04 ` [PATCH v4 1/3] arm64: add ZTE ZX SoC family Jun Nie
@ 2016-09-06 6:04 ` Jun Nie
2016-09-08 9:11 ` Shawn Guo
2016-09-09 11:53 ` Shawn Guo
2016-09-06 6:04 ` [PATCH v4 3/3] arm64: defconfig: enable ZTE ZX related config Jun Nie
2 siblings, 2 replies; 9+ messages in thread
From: Jun Nie @ 2016-09-06 6:04 UTC (permalink / raw)
To: linux-arm-kernel
Add device tree support for ZX296718 SoC and evaluation board based on it.
Also document new values.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
Documentation/devicetree/bindings/arm/zte.txt | 24 +++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/zte/Makefile | 5 +
arch/arm64/boot/dts/zte/zx296718-evb.dts | 25 +++
arch/arm64/boot/dts/zte/zx296718.dtsi | 254 ++++++++++++++++++++++++++
5 files changed, 309 insertions(+)
create mode 100644 arch/arm64/boot/dts/zte/Makefile
create mode 100644 arch/arm64/boot/dts/zte/zx296718-evb.dts
create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi
diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt
index 3ff5c9e..8336978 100644
--- a/Documentation/devicetree/bindings/arm/zte.txt
+++ b/Documentation/devicetree/bindings/arm/zte.txt
@@ -13,3 +13,27 @@ Low power management required properties:
Bus matrix required properties:
- compatible = "zte,zx-bus-matrix"
+
+
+---------------------------------------
+- ZX296718 SoC:
+ Required root node properties:
+ - compatible = "zte,zx296718"
+
+ZX296718 EVB board:
+ - "zte,zx296718-evb"
+
+System management required properties:
+ - compatible = "zte,zx296718-aon-sysctrl"
+ - compatible = "zte,zx296718-sysctrl"
+
+Example:
+aon_sysctrl: aon-sysctrl at 116000 {
+ compatible = "zte,zx296718-aon-sysctrl", "syscon";
+ reg = <0x116000 0x1000>;
+};
+
+sysctrl: sysctrl at 1463000 {
+ compatible = "zte,zx296718-sysctrl", "syscon";
+ reg = <0x1463000 0x1000>;
+};
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 6e199c9..6684f97 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -19,6 +19,7 @@ dts-dirs += socionext
dts-dirs += sprd
dts-dirs += xilinx
dts-dirs += lg
+dts-dirs += zte
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile
new file mode 100644
index 0000000..6678066
--- /dev/null
+++ b/arch/arm64/boot/dts/zte/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts
new file mode 100644
index 0000000..d7cefb4
--- /dev/null
+++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts
@@ -0,0 +1,25 @@
+/*
+ * ZTE Ltd. zx296718 Plaform
+ *
+ */
+/dts-v1/;
+#include "zx296718.dtsi"
+
+/ {
+ model = "ZTE zx296718 evaluation board";
+ compatible = "zte,zx296718-evb", "zte,zx296718";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
new file mode 100644
index 0000000..c75a819
--- /dev/null
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -0,0 +1,254 @@
+/*
+ * DTS File for ZTE ZX296718 Plaform
+ *
+ * Copyright (c) 2016 ZTE Semiconductor Co., Ltd.
+ */
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "zte,zx296718";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ osc12m: osc12m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ clock-output-names = "osc12m";
+ };
+
+ osc24m: osc24m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24m";
+ };
+
+ osc25m: osc25m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "osc25m";
+ };
+
+ clk24k: clk-24k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000>;
+ clock-output-names = "rtcclk";
+ };
+
+ osc32k: osc32k-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "osc32k";
+ };
+
+ osc60m: osc60m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ clock-output-names = "osc60m";
+ };
+
+ osc99m: osc99m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <99000000>;
+ clock-output-names = "osc99m";
+ };
+
+ osc125m: osc125m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "osc125m";
+ };
+
+ osc198m: osc198m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <198000000>;
+ clock-output-names = "osc198m";
+ };
+
+ pll_vga: pll-1073m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1073000000>;
+ clock-output-names = "pll_vga";
+ };
+
+ pll_ddr: pll-932m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <932000000>;
+ clock-output-names = "pll_ddr";
+ };
+
+ pll_mac: pll-1000m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ clock-output-names = "pll_mac";
+ };
+
+ pll_mm0: pll-1188m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1188000000>;
+ clock-output-names = "pll_mm0";
+ };
+
+ pll_mm1: pll-1296m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1296000000>;
+ clock-output-names = "pll_mm1";
+ };
+
+ pll_audio: pll-884m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <884000000>;
+ clock-output-names = "pll_audio";
+ };
+
+ pll_hsic: pll-960m-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <960000000>;
+ clock-output-names = "pll_hsic";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ aon_sysctrl: aon-sysctrl at 116000 {
+ compatible = "zte,zx296718-aon-sysctrl", "syscon";
+ reg = <0x116000 0x1000>;
+ };
+
+ uart0: uart at 11f000 {
+ compatible = "arm,pl011", "arm,primecell";
+ arm,primecell-periphid = <0x001feffe>;
+ reg = <0x11f000 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24m>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ dma: dma-controller at 1460000 {
+ compatible = "zte,zx296702-dma";
+ reg = <0x01460000 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24m>;
+ clock-names = "dmaclk";
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <32>;
+ };
+
+ sysctrl: sysctrl at 1463000 {
+ compatible = "zte,zx296718-sysctrl", "syscon";
+ reg = <0x1463000 0x1000>;
+ };
+
+ gic: interrupt-controller at 2a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ #redistributor-regions = <6>;
+ redistributor-stride = <0x0 0x40000>;
+ interrupt-controller;
+ reg = <0x02a00000 0x10000>,
+ <0x02b00000 0x20000>,
+ <0x02b20000 0x20000>,
+ <0x02b40000 0x20000>,
+ <0x02b60000 0x20000>,
+ <0x02b80000 0x20000>,
+ <0x02ba0000 0x20000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 3/3] arm64: defconfig: enable ZTE ZX related config
2016-09-06 6:04 [PATCH v4 0/3] Add ZTE ZX296718 support Jun Nie
2016-09-06 6:04 ` [PATCH v4 1/3] arm64: add ZTE ZX SoC family Jun Nie
2016-09-06 6:04 ` [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile Jun Nie
@ 2016-09-06 6:04 ` Jun Nie
2 siblings, 0 replies; 9+ messages in thread
From: Jun Nie @ 2016-09-06 6:04 UTC (permalink / raw)
To: linux-arm-kernel
This patch enables the configuration for the ZTE ZX family.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index eadf485..2bd5c88 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -57,6 +57,7 @@ CONFIG_ARCH_UNIPHIER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_VULCAN=y
CONFIG_ARCH_XGENE=y
+CONFIG_ARCH_ZX=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
2016-09-06 6:04 ` [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile Jun Nie
@ 2016-09-08 9:11 ` Shawn Guo
2016-09-12 7:13 ` Jun Nie
2016-09-09 11:53 ` Shawn Guo
1 sibling, 1 reply; 9+ messages in thread
From: Shawn Guo @ 2016-09-08 9:11 UTC (permalink / raw)
To: linux-arm-kernel
This version looks pretty good to me. Some nit-picks below though ...
On Tue, Sep 06, 2016 at 02:04:20PM +0800, Jun Nie wrote:
> Add device tree support for ZX296718 SoC and evaluation board based on it.
Please wrap the commit log around column 70.
> Also document new values.
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
> Documentation/devicetree/bindings/arm/zte.txt | 24 +++
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/zte/Makefile | 5 +
> arch/arm64/boot/dts/zte/zx296718-evb.dts | 25 +++
> arch/arm64/boot/dts/zte/zx296718.dtsi | 254 ++++++++++++++++++++++++++
> 5 files changed, 309 insertions(+)
> create mode 100644 arch/arm64/boot/dts/zte/Makefile
> create mode 100644 arch/arm64/boot/dts/zte/zx296718-evb.dts
> create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi
<snip>
> diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile
> new file mode 100644
> index 0000000..6678066
> --- /dev/null
> +++ b/arch/arm64/boot/dts/zte/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts
> new file mode 100644
> index 0000000..d7cefb4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts
> @@ -0,0 +1,25 @@
> +/*
> + * ZTE Ltd. zx296718 Plaform
> + *
> + */
We should probably consider to add a proper licence. GPL/X11 dual is
mostly used and recommended, and there are quite a lot examples in the
DTS folder.
> +/dts-v1/;
> +#include "zx296718.dtsi"
> +
> +/ {
> + model = "ZTE zx296718 evaluation board";
> + compatible = "zte,zx296718-evb", "zte,zx296718";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory at 40000000 {
> + device_type = "memory";
> + reg = <0x40000000 0x40000000>;
> + };
> +
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
> new file mode 100644
> index 0000000..c75a819
> --- /dev/null
> +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
> @@ -0,0 +1,254 @@
> +/*
> + * DTS File for ZTE ZX296718 Plaform
> + *
> + * Copyright (c) 2016 ZTE Semiconductor Co., Ltd.
> + */
Ditto
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + compatible = "zte,zx296718";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x0 0x2>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x0 0x3>;
> + enable-method = "psci";
> + };
> + };
> +
> + osc12m: osc12m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12000000>;
> + clock-output-names = "osc12m";
> + };
> +
> + osc24m: osc24m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24m";
> + };
> +
> + osc25m: osc25m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "osc25m";
> + };
> +
> + clk24k: clk-24k {
I would suggest we name node of fixed rate clock in an unified way like
clock-xxx.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000>;
> + clock-output-names = "rtcclk";
> + };
> +
> + osc32k: osc32k-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + clock-output-names = "osc32k";
> + };
> +
> + osc60m: osc60m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <60000000>;
> + clock-output-names = "osc60m";
> + };
> +
> + osc99m: osc99m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <99000000>;
> + clock-output-names = "osc99m";
> + };
> +
> + osc125m: osc125m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + clock-output-names = "osc125m";
> + };
> +
> + osc198m: osc198m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <198000000>;
> + clock-output-names = "osc198m";
> + };
> +
> + pll_vga: pll-1073m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1073000000>;
> + clock-output-names = "pll_vga";
> + };
> +
> + pll_ddr: pll-932m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <932000000>;
> + clock-output-names = "pll_ddr";
> + };
> +
> + pll_mac: pll-1000m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1000000000>;
> + clock-output-names = "pll_mac";
> + };
> +
> + pll_mm0: pll-1188m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1188000000>;
> + clock-output-names = "pll_mm0";
> + };
> +
> + pll_mm1: pll-1296m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1296000000>;
> + clock-output-names = "pll_mm1";
> + };
> +
> + pll_audio: pll-884m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <884000000>;
> + clock-output-names = "pll_audio";
> + };
> +
> + pll_hsic: pll-960m-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <960000000>;
> + clock-output-names = "pll_hsic";
> + };
Do we really have so many uncontrolled clocks with fixed rate in the
SoC?
Shawn
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
2016-09-06 6:04 ` [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile Jun Nie
2016-09-08 9:11 ` Shawn Guo
@ 2016-09-09 11:53 ` Shawn Guo
2016-09-12 12:18 ` Shawn Guo
1 sibling, 1 reply; 9+ messages in thread
From: Shawn Guo @ 2016-09-09 11:53 UTC (permalink / raw)
To: linux-arm-kernel
A bit more comments as below ...
On Tue, Sep 06, 2016 at 02:04:20PM +0800, Jun Nie wrote:
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
Affinity bits are missing for PPI interrupt. You can use a bit help
from defines in include/dt-bindings/interrupt-controller/arm-gic.h.
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
There are no unit-address for timer and pmu, so we should probably move
them out of soc simple-bus and put them directly under root.
> +
> + aon_sysctrl: aon-sysctrl at 116000 {
> + compatible = "zte,zx296718-aon-sysctrl", "syscon";
> + reg = <0x116000 0x1000>;
> + };
> +
> + uart0: uart at 11f000 {
> + compatible = "arm,pl011", "arm,primecell";
> + arm,primecell-periphid = <0x001feffe>;
> + reg = <0x11f000 0x1000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24m>;
> + clock-names = "apb_pclk";
> + status = "disabled";
> + };
> +
> + dma: dma-controller at 1460000 {
> + compatible = "zte,zx296702-dma";
> + reg = <0x01460000 0x1000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24m>;
> + clock-names = "dmaclk";
> + #dma-cells = <1>;
> + dma-channels = <32>;
> + dma-requests = <32>;
> + };
> +
> + sysctrl: sysctrl at 1463000 {
> + compatible = "zte,zx296718-sysctrl", "syscon";
> + reg = <0x1463000 0x1000>;
> + };
> +
> + gic: interrupt-controller at 2a00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + #redistributor-regions = <6>;
> + redistributor-stride = <0x0 0x40000>;
> + interrupt-controller;
> + reg = <0x02a00000 0x10000>,
> + <0x02b00000 0x20000>,
> + <0x02b20000 0x20000>,
> + <0x02b40000 0x20000>,
> + <0x02b60000 0x20000>,
> + <0x02b80000 0x20000>,
> + <0x02ba0000 0x20000>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
Affinity bits are missing.
Shawn
> + };
> + };
> +};
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
2016-09-08 9:11 ` Shawn Guo
@ 2016-09-12 7:13 ` Jun Nie
2016-09-12 12:14 ` Shawn Guo
0 siblings, 1 reply; 9+ messages in thread
From: Jun Nie @ 2016-09-12 7:13 UTC (permalink / raw)
To: linux-arm-kernel
2016-09-08 17:11 GMT+08:00 Shawn Guo <shawnguo@kernel.org>:
> This version looks pretty good to me. Some nit-picks below though ...
>
> On Tue, Sep 06, 2016 at 02:04:20PM +0800, Jun Nie wrote:
>> Add device tree support for ZX296718 SoC and evaluation board based on it.
>
> Please wrap the commit log around column 70.
>
>> Also document new values.
>>
>> Signed-off-by: Jun Nie <jun.nie@linaro.org>
>> ---
>> Documentation/devicetree/bindings/arm/zte.txt | 24 +++
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/zte/Makefile | 5 +
>> arch/arm64/boot/dts/zte/zx296718-evb.dts | 25 +++
>> arch/arm64/boot/dts/zte/zx296718.dtsi | 254 ++++++++++++++++++++++++++
>> 5 files changed, 309 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/zte/Makefile
>> create mode 100644 arch/arm64/boot/dts/zte/zx296718-evb.dts
>> create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi
>
> <snip>
>
>> diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile
>> new file mode 100644
>> index 0000000..6678066
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/zte/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
>> +
>> +always := $(dtb-y)
>> +subdir-y := $(dts-dirs)
>> +clean-files := *.dtb
>> diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts
>> new file mode 100644
>> index 0000000..d7cefb4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts
>> @@ -0,0 +1,25 @@
>> +/*
>> + * ZTE Ltd. zx296718 Plaform
>> + *
>> + */
>
> We should probably consider to add a proper licence. GPL/X11 dual is
> mostly used and recommended, and there are quite a lot examples in the
> DTS folder.
>
Will do.
>> +/dts-v1/;
>> +#include "zx296718.dtsi"
>> +
>> +/ {
>> + model = "ZTE zx296718 evaluation board";
>> + compatible = "zte,zx296718-evb", "zte,zx296718";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory at 40000000 {
>> + device_type = "memory";
>> + reg = <0x40000000 0x40000000>;
>> + };
>> +
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
>> new file mode 100644
>> index 0000000..c75a819
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
>> @@ -0,0 +1,254 @@
>> +/*
>> + * DTS File for ZTE ZX296718 Plaform
>> + *
>> + * Copyright (c) 2016 ZTE Semiconductor Co., Ltd.
>> + */
>
> Ditto
Will do.
>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + compatible = "zte,zx296718";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&cpu0>;
>> + };
>> + core1 {
>> + cpu = <&cpu1>;
>> + };
>> + core2 {
>> + cpu = <&cpu2>;
>> + };
>> + core3 {
>> + cpu = <&cpu3>;
>> + };
>> + };
>> + };
>> +
>> + cpu0: cpu at 0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53","arm,armv8";
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu1: cpu at 1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53","arm,armv8";
>> + reg = <0x0 0x1>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu2: cpu at 2 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53","arm,armv8";
>> + reg = <0x0 0x2>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu3: cpu at 3 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53","arm,armv8";
>> + reg = <0x0 0x3>;
>> + enable-method = "psci";
>> + };
>> + };
>> +
>> + osc12m: osc12m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <12000000>;
>> + clock-output-names = "osc12m";
>> + };
>> +
>> + osc24m: osc24m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24m";
>> + };
>> +
>> + osc25m: osc25m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <25000000>;
>> + clock-output-names = "osc25m";
>> + };
>> +
>> + clk24k: clk-24k {
>
> I would suggest we name node of fixed rate clock in an unified way like
> clock-xxx.
>
Will do.
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000>;
>> + clock-output-names = "rtcclk";
>> + };
>> +
>> + osc32k: osc32k-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <32000>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + osc60m: osc60m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <60000000>;
>> + clock-output-names = "osc60m";
>> + };
>> +
>> + osc99m: osc99m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <99000000>;
>> + clock-output-names = "osc99m";
>> + };
>> +
>> + osc125m: osc125m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + clock-output-names = "osc125m";
>> + };
>> +
>> + osc198m: osc198m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <198000000>;
>> + clock-output-names = "osc198m";
>> + };
>> +
>> + pll_vga: pll-1073m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <1073000000>;
>> + clock-output-names = "pll_vga";
>> + };
>> +
>> + pll_ddr: pll-932m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <932000000>;
>> + clock-output-names = "pll_ddr";
>> + };
>> +
>> + pll_mac: pll-1000m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <1000000000>;
>> + clock-output-names = "pll_mac";
>> + };
>> +
>> + pll_mm0: pll-1188m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <1188000000>;
>> + clock-output-names = "pll_mm0";
>> + };
>> +
>> + pll_mm1: pll-1296m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <1296000000>;
>> + clock-output-names = "pll_mm1";
>> + };
>> +
>> + pll_audio: pll-884m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <884000000>;
>> + clock-output-names = "pll_audio";
>> + };
>> +
>> + pll_hsic: pll-960m-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <960000000>;
>> + clock-output-names = "pll_hsic";
>> + };
>
> Do we really have so many uncontrolled clocks with fixed rate in the
> SoC?
PLL clocks can be configured actually according to register. But I
prefer to keep them as fixed clocks due to two reasons:
1. ZTE do not want to expose too much information of PLL.
2. All clients blocks, such as MMC and video codec, assume the
related input clock's frequency as a derivation from PLL default
frequency value in block clock control register description.
>
> Shawn
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
2016-09-12 7:13 ` Jun Nie
@ 2016-09-12 12:14 ` Shawn Guo
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Guo @ 2016-09-12 12:14 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Sep 12, 2016 at 03:13:58PM +0800, Jun Nie wrote:
> PLL clocks can be configured actually according to register. But I
> prefer to keep them as fixed clocks due to two reasons:
> 1. ZTE do not want to expose too much information of PLL.
> 2. All clients blocks, such as MMC and video codec, assume the
> related input clock's frequency as a derivation from PLL default
> frequency value in block clock control register description.
Okay, just try to understand the reason behind it. Thanks.
Shawn
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
2016-09-09 11:53 ` Shawn Guo
@ 2016-09-12 12:18 ` Shawn Guo
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Guo @ 2016-09-12 12:18 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Sep 09, 2016 at 07:53:36PM +0800, Shawn Guo wrote:
> A bit more comments as below ...
>
> On Tue, Sep 06, 2016 at 02:04:20PM +0800, Jun Nie wrote:
> > + soc {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "simple-bus";
> > + interrupt-parent = <&gic>;
> > + ranges;
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>
> Affinity bits are missing for PPI interrupt. You can use a bit help
> from defines in include/dt-bindings/interrupt-controller/arm-gic.h.
Sorry, I missed the fact that affinity bits is only required for gic-v2,
while what we have here is a gic-v3. So please ignore the comment.
Shawn
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-09-12 12:18 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-06 6:04 [PATCH v4 0/3] Add ZTE ZX296718 support Jun Nie
2016-09-06 6:04 ` [PATCH v4 1/3] arm64: add ZTE ZX SoC family Jun Nie
2016-09-06 6:04 ` [PATCH v4 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile Jun Nie
2016-09-08 9:11 ` Shawn Guo
2016-09-12 7:13 ` Jun Nie
2016-09-12 12:14 ` Shawn Guo
2016-09-09 11:53 ` Shawn Guo
2016-09-12 12:18 ` Shawn Guo
2016-09-06 6:04 ` [PATCH v4 3/3] arm64: defconfig: enable ZTE ZX related config Jun Nie
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