Add support for GuC-based SLPC

Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features.  The SLPC
implementation runs in firmware on GuC.

This series has been tested with SKL GuC firmware
version 9.18 which is yet to be released. Performance and
power testing with these patches and 9.18 firmware is at
parity and in some cases better than host solution today
on various Linux benchmarks.

The graphics power management features in SLPC in this
version are called GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate.  Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios.  BALANCER is only
active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.

The last series can be found in the archive at
"[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/094445.html

This series incorporates feedback from code reviews on earlier series.
It drops the display mode notification patches as it is not needed for
Turbo part of GTPERF. This series also adds new interface changes for
SLPC support on 9.18 GuC Firmware which is not yet published.
Will like to get review started prior to firmware is published.

With SLPC disabled by default, this series should be 
safe to merge now and it can be enabled when 9.18 firmware is released. 

VIZ-6773, VIZ-6889

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Beuchat, Marc <marc.beuchat@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>

Sagar Arun Kamble (7):
  drm/i915: Remove RPM suspend dependency on rps.enabled and related
    changes
  drm/i915: Check GuC load status for Host to GuC action and SLPC status
  drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
  drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS
    Stall
  drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
  drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC
  drm/i915/slpc: Update freq min/max softlimits

Tom O'Rourke (19):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize SLPC version
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Update current requested frequency
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add broxton support
  drm/i915/slpc: Enable SLPC, where supported

 drivers/gpu/drm/i915/Makefile              |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 461 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c            |  17 +-
 drivers/gpu/drm/i915/i915_drv.h            |   7 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  21 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_pci.c            |   3 +
 drivers/gpu/drm/i915/i915_reg.h            |   1 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  26 ++
 drivers/gpu/drm/i915/intel_drv.h           |  13 +
 drivers/gpu/drm/i915/intel_guc.h           |  10 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  50 +++-
 drivers/gpu/drm/i915/intel_pm.c            | 132 ++++++---
 drivers/gpu/drm/i915/intel_slpc.c          | 370 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 212 +++++++++++++
 16 files changed, 1281 insertions(+), 52 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[Sagar Arun Kamble]

For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled.
RPM Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other GENs
this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case of
disabling of RPS in gen9_enable_rps.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 10 +++++++++-
 drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++--
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 13ae340..bc2c67b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2284,9 +2284,17 @@ static int intel_runtime_suspend(struct device *device)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
 		return -ENODEV;
 
+	/*
+	 * Once RC6 and RPS enabling is separated for non-GEN9 platforms
+	 * below check should be removed.
+	*/
+	if (!IS_GEN9(dev))
+		if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+			return -ENODEV;
+
 	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
 		return -ENODEV;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 99014d7..954e332 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4966,6 +4966,7 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+	dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -4973,11 +4974,16 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
+
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -4989,6 +4995,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5206,6 +5214,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5349,6 +5359,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5445,6 +5457,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -5919,6 +5933,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -5999,6 +6015,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6588,7 +6606,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		ironlake_disable_drps(dev_priv);
 	}
 
-	dev_priv->rps.enabled = false;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -6632,7 +6649,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-- 
1.9.1

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drm/i915/slpc: Expose guc functions for use with SLPC

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

v5: Updated function names as they need to be made extern. (ChrisW)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_guc.h           |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index bb40792..680d9b4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -47,7 +47,7 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
  *
  * Doorbells:
  * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 	return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	u32 status;
@@ -141,7 +141,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -152,7 +152,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -169,7 +169,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 		/* bit 0 and 1 are for Render and Media domain separately */
 		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 /*
@@ -621,7 +621,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
@@ -1066,7 +1066,7 @@ int intel_guc_suspend(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 
@@ -1091,5 +1091,5 @@ int intel_guc_resume(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c973262..9e6b948 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
 
-- 
1.9.1

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drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v2: fix whitespace (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35caa9b..764fad0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -646,6 +646,7 @@ struct intel_csr {
 	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
+	func(has_slpc) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2800,6 +2801,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev)		(IS_GEN9(dev))
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
+#define HAS_SLPC(dev)		(INTEL_INFO(dev)->has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
-- 
1.9.1

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drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v2: Move slpc_version_check to intel_guc_ucode_init
v3: fix whitespace (Sagar)
v5: Moved version check to different patch as has_slpc
    should not be updated based on it. Instead module paramter
    should be updated based on version check. (Sagar)
    Added support to skylake_gt3 as well. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e678051 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,12 +322,14 @@ static const struct intel_device_info intel_skylake_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v2: Add early call to sanitize enable_slpc in intel_guc_ucode_init

v5: Remove sanitize enable_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as
    part of slpc_enable_sanitize function in the next patch. (Sagar)
    Updated slpc option sanitize function call for platforms without
    GuC support. This was caught by CI BAT.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_guc.h        |  6 ++++++
 drivers/gpu/drm/i915/intel_guc_loader.c | 30 ++++++++++++++++++++++++++----
 4 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
+	int enable_slpc;
 	int enable_psr;
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..27a7459 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
 	uint32_t last_seqno[I915_NUM_ENGINES];
 };
 
+static inline int intel_slpc_enabled(void)
+{
+        WARN_ON(i915.enable_slpc < 0);
+        return i915.enable_slpc;
+}
+
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_device *dev);
 extern int intel_guc_setup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 324812d..75b360f 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void sanitize_slpc_option(struct drm_device *dev)
+{
+	/* Handle default case */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev);
+
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc loaded */
+	if (!i915.enable_guc_loading)
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
 	/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -728,18 +747,21 @@ void intel_guc_init(struct drm_device *dev)
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 
-	/* Early (and silent) return if GuC loading is disabled */
+	/* Return if GuC loading is disabled sanitizing SLPC option */
 	if (!i915.enable_guc_loading)
-		return;
+		goto out;
 	if (fw_path == NULL)
-		return;
+		goto out;
 	if (*fw_path == '\0')
-		return;
+		goto out;
 
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 	guc_fw_fetch(dev, guc_fw);
 	/* status must now be FAIL or SUCCESS */
+
+out:
+	sanitize_slpc_option(dev);
 }
 
 /**
-- 
1.9.1

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drm/i915/slpc: Sanitize SLPC version

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v5: Updated with modified sanitize_slpc_option in earlier patch.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 75b360f..6765edf 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -146,6 +146,9 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 
 static void sanitize_slpc_option(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
 	/* Handle default case */
 	if (i915.enable_slpc < 0)
 		i915.enable_slpc = HAS_SLPC(dev);
@@ -161,6 +164,9 @@ static void sanitize_slpc_option(struct drm_device *dev)
 	/* slpc requires guc submission */
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
+
+	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+		i915.enable_slpc = 0;
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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drm/i915/slpc: Use intel_slpc_* functions if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v2: return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
v3: Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"

v5: Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v6: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  3 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_guc.h  |  1 +
 drivers/gpu/drm/i915/intel_pm.c   | 98 ++++++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_slpc.c | 56 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 35 ++++++++++++++
 6 files changed, 165 insertions(+), 32 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3412413..b768c66 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -51,7 +51,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+	  i915_guc_submission.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1c700b0..16fe13d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1692,6 +1692,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 			  enum dpio_channel ch, bool override);
 
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
+{
+	return 0;
+}
 
 /* intel_pm.c */
 void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 27a7459..cd23c4e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 954e332..7156fb5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4893,7 +4893,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	 * our rpm wakeref. And then disable the interrupts to stop any
 	 * futher RPS reclocking whilst we are asleep.
 	 */
-	gen6_disable_rps_interrupts(dev_priv);
+	if (!intel_slpc_active(dev_priv))
+		gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
@@ -6544,6 +6545,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 	/* Finally allow us to boost to max by default */
 	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
 
+	if (intel_slpc_enabled())
+		intel_slpc_init(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
@@ -6552,7 +6556,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (IS_VALLEYVIEW(dev_priv))
+	if (intel_slpc_enabled())
+		intel_slpc_cleanup(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
 	if (!i915.enable_rc6)
@@ -6572,28 +6578,42 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
+	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) {
+		if (intel_slpc_active(dev_priv))
+			intel_slpc_suspend(dev_priv);
 		intel_runtime_pm_put(dev_priv);
+	}
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
-	intel_disable_gt_powersave(dev_priv);
+	if (intel_slpc_enabled()) {
+		/* TODO: Set SLPC enabled forcefully */
+		intel_disable_gt_powersave(dev_priv);
+	} else {
+		dev_priv->rps.enabled = true; /* force disabling */
+		intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+		gen6_reset_rps_interrupts(dev_priv);
+	}
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (!intel_slpc_active(dev_priv))
+			return;
+	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_active(dev_priv)) {
+		gen9_disable_rc6(dev_priv);
+		intel_slpc_disable(dev_priv);
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_disable_rc6(dev_priv);
 		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
@@ -6614,7 +6634,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	/* Powersaving is controlled by the host when inside a VM */
@@ -6623,31 +6646,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (IS_CHERRYVIEW(dev_priv)) {
-		cherryview_enable_rps(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
-		valleyview_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_enabled()) {
 		gen9_enable_rc6(dev_priv);
-		gen9_enable_rps(dev_priv);
+		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		gen8_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
-		gen6_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (IS_IRONLAKE_M(dev_priv)) {
-		ironlake_enable_drps(dev_priv);
-		intel_init_emon(dev_priv);
-	}
+	} else {
+		if (IS_CHERRYVIEW(dev_priv)) {
+			cherryview_enable_rps(dev_priv);
+		} else if (IS_VALLEYVIEW(dev_priv)) {
+			valleyview_enable_rps(dev_priv);
+		} else if (INTEL_INFO(dev_priv)->gen >= 9) {
+			gen9_enable_rc6(dev_priv);
+			gen9_enable_rps(dev_priv);
+			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+				gen6_update_ring_freq(dev_priv);
+		} else if (IS_BROADWELL(dev_priv)) {
+			gen8_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 6) {
+			gen6_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (IS_IRONLAKE_M(dev_priv)) {
+			ironlake_enable_drps(dev_priv);
+			intel_init_emon(dev_priv);
+		}
 
-	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
 
-	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+	}
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
@@ -6659,7 +6689,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			goto out;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		goto out;
 
 	rcs = &dev_priv->engine[RCS];
@@ -6689,7 +6722,10 @@ out:
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..b2e8d91
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+	return;
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+	return;
+}
+
+void intel_slpc_suspend(struct drm_i915_private *dev_priv)
+{
+	return;
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+	return;
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+	return;
+}
+
+void intel_slpc_reset(struct drm_i915_private *dev_priv)
+{
+	return;
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..ae52146
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_suspend(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+void intel_slpc_reset(struct drm_i915_private *dev_priv);
+
+#endif
-- 
1.9.1

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drm/i915/slpc: Enable SLPC in guc if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v2: Use intel_slpc_enabled() (Paulo)

v5: Rebase. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6765edf..2edd255 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -212,6 +212,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (intel_slpc_enabled())
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	if (i915.guc_log_level >= 0) {
 		params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 		params[GUC_CTL_DEBUG] =
-- 
1.9.1

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drm/i915/slpc: If using SLPC, do not set frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v2: Use intel_slpc_active instead of HAS_SLPC (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7156fb5..3b3f487 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4952,6 +4952,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+	if (intel_slpc_active(dev_priv))
+		return;
+
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		valleyview_set_rps(dev_priv, val);
 	else
-- 
1.9.1

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drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC shared data is used to pass information
to/from SLPC in GuC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v2: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
v3: change default host_os to "Windows"
v4: Spelling fixes (Sagar Kamble and Nick Hoath)
v5: Added WARN for checking if upper 32bits of GTT offset
    of shared object are zero. (ChrisW)
    Changed function call from gem_allocate/release_guc_obj to
    i915_guc_allocate/release_gem_obj. (Sagar)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE
    definition from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable
    to determine if it is active as it not just dependent on shared
    data setup.
    Rebase with guc_allocate_vma related changes.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
 drivers/gpu/drm/i915/intel_guc.h  |  2 +
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
 drivers/gpu/drm/i915/intel_slpc.c | 90 ++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_slpc.h | 78 +++++++++++++++++++++++++++++++++
 5 files changed, 178 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 16fe13d..c46d619 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,7 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
-	return 0;
+	int ret = 0;
+
+	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
+		ret = 1;
+
+	return ret;
 }
 
 /* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index cd23c4e..4a551f6 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -145,6 +145,8 @@ struct intel_guc {
 
 	uint64_t submissions[I915_NUM_ENGINES];
 	uint32_t last_seqno[I915_NUM_ENGINES];
+
+	struct intel_slpc slpc;
 };
 
 static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3b3f487..6dc33cf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6559,7 +6559,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (intel_slpc_enabled())
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma)
 		intel_slpc_cleanup(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
@@ -6649,7 +6650,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (intel_slpc_enabled()) {
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma) {
 		gen9_enable_rc6(dev_priv);
 		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b2e8d91..ba5b23a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,17 +22,103 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static u8 slpc_get_platform_sku(struct drm_device *dev)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	return (u8) platform_sku;
+}
+
+static u8 slpc_get_slice_count(struct drm_device *dev)
+{
+	u8 slice_count = 1;
+
+	if (IS_SKYLAKE(dev))
+		slice_count = INTEL_INFO(dev)->slice_total;
+
+	return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 msr_value;
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+
+	page = i915_gem_object_get_page(obj, 0);
+	if (page) {
+		data = kmap_atomic(page);
+		memset(data, 0, sizeof(struct slpc_shared_data));
+
+		data->slpc_version = SLPC_VERSION;
+		data->shared_data_size = sizeof(struct slpc_shared_data);
+		data->global_state = (u32) SLPC_GLOBAL_STATE_NOT_RUNNING;
+		data->platform_info.platform_sku = slpc_get_platform_sku(&dev_priv->drm);
+		data->platform_info.slice_count = slpc_get_slice_count(&dev_priv->drm);
+		data->platform_info.host_os = (u8) SLPC_HOST_OS_WINDOWS_8;
+		data->platform_info.power_plan_source =
+			(u8) SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+						    SLPC_POWER_SOURCE_AC);
+		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+		data->platform_info.P0_freq = (u8) msr_value;
+		rdmsrl(MSR_PLATFORM_INFO, msr_value);
+		data->platform_info.P1_freq = (u8) (msr_value >> 8);
+		data->platform_info.Pe_freq = (u8) (msr_value >> 40);
+		data->platform_info.Pn_freq = (u8) (msr_value >> 48);
+		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
+		data->platform_info.package_rapl_limit_high =
+							(u32) (msr_value >> 32);
+		data->platform_info.package_rapl_limit_low = (u32) msr_value;
+
+		kunmap_atomic(data);
+	}
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
-	return;
+	struct intel_guc *guc = &dev_priv->guc;
+	struct i915_vma *vma;
+
+	/* Allocate shared data structure */
+	vma = dev_priv->guc.slpc.vma;
+	if (!vma) {
+		vma = guc_allocate_vma(guc,
+				       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		if (IS_ERR(vma)) {
+			DRM_ERROR("slpc_shared_data allocation failed\n");
+			i915.enable_slpc = 0;
+			return;
+		}
+
+		dev_priv->guc.slpc.vma = vma;
+	}
+
+	slpc_shared_data_init(dev_priv);
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 {
-	return;
+	struct intel_guc *guc = &dev_priv->guc;
+
+	/* Release shared data structure */
+	i915_vma_unpin_and_release(&guc->slpc.vma);
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index ae52146..e951289 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,84 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+#define SLPC_MAJOR_VER 2
+#define SLPC_MINOR_VER 4
+#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_host_os {
+	SLPC_HOST_OS_UNDEFINED = 0,
+	SLPC_HOST_OS_WINDOWS_8 = 1,
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 host_os;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 package_rapl_limit_high;
+	u32 package_rapl_limit_low;
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 slpc_version;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	u32 task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+struct intel_slpc {
+	struct i915_vma *vma;
+	bool enabled;
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
-- 
1.9.1

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drm/i915/slpc: Update current requested frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Before using rps.cur_freq in sysfs or debugfs, read
requested frequency from register to get the value
most recently requested by SLPC firmware.

v2: replace HAS_SLPC with intel_slpc_active (Paulo)
v3: Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 drivers/gpu/drm/i915/i915_sysfs.c   | 8 ++++++++
 4 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 01ae5ee..a99a3f6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1110,6 +1110,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (intel_slpc_active(dev_priv))
+		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+
 	if (IS_GEN5(dev)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2372,6 +2375,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_file *file;
 
+	if (intel_slpc_active(dev_priv))
+		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
 	seq_printf(m, "GPU busy? %s [%x]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 764fad0..fcd2e98 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3913,4 +3913,9 @@ bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
 	__T;								\
 })
 
+static inline u8 gen9_read_requested_freq(struct drm_i915_private *dev_priv)
+{
+	return (u8) GEN9_GET_FREQUENCY(I915_READ(GEN6_RPNSWREQ));
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4adf28..1654245 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6997,6 +6997,7 @@ enum {
 #define   GEN6_FREQUENCY(x)			((x)<<25)
 #define   HSW_FREQUENCY(x)			((x)<<24)
 #define   GEN9_FREQUENCY(x)			((x)<<23)
+#define   GEN9_GET_FREQUENCY(x)			((x)>>23)
 #define   GEN6_OFFSET(x)			((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index f1ffde7..8404816 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -302,6 +302,14 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 	struct drm_device *dev = minor->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_runtime_pm_get(dev_priv);
+		mutex_lock(&dev_priv->rps.hw_lock);
+		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+	}
+
 	return snprintf(buf, PAGE_SIZE, "%d\n",
 			intel_gpu_freq(dev_priv,
 				       dev_priv->rps.cur_freq));
-- 
1.9.1

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drm/i915/slpc: Send reset event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add host2guc SLPC reset event and send reset event
during enable.

v2: extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)

v5: Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index ba5b23a..161cd13 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+	int ret = i915_guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= SLPC_EVENT_STATUS_MASK;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static u8 slpc_get_platform_sku(struct drm_device *dev)
 {
 	enum slpc_platform_sku platform_sku;
@@ -133,6 +159,9 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_reset(dev_priv);
+	dev_priv->guc.slpc.enabled = true;
+
 	return;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index e951289..031e36b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK	0xFF
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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drm/i915/slpc: Send shutdown event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations.  Sending shutdown event while already shutdown
is OK.

v2: return void instead of ignored error code (Paulo)

v5: Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 161cd13..5a1e6f2 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static u8 slpc_get_platform_sku(struct drm_device *dev)
 {
 	enum slpc_platform_sku platform_sku;
@@ -149,12 +162,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
-	return;
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
-	return;
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
@@ -167,5 +182,6 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
 {
-	return;
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
-- 
1.9.1

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drm/i915/slpc: Add slpc_status enum values

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

v2: fix whitespace (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 031e36b..9fe9ae3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,33 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MISMATCHING_VERSION = 16,
+	SLPC_STATUS_MEMIO_ERROR = 17,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
+	SLPC_STATUS_NO_EVENT_QUEUED = 20,
+	SLPC_STATUS_OUT_OF_SPACE = 21,
+	SLPC_STATUS_TIMEOUT = 22,
+	SLPC_STATUS_NO_LOCK = 23,
+};
+
 enum slpc_event_id {
 	SLPC_EVENT_RESET = 0,
 	SLPC_EVENT_SHUTDOWN = 1,
-- 
1.9.1

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drm/i915/slpc: Add parameter unset/set/get functions

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add slpc_param_id enum values.
Add events for setting/unsetting parameters.

v2: use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 99 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 26 +++++++++-
 2 files changed, 124 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 5a1e6f2..120bdab 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,105 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+				    enum slpc_param_id id, u32 value)
+{
+	u32 data[4];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data[2] = (u32) id;
+	data[3] = value;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+				      enum slpc_param_id id)
+{
+	u32 data[3];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data[2] = (u32) id;
+
+	host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv, enum slpc_param_id id)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							&= (~(1 << (id % 32)));
+		data->override_parameters_values[id] = 0;
+		kunmap_atomic(data);
+
+		host2guc_slpc_unset_param(dev_priv, id);
+	}
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv, enum slpc_param_id id,
+			  u32 value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							|= (1 << (id % 32));
+		data->override_parameters_values[id] = value;
+		kunmap_atomic(data);
+
+		host2guc_slpc_set_param(dev_priv, id, value);
+	}
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv, enum slpc_param_id id,
+			  int *overriding, u32 *value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		if (overriding) {
+			bits = data->override_parameters_set_bits[id >> 5];
+			*overriding = (0 != (bits & (1 << (id % 32))));
+		}
+		if (value)
+			*value = data->override_parameters_values[id];
+
+		kunmap_atomic(data);
+	}
+}
+
 static u8 slpc_get_platform_sku(struct drm_device *dev)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 9fe9ae3..040c240 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -69,6 +69,26 @@ enum slpc_event_id {
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 #define SLPC_EVENT_STATUS_MASK	0xFF
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -150,5 +170,9 @@ void intel_slpc_suspend(struct drm_i915_private *dev_priv);
 void intel_slpc_disable(struct drm_i915_private *dev_priv);
 void intel_slpc_enable(struct drm_i915_private *dev_priv);
 void intel_slpc_reset(struct drm_i915_private *dev_priv);
-
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv, enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_i915_private *dev_priv, enum slpc_param_id id,
+			  u32 value);
+void intel_slpc_get_param(struct drm_i915_private *dev_priv, enum slpc_param_id id,
+			  int *overriding, u32 *value);
 #endif
-- 
1.9.1

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drm/i915/slpc: Add slpc support for max/min freq

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a99a3f6..fb497ea1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4959,6 +4959,15 @@ i915_max_freq_set(void *data, u64 val)
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -5015,6 +5024,15 @@ i915_min_freq_set(void *data, u64 val)
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 8404816..57f9ada 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -408,6 +408,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
@@ -465,6 +474,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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drm/i915/slpc: Add enable/disable debugfs for slpc

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v2: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
v3: Avoid magic numbers (Jon Bloomfield)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 252 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   5 +
 2 files changed, 257 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fb497ea1..7e125a1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1101,6 +1101,255 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			i915_next_seqno_get, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+				     &value_disable);
+
+		/* set the output value:
+		* 0: default
+		* 1: enabled
+		* 2: disabled
+		* 3: unknown (should not happen)
+		*/
+		if (override_disable && (1 == value_disable))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (1 == value_enable))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (SLPC_PARAM_TASK_DEFAULT == val) {
+		/* set default */
+		intel_slpc_unset_param(dev_priv, enable_id);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (SLPC_PARAM_TASK_ENABLED == val) {
+		/* set enable */
+		intel_slpc_set_param(dev_priv, enable_id, 1);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (SLPC_PARAM_TASK_DISABLED == val) {
+		/* set disable */
+		intel_slpc_set_param(dev_priv, disable_id, 1);
+		intel_slpc_unset_param(dev_priv, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = slpc_enable_disable_set(dev, val, enable_id, disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			       SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = m->private;
@@ -5419,6 +5668,9 @@ static const struct i915_debugfs_files {
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 040c240..f1c8334 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -89,6 +89,11 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
 };
 
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v2: reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
v3: Avoid magic numbers and use local variables (Jon Bloomfield)
v5: Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Moved definition of power plan and power source to earlier
    patch in the series.
    drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
    (Akash)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 184 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   |  19 ++++
 drivers/gpu/drm/i915/intel_slpc.h   |   1 +
 3 files changed, 204 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7e125a1..cfe6dac 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1350,6 +1350,189 @@ static const struct file_operations i915_slpc_dcc_fops = {
 	.llseek	 = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
+	int i, value;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	enum slpc_host_os host_os;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		intel_slpc_query_task_state(dev_priv);
+
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			pv = kmap_atomic(page);
+	}
+
+	if (pv) {
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
+			   data.slpc_version >> 16,
+			   (data.slpc_version >> 8) & 0xFF,
+			   data.slpc_version & 0xFF,
+			   data.slpc_version);
+		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+		global_state = (enum slpc_global_state) data.global_state;
+		seq_printf(m, "global state: %d (", global_state);
+		switch (global_state) {
+		case SLPC_GLOBAL_STATE_NOT_RUNNING:
+			seq_puts(m, "not running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_INITIALIZING:
+			seq_puts(m, "initializing)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RESETTING:
+			seq_puts(m, "resetting)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RUNNING:
+			seq_puts(m, "running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+			seq_puts(m, "shutting down)\n");
+			break;
+		case SLPC_GLOBAL_STATE_ERROR:
+			seq_puts(m, "error)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		platform_sku = (enum slpc_platform_sku)
+				data.platform_info.platform_sku;
+		seq_printf(m, "sku: %d (", platform_sku);
+		switch (platform_sku) {
+		case SLPC_PLATFORM_SKU_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULX:
+			seq_puts(m, "ULX)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULT:
+			seq_puts(m, "ULT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_T:
+			seq_puts(m, "T)\n");
+			break;
+		case SLPC_PLATFORM_SKU_MOBL:
+			seq_puts(m, "Mobile)\n");
+			break;
+		case SLPC_PLATFORM_SKU_DT:
+			seq_puts(m, "DT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_UNKNOWN:
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+		seq_printf(m, "slice count: %d\n",
+			   data.platform_info.slice_count);
+
+		host_os = (enum slpc_host_os) data.platform_info.host_os;
+		seq_printf(m, "host OS: %d (", host_os);
+		switch (host_os) {
+		case SLPC_HOST_OS_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_HOST_OS_WINDOWS_8:
+			seq_puts(m, "Windows 8)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+			   data.platform_info.power_plan_source);
+		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+					data.platform_info.power_plan_source);
+		power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+					data.platform_info.power_plan_source);
+		switch (power_plan) {
+		case SLPC_POWER_PLAN_UNDEFINED:
+			seq_puts(m, "undefined");
+			break;
+		case SLPC_POWER_PLAN_BATTERY_SAVER:
+			seq_puts(m, "battery saver");
+			break;
+		case SLPC_POWER_PLAN_BALANCED:
+			seq_puts(m, "balanced");
+			break;
+		case SLPC_POWER_PLAN_PERFORMANCE:
+			seq_puts(m, "performance");
+			break;
+		case SLPC_POWER_PLAN_UNKNOWN:
+		default:
+			seq_puts(m, "unknown");
+			break;
+		}
+		seq_puts(m, "\n\tsource:\t");
+		switch (power_source) {
+		case SLPC_POWER_SOURCE_UNDEFINED:
+			seq_puts(m, "undefined\n");
+			break;
+		case SLPC_POWER_SOURCE_AC:
+			seq_puts(m, "AC\n");
+			break;
+		case SLPC_POWER_SOURCE_DC:
+			seq_puts(m, "DC\n");
+			break;
+		case SLPC_POWER_SOURCE_UNKNOWN:
+		default:
+			seq_puts(m, "unknown\n");
+			break;
+		}
+
+		seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+			   data.platform_info.P0_freq * 50,
+			   data.platform_info.P1_freq * 50,
+			   data.platform_info.Pe_freq * 50,
+			   data.platform_info.Pn_freq * 50);
+		seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
+			   data.platform_info.package_rapl_limit_high,
+			   data.platform_info.package_rapl_limit_low);
+		seq_printf(m, "task state data: 0x%08x\n",
+			   data.task_state_data);
+		seq_printf(m, "\tturbo active: %d\n",
+			   (data.task_state_data & 1));
+		seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
+			   (data.task_state_data & 2),
+			   (data.task_state_data & 4),
+			   (data.task_state_data >> 3) & 0xFF);
+
+		seq_puts(m, "override parameter bitfield\n");
+		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+			seq_printf(m, "%d: 0x%08x\n", i,
+				   data.override_parameters_set_bits[i]);
+
+		seq_puts(m, "override parameters (only non-zero shown)\n");
+		for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+			value = data.override_parameters_values[i];
+			if (value)
+				seq_printf(m, "%d: 0x%8x\n", i, value);
+		}
+
+	} else {
+		seq_puts(m, "no SLPC info available\n");
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = m->private;
@@ -5626,6 +5809,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 120bdab..bf0840a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -164,6 +164,25 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv, enum slpc_param_id
 	}
 }
 
+static void host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	if (intel_slpc_active(dev_priv))
+		host2guc_slpc_query_task_state(dev_priv);
+}
+
 static u8 slpc_get_platform_sku(struct drm_device *dev)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index f1c8334..3d2e4ce 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -180,4 +180,5 @@ void intel_slpc_set_param(struct drm_i915_private *dev_priv, enum slpc_param_id
 			  u32 value);
 void intel_slpc_get_param(struct drm_i915_private *dev_priv, enum slpc_param_id id,
 			  int *overriding, u32 *value);
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
 #endif
-- 
1.9.1

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drm/i915/slpc: Add broxton support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.

v2-v4: Rebase.

v5: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c         | 1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e678051..60a5eb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -342,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
+	.has_slpc = 1,
 	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2edd255..a4ab8f9 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -165,8 +165,11 @@ static void sanitize_slpc_option(struct drm_device *dev)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
+	}
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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drm/i915/slpc: Enable SLPC, where supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch makes SLPC enabled by default on
platforms with hardware/firmware support.

v5: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 drivers/gpu/drm/i915/intel_guc.h   | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 72b3097..7b3b3fd 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
-	.enable_slpc = 0,
+	.enable_slpc = -1,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -135,7 +135,7 @@ MODULE_PARM_DESC(enable_execlists,
 module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
 MODULE_PARM_DESC(enable_slpc,
 	"Override single-loop-power-controller (slpc) usage. "
-	"(-1=auto, 0=disabled [default], 1=enabled)");
+	"(-1=auto [default], 0=disabled, 1=enabled)");
 
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4a551f6..b340733 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -151,7 +151,6 @@ struct intel_guc {
 
 static inline int intel_slpc_enabled(void)
 {
-        WARN_ON(i915.enable_slpc < 0);
         return i915.enable_slpc;
 }
 
-- 
1.9.1

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drm/i915: Check GuC load status for Host to GuC action and SLPC status

[Sagar Arun Kamble]

Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 5 +++++
 drivers/gpu/drm/i915/intel_drv.h           | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 680d9b4..27c937b 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -78,6 +78,8 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct intel_guc_fw *guc_fw = &guc->guc_fw;
+
 	u32 status;
 	int i;
 	int ret;
@@ -85,6 +87,9 @@ int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 	if (WARN_ON(len < 1 || len > 15))
 		return -EINVAL;
 
+	if (WARN_ON(guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS))
+		return -ENODEV;
+
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	dev_priv->guc.action_count += 1;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c46d619..71936dc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,8 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int ret = 0;
 
+	if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+		return 0;
+
 	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
 		ret = 1;
 
-- 
1.9.1

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drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

[Sagar Arun Kamble]

This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bc2c67b..b6921c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1629,6 +1629,7 @@ static int i915_drm_resume(struct drm_device *dev)
 static int i915_drm_resume_early(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int ret;
 
 	/*
@@ -1685,6 +1686,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 			  ret);
 
+	/*
+	 * Mark GuC FW load status as PENDING to avoid any Host to GuC actions
+	 * invoked till GuC gets loaded in i915_drm_resume.
+	*/
+	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+
 	intel_uncore_early_sanitize(dev_priv, true);
 
 	if (IS_BROXTON(dev_priv)) {
-- 
1.9.1

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drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall

[Sagar Arun Kamble]

v2: Updated tasks and frequency post reset.
v3: Added DFPS param update for MAX_FPS and FPS Stall.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/intel_slpc.c   | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 +++++
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cfe6dac..0efb3f8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1140,7 +1140,7 @@ static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
 	return ret;
 }
 
-static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
 				   enum slpc_param_id enable_id,
 				   enum slpc_param_id disable_id)
 {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index bf0840a..4356dfa 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -292,9 +292,38 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	u64 val;
+
 	host2guc_slpc_reset(dev_priv);
 	dev_priv->guc.slpc.enabled = true;
 
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_GTPERF,
+				SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_BALANCER,
+				SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_DCC,
+				SLPC_PARAM_TASK_DISABLE_DCC);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
+			     1);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
+			     1);
+
 	return;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 3d2e4ce..a1e573e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -181,4 +181,9 @@ void intel_slpc_set_param(struct drm_i915_private *dev_priv, enum slpc_param_id
 void intel_slpc_get_param(struct drm_i915_private *dev_priv, enum slpc_param_id id,
 			  int *overriding, u32 *value);
 void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
+
+/* i915_debugfs.c */
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+			    enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id);
 #endif
-- 
1.9.1

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drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

[Sagar Arun Kamble]

With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6dc33cf..a0b0b3c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4969,7 +4969,14 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(GEN6_RP_CONTROL, 0);
+	uint32_t rp_ctl = 0;
+
+	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
+	if (i915.enable_slpc)
+		rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
+
+	I915_WRITE(GEN6_RP_CONTROL, rp_ctl);
+
 	dev_priv->rps.enabled = false;
 }
 
-- 
1.9.1

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drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC

[Sagar Arun Kamble]

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 63 ++++++++++++++--------------
 drivers/gpu/drm/i915/intel_guc_loader.c | 12 +++---
 drivers/gpu/drm/i915/intel_slpc.c       | 28 ++++++++-----
 drivers/gpu/drm/i915/intel_slpc.h       | 73 ++++++++++++++++++++++-----------
 4 files changed, 103 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0efb3f8..961a125 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1359,10 +1359,10 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 	struct page *page;
 	void *pv = NULL;
 	struct slpc_shared_data data;
+	struct slpc_task_state_data *task_data;
 	int i, value;
 	enum slpc_global_state global_state;
 	enum slpc_platform_sku platform_sku;
-	enum slpc_host_os host_os;
 	enum slpc_power_plan power_plan;
 	enum slpc_power_source power_source;
 
@@ -1379,11 +1379,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 		data = *(struct slpc_shared_data *) pv;
 		kunmap_atomic(pv);
 
-		seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
-			   data.slpc_version >> 16,
-			   (data.slpc_version >> 8) & 0xFF,
-			   data.slpc_version & 0xFF,
-			   data.slpc_version);
 		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
 
 		global_state = (enum slpc_global_state) data.global_state;
@@ -1442,20 +1437,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 		seq_printf(m, "slice count: %d\n",
 			   data.platform_info.slice_count);
 
-		host_os = (enum slpc_host_os) data.platform_info.host_os;
-		seq_printf(m, "host OS: %d (", host_os);
-		switch (host_os) {
-		case SLPC_HOST_OS_UNDEFINED:
-			seq_puts(m, "undefined)\n");
-			break;
-		case SLPC_HOST_OS_WINDOWS_8:
-			seq_puts(m, "Windows 8)\n");
-			break;
-		default:
-			seq_puts(m, "unknown)\n");
-			break;
-		}
-
 		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
 			   data.platform_info.power_plan_source);
 		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
@@ -1502,17 +1483,37 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 			   data.platform_info.P1_freq * 50,
 			   data.platform_info.Pe_freq * 50,
 			   data.platform_info.Pn_freq * 50);
-		seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
-			   data.platform_info.package_rapl_limit_high,
-			   data.platform_info.package_rapl_limit_low);
-		seq_printf(m, "task state data: 0x%08x\n",
-			   data.task_state_data);
-		seq_printf(m, "\tturbo active: %d\n",
-			   (data.task_state_data & 1));
-		seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
-			   (data.task_state_data & 2),
-			   (data.task_state_data & 4),
-			   (data.task_state_data >> 3) & 0xFF);
+		task_data = &data.task_state_data;
+		seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+			   task_data->bitfield1, task_data->bitfield2);
+
+		seq_printf(m, "\tgtperf task active: %s\n",
+			   yesno(task_data->gtperf_task_active));
+		seq_printf(m, "\tgtperf stall possible: %s\n",
+			   yesno(task_data->gtperf_stall_possible));
+		seq_printf(m, "\tgtperf gaming mode: %s\n",
+			   yesno(task_data->gtperf_gaming_mode));
+		seq_printf(m, "\tgtperf target fps: %d\n",
+			   task_data->gtperf_target_fps);
+
+		seq_printf(m, "\tdcc task active: %s\n",
+			   yesno(task_data->dcc_task_active));
+		seq_printf(m, "\tin dcc: %s\n",
+			   yesno(task_data->in_dcc));
+		seq_printf(m, "\tin dct: %s\n",
+			   yesno(task_data->in_dct));
+		seq_printf(m, "\tfreq switch active: %d\n",
+			   task_data->freq_switch_active);
+
+		seq_printf(m, "\tibc enabled: %s\n", yesno(task_data->ibc_enabled));
+		seq_printf(m, "\tibc active: %s\n", yesno(task_data->ibc_active));
+		seq_printf(m, "\tpg1 enabled: %s\n", yesno(task_data->pg1_enabled));
+		seq_printf(m, "\tpg1 active: %s\n", yesno(task_data->pg1_active));
+
+		seq_printf(m, "\tunslice max freq: %d\n", task_data->freq_unslice_max);
+		seq_printf(m, "\tunslice min freq: %d\n", task_data->freq_unslice_min);
+		seq_printf(m, "\tslice max freq: %d\n", task_data->freq_slice_max);
+		seq_printf(m, "\tslice min freq: %d\n", task_data->freq_slice_min);
 
 		seq_puts(m, "override parameter bitfield\n");
 		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index a4ab8f9..c87d2c6 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -59,11 +59,11 @@
  *
  */
 
-#define SKL_FW_MAJOR 6
-#define SKL_FW_MINOR 1
+#define SKL_FW_MAJOR 9
+#define SKL_FW_MINOR 18
 
-#define BXT_FW_MAJOR 8
-#define BXT_FW_MINOR 7
+#define BXT_FW_MAJOR 9
+#define BXT_FW_MINOR 18
 
 #define KBL_FW_MAJOR 9
 #define KBL_FW_MINOR 14
@@ -165,8 +165,8 @@ static void sanitize_slpc_option(struct drm_device *dev)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
-	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
 		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
 	}
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 4356dfa..26cea21 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -224,12 +224,10 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
 		data = kmap_atomic(page);
 		memset(data, 0, sizeof(struct slpc_shared_data));
 
-		data->slpc_version = SLPC_VERSION;
 		data->shared_data_size = sizeof(struct slpc_shared_data);
 		data->global_state = (u32) SLPC_GLOBAL_STATE_NOT_RUNNING;
 		data->platform_info.platform_sku = slpc_get_platform_sku(&dev_priv->drm);
 		data->platform_info.slice_count = slpc_get_slice_count(&dev_priv->drm);
-		data->platform_info.host_os = (u8) SLPC_HOST_OS_WINDOWS_8;
 		data->platform_info.power_plan_source =
 			(u8) SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
 						    SLPC_POWER_SOURCE_AC);
@@ -239,10 +237,6 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
 		data->platform_info.P1_freq = (u8) (msr_value >> 8);
 		data->platform_info.Pe_freq = (u8) (msr_value >> 40);
 		data->platform_info.Pn_freq = (u8) (msr_value >> 48);
-		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
-		data->platform_info.package_rapl_limit_high =
-							(u32) (msr_value >> 32);
-		data->platform_info.package_rapl_limit_low = (u32) msr_value;
 
 		kunmap_atomic(data);
 	}
@@ -313,16 +307,28 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 				SLPC_PARAM_TASK_DISABLE_DCC);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
-			     1);
+			     SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+			     0);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+			     SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
 			     0);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
-			     1);
+			     SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			     0);
 
 	return;
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a1e573e..80f3559 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,10 +24,6 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
-#define SLPC_MAJOR_VER 2
-#define SLPC_MINOR_VER 4
-#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
-
 enum slpc_status {
 	SLPC_STATUS_OK = 0,
 	SLPC_STATUS_ERROR = 1,
@@ -45,14 +41,13 @@ enum slpc_status {
 	SLPC_STATUS_VALUE_ALREADY_SET = 13,
 	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
 	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
-	SLPC_STATUS_MISMATCHING_VERSION = 16,
-	SLPC_STATUS_MEMIO_ERROR = 17,
-	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
-	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
-	SLPC_STATUS_NO_EVENT_QUEUED = 20,
-	SLPC_STATUS_OUT_OF_SPACE = 21,
-	SLPC_STATUS_TIMEOUT = 22,
-	SLPC_STATUS_NO_LOCK = 23,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
 };
 
 enum slpc_event_id {
@@ -80,13 +75,16 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
 	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
 	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
-	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
 	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
-	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
 	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
 	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
 	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
-	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
 };
 
 #define SLPC_PARAM_TASK_DEFAULT 0
@@ -103,11 +101,6 @@ enum slpc_global_state {
 	SLPC_GLOBAL_STATE_ERROR = 5
 };
 
-enum slpc_host_os {
-	SLPC_HOST_OS_UNDEFINED = 0,
-	SLPC_HOST_OS_WINDOWS_8 = 1,
-};
-
 enum slpc_platform_sku {
 	SLPC_PLATFORM_SKU_UNDEFINED = 0,
 	SLPC_PLATFORM_SKU_ULX = 1,
@@ -140,25 +133,55 @@ enum slpc_power_source {
 struct slpc_platform_info {
 	u8 platform_sku;
 	u8 slice_count;
-	u8 host_os;
+	u8 reserved;
 	u8 power_plan_source;
 	u8 P0_freq;
 	u8 P1_freq;
 	u8 Pe_freq;
 	u8 Pn_freq;
-	u32 package_rapl_limit_high;
-	u32 package_rapl_limit_low;
+	u32 reserved1;
+	u32 reserved2;
 } __packed;
 
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 freq_unslice_max:8;
+			u32 freq_unslice_min:8;
+			u32 freq_slice_max:8;
+			u32 freq_slice_min:8;
+		};
+	};
+};
+
 #define SLPC_MAX_OVERRIDE_PARAMETERS 192
 #define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
 
 struct slpc_shared_data {
-	u32 slpc_version;
+	u32 reserved;
 	u32 shared_data_size;
 	u32 global_state;
 	struct slpc_platform_info platform_info;
-	u32 task_state_data;
+	struct slpc_task_state_data task_state_data;
 	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
 	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
 } __packed;
-- 
1.9.1

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drm/i915/slpc: Update freq min/max softlimits

[Sagar Arun Kamble]

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 26cea21..2bfb30f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -286,6 +286,10 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
 	u64 val;
 
 	host2guc_slpc_reset(dev_priv);
@@ -330,6 +334,32 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			     0);
 
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		intel_slpc_query_task_state(dev_priv);
+
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			pv = kmap_atomic(page);
+	}
+
+	if (pv) {
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		/*
+		 * TODO: Define separate variables for slice and unslice
+		 *	 frequencies for driver state variable.
+		 */
+		dev_priv->rps.max_freq_softlimit =
+				data.task_state_data.freq_unslice_max;
+		dev_priv->rps.min_freq_softlimit =
+				data.task_state_data.freq_unslice_min;
+
+		dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
+	}
+
 	return;
 }
 
-- 
1.9.1

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Re: drm/i915: Check GuC load status for Host to GuC action and SLPC status

[Deepak S]

On 20/08/16 10:39 AM, Sagar Arun Kamble wrote:
> Host to GuC actions should not be invoked when GuC isn't loaded hence
> add early return in i915_guc_action if GuC load status is not SUCCESS.
> Also, SLPC status has to be linked with GuC load status to make sure
> SLPC actions get invoked when GuC is loaded.
>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_submission.c | 5 +++++
>   drivers/gpu/drm/i915/intel_drv.h           | 4 ++++
>   2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 680d9b4..27c937b 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -78,6 +78,8 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
>   int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct intel_guc_fw *guc_fw = &guc->guc_fw;
> +
remove the blank line
>   	u32 status;
>   	int i;
>   	int ret;
> @@ -85,6 +87,9 @@ int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
>   	if (WARN_ON(len < 1 || len > 15))
>   		return -EINVAL;
>   
> +	if (WARN_ON(guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS))
> +		return -ENODEV;
> +
>   	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>   
>   	dev_priv->guc.action_count += 1;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c46d619..71936dc 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1694,8 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>   
>   static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
>   {
> +	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>   	int ret = 0;
>   
> +	if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> +		return 0;
> +
Since we are initializing ret=0, I think can do "return ret" right?
>   	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
>   		ret = 1;
>   

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✗ Ro.CI.BAT: failure for drm/i915/slpc: Add slpc support for max/min freq

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Add slpc support for max/min freq
URL   : https://patchwork.freedesktop.org/series/11356/
State : failure

== Summary ==

Series 11356v1 drm/i915/slpc: Add slpc support for max/min freq
http://patchwork.freedesktop.org/api/1.0/series/11356/revisions/1/mbox

Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> INCOMPLETE (fi-hsw-i7-4770k)
Test kms_cursor_legacy:
        Subgroup basic-cursor-vs-flip-legacy:
                pass       -> FAIL       (ro-byt-n2820)
                dmesg-warn -> FAIL       (ro-bdw-i5-5250u)
        Subgroup basic-cursor-vs-flip-varying-size:
                dmesg-warn -> PASS       (ro-bdw-i5-5250u)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> SKIP       (ro-bdw-i5-5250u)
        Subgroup suspend-read-crc-pipe-c:
                skip       -> DMESG-WARN (ro-bdw-i5-5250u)

fi-hsw-i7-4770k  total:107  pass:91   dwarn:0   dfail:0   fail:0   skip:15 
fi-kbl-qkkr      total:244  pass:185  dwarn:30  dfail:0   fail:2   skip:27 
fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22 
fi-snb-i7-2600   total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
ro-bdw-i5-5250u  total:240  pass:219  dwarn:2   dfail:0   fail:1   skip:18 
ro-bdw-i7-5600u  total:240  pass:206  dwarn:0   dfail:0   fail:2   skip:32 
ro-bsw-n3050     total:240  pass:195  dwarn:0   dfail:0   fail:3   skip:42 
ro-byt-n2820     total:240  pass:195  dwarn:0   dfail:0   fail:5   skip:40 
ro-hsw-i3-4010u  total:240  pass:213  dwarn:0   dfail:0   fail:1   skip:26 
ro-hsw-i7-4770r  total:240  pass:185  dwarn:0   dfail:0   fail:0   skip:55 
ro-ilk1-i5-650   total:235  pass:174  dwarn:0   dfail:0   fail:2   skip:59 
ro-ivb-i7-3770   total:240  pass:204  dwarn:0   dfail:0   fail:1   skip:35 
ro-ivb2-i7-3770  total:240  pass:208  dwarn:0   dfail:0   fail:1   skip:31 
ro-skl3-i5-6260u total:240  pass:223  dwarn:0   dfail:0   fail:3   skip:14 
ro-bdw-i7-5557U failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1950/

f53a8d1 drm-intel-nightly: 2016y-08m-19d-16h-24m-21s UTC integration manifest
d2008dd drm/i915/slpc: Expose guc functions for use with SLPC

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Re: drm/i915/slpc: Update freq min/max softlimits

[Chris Wilson]

On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:
> +	obj = dev_priv->guc.slpc.vma->obj;
> +	if (obj) {

OOPS.

> +		intel_slpc_query_task_state(dev_priv);
> +
> +		page = i915_gem_object_get_page(obj, 0);
> +		if (page)
> +			pv = kmap_atomic(page);
> +	}
> +
> +	if (pv) {
> +		data = *(struct slpc_shared_data *) pv;
> +		kunmap_atomic(pv);

Can kmap_atomic return zero?

> +
> +		/*
> +		 * TODO: Define separate variables for slice and unslice
> +		 *	 frequencies for driver state variable.
> +		 */
> +		dev_priv->rps.max_freq_softlimit =
> +				data.task_state_data.freq_unslice_max;
> +		dev_priv->rps.min_freq_softlimit =
> +				data.task_state_data.freq_unslice_min;

These are user values, you do not get to arbitrarily rewrite them.

You control dev_priv->rps.[min|max]_freq.
-Chris

-- 
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Re: drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:00AM +0530, Sagar Arun Kamble wrote:
> For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for
> other platforms as RC6 and RPS enabling is indicated by rps.enabled.
> RPM Suspend depends only on RC6, so we need to remove the check of rps.enabled.
> For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
> for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other GENs
> this check can be completely removed.
> Moved setting of rps.enabled to platform level functions as there is case of
> disabling of RPS in gen9_enable_rps.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 10 +++++++++-
>  drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++--
>  2 files changed, 27 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 13ae340..bc2c67b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2284,9 +2284,17 @@ static int intel_runtime_suspend(struct device *device)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int ret;
>  
> -	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
> +	if (WARN_ON_ONCE(!intel_enable_rc6()))
>  		return -ENODEV;
>  
> +	/*
> +	 * Once RC6 and RPS enabling is separated for non-GEN9 platforms
> +	 * below check should be removed.
> +	*/
> +	if (!IS_GEN9(dev))

IS_GEN9(dev_priv)

> +		if (WARN_ON_ONCE(!dev_priv->rps.enabled))
> +			return -ENODEV;
> +
>  	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))

And while at it you could change this one too. Eventually
all feature macros will be modified to take only dev_priv,
and having things slowly migrate while other things are
changed will make that transition easier.

>  		return -ENODEV;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 99014d7..954e332 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4966,6 +4966,7 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
>  static void gen9_disable_rps(struct drm_i915_private *dev_priv)
>  {
>  	I915_WRITE(GEN6_RP_CONTROL, 0);
> +	dev_priv->rps.enabled = false;
>  }

Inconsistent coding style -- all other functions like this have a
newline before that line you added.
 
>  static void gen6_disable_rps(struct drm_i915_private *dev_priv)
> @@ -4973,11 +4974,16 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN6_RC_CONTROL, 0);
>  	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
>  	I915_WRITE(GEN6_RP_CONTROL, 0);
> +
> +	dev_priv->rps.enabled = false;
> +
>  }

Don't add an extra newline after that statement, please.

>  static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
>  {
>  	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> +	dev_priv->rps.enabled = false;
>  }
>  
>  static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
> @@ -4989,6 +4995,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN6_RC_CONTROL, 0);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> +	dev_priv->rps.enabled = false;
>  }
>  
>  static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
> @@ -5206,6 +5214,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
>  	reset_rps(dev_priv, gen6_set_rps);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> +	dev_priv->rps.enabled = true;
>  }
>  
>  static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -5349,6 +5359,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
>  	reset_rps(dev_priv, gen6_set_rps);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> +	dev_priv->rps.enabled = true;
>  }
>  
>  static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> @@ -5445,6 +5457,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
>  	}
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> +	dev_priv->rps.enabled = true;
>  }
>  
>  static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> @@ -5919,6 +5933,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
>  	reset_rps(dev_priv, valleyview_set_rps);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> +	dev_priv->rps.enabled = true;
>  }
>  
>  static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
> @@ -5999,6 +6015,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
>  	reset_rps(dev_priv, valleyview_set_rps);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> +	dev_priv->rps.enabled = true;
>  }
>  
>  static unsigned long intel_pxfreq(u32 vidfreq)
> @@ -6588,7 +6606,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
>  		ironlake_disable_drps(dev_priv);
>  	}
>  
> -	dev_priv->rps.enabled = false;
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  }
>  
> @@ -6632,7 +6649,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>  	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
>  	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
>  
> -	dev_priv->rps.enabled = true;
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  }

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

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Re: drm/i915/slpc: Expose guc functions for use with SLPC

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:01AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> Expose host2guc_action for use by SLPC in intel_slpc.c.
> 
> Expose functions to allocate and release objects used
> by GuC to be used for SLPC shared memory object.
> 
> v5: Updated function names as they need to be made extern. (ChrisW)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_submission.c | 16 ++++++++--------
>  drivers/gpu/drm/i915/intel_guc.h           |  2 ++
>  2 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index bb40792..680d9b4 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -47,7 +47,7 @@
>   * Firmware writes a success/fail code back to the action register after
>   * processes the request. The kernel driver polls waiting for this update and
>   * then proceeds.
> - * See host2guc_action()
> + * See i915_guc_action()
>   *
>   * Doorbells:
>   * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
> @@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
>  	return GUC2HOST_IS_RESPONSE(val);
>  }
>  
> -static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
> +int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
>  {
>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>  	u32 status;
> @@ -141,7 +141,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
>  	data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
>  	data[1] = client->ctx_index;
>  
> -	return host2guc_action(guc, data, 2);
> +	return i915_guc_action(guc, data, 2);
>  }
>  
>  static int host2guc_release_doorbell(struct intel_guc *guc,
> @@ -152,7 +152,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
>  	data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
>  	data[1] = client->ctx_index;
>  
> -	return host2guc_action(guc, data, 2);
> +	return i915_guc_action(guc, data, 2);
>  }
>  
>  static int host2guc_sample_forcewake(struct intel_guc *guc,
> @@ -169,7 +169,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
>  		/* bit 0 and 1 are for Render and Media domain separately */
>  		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
>  
> -	return host2guc_action(guc, data, ARRAY_SIZE(data));
> +	return i915_guc_action(guc, data, ARRAY_SIZE(data));
>  }
>  
>  /*
> @@ -621,7 +621,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
>   *
>   * Return:	A i915_vma if successful, otherwise an ERR_PTR.
>   */
> -static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
> +struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
>  {
>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>  	struct drm_i915_gem_object *obj;
> @@ -1066,7 +1066,7 @@ int intel_guc_suspend(struct drm_device *dev)
>  	/* first page is shared data with GuC */
>  	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
>  
> -	return host2guc_action(guc, data, ARRAY_SIZE(data));
> +	return i915_guc_action(guc, data, ARRAY_SIZE(data));
>  }
>  
>  
> @@ -1091,5 +1091,5 @@ int intel_guc_resume(struct drm_device *dev)
>  	/* first page is shared data with GuC */
>  	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
>  
> -	return host2guc_action(guc, data, ARRAY_SIZE(data));
> +	return i915_guc_action(guc, data, ARRAY_SIZE(data));
>  }
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index c973262..9e6b948 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
>  extern int intel_guc_resume(struct drm_device *dev);
>  
>  /* i915_guc_submission.c */
> +int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
>  int i915_guc_submission_init(struct drm_i915_private *dev_priv);
>  int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
>  int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
> +struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
>  void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
>  void i915_guc_submission_fini(struct drm_i915_private *dev_priv);

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

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//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Sanitize SLPC version

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:05AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> The SLPC interface has changed and could continue to
> change.  Only GuC versions known to be compatible are
> supported here.
> 
> On Skylake, GuC firmware v6 is supported.  Other
> platforms and versions can be added here later.
> 
> v5: Updated with modified sanitize_slpc_option in earlier patch.
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_loader.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 75b360f..6765edf 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -146,6 +146,9 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
>  
>  static void sanitize_slpc_option(struct drm_device *dev)
>  {
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +
>  	/* Handle default case */
>  	if (i915.enable_slpc < 0)
>  		i915.enable_slpc = HAS_SLPC(dev);
> @@ -161,6 +164,9 @@ static void sanitize_slpc_option(struct drm_device *dev)
>  	/* slpc requires guc submission */
>  	if (!i915.enable_guc_submission)
>  		i915.enable_slpc = 0;
> +
> +	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
> +		i915.enable_slpc = 0;
>  }
>  
>  static u32 get_gttype(struct drm_i915_private *dev_priv)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
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Re: drm/i915/slpc: Add SKL SLPC Support

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:03AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> This patch adds has_slpc to skylake info.
> 
> The SLPC interface has changed and could continue to
> change.  Only GuC versions known to be compatible are
> supported here.
> 
> On Skylake, GuC firmware v6 is supported.  Other
> platforms and versions can be added here later.
> 
> v2: Move slpc_version_check to intel_guc_ucode_init
> v3: fix whitespace (Sagar)
> v5: Moved version check to different patch as has_slpc
>     should not be updated based on it. Instead module paramter
>     should be updated based on version check. (Sagar)
>     Added support to skylake_gt3 as well. (Sagar)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 2587b1b..e678051 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -322,12 +322,14 @@ static const struct intel_device_info intel_skylake_info = {
>  	BDW_FEATURES,
>  	.is_skylake = 1,
>  	.gen = 9,
> +	.has_slpc = 1,
>  };
>  
>  static const struct intel_device_info intel_skylake_gt3_info = {
>  	BDW_FEATURES,
>  	.is_skylake = 1,
>  	.gen = 9,
> +	.has_slpc = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Add has_slpc capability flag

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:02AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> Add has_slpc capablity flag to indicate GuC firmware
> supports single loop power control (SLPC).  SLPC is
> a replacement for some host-based power management
> features.
> 
> v2: fix whitespace (Sagar)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 35caa9b..764fad0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -646,6 +646,7 @@ struct intel_csr {
>  	func(is_kabylake) sep \
>  	func(is_preliminary) sep \
>  	func(has_fbc) sep \
> +	func(has_slpc) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2800,6 +2801,7 @@ struct drm_i915_cmd_table {
>  #define HAS_GUC(dev)		(IS_GEN9(dev))
>  #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
>  #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
> +#define HAS_SLPC(dev)		(INTEL_INFO(dev)->has_slpc)
>  
>  #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
>  				    INTEL_INFO(dev)->gen >= 8)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Enable SLPC in guc if supported

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:07AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> If slpc enabled, then add enable SLPC flag to guc
> control parameter during guc load.
> 
> v2: Use intel_slpc_enabled() (Paulo)
> 
> v5: Rebase. (Sagar)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 6765edf..2edd255 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -212,6 +212,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
>  	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
>  			GUC_CTL_VCS2_ENABLED;
>  
> +	if (intel_slpc_enabled())
> +		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
> +
>  	if (i915.guc_log_level >= 0) {
>  		params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
>  		params[GUC_CTL_DEBUG] =

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Update current requested frequency

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:10AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> When SLPC is controlling requested frequency, the rps.cur_freq
> value is not used to make the frequency request.
> 
> Before using rps.cur_freq in sysfs or debugfs, read
> requested frequency from register to get the value
> most recently requested by SLPC firmware.
> 
> v2: replace HAS_SLPC with intel_slpc_active (Paulo)
> v3: Avoid magic numbers (Nick)
>     Use a function for repeated code (Jon)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  drivers/gpu/drm/i915/i915_sysfs.c   | 8 ++++++++
>  4 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 01ae5ee..a99a3f6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1110,6 +1110,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  
>  	intel_runtime_pm_get(dev_priv);
>  
> +	if (intel_slpc_active(dev_priv))
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
> +
>  	if (IS_GEN5(dev)) {
>  		u16 rgvswctl = I915_READ16(MEMSWCTL);
>  		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
> @@ -2372,6 +2375,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct drm_file *file;
>  
> +	if (intel_slpc_active(dev_priv))
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
> +
>  	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
>  	seq_printf(m, "GPU busy? %s [%x]\n",
>  		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 764fad0..fcd2e98 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3913,4 +3913,9 @@ bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
>  	__T;								\
>  })
>  
> +static inline u8 gen9_read_requested_freq(struct drm_i915_private *dev_priv)
> +{
> +	return (u8) GEN9_GET_FREQUENCY(I915_READ(GEN6_RPNSWREQ));
> +}
> +
>  #endif
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4adf28..1654245 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6997,6 +6997,7 @@ enum {
>  #define   GEN6_FREQUENCY(x)			((x)<<25)
>  #define   HSW_FREQUENCY(x)			((x)<<24)
>  #define   GEN9_FREQUENCY(x)			((x)<<23)
> +#define   GEN9_GET_FREQUENCY(x)			((x)>>23)
>  #define   GEN6_OFFSET(x)			((x)<<19)
>  #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
>  #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index f1ffde7..8404816 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -302,6 +302,14 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>  	struct drm_device *dev = minor->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> +	if (intel_slpc_active(dev_priv)) {
> +		intel_runtime_pm_get(dev_priv);
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +		intel_runtime_pm_put(dev_priv);
> +	}
> +
>  	return snprintf(buf, PAGE_SIZE, "%d\n",
>  			intel_gpu_freq(dev_priv,
>  				       dev_priv->rps.cur_freq));

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Send reset event

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:11AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> Add host2guc SLPC reset event and send reset event
> during enable.
> 
> v2: extract host2guc_slpc to handle slpc status code
>     coding style changes (Paulo)
> 
> v5: Removed WARN_ON for checking msb of gtt address of
>     shared gem obj. (ChrisW)
>     host2guc_action to i915_guc_action change.(Sagar)
>     Updating SLPC enabled status. (Sagar)

Wait, what? From v2 to v5? Whatever happened to v3 & v4?

> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_slpc.c | 29 +++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
>  2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> index ba5b23a..161cd13 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -26,6 +26,32 @@
>  #include "i915_drv.h"
>  #include "intel_guc.h"
>  
> +static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
> +{
> +	int ret = i915_guc_action(&dev_priv->guc, data, len);
> +
> +	if (!ret) {
> +		ret = I915_READ(SOFT_SCRATCH(1));
> +		ret &= SLPC_EVENT_STATUS_MASK;
> +	}
> +
> +	if (ret)
> +		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
> +}
> +
> +static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
> +{
> +	u32 data[4];
> +	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
> +
> +	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
> +	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
> +	data[2] = shared_data_gtt_offset;
> +	data[3] = 0;
> +
> +	host2guc_slpc(dev_priv, data, 4);
> +}
> +
>  static u8 slpc_get_platform_sku(struct drm_device *dev)
>  {
>  	enum slpc_platform_sku platform_sku;
> @@ -133,6 +159,9 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
>  
>  void intel_slpc_enable(struct drm_i915_private *dev_priv)
>  {
> +	host2guc_slpc_reset(dev_priv);
> +	dev_priv->guc.slpc.enabled = true;
> +
>  	return;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
> index e951289..031e36b 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_slpc.h
> @@ -28,6 +28,20 @@
>  #define SLPC_MINOR_VER 4
>  #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
>  
> +enum slpc_event_id {
> +	SLPC_EVENT_RESET = 0,
> +	SLPC_EVENT_SHUTDOWN = 1,
> +	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
> +	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
> +	SLPC_EVENT_FLIP_COMPLETE = 4,
> +	SLPC_EVENT_QUERY_TASK_STATE = 5,
> +	SLPC_EVENT_PARAMETER_SET = 6,
> +	SLPC_EVENT_PARAMETER_UNSET = 7,
> +};
> +
> +#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
> +#define SLPC_EVENT_STATUS_MASK	0xFF
> +
>  enum slpc_global_state {
>  	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
>  	SLPC_GLOBAL_STATE_INITIALIZING = 1,

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Add enable_slpc module parameter

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:04AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> i915.enable_slpc is used to override the default for slpc usage.
> The expected values are -1=auto, 0=disabled [default], 1=enabled.
> 
> slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
> Interpretation of default value is based on HAS_SLPC(), after
> slpc_version_check().  This function also enforces the requirement
> that guc_submission is required for slpc.
> 
> intel_slpc_enabled() returns 1 if SLPC should be used.
> 
> v2: Add early call to sanitize enable_slpc in intel_guc_ucode_init
> 
> v5: Remove sanitize enable_slpc call before firmware version check
>     is performed. (ChrisW)
>     Version check is added in next patch and that will be done as
>     part of slpc_enable_sanitize function in the next patch. (Sagar)
>     Updated slpc option sanitize function call for platforms without
>     GuC support. This was caught by CI BAT.
> 
> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
>  drivers/gpu/drm/i915/i915_params.h      |  1 +
>  drivers/gpu/drm/i915/intel_guc.h        |  6 ++++++
>  drivers/gpu/drm/i915/intel_guc_loader.c | 30 ++++++++++++++++++++++++++----
>  4 files changed, 39 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 768ad89..72b3097 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
>  	.enable_dc = -1,
>  	.enable_fbc = -1,
>  	.enable_execlists = -1,
> +	.enable_slpc = 0,
>  	.enable_hangcheck = true,
>  	.enable_ppgtt = -1,
>  	.enable_psr = -1,
> @@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
>  	"Override execlists usage. "
>  	"(-1=auto [default], 0=disabled, 1=enabled)");
>  
> +module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
> +MODULE_PARM_DESC(enable_slpc,
> +	"Override single-loop-power-controller (slpc) usage. "
> +	"(-1=auto, 0=disabled [default], 1=enabled)");
> +
>  module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
>  MODULE_PARM_DESC(enable_psr, "Enable PSR "
>  		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 3a0dd78..391c471 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -39,6 +39,7 @@ struct i915_params {
>  	int enable_fbc;
>  	int enable_ppgtt;
>  	int enable_execlists;
> +	int enable_slpc;
>  	int enable_psr;
>  	unsigned int preliminary_hw_support;
>  	int disable_power_well;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 9e6b948..27a7459 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -146,6 +146,12 @@ struct intel_guc {
>  	uint32_t last_seqno[I915_NUM_ENGINES];
>  };
>  
> +static inline int intel_slpc_enabled(void)
> +{
> +        WARN_ON(i915.enable_slpc < 0);
> +        return i915.enable_slpc;
> +}
> +
>  /* intel_guc_loader.c */
>  extern void intel_guc_init(struct drm_device *dev);
>  extern int intel_guc_setup(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 324812d..75b360f 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void sanitize_slpc_option(struct drm_device *dev)
> +{
> +	/* Handle default case */
> +	if (i915.enable_slpc < 0)
> +		i915.enable_slpc = HAS_SLPC(dev);
> +
> +	/* slpc requires hardware support and compatible firmware */
> +	if (!HAS_SLPC(dev))
> +		i915.enable_slpc = 0;

I'd prefer if you pass dev_priv to HAS_SLPC
(and thus pass in drm_i915_private * to the function instead).

> +
> +	/* slpc requires guc loaded */
> +	if (!i915.enable_guc_loading)
> +		i915.enable_slpc = 0;
> +
> +	/* slpc requires guc submission */
> +	if (!i915.enable_guc_submission)
> +		i915.enable_slpc = 0;
> +}
> +
>  static u32 get_gttype(struct drm_i915_private *dev_priv)
>  {
>  	/* XXX: GT type based on PCI device ID? field seems unused by fw */
> @@ -728,18 +747,21 @@ void intel_guc_init(struct drm_device *dev)
>  	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
>  	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
>  
> -	/* Early (and silent) return if GuC loading is disabled */
> +	/* Return if GuC loading is disabled sanitizing SLPC option */
>  	if (!i915.enable_guc_loading)
> -		return;
> +		goto out;
>  	if (fw_path == NULL)
> -		return;
> +		goto out;
>  	if (*fw_path == '\0')
> -		return;
> +		goto out;
>  
>  	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
>  	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
>  	guc_fw_fetch(dev, guc_fw);
>  	/* status must now be FAIL or SUCCESS */
> +
> +out:
> +	sanitize_slpc_option(dev);
>  }
>  
>  /**

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Update current requested frequency

[Chris Wilson]

On Sat, Aug 20, 2016 at 10:39:10AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> When SLPC is controlling requested frequency, the rps.cur_freq
> value is not used to make the frequency request.
> 
> Before using rps.cur_freq in sysfs or debugfs, read
> requested frequency from register to get the value
> most recently requested by SLPC firmware.
> 
> v2: replace HAS_SLPC with intel_slpc_active (Paulo)
> v3: Avoid magic numbers (Nick)
>     Use a function for repeated code (Jon)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  drivers/gpu/drm/i915/i915_sysfs.c   | 8 ++++++++
>  4 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 01ae5ee..a99a3f6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1110,6 +1110,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  
>  	intel_runtime_pm_get(dev_priv);
>  
> +	if (intel_slpc_active(dev_priv))
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);

Do not alter cur_freq here, as we print out RPNSWEQ and updating
cur_freq defeats the purpose of showing the internal value vs the hw
value.

Instead add "SLPC active" to the output.

> +
>  	if (IS_GEN5(dev)) {
>  		u16 rgvswctl = I915_READ16(MEMSWCTL);
>  		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
> @@ -2372,6 +2375,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct drm_file *file;

if (intel_slpc_active(dev_priv))
	return -ENODEV;
>  
> +	if (intel_slpc_active(dev_priv))
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
> +
>  	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
>  	seq_printf(m, "GPU busy? %s [%x]\n",
>  		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 764fad0..fcd2e98 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3913,4 +3913,9 @@ bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
>  	__T;								\
>  })
>  
> +static inline u8 gen9_read_requested_freq(struct drm_i915_private *dev_priv)
> +{
> +	return (u8) GEN9_GET_FREQUENCY(I915_READ(GEN6_RPNSWREQ));
> +}

Move to sysfs and look carefully at what you wrote.

>  #endif
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4adf28..1654245 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6997,6 +6997,7 @@ enum {
>  #define   GEN6_FREQUENCY(x)			((x)<<25)
>  #define   HSW_FREQUENCY(x)			((x)<<24)
>  #define   GEN9_FREQUENCY(x)			((x)<<23)
> +#define   GEN9_GET_FREQUENCY(x)			((x)>>23)
>  #define   GEN6_OFFSET(x)			((x)<<19)
>  #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
>  #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index f1ffde7..8404816 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -302,6 +302,14 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>  	struct drm_device *dev = minor->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> +	if (intel_slpc_active(dev_priv)) {
> +		intel_runtime_pm_get(dev_priv);

Use get_if_in_use and just show a stale value when the hw is asleep
would be my preference. cur_freq is just our request, act_freq is the
actual hw value.

> +		mutex_lock(&dev_priv->rps.hw_lock);

Useless mutex.

> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +		intel_runtime_pm_put(dev_priv);
> +	}
> +
>  	return snprintf(buf, PAGE_SIZE, "%d\n",
>  			intel_gpu_freq(dev_priv,
>  				       dev_priv->rps.cur_freq));
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: drm/i915/slpc: Send shutdown event

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:12AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> Send SLPC shutdown event during disable, suspend, and reset
> operations.  Sending shutdown event while already shutdown
> is OK.
> 
> v2: return void instead of ignored error code (Paulo)
> 
> v5: Removed WARN_ON for checking msb of gtt address of
>     shared gem obj. (ChrisW)
>     Added SLPC state update during disable, suspend and reset.
>     Changed semantics of reset. It is supposed to just disable. (Sagar)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_slpc.c | 22 +++++++++++++++++++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> index 161cd13..5a1e6f2 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
>  	host2guc_slpc(dev_priv, data, 4);
>  }
>  
> +static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
> +{
> +	u32 data[4];
> +	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
> +
> +	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
> +	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
> +	data[2] = shared_data_gtt_offset;
> +	data[3] = 0;
> +
> +	host2guc_slpc(dev_priv, data, 4);
> +}
> +
>  static u8 slpc_get_platform_sku(struct drm_device *dev)
>  {
>  	enum slpc_platform_sku platform_sku;
> @@ -149,12 +162,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
>  
>  void intel_slpc_suspend(struct drm_i915_private *dev_priv)
>  {
> -	return;
> +	host2guc_slpc_shutdown(dev_priv);
> +	dev_priv->guc.slpc.enabled = false;
>  }
>  
>  void intel_slpc_disable(struct drm_i915_private *dev_priv)
>  {
> -	return;
> +	host2guc_slpc_shutdown(dev_priv);
> +	dev_priv->guc.slpc.enabled = false;
>  }
>  
>  void intel_slpc_enable(struct drm_i915_private *dev_priv)
> @@ -167,5 +182,6 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
>  
>  void intel_slpc_reset(struct drm_i915_private *dev_priv)
>  {
> -	return;
> +	host2guc_slpc_shutdown(dev_priv);
> +	dev_priv->guc.slpc.enabled = false;
>  }

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: Add support for GuC-based SLPC

[Chris Wilson]

On Sat, Aug 20, 2016 at 10:38:59AM +0530, Sagar Arun Kamble wrote:
> This series has been tested with SKL GuC firmware
> version 9.18 which is yet to be released. Performance and
> power testing with these patches and 9.18 firmware is at
> parity and in some cases better than host solution today
> on various Linux benchmarks.

Patches pending to support your claims?
-Chris

-- 
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Re: drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:09AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> SLPC shared data is used to pass information
> to/from SLPC in GuC firmware.
> 
> For Skylake, platform sku type and slice count
> are identified from device id and fuse values.
> 
> Support for other platforms needs to be added.
> 
> v2: Update for SLPC interface version 2015.2.4
>     intel_slpc_active() returns 1 if slpc initialized (Paulo)
> v3: change default host_os to "Windows"
> v4: Spelling fixes (Sagar Kamble and Nick Hoath)
> v5: Added WARN for checking if upper 32bits of GTT offset
>     of shared object are zero. (ChrisW)
>     Changed function call from gem_allocate/release_guc_obj to
>     i915_guc_allocate/release_gem_obj. (Sagar)
>     Updated commit message and moved POWER_PLAN and POWER_SOURCE
>     definition from later patch. (Akash)
>     Add struct_mutex locking while allocating/releasing slpc shared
>     object. This was caught by CI BAT. Adding SLPC state variable
>     to determine if it is active as it not just dependent on shared
>     data setup.
>     Rebase with guc_allocate_vma related changes.
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
>  drivers/gpu/drm/i915/intel_guc.h  |  2 +
>  drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
>  drivers/gpu/drm/i915/intel_slpc.c | 90 ++++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_slpc.h | 78 +++++++++++++++++++++++++++++++++
>  5 files changed, 178 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 16fe13d..c46d619 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1694,7 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>  
>  static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
>  {
> -	return 0;
> +	int ret = 0;
> +
> +	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
> +		ret = 1;
> +
> +	return ret;
>  }
>  
>  /* intel_pm.c */
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index cd23c4e..4a551f6 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -145,6 +145,8 @@ struct intel_guc {
>  
>  	uint64_t submissions[I915_NUM_ENGINES];
>  	uint32_t last_seqno[I915_NUM_ENGINES];
> +
> +	struct intel_slpc slpc;
>  };
>  
>  static inline int intel_slpc_enabled(void)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3b3f487..6dc33cf 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6559,7 +6559,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>  
>  void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>  {
> -	if (intel_slpc_enabled())
> +	if (intel_slpc_enabled() &&
> +	    dev_priv->guc.slpc.vma)
>  		intel_slpc_cleanup(dev_priv);
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		valleyview_cleanup_gt_powersave(dev_priv);
> @@ -6649,7 +6650,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
> -	if (intel_slpc_enabled()) {
> +	if (intel_slpc_enabled() &&
> +	    dev_priv->guc.slpc.vma) {
>  		gen9_enable_rc6(dev_priv);
>  		intel_slpc_enable(dev_priv);
>  		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> index b2e8d91..ba5b23a 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -22,17 +22,103 @@
>   *
>   */
>  #include <linux/firmware.h>
> +#include <asm/msr-index.h>
>  #include "i915_drv.h"
>  #include "intel_guc.h"
>  
> +static u8 slpc_get_platform_sku(struct drm_device *dev)
> +{
> +	enum slpc_platform_sku platform_sku;
> +
> +	if (IS_SKL_ULX(dev))
> +		platform_sku = SLPC_PLATFORM_SKU_ULX;
> +	else if (IS_SKL_ULT(dev))
> +		platform_sku = SLPC_PLATFORM_SKU_ULT;

dev_priv for the two of these, pass in drm_i915_private *
instead.

> +	else
> +		platform_sku = SLPC_PLATFORM_SKU_DT;
> +
> +	return (u8) platform_sku;

(u8)platform_sku;

But the cast isn't a good idea here. In the case where your
enum ever grows to have so many entries that it no longer fits
in an u8, or if you use negative values in the enum, you'd
want a warning, not a cast that silences it.

> +}
> +
> +static u8 slpc_get_slice_count(struct drm_device *dev)
> +{
> +	u8 slice_count = 1;
> +
> +	if (IS_SKYLAKE(dev))
> +		slice_count = INTEL_INFO(dev)->slice_total;

dev_priv, dev_priv, drm_i915_private * passed in.
> +
> +	return slice_count;
> +}
> +
> +static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_i915_gem_object *obj;
> +	struct page *page;
> +	struct slpc_shared_data *data;
> +	u64 msr_value;
> +
> +	if (!dev_priv->guc.slpc.vma)
> +		return;
> +
> +	obj = dev_priv->guc.slpc.vma->obj;
> +
> +	page = i915_gem_object_get_page(obj, 0);
> +	if (page) {
> +		data = kmap_atomic(page);
> +		memset(data, 0, sizeof(struct slpc_shared_data));
> +
> +		data->slpc_version = SLPC_VERSION;
> +		data->shared_data_size = sizeof(struct slpc_shared_data);
> +		data->global_state = (u32) SLPC_GLOBAL_STATE_NOT_RUNNING;
> +		data->platform_info.platform_sku = slpc_get_platform_sku(&dev_priv->drm);
> +		data->platform_info.slice_count = slpc_get_slice_count(&dev_priv->drm);

If you follow my advice above you can pass dev_priv here.

> +		data->platform_info.host_os = (u8) SLPC_HOST_OS_WINDOWS_8;
> +		data->platform_info.power_plan_source =
> +			(u8) SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
> +						    SLPC_POWER_SOURCE_AC);
> +		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
> +		data->platform_info.P0_freq = (u8) msr_value;
> +		rdmsrl(MSR_PLATFORM_INFO, msr_value);
> +		data->platform_info.P1_freq = (u8) (msr_value >> 8);
> +		data->platform_info.Pe_freq = (u8) (msr_value >> 40);
> +		data->platform_info.Pn_freq = (u8) (msr_value >> 48);

No spaces after the cast.

> +		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
> +		data->platform_info.package_rapl_limit_high =
> +							(u32) (msr_value >> 32);
> +		data->platform_info.package_rapl_limit_low = (u32) msr_value;

And again for these.

> +
> +		kunmap_atomic(data);
> +	}
> +}
> +
>  void intel_slpc_init(struct drm_i915_private *dev_priv)
>  {
> -	return;
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct i915_vma *vma;
> +
> +	/* Allocate shared data structure */
> +	vma = dev_priv->guc.slpc.vma;
> +	if (!vma) {
> +		vma = guc_allocate_vma(guc,
> +				       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
> +		if (IS_ERR(vma)) {
> +			DRM_ERROR("slpc_shared_data allocation failed\n");
> +			i915.enable_slpc = 0;
> +			return;
> +		}
> +
> +		dev_priv->guc.slpc.vma = vma;
> +	}
> +
> +	slpc_shared_data_init(dev_priv);
>  }
>  
>  void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
>  {
> -	return;
> +	struct intel_guc *guc = &dev_priv->guc;
> +
> +	/* Release shared data structure */
> +	i915_vma_unpin_and_release(&guc->slpc.vma);
>  }
>  
>  void intel_slpc_suspend(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
> index ae52146..e951289 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_slpc.h
> @@ -24,6 +24,84 @@
>  #ifndef _INTEL_SLPC_H_
>  #define _INTEL_SLPC_H_
>  
> +#define SLPC_MAJOR_VER 2
> +#define SLPC_MINOR_VER 4
> +#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
> +
> +enum slpc_global_state {
> +	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
> +	SLPC_GLOBAL_STATE_INITIALIZING = 1,
> +	SLPC_GLOBAL_STATE_RESETTING = 2,
> +	SLPC_GLOBAL_STATE_RUNNING = 3,
> +	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
> +	SLPC_GLOBAL_STATE_ERROR = 5
> +};
> +
> +enum slpc_host_os {
> +	SLPC_HOST_OS_UNDEFINED = 0,
> +	SLPC_HOST_OS_WINDOWS_8 = 1,
> +};
> +
> +enum slpc_platform_sku {
> +	SLPC_PLATFORM_SKU_UNDEFINED = 0,
> +	SLPC_PLATFORM_SKU_ULX = 1,
> +	SLPC_PLATFORM_SKU_ULT = 2,
> +	SLPC_PLATFORM_SKU_T = 3,
> +	SLPC_PLATFORM_SKU_MOBL = 4,
> +	SLPC_PLATFORM_SKU_DT = 5,
> +	SLPC_PLATFORM_SKU_UNKNOWN = 6,
> +};
> +
> +enum slpc_power_plan {
> +	SLPC_POWER_PLAN_UNDEFINED = 0,
> +	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
> +	SLPC_POWER_PLAN_BALANCED = 2,
> +	SLPC_POWER_PLAN_PERFORMANCE = 3,
> +	SLPC_POWER_PLAN_UNKNOWN = 4,
> +};
> +
> +enum slpc_power_source {
> +	SLPC_POWER_SOURCE_UNDEFINED = 0,
> +	SLPC_POWER_SOURCE_AC = 1,
> +	SLPC_POWER_SOURCE_DC = 2,
> +	SLPC_POWER_SOURCE_UNKNOWN = 3,
> +};
> +
> +#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
> +#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
> +#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
> +
> +struct slpc_platform_info {
> +	u8 platform_sku;
> +	u8 slice_count;
> +	u8 host_os;
> +	u8 power_plan_source;
> +	u8 P0_freq;
> +	u8 P1_freq;
> +	u8 Pe_freq;
> +	u8 Pn_freq;
> +	u32 package_rapl_limit_high;
> +	u32 package_rapl_limit_low;
> +} __packed;
> +
> +#define SLPC_MAX_OVERRIDE_PARAMETERS 192
> +#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
> +
> +struct slpc_shared_data {
> +	u32 slpc_version;
> +	u32 shared_data_size;
> +	u32 global_state;
> +	struct slpc_platform_info platform_info;
> +	u32 task_state_data;
> +	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
> +	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
> +} __packed;
> +
> +struct intel_slpc {
> +	struct i915_vma *vma;
> +	bool enabled;
> +};
> +
>  /* intel_slpc.c */
>  void intel_slpc_init(struct drm_i915_private *dev_priv);
>  void intel_slpc_cleanup(struct drm_i915_private *dev_priv);

With those changes:

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
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Re: drm/i915/slpc: Use intel_slpc_* functions if supported

[David Weinehall]

On Sat, Aug 20, 2016 at 10:39:06AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> On platforms with SLPC support: call intel_slpc_*()
> functions from corresponding intel_*_gt_powersave()
> functions; and do not use rps functions.
> 
> v2: return void instead of ignored error code (Paulo)
>     enable/disable RC6 in SLPC flows (Sagar)
>     replace HAS_SLPC() use with intel_slpc_enabled()
> 	or intel_slpc_active() (Paulo)
> v3: Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
>     "drm/i915/bxt: Explicitly clear the Turbo control register"

v4?

> v5: Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
>     Performance drop with SLPC was happening as ring frequency table
>     was not programmed when SLPC was enabled. This patch programs ring
>     frequency table with SLPC. Initial reset of SLPC is based on kernel
>     parameter as planning to add slpc state in intel_slpc_active. Cleanup
>     is also based on kernel parameter as SLPC gets disabled in
>     disable/suspend.(Sagar)
> 
> v6: Rebase.
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile     |  3 +-
>  drivers/gpu/drm/i915/intel_drv.h  |  4 ++
>  drivers/gpu/drm/i915/intel_guc.h  |  1 +
>  drivers/gpu/drm/i915/intel_pm.c   | 98 ++++++++++++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_slpc.c | 56 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_slpc.h | 35 ++++++++++++++
>  6 files changed, 165 insertions(+), 32 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
>  create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 3412413..b768c66 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -51,7 +51,8 @@ i915-y += i915_cmd_parser.o \
>  
>  # general-purpose microcontroller (GuC) support
>  i915-y += intel_guc_loader.o \
> -	  i915_guc_submission.o
> +	  i915_guc_submission.o \
> +	  intel_slpc.o
>  
>  # autogenerated null render state
>  i915-y += intel_renderstate_gen6.o \
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1c700b0..16fe13d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1692,6 +1692,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
>  bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>  			  enum dpio_channel ch, bool override);
>  
> +static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
> +{
> +	return 0;
> +}
>  
>  /* intel_pm.c */
>  void intel_init_clock_gating(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 27a7459..cd23c4e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -27,6 +27,7 @@
>  #include "intel_guc_fwif.h"
>  #include "i915_guc_reg.h"
>  #include "intel_ringbuffer.h"
> +#include "intel_slpc.h"
>  
>  struct drm_i915_gem_request;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 954e332..7156fb5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4893,7 +4893,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>  	 * our rpm wakeref. And then disable the interrupts to stop any
>  	 * futher RPS reclocking whilst we are asleep.
>  	 */
> -	gen6_disable_rps_interrupts(dev_priv);
> +	if (!intel_slpc_active(dev_priv))
> +		gen6_disable_rps_interrupts(dev_priv);
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	if (dev_priv->rps.enabled) {
> @@ -6544,6 +6545,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>  	/* Finally allow us to boost to max by default */
>  	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
>  
> +	if (intel_slpc_enabled())
> +		intel_slpc_init(dev_priv);
> +
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  	mutex_unlock(&dev_priv->drm.struct_mutex);
>  
> @@ -6552,7 +6556,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>  
>  void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_VALLEYVIEW(dev_priv))
> +	if (intel_slpc_enabled())
> +		intel_slpc_cleanup(dev_priv);
> +	else if (IS_VALLEYVIEW(dev_priv))
>  		valleyview_cleanup_gt_powersave(dev_priv);
>  
>  	if (!i915.enable_rc6)
> @@ -6572,28 +6578,42 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
>  	if (INTEL_GEN(dev_priv) < 6)
>  		return;
>  
> -	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
> +	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) {
> +		if (intel_slpc_active(dev_priv))
> +			intel_slpc_suspend(dev_priv);
>  		intel_runtime_pm_put(dev_priv);
> +	}
>  
>  	/* gen6_rps_idle() will be called later to disable interrupts */
>  }
>  
>  void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
>  {
> -	dev_priv->rps.enabled = true; /* force disabling */
> -	intel_disable_gt_powersave(dev_priv);
> +	if (intel_slpc_enabled()) {
> +		/* TODO: Set SLPC enabled forcefully */
> +		intel_disable_gt_powersave(dev_priv);
> +	} else {
> +		dev_priv->rps.enabled = true; /* force disabling */
> +		intel_disable_gt_powersave(dev_priv);
>  
> -	gen6_reset_rps_interrupts(dev_priv);
> +		gen6_reset_rps_interrupts(dev_priv);
> +	}
>  }
>  
>  void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
>  {
> -	if (!READ_ONCE(dev_priv->rps.enabled))
> +	if (intel_slpc_enabled()) {
> +		if (!intel_slpc_active(dev_priv))
> +			return;
> +	} else if (!READ_ONCE(dev_priv->rps.enabled))
>  		return;
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (intel_slpc_active(dev_priv)) {
> +		gen9_disable_rc6(dev_priv);
> +		intel_slpc_disable(dev_priv);
> +	} else if (INTEL_GEN(dev_priv) >= 9) {
>  		gen9_disable_rc6(dev_priv);
>  		gen9_disable_rps(dev_priv);
>  	} else if (IS_CHERRYVIEW(dev_priv)) {
> @@ -6614,7 +6634,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>  	/* We shouldn't be disabling as we submit, so this should be less
>  	 * racy than it appears!
>  	 */
> -	if (READ_ONCE(dev_priv->rps.enabled))
> +	if (intel_slpc_enabled()) {
> +		if (intel_slpc_active(dev_priv))
> +			return;
> +	} else if (READ_ONCE(dev_priv->rps.enabled))
>  		return;
>  
>  	/* Powersaving is controlled by the host when inside a VM */
> @@ -6623,31 +6646,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
> -	if (IS_CHERRYVIEW(dev_priv)) {
> -		cherryview_enable_rps(dev_priv);
> -	} else if (IS_VALLEYVIEW(dev_priv)) {
> -		valleyview_enable_rps(dev_priv);
> -	} else if (INTEL_GEN(dev_priv) >= 9) {
> +	if (intel_slpc_enabled()) {
>  		gen9_enable_rc6(dev_priv);
> -		gen9_enable_rps(dev_priv);
> +		intel_slpc_enable(dev_priv);
>  		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  			gen6_update_ring_freq(dev_priv);
> -	} else if (IS_BROADWELL(dev_priv)) {
> -		gen8_enable_rps(dev_priv);
> -		gen6_update_ring_freq(dev_priv);
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> -		gen6_enable_rps(dev_priv);
> -		gen6_update_ring_freq(dev_priv);
> -	} else if (IS_IRONLAKE_M(dev_priv)) {
> -		ironlake_enable_drps(dev_priv);
> -		intel_init_emon(dev_priv);
> -	}
> +	} else {
> +		if (IS_CHERRYVIEW(dev_priv)) {
> +			cherryview_enable_rps(dev_priv);
> +		} else if (IS_VALLEYVIEW(dev_priv)) {
> +			valleyview_enable_rps(dev_priv);
> +		} else if (INTEL_INFO(dev_priv)->gen >= 9) {

INTEL_GEN(dev_priv) >= 9

> +			gen9_enable_rc6(dev_priv);
> +			gen9_enable_rps(dev_priv);
> +			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> +				gen6_update_ring_freq(dev_priv);
> +		} else if (IS_BROADWELL(dev_priv)) {
> +			gen8_enable_rps(dev_priv);
> +			gen6_update_ring_freq(dev_priv);
> +		} else if (INTEL_GEN(dev_priv) >= 6) {
> +			gen6_enable_rps(dev_priv);
> +			gen6_update_ring_freq(dev_priv);
> +		} else if (IS_IRONLAKE_M(dev_priv)) {
> +			ironlake_enable_drps(dev_priv);
> +			intel_init_emon(dev_priv);
> +		}
>  
> -	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
> -	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
> +		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
> +		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
>  
> -	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
> -	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
> +		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
> +		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
> +	}
>  
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  }
> @@ -6659,7 +6689,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
>  	struct intel_engine_cs *rcs;
>  	struct drm_i915_gem_request *req;
>  
> -	if (READ_ONCE(dev_priv->rps.enabled))
> +	if (intel_slpc_enabled()) {
> +		if (intel_slpc_active(dev_priv))
> +			goto out;
> +	} else if (READ_ONCE(dev_priv->rps.enabled))
>  		goto out;
>  
>  	rcs = &dev_priv->engine[RCS];
> @@ -6689,7 +6722,10 @@ out:
>  
>  void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
>  {
> -	if (READ_ONCE(dev_priv->rps.enabled))
> +	if (intel_slpc_enabled()) {
> +		if (intel_slpc_active(dev_priv))
> +			return;
> +	} else if (READ_ONCE(dev_priv->rps.enabled))
>  		return;
>  
>  	if (IS_IRONLAKE_M(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> new file mode 100644
> index 0000000..b2e8d91
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#include <linux/firmware.h>
> +#include "i915_drv.h"
> +#include "intel_guc.h"
> +
> +void intel_slpc_init(struct drm_i915_private *dev_priv)
> +{
> +	return;
> +}
> +
> +void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
> +{
> +	return;
> +}
> +
> +void intel_slpc_suspend(struct drm_i915_private *dev_priv)
> +{
> +	return;
> +}
> +
> +void intel_slpc_disable(struct drm_i915_private *dev_priv)
> +{
> +	return;
> +}
> +
> +void intel_slpc_enable(struct drm_i915_private *dev_priv)
> +{
> +	return;
> +}
> +
> +void intel_slpc_reset(struct drm_i915_private *dev_priv)
> +{
> +	return;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
> new file mode 100644
> index 0000000..ae52146
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_slpc.h
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#ifndef _INTEL_SLPC_H_
> +#define _INTEL_SLPC_H_
> +
> +/* intel_slpc.c */
> +void intel_slpc_init(struct drm_i915_private *dev_priv);
> +void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
> +void intel_slpc_suspend(struct drm_i915_private *dev_priv);
> +void intel_slpc_disable(struct drm_i915_private *dev_priv);
> +void intel_slpc_enable(struct drm_i915_private *dev_priv);
> +void intel_slpc_reset(struct drm_i915_private *dev_priv);
> +
> +#endif

-- 
 /) David Weinehall <tao@acc.umu.se> /) Northern lights wander      (\
//  Maintainer of the v2.0 kernel   //  Dance across the winter sky //
\)  http://www.acc.umu.se/~tao/    (/   Full colour fire           (/
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Re: drm/i915/slpc: Use intel_slpc_* functions if supported

[Kamble, Sagar A]

Thanks for the review David.

Have incorporated the changes and will send in next series.


On 8/20/2016 1:57 PM, David Weinehall wrote:
> On Sat, Aug 20, 2016 at 10:39:06AM +0530, Sagar Arun Kamble wrote:
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> On platforms with SLPC support: call intel_slpc_*()
>> functions from corresponding intel_*_gt_powersave()
>> functions; and do not use rps functions.
>>
>> v2: return void instead of ignored error code (Paulo)
>>      enable/disable RC6 in SLPC flows (Sagar)
>>      replace HAS_SLPC() use with intel_slpc_enabled()
>> 	or intel_slpc_active() (Paulo)
>> v3: Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
>>      "drm/i915/bxt: Explicitly clear the Turbo control register"
> v4?
>
>> v5: Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
>>      Performance drop with SLPC was happening as ring frequency table
>>      was not programmed when SLPC was enabled. This patch programs ring
>>      frequency table with SLPC. Initial reset of SLPC is based on kernel
>>      parameter as planning to add slpc state in intel_slpc_active. Cleanup
>>      is also based on kernel parameter as SLPC gets disabled in
>>      disable/suspend.(Sagar)
>>
>> v6: Rebase.
>>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/Makefile     |  3 +-
>>   drivers/gpu/drm/i915/intel_drv.h  |  4 ++
>>   drivers/gpu/drm/i915/intel_guc.h  |  1 +
>>   drivers/gpu/drm/i915/intel_pm.c   | 98 ++++++++++++++++++++++++++-------------
>>   drivers/gpu/drm/i915/intel_slpc.c | 56 ++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_slpc.h | 35 ++++++++++++++
>>   6 files changed, 165 insertions(+), 32 deletions(-)
>>   create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
>>   create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 3412413..b768c66 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -51,7 +51,8 @@ i915-y += i915_cmd_parser.o \
>>   
>>   # general-purpose microcontroller (GuC) support
>>   i915-y += intel_guc_loader.o \
>> -	  i915_guc_submission.o
>> +	  i915_guc_submission.o \
>> +	  intel_slpc.o
>>   
>>   # autogenerated null render state
>>   i915-y += intel_renderstate_gen6.o \
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 1c700b0..16fe13d 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1692,6 +1692,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
>>   bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>>   			  enum dpio_channel ch, bool override);
>>   
>> +static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
>> +{
>> +	return 0;
>> +}
>>   
>>   /* intel_pm.c */
>>   void intel_init_clock_gating(struct drm_device *dev);
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
>> index 27a7459..cd23c4e 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -27,6 +27,7 @@
>>   #include "intel_guc_fwif.h"
>>   #include "i915_guc_reg.h"
>>   #include "intel_ringbuffer.h"
>> +#include "intel_slpc.h"
>>   
>>   struct drm_i915_gem_request;
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 954e332..7156fb5 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4893,7 +4893,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>>   	 * our rpm wakeref. And then disable the interrupts to stop any
>>   	 * futher RPS reclocking whilst we are asleep.
>>   	 */
>> -	gen6_disable_rps_interrupts(dev_priv);
>> +	if (!intel_slpc_active(dev_priv))
>> +		gen6_disable_rps_interrupts(dev_priv);
>>   
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   	if (dev_priv->rps.enabled) {
>> @@ -6544,6 +6545,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>>   	/* Finally allow us to boost to max by default */
>>   	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
>>   
>> +	if (intel_slpc_enabled())
>> +		intel_slpc_init(dev_priv);
>> +
>>   	mutex_unlock(&dev_priv->rps.hw_lock);
>>   	mutex_unlock(&dev_priv->drm.struct_mutex);
>>   
>> @@ -6552,7 +6556,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>>   
>>   void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>>   {
>> -	if (IS_VALLEYVIEW(dev_priv))
>> +	if (intel_slpc_enabled())
>> +		intel_slpc_cleanup(dev_priv);
>> +	else if (IS_VALLEYVIEW(dev_priv))
>>   		valleyview_cleanup_gt_powersave(dev_priv);
>>   
>>   	if (!i915.enable_rc6)
>> @@ -6572,28 +6578,42 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
>>   	if (INTEL_GEN(dev_priv) < 6)
>>   		return;
>>   
>> -	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
>> +	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) {
>> +		if (intel_slpc_active(dev_priv))
>> +			intel_slpc_suspend(dev_priv);
>>   		intel_runtime_pm_put(dev_priv);
>> +	}
>>   
>>   	/* gen6_rps_idle() will be called later to disable interrupts */
>>   }
>>   
>>   void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
>>   {
>> -	dev_priv->rps.enabled = true; /* force disabling */
>> -	intel_disable_gt_powersave(dev_priv);
>> +	if (intel_slpc_enabled()) {
>> +		/* TODO: Set SLPC enabled forcefully */
>> +		intel_disable_gt_powersave(dev_priv);
>> +	} else {
>> +		dev_priv->rps.enabled = true; /* force disabling */
>> +		intel_disable_gt_powersave(dev_priv);
>>   
>> -	gen6_reset_rps_interrupts(dev_priv);
>> +		gen6_reset_rps_interrupts(dev_priv);
>> +	}
>>   }
>>   
>>   void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
>>   {
>> -	if (!READ_ONCE(dev_priv->rps.enabled))
>> +	if (intel_slpc_enabled()) {
>> +		if (!intel_slpc_active(dev_priv))
>> +			return;
>> +	} else if (!READ_ONCE(dev_priv->rps.enabled))
>>   		return;
>>   
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (intel_slpc_active(dev_priv)) {
>> +		gen9_disable_rc6(dev_priv);
>> +		intel_slpc_disable(dev_priv);
>> +	} else if (INTEL_GEN(dev_priv) >= 9) {
>>   		gen9_disable_rc6(dev_priv);
>>   		gen9_disable_rps(dev_priv);
>>   	} else if (IS_CHERRYVIEW(dev_priv)) {
>> @@ -6614,7 +6634,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>>   	/* We shouldn't be disabling as we submit, so this should be less
>>   	 * racy than it appears!
>>   	 */
>> -	if (READ_ONCE(dev_priv->rps.enabled))
>> +	if (intel_slpc_enabled()) {
>> +		if (intel_slpc_active(dev_priv))
>> +			return;
>> +	} else if (READ_ONCE(dev_priv->rps.enabled))
>>   		return;
>>   
>>   	/* Powersaving is controlled by the host when inside a VM */
>> @@ -6623,31 +6646,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>>   
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   
>> -	if (IS_CHERRYVIEW(dev_priv)) {
>> -		cherryview_enable_rps(dev_priv);
>> -	} else if (IS_VALLEYVIEW(dev_priv)) {
>> -		valleyview_enable_rps(dev_priv);
>> -	} else if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (intel_slpc_enabled()) {
>>   		gen9_enable_rc6(dev_priv);
>> -		gen9_enable_rps(dev_priv);
>> +		intel_slpc_enable(dev_priv);
>>   		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>>   			gen6_update_ring_freq(dev_priv);
>> -	} else if (IS_BROADWELL(dev_priv)) {
>> -		gen8_enable_rps(dev_priv);
>> -		gen6_update_ring_freq(dev_priv);
>> -	} else if (INTEL_GEN(dev_priv) >= 6) {
>> -		gen6_enable_rps(dev_priv);
>> -		gen6_update_ring_freq(dev_priv);
>> -	} else if (IS_IRONLAKE_M(dev_priv)) {
>> -		ironlake_enable_drps(dev_priv);
>> -		intel_init_emon(dev_priv);
>> -	}
>> +	} else {
>> +		if (IS_CHERRYVIEW(dev_priv)) {
>> +			cherryview_enable_rps(dev_priv);
>> +		} else if (IS_VALLEYVIEW(dev_priv)) {
>> +			valleyview_enable_rps(dev_priv);
>> +		} else if (INTEL_INFO(dev_priv)->gen >= 9) {
> INTEL_GEN(dev_priv) >= 9
>
>> +			gen9_enable_rc6(dev_priv);
>> +			gen9_enable_rps(dev_priv);
>> +			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>> +				gen6_update_ring_freq(dev_priv);
>> +		} else if (IS_BROADWELL(dev_priv)) {
>> +			gen8_enable_rps(dev_priv);
>> +			gen6_update_ring_freq(dev_priv);
>> +		} else if (INTEL_GEN(dev_priv) >= 6) {
>> +			gen6_enable_rps(dev_priv);
>> +			gen6_update_ring_freq(dev_priv);
>> +		} else if (IS_IRONLAKE_M(dev_priv)) {
>> +			ironlake_enable_drps(dev_priv);
>> +			intel_init_emon(dev_priv);
>> +		}
>>   
>> -	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
>> -	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
>> +		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
>> +		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
>>   
>> -	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
>> -	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
>> +		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
>> +		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
>> +	}
>>   
>>   	mutex_unlock(&dev_priv->rps.hw_lock);
>>   }
>> @@ -6659,7 +6689,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
>>   	struct intel_engine_cs *rcs;
>>   	struct drm_i915_gem_request *req;
>>   
>> -	if (READ_ONCE(dev_priv->rps.enabled))
>> +	if (intel_slpc_enabled()) {
>> +		if (intel_slpc_active(dev_priv))
>> +			goto out;
>> +	} else if (READ_ONCE(dev_priv->rps.enabled))
>>   		goto out;
>>   
>>   	rcs = &dev_priv->engine[RCS];
>> @@ -6689,7 +6722,10 @@ out:
>>   
>>   void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
>>   {
>> -	if (READ_ONCE(dev_priv->rps.enabled))
>> +	if (intel_slpc_enabled()) {
>> +		if (intel_slpc_active(dev_priv))
>> +			return;
>> +	} else if (READ_ONCE(dev_priv->rps.enabled))
>>   		return;
>>   
>>   	if (IS_IRONLAKE_M(dev_priv)) {
>> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
>> new file mode 100644
>> index 0000000..b2e8d91
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_slpc.c
>> @@ -0,0 +1,56 @@
>> +/*
>> + * Copyright © 2015 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
>> +#include <linux/firmware.h>
>> +#include "i915_drv.h"
>> +#include "intel_guc.h"
>> +
>> +void intel_slpc_init(struct drm_i915_private *dev_priv)
>> +{
>> +	return;
>> +}
>> +
>> +void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
>> +{
>> +	return;
>> +}
>> +
>> +void intel_slpc_suspend(struct drm_i915_private *dev_priv)
>> +{
>> +	return;
>> +}
>> +
>> +void intel_slpc_disable(struct drm_i915_private *dev_priv)
>> +{
>> +	return;
>> +}
>> +
>> +void intel_slpc_enable(struct drm_i915_private *dev_priv)
>> +{
>> +	return;
>> +}
>> +
>> +void intel_slpc_reset(struct drm_i915_private *dev_priv)
>> +{
>> +	return;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
>> new file mode 100644
>> index 0000000..ae52146
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_slpc.h
>> @@ -0,0 +1,35 @@
>> +/*
>> + * Copyright © 2015 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
>> +#ifndef _INTEL_SLPC_H_
>> +#define _INTEL_SLPC_H_
>> +
>> +/* intel_slpc.c */
>> +void intel_slpc_init(struct drm_i915_private *dev_priv);
>> +void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
>> +void intel_slpc_suspend(struct drm_i915_private *dev_priv);
>> +void intel_slpc_disable(struct drm_i915_private *dev_priv);
>> +void intel_slpc_enable(struct drm_i915_private *dev_priv);
>> +void intel_slpc_reset(struct drm_i915_private *dev_priv);
>> +
>> +#endif

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Re: drm/i915: Check GuC load status for Host to GuC action and SLPC status

[Kamble, Sagar A]

Thanks for the review Deepak.

Have incorporated the changes and will send in next series.


On 8/20/2016 10:40 AM, Deepak S wrote:
>
>
> On 20/08/16 10:39 AM, Sagar Arun Kamble wrote:
>> Host to GuC actions should not be invoked when GuC isn't loaded hence
>> add early return in i915_guc_action if GuC load status is not SUCCESS.
>> Also, SLPC status has to be linked with GuC load status to make sure
>> SLPC actions get invoked when GuC is loaded.
>>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_guc_submission.c | 5 +++++
>>   drivers/gpu/drm/i915/intel_drv.h           | 4 ++++
>>   2 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
>> b/drivers/gpu/drm/i915/i915_guc_submission.c
>> index 680d9b4..27c937b 100644
>> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
>> @@ -78,6 +78,8 @@ static inline bool host2guc_action_response(struct 
>> drm_i915_private *dev_priv,
>>   int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
>>   {
>>       struct drm_i915_private *dev_priv = guc_to_i915(guc);
>> +    struct intel_guc_fw *guc_fw = &guc->guc_fw;
>> +
> remove the blank line
>>       u32 status;
>>       int i;
>>       int ret;
>> @@ -85,6 +87,9 @@ int i915_guc_action(struct intel_guc *guc, u32 
>> *data, u32 len)
>>       if (WARN_ON(len < 1 || len > 15))
>>           return -EINVAL;
>>   +    if (WARN_ON(guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS))
>> +        return -ENODEV;
>> +
>>       intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>>         dev_priv->guc.action_count += 1;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index c46d619..71936dc 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1694,8 +1694,12 @@ bool chv_phy_powergate_ch(struct 
>> drm_i915_private *dev_priv, enum dpio_phy phy,
>>     static inline int intel_slpc_active(struct drm_i915_private 
>> *dev_priv)
>>   {
>> +    struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>>       int ret = 0;
>>   +    if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
>> +        return 0;
>> +
> Since we are initializing ret=0, I think can do "return ret" right?
>>       if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
>>           ret = 1;
>
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> Intel-gfx@lists.freedesktop.org
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Re: drm/i915/slpc: Update freq min/max softlimits

[Kamble, Sagar A]

On 8/20/2016 1:32 PM, Chris Wilson wrote:
> On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:
>> +	obj = dev_priv->guc.slpc.vma->obj;
>> +	if (obj) {
> OOPS.
Fixed in next series.
>
>> +		intel_slpc_query_task_state(dev_priv);
>> +
>> +		page = i915_gem_object_get_page(obj, 0);
>> +		if (page)
>> +			pv = kmap_atomic(page);
>> +	}
>> +
>> +	if (pv) {
>> +		data = *(struct slpc_shared_data *) pv;
>> +		kunmap_atomic(pv);
> Can kmap_atomic return zero?
Fixed in next series.
>
>> +
>> +		/*
>> +		 * TODO: Define separate variables for slice and unslice
>> +		 *	 frequencies for driver state variable.
>> +		 */
>> +		dev_priv->rps.max_freq_softlimit =
>> +				data.task_state_data.freq_unslice_max;
>> +		dev_priv->rps.min_freq_softlimit =
>> +				data.task_state_data.freq_unslice_min;
> These are user values, you do not get to arbitrarily rewrite them.
>
> You control dev_priv->rps.[min|max]_freq.
With SLPC, GuC firmware SLPC S/W requested frequency be operated in the 
softlimits analogous to
Host softlimits. Limits might be different with SLPC and can be 
controlled through regular interfaces.
dev_priv->rps.[min|max]_freq are HW Min/Max.
> -Chris
>

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Re: drm/i915/slpc: Update current requested frequency

[Kamble, Sagar A]

On 8/20/2016 1:45 PM, Chris Wilson wrote:
> On Sat, Aug 20, 2016 at 10:39:10AM +0530, Sagar Arun Kamble wrote:
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> When SLPC is controlling requested frequency, the rps.cur_freq
>> value is not used to make the frequency request.
>>
>> Before using rps.cur_freq in sysfs or debugfs, read
>> requested frequency from register to get the value
>> most recently requested by SLPC firmware.
>>
>> v2: replace HAS_SLPC with intel_slpc_active (Paulo)
>> v3: Avoid magic numbers (Nick)
>>      Use a function for repeated code (Jon)
>>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
>>   drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
>>   drivers/gpu/drm/i915/i915_reg.h     | 1 +
>>   drivers/gpu/drm/i915/i915_sysfs.c   | 8 ++++++++
>>   4 files changed, 20 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 01ae5ee..a99a3f6 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1110,6 +1110,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>   
>>   	intel_runtime_pm_get(dev_priv);
>>   
>> +	if (intel_slpc_active(dev_priv))
>> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
> Do not alter cur_freq here, as we print out RPNSWEQ and updating
> cur_freq defeats the purpose of showing the internal value vs the hw
> value.
>
> Instead add "SLPC active" to the output.
Fixed in the next series.
>
>> +
>>   	if (IS_GEN5(dev)) {
>>   		u16 rgvswctl = I915_READ16(MEMSWCTL);
>>   		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
>> @@ -2372,6 +2375,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>>   	struct drm_i915_private *dev_priv = to_i915(dev);
>>   	struct drm_file *file;
> if (intel_slpc_active(dev_priv))
> 	return -ENODEV;
Fixed in the next series.
>>   
>> +	if (intel_slpc_active(dev_priv))
>> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
>> +
>>   	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
>>   	seq_printf(m, "GPU busy? %s [%x]\n",
>>   		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 764fad0..fcd2e98 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -3913,4 +3913,9 @@ bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
>>   	__T;								\
>>   })
>>   
>> +static inline u8 gen9_read_requested_freq(struct drm_i915_private *dev_priv)
>> +{
>> +	return (u8) GEN9_GET_FREQUENCY(I915_READ(GEN6_RPNSWREQ));
>> +}
Removed in the next series.
> Move to sysfs and look carefully at what you wrote.
>
>>   #endif
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d4adf28..1654245 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6997,6 +6997,7 @@ enum {
>>   #define   GEN6_FREQUENCY(x)			((x)<<25)
>>   #define   HSW_FREQUENCY(x)			((x)<<24)
>>   #define   GEN9_FREQUENCY(x)			((x)<<23)
>> +#define   GEN9_GET_FREQUENCY(x)			((x)>>23)
>>   #define   GEN6_OFFSET(x)			((x)<<19)
>>   #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
>>   #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
>> index f1ffde7..8404816 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -302,6 +302,14 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>>   	struct drm_device *dev = minor->dev;
>>   	struct drm_i915_private *dev_priv = to_i915(dev);
>>   
>> +	if (intel_slpc_active(dev_priv)) {
>> +		intel_runtime_pm_get(dev_priv);
> Use get_if_in_use and just show a stale value when the hw is asleep
> would be my preference. cur_freq is just our request, act_freq is the
> actual hw value.
With cur_freq not making sense currently with SLPC, I am removing this 
altogether and adding new sysfs interface
for knowing HW requested frequency which will be ideally SLPC requested.
>
>> +		mutex_lock(&dev_priv->rps.hw_lock);
> Useless mutex.
>
>> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
>> +		mutex_unlock(&dev_priv->rps.hw_lock);
>> +		intel_runtime_pm_put(dev_priv);
>> +	}
>> +
>>   	return snprintf(buf, PAGE_SIZE, "%d\n",
>>   			intel_gpu_freq(dev_priv,
>>   				       dev_priv->rps.cur_freq));
>> -- 
>> 1.9.1
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: Add support for GuC-based SLPC

[Kamble, Sagar A]

On 8/20/2016 1:46 PM, Chris Wilson wrote:
> On Sat, Aug 20, 2016 at 10:38:59AM +0530, Sagar Arun Kamble wrote:
>> This series has been tested with SKL GuC firmware
>> version 9.18 which is yet to be released. Performance and
>> power testing with these patches and 9.18 firmware is at
>> parity and in some cases better than host solution today
>> on various Linux benchmarks.
> Patches pending to support your claims?
> -Chris
Only pending GuC firmware 9.18 integration. All kernel side changes for 
SLPC are part of the series.
I added patch to enable SLPC by default in this series, will remove in 
the next series and can add it
once 9.18 firmware gets integrated.
>

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Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features.  The SLPC
implementation runs in firmware on GuC.

This series has been tested with SKL GuC firmware
version 9.18 which is yet to be released. Performance and
power testing with these patches and 9.18 firmware is at
parity and in some cases better than host solution today
on various Linux benchmarks.

The graphics power management features in SLPC in this
version are called GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate.  Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios.  BALANCER is only
active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.

The last series can be found in the archive at
"[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/094445.html

This series incorporates feedback from code reviews on earlier series.
It drops the display mode notification patches as it is not needed for
Turbo part of GTPERF. This series also adds new interface changes for
SLPC support on 9.18 GuC Firmware which is not yet published.
Will like to get review started prior to firmware is published.

With SLPC disabled by default, this series should be 
safe to merge now and it can be enabled when 9.18 firmware is released. 

v2: Addressed review comments on v1. Removed patch to enable SLPC by default.

VIZ-6773, VIZ-6889

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Beuchat, Marc <marc.beuchat@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>


Sagar Arun Kamble (7):
  drm/i915: Remove RPM suspend dependency on rps.enabled and related
    changes
  drm/i915: Check GuC load status for Host to GuC action and SLPC status
  drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
  drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS
    Stall
  drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
  drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC
  drm/i915/slpc: Update freq min/max softlimits

Tom O'Rourke (18):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize SLPC version
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Add/Update interface for requested frequency
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add broxton support

 drivers/gpu/drm/i915/Makefile              |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 469 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c            |  21 +-
 drivers/gpu/drm/i915/i915_drv.h            |   2 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  20 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_pci.c            |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  51 ++++
 drivers/gpu/drm/i915/intel_drv.h           |  13 +
 drivers/gpu/drm/i915/intel_guc.h           |  11 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  49 ++-
 drivers/gpu/drm/i915/intel_pm.c            | 131 +++++---
 drivers/gpu/drm/i915/intel_runtime_pm.c    |   2 +-
 drivers/gpu/drm/i915/intel_slpc.c          | 368 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 215 +++++++++++++
 16 files changed, 1310 insertions(+), 55 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[Sagar Arun Kamble]

For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM
Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other
GENs this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.

v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
    spacing changes. (David)
    and commit message update for checkpatch issues.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 14 +++++++++++---
 drivers/gpu/drm/i915/intel_pm.c         | 20 ++++++++++++++++++--
 drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 13ae340..d5d0a50 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2284,10 +2284,18 @@ static int intel_runtime_suspend(struct device *device)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
 		return -ENODEV;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	/*
+	 * Once RC6 and RPS enabling is separated for non-GEN9 platforms
+	 * below check should be removed.
+	*/
+	if (!IS_GEN9(dev_priv))
+		if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+			return -ENODEV;
+
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Suspending device\n");
@@ -2391,7 +2399,7 @@ static int intel_runtime_resume(struct device *device)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret = 0;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a6751e..5a73672 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4979,6 +4979,8 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -4986,11 +4988,15 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5002,6 +5008,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5219,6 +5227,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5362,6 +5372,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5458,6 +5470,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -5932,6 +5946,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6012,6 +6028,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6601,7 +6619,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		ironlake_disable_drps(dev_priv);
 	}
 
-	dev_priv->rps.enabled = false;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -6645,7 +6662,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a1d73c2..d86d9e9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2768,7 +2768,7 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 	 * so the driver's own RPM reference tracking asserts also work on
 	 * platforms without RPM support.
 	 */
-	if (!HAS_RUNTIME_PM(dev)) {
+	if (!HAS_RUNTIME_PM(dev_priv)) {
 		pm_runtime_dont_use_autosuspend(device);
 		pm_runtime_get_sync(device);
 	} else {
-- 
1.9.1

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drm/i915/slpc: Expose guc functions for use with SLPC

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

v1: Updated function names as they need to be made extern. (ChrisW)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_guc.h           |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index e436941..9a69bf1 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -47,7 +47,7 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
  *
  * Doorbells:
  * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 	return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	u32 status;
@@ -141,7 +141,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -152,7 +152,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -169,7 +169,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 		/* bit 0 and 1 are for Render and Media domain separately */
 		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 /*
@@ -621,7 +621,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
@@ -1067,7 +1067,7 @@ int intel_guc_suspend(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 
@@ -1092,5 +1092,5 @@ int intel_guc_resume(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c973262..9e6b948 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
 
-- 
1.9.1

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drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cd102c..d853d7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -652,6 +652,7 @@ struct intel_csr {
 	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
+	func(has_slpc) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2784,6 +2785,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev)		(IS_GEN9(dev))
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
+#define HAS_SLPC(dev)		(INTEL_INFO(dev)->has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
-- 
1.9.1

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drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Move slpc_version_check to intel_guc_ucode_init.
    fix whitespace (Sagar)
    Moved version check to different patch as has_slpc
    should not be updated based on it. Instead module parameter
    should be updated based on version check. (Sagar)
    Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e678051 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,12 +322,14 @@ static const struct intel_device_info intel_skylake_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
    Remove sanitize enable_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as
    part of slpc_enable_sanitize function in the next patch. (Sagar)
    Updated slpc option sanitize function call for platforms without
    GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_guc.h        |  6 ++++++
 drivers/gpu/drm/i915/intel_guc_loader.c | 30 ++++++++++++++++++++++++++----
 4 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
+	int enable_slpc;
 	int enable_psr;
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..bf7624f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
 	uint32_t last_seqno[I915_NUM_ENGINES];
 };
 
+static inline int intel_slpc_enabled(void)
+{
+	WARN_ON(i915.enable_slpc < 0);
+	return i915.enable_slpc;
+}
+
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_device *dev);
 extern int intel_guc_setup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 324812d..2dfdb24 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+	/* Handle default case */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev_priv);
+
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev_priv))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc loaded */
+	if (!i915.enable_guc_loading)
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
 	/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -728,18 +747,21 @@ void intel_guc_init(struct drm_device *dev)
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 
-	/* Early (and silent) return if GuC loading is disabled */
+	/* Return if GuC loading is disabled sanitizing SLPC option */
 	if (!i915.enable_guc_loading)
-		return;
+		goto out;
 	if (fw_path == NULL)
-		return;
+		goto out;
 	if (*fw_path == '\0')
-		return;
+		goto out;
 
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 	guc_fw_fetch(dev, guc_fw);
 	/* status must now be FAIL or SUCCESS */
+
+out:
+	sanitize_slpc_option(dev_priv);
 }
 
 /**
-- 
1.9.1

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drm/i915/slpc: Sanitize SLPC version

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Updated with modified sanitize_slpc_option in earlier patch.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2dfdb24..023064d 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -146,6 +146,8 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 
 static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
 	/* Handle default case */
 	if (i915.enable_slpc < 0)
 		i915.enable_slpc = HAS_SLPC(dev_priv);
@@ -161,6 +163,9 @@ static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	/* slpc requires guc submission */
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
+
+	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+		i915.enable_slpc = 0;
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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drm/i915/slpc: Use intel_slpc_* functions if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  3 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_guc.h  |  1 +
 drivers/gpu/drm/i915/intel_pm.c   | 98 ++++++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_slpc.c | 50 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 35 ++++++++++++++
 6 files changed, 159 insertions(+), 32 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da246..229290d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,7 +52,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+	  i915_guc_submission.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 774aab3..353cb51 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1692,6 +1692,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 			  enum dpio_channel ch, bool override);
 
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
+{
+	return 0;
+}
 
 /* intel_pm.c */
 void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index bf7624f..6fdbac5 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a73672..21dafe0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4906,7 +4906,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	 * our rpm wakeref. And then disable the interrupts to stop any
 	 * futher RPS reclocking whilst we are asleep.
 	 */
-	gen6_disable_rps_interrupts(dev_priv);
+	if (!intel_slpc_active(dev_priv))
+		gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
@@ -6557,6 +6558,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 	/* Finally allow us to boost to max by default */
 	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
 
+	if (intel_slpc_enabled())
+		intel_slpc_init(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
@@ -6565,7 +6569,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (IS_VALLEYVIEW(dev_priv))
+	if (intel_slpc_enabled())
+		intel_slpc_cleanup(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
 	if (!i915.enable_rc6)
@@ -6585,28 +6591,42 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
+	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) {
+		if (intel_slpc_active(dev_priv))
+			intel_slpc_suspend(dev_priv);
 		intel_runtime_pm_put(dev_priv);
+	}
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
-	intel_disable_gt_powersave(dev_priv);
+	if (intel_slpc_enabled()) {
+		/* TODO: Set SLPC enabled forcefully */
+		intel_disable_gt_powersave(dev_priv);
+	} else {
+		dev_priv->rps.enabled = true; /* force disabling */
+		intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+		gen6_reset_rps_interrupts(dev_priv);
+	}
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (!intel_slpc_active(dev_priv))
+			return;
+	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_active(dev_priv)) {
+		gen9_disable_rc6(dev_priv);
+		intel_slpc_disable(dev_priv);
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_disable_rc6(dev_priv);
 		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
@@ -6627,7 +6647,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	/* Powersaving is controlled by the host when inside a VM */
@@ -6636,31 +6659,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (IS_CHERRYVIEW(dev_priv)) {
-		cherryview_enable_rps(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
-		valleyview_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_enabled()) {
 		gen9_enable_rc6(dev_priv);
-		gen9_enable_rps(dev_priv);
+		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		gen8_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
-		gen6_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (IS_IRONLAKE_M(dev_priv)) {
-		ironlake_enable_drps(dev_priv);
-		intel_init_emon(dev_priv);
-	}
+	} else {
+		if (IS_CHERRYVIEW(dev_priv)) {
+			cherryview_enable_rps(dev_priv);
+		} else if (IS_VALLEYVIEW(dev_priv)) {
+			valleyview_enable_rps(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 9) {
+			gen9_enable_rc6(dev_priv);
+			gen9_enable_rps(dev_priv);
+			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+				gen6_update_ring_freq(dev_priv);
+		} else if (IS_BROADWELL(dev_priv)) {
+			gen8_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 6) {
+			gen6_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (IS_IRONLAKE_M(dev_priv)) {
+			ironlake_enable_drps(dev_priv);
+			intel_init_emon(dev_priv);
+		}
 
-	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
 
-	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+	}
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
@@ -6672,7 +6702,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			goto out;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		goto out;
 
 	rcs = &dev_priv->engine[RCS];
@@ -6702,7 +6735,10 @@ out:
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..2e509a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_suspend(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_reset(struct drm_i915_private *dev_priv)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..ae52146
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_suspend(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+void intel_slpc_reset(struct drm_i915_private *dev_priv);
+
+#endif
-- 
1.9.1

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drm/i915/slpc: Enable SLPC in guc if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 023064d..8d737b4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -211,6 +211,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (intel_slpc_enabled())
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	if (i915.guc_log_level >= 0) {
 		params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 		params[GUC_CTL_DEBUG] =
-- 
1.9.1

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drm/i915/slpc: If using SLPC, do not set frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 21dafe0..14c29b1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4965,6 +4965,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+	if (intel_slpc_active(dev_priv))
+		return;
+
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		valleyview_set_rps(dev_priv, val);
 	else
-- 
1.9.1

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drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC shared data is used to pass information
to/from SLPC in GuC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v1: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
    change default host_os to "Windows"
    Spelling fixes (Sagar Kamble and Nick Hoath)
    Added WARN for checking if upper 32bits of GTT offset
    of shared object are zero. (ChrisW)
    Changed function call from gem_allocate/release_guc_obj to
    i915_guc_allocate/release_gem_obj. (Sagar)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE
    definition from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable
    to determine if it is active as it not just dependent on shared
    data setup.
    Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes. (David)
    Checkpatch update.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
 drivers/gpu/drm/i915/intel_guc.h  |  2 +
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
 drivers/gpu/drm/i915/intel_slpc.c | 92 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 78 +++++++++++++++++++++++++++++++++
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 353cb51..af96012 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,7 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
-	return 0;
+	int ret = 0;
+
+	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
+		ret = 1;
+
+	return ret;
 }
 
 /* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 6fdbac5..af4310c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -145,6 +145,8 @@ struct intel_guc {
 
 	uint64_t submissions[I915_NUM_ENGINES];
 	uint32_t last_seqno[I915_NUM_ENGINES];
+
+	struct intel_slpc slpc;
 };
 
 static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 14c29b1..0c739c6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6572,7 +6572,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (intel_slpc_enabled())
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma)
 		intel_slpc_cleanup(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
@@ -6662,7 +6663,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (intel_slpc_enabled()) {
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma) {
 		gen9_enable_rc6(dev_priv);
 		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 2e509a7..bb2e5fe 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,15 +22,107 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	WARN_ON(platform_sku > 0xFF);
+
+	return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+	unsigned int slice_count = 1;
+
+	if (IS_SKYLAKE(dev_priv))
+		slice_count = INTEL_INFO(dev_priv)->slice_total;
+
+	return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 msr_value;
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+
+	page = i915_gem_object_get_page(obj, 0);
+	if (page) {
+		data = kmap_atomic(page);
+		memset(data, 0, sizeof(struct slpc_shared_data));
+
+		data->slpc_version = SLPC_VERSION;
+		data->shared_data_size = sizeof(struct slpc_shared_data);
+		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
+		data->platform_info.platform_sku =
+					(u8)slpc_get_platform_sku(dev_priv);
+		data->platform_info.slice_count =
+					(u8)slpc_get_slice_count(dev_priv);
+		data->platform_info.host_os = (u8)SLPC_HOST_OS_WINDOWS_8;
+		data->platform_info.power_plan_source =
+			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+						    SLPC_POWER_SOURCE_AC);
+		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+		data->platform_info.P0_freq = (u8)msr_value;
+		rdmsrl(MSR_PLATFORM_INFO, msr_value);
+		data->platform_info.P1_freq = (u8)(msr_value >> 8);
+		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
+		data->platform_info.Pn_freq = (u8)(msr_value >> 48);
+		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
+		data->platform_info.package_rapl_limit_high =
+							(u32)(msr_value >> 32);
+		data->platform_info.package_rapl_limit_low = (u32)msr_value;
+
+		kunmap_atomic(data);
+	}
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+	struct i915_vma *vma;
+
+	/* Allocate shared data structure */
+	vma = dev_priv->guc.slpc.vma;
+	if (!vma) {
+		vma = guc_allocate_vma(guc,
+			       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		if (IS_ERR(vma)) {
+			DRM_ERROR("slpc_shared_data allocation failed\n");
+			i915.enable_slpc = 0;
+			return;
+		}
+
+		dev_priv->guc.slpc.vma = vma;
+	}
+
+	slpc_shared_data_init(dev_priv);
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+
+	/* Release shared data structure */
+	i915_vma_unpin_and_release(&guc->slpc.vma);
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index ae52146..e951289 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,84 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+#define SLPC_MAJOR_VER 2
+#define SLPC_MINOR_VER 4
+#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_host_os {
+	SLPC_HOST_OS_UNDEFINED = 0,
+	SLPC_HOST_OS_WINDOWS_8 = 1,
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 host_os;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 package_rapl_limit_high;
+	u32 package_rapl_limit_low;
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 slpc_version;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	u32 task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+struct intel_slpc {
+	struct i915_vma *vma;
+	bool enabled;
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
-- 
1.9.1

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drm/i915/slpc: Add/Update interface for requested frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLPC requested value needs to be made available to i915 without
reading RPNSWREQ.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
    Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
    don't update cur_freq as it is driver internal request. (Chris)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  6 ++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a95d7bc..2ae1fff 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1110,6 +1110,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (intel_slpc_active(dev_priv))
+		seq_puts(m, "SLPC Active\n");
+
 	if (IS_GEN5(dev)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2372,6 +2375,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_file *file;
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
 	seq_printf(m, "GPU busy? %s [%x]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index f1ffde7..5547f41 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -302,11 +302,42 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 	struct drm_device *dev = minor->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	return snprintf(buf, PAGE_SIZE, "%d\n",
 			intel_gpu_freq(dev_priv,
 				       dev_priv->rps.cur_freq));
 }
 
+static ssize_t gt_req_freq_mhz_show(struct device *kdev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct drm_minor *minor = dev_to_drm_minor(kdev);
+	struct drm_device *dev = minor->dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	u32 reqf;
+
+	if (!intel_runtime_pm_get_if_in_use(dev_priv))
+		return -ENODEV;
+
+	reqf = I915_READ(GEN6_RPNSWREQ);
+	intel_runtime_pm_put(dev_priv);
+
+	if (IS_GEN9(dev))
+		reqf >>= 23;
+	else {
+		reqf &= ~GEN6_TURBO_DISABLE;
+		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+			reqf >>= 24;
+		else
+			reqf >>= 25;
+	}
+	reqf = intel_gpu_freq(dev_priv, reqf);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", reqf);
+}
+
 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_minor *minor = dev_to_drm_minor(kdev);
@@ -476,6 +507,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
+static DEVICE_ATTR(gt_req_freq_mhz, S_IRUGO, gt_req_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
@@ -510,6 +542,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 static const struct attribute *gen6_attrs[] = {
 	&dev_attr_gt_act_freq_mhz.attr,
 	&dev_attr_gt_cur_freq_mhz.attr,
+	&dev_attr_gt_req_freq_mhz.attr,
 	&dev_attr_gt_boost_freq_mhz.attr,
 	&dev_attr_gt_max_freq_mhz.attr,
 	&dev_attr_gt_min_freq_mhz.attr,
-- 
1.9.1

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drm/i915/slpc: Send reset event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add host2guc SLPC reset event and send reset event
during enable.

v1: Extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 28 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index bb2e5fe..b6de200 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+	int ret = i915_guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= SLPC_EVENT_STATUS_MASK;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -135,6 +161,8 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_reset(dev_priv);
+	dev_priv->guc.slpc.enabled = true;
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index e951289..031e36b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK	0xFF
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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drm/i915/slpc: Send shutdown event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b6de200..637eacb 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -153,10 +166,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
@@ -167,4 +184,6 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
-- 
1.9.1

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drm/i915/slpc: Add slpc_status enum values

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

v1: fix whitespace (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 031e36b..9fe9ae3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,33 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MISMATCHING_VERSION = 16,
+	SLPC_STATUS_MEMIO_ERROR = 17,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
+	SLPC_STATUS_NO_EVENT_QUEUED = 20,
+	SLPC_STATUS_OUT_OF_SPACE = 21,
+	SLPC_STATUS_TIMEOUT = 22,
+	SLPC_STATUS_NO_LOCK = 23,
+};
+
 enum slpc_event_id {
 	SLPC_EVENT_RESET = 0,
 	SLPC_EVENT_SHUTDOWN = 1,
-- 
1.9.1

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drm/i915/slpc: Add parameter unset/set/get functions

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add slpc_param_id enum values.
Add events for setting/unsetting parameters.

v1: Use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

v2: Checkpatch update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 102 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  29 ++++++++++-
 2 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 637eacb..db912bc 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,108 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+				    enum slpc_param_id id, u32 value)
+{
+	u32 data[4];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data[2] = (u32) id;
+	data[3] = value;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+				      enum slpc_param_id id)
+{
+	u32 data[3];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data[2] = (u32) id;
+
+	host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							&= (~(1 << (id % 32)));
+		data->override_parameters_values[id] = 0;
+		kunmap_atomic(data);
+
+		host2guc_slpc_unset_param(dev_priv, id);
+	}
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							|= (1 << (id % 32));
+		data->override_parameters_values[id] = value;
+		kunmap_atomic(data);
+
+		host2guc_slpc_set_param(dev_priv, id, value);
+	}
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		if (overriding) {
+			bits = data->override_parameters_set_bits[id >> 5];
+			*overriding = (0 != (bits & (1 << (id % 32))));
+		}
+		if (value)
+			*value = data->override_parameters_values[id];
+
+		kunmap_atomic(data);
+	}
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 9fe9ae3..018f772 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -69,6 +69,26 @@ enum slpc_event_id {
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 #define SLPC_EVENT_STATUS_MASK	0xFF
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -150,5 +170,12 @@ void intel_slpc_suspend(struct drm_i915_private *dev_priv);
 void intel_slpc_disable(struct drm_i915_private *dev_priv);
 void intel_slpc_enable(struct drm_i915_private *dev_priv);
 void intel_slpc_reset(struct drm_i915_private *dev_priv);
-
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value);
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value);
 #endif
-- 
1.9.1

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drm/i915/slpc: Add slpc support for max/min freq

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2ae1fff..6bbed50 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4959,6 +4959,15 @@ i915_max_freq_set(void *data, u64 val)
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -5015,6 +5024,15 @@ i915_min_freq_set(void *data, u64 val)
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 5547f41..6a0b319 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -431,6 +431,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
@@ -488,6 +497,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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drm/i915/slpc: Add enable/disable debugfs for slpc

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
    Avoid magic numbers (Jon Bloomfield)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 252 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   5 +
 2 files changed, 257 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6bbed50..755941e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1101,6 +1101,255 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			i915_next_seqno_get, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+				     &value_disable);
+
+		/* set the output value:
+		* 0: default
+		* 1: enabled
+		* 2: disabled
+		* 3: unknown (should not happen)
+		*/
+		if (override_disable && (value_disable == 1))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (value_enable == 1))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		intel_slpc_unset_param(dev_priv, enable_id);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		intel_slpc_set_param(dev_priv, enable_id, 1);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		intel_slpc_set_param(dev_priv, disable_id, 1);
+		intel_slpc_unset_param(dev_priv, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = slpc_enable_disable_set(dev, val, enable_id, disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			       SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = m->private;
@@ -5419,6 +5668,9 @@ static const struct i915_debugfs_files {
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 018f772..aef8324 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -89,6 +89,11 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
 };
 
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
    Avoid magic numbers and use local variables (Jon Bloomfield)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Moved definition of power plan and power source to earlier
    patch in the series.
    drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
    (Akash)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 184 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   |  19 ++++
 drivers/gpu/drm/i915/intel_slpc.h   |   1 +
 3 files changed, 204 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 755941e..1a8e4bb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1350,6 +1350,189 @@ static const struct file_operations i915_slpc_dcc_fops = {
 	.llseek	 = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
+	int i, value;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	enum slpc_host_os host_os;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		intel_slpc_query_task_state(dev_priv);
+
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			pv = kmap_atomic(page);
+	}
+
+	if (pv) {
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
+			   data.slpc_version >> 16,
+			   (data.slpc_version >> 8) & 0xFF,
+			   data.slpc_version & 0xFF,
+			   data.slpc_version);
+		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+		global_state = (enum slpc_global_state) data.global_state;
+		seq_printf(m, "global state: %d (", global_state);
+		switch (global_state) {
+		case SLPC_GLOBAL_STATE_NOT_RUNNING:
+			seq_puts(m, "not running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_INITIALIZING:
+			seq_puts(m, "initializing)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RESETTING:
+			seq_puts(m, "resetting)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RUNNING:
+			seq_puts(m, "running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+			seq_puts(m, "shutting down)\n");
+			break;
+		case SLPC_GLOBAL_STATE_ERROR:
+			seq_puts(m, "error)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		platform_sku = (enum slpc_platform_sku)
+				data.platform_info.platform_sku;
+		seq_printf(m, "sku: %d (", platform_sku);
+		switch (platform_sku) {
+		case SLPC_PLATFORM_SKU_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULX:
+			seq_puts(m, "ULX)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULT:
+			seq_puts(m, "ULT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_T:
+			seq_puts(m, "T)\n");
+			break;
+		case SLPC_PLATFORM_SKU_MOBL:
+			seq_puts(m, "Mobile)\n");
+			break;
+		case SLPC_PLATFORM_SKU_DT:
+			seq_puts(m, "DT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_UNKNOWN:
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+		seq_printf(m, "slice count: %d\n",
+			   data.platform_info.slice_count);
+
+		host_os = (enum slpc_host_os) data.platform_info.host_os;
+		seq_printf(m, "host OS: %d (", host_os);
+		switch (host_os) {
+		case SLPC_HOST_OS_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_HOST_OS_WINDOWS_8:
+			seq_puts(m, "Windows 8)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+			   data.platform_info.power_plan_source);
+		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+					data.platform_info.power_plan_source);
+		power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+					data.platform_info.power_plan_source);
+		switch (power_plan) {
+		case SLPC_POWER_PLAN_UNDEFINED:
+			seq_puts(m, "undefined");
+			break;
+		case SLPC_POWER_PLAN_BATTERY_SAVER:
+			seq_puts(m, "battery saver");
+			break;
+		case SLPC_POWER_PLAN_BALANCED:
+			seq_puts(m, "balanced");
+			break;
+		case SLPC_POWER_PLAN_PERFORMANCE:
+			seq_puts(m, "performance");
+			break;
+		case SLPC_POWER_PLAN_UNKNOWN:
+		default:
+			seq_puts(m, "unknown");
+			break;
+		}
+		seq_puts(m, "\n\tsource:\t");
+		switch (power_source) {
+		case SLPC_POWER_SOURCE_UNDEFINED:
+			seq_puts(m, "undefined\n");
+			break;
+		case SLPC_POWER_SOURCE_AC:
+			seq_puts(m, "AC\n");
+			break;
+		case SLPC_POWER_SOURCE_DC:
+			seq_puts(m, "DC\n");
+			break;
+		case SLPC_POWER_SOURCE_UNKNOWN:
+		default:
+			seq_puts(m, "unknown\n");
+			break;
+		}
+
+		seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+			   data.platform_info.P0_freq * 50,
+			   data.platform_info.P1_freq * 50,
+			   data.platform_info.Pe_freq * 50,
+			   data.platform_info.Pn_freq * 50);
+		seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
+			   data.platform_info.package_rapl_limit_high,
+			   data.platform_info.package_rapl_limit_low);
+		seq_printf(m, "task state data: 0x%08x\n",
+			   data.task_state_data);
+		seq_printf(m, "\tturbo active: %d\n",
+			   (data.task_state_data & 1));
+		seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
+			   (data.task_state_data & 2),
+			   (data.task_state_data & 4),
+			   (data.task_state_data >> 3) & 0xFF);
+
+		seq_puts(m, "override parameter bitfield\n");
+		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+			seq_printf(m, "%d: 0x%08x\n", i,
+				   data.override_parameters_set_bits[i]);
+
+		seq_puts(m, "override parameters (only non-zero shown)\n");
+		for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+			value = data.override_parameters_values[i];
+			if (value)
+				seq_printf(m, "%d: 0x%8x\n", i, value);
+		}
+
+	} else {
+		seq_puts(m, "no SLPC info available\n");
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = m->private;
@@ -5626,6 +5809,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index db912bc..06e4a95 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -167,6 +167,25 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	if (intel_slpc_active(dev_priv))
+		host2guc_slpc_query_task_state(dev_priv);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index aef8324..e236d9d 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -183,4 +183,5 @@ void intel_slpc_set_param(struct drm_i915_private *dev_priv,
 void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
 #endif
-- 
1.9.1

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drm/i915/slpc: Add broxton support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.

v1: Adjusted slpc version check for major version 8.
    Added message if version mismatch happens for easier debug. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c         | 1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e678051..60a5eb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -342,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
+	.has_slpc = 1,
 	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8d737b4..13ffd47 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -164,8 +164,11 @@ static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
+	}
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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drm/i915: Check GuC load status for Host to GuC action and SLPC status

[Sagar Arun Kamble]

Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.

v2: Space and function return convention issues. (Deepak)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++++
 drivers/gpu/drm/i915/intel_drv.h           | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 9a69bf1..cc1d5e3 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -78,6 +78,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct intel_guc_fw *guc_fw = &guc->guc_fw;
 	u32 status;
 	int i;
 	int ret;
@@ -85,6 +86,9 @@ int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 	if (WARN_ON(len < 1 || len > 15))
 		return -EINVAL;
 
+	if (WARN_ON(guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS))
+		return -ENODEV;
+
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	dev_priv->guc.action_count += 1;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index af96012..64ca0d3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,8 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int ret = 0;
 
+	if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+		return ret;
+
 	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
 		ret = 1;
 
-- 
1.9.1

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drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

[Sagar Arun Kamble]

This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d5d0a50..627d223 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1629,6 +1629,7 @@ static int i915_drm_resume(struct drm_device *dev)
 static int i915_drm_resume_early(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int ret;
 
 	/*
@@ -1685,6 +1686,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 			  ret);
 
+	/*
+	 * Mark GuC FW load status as PENDING to avoid any Host to GuC actions
+	 * invoked till GuC gets loaded in i915_drm_resume.
+	*/
+	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+
 	intel_uncore_early_sanitize(dev_priv, true);
 
 	if (IS_BROXTON(dev_priv)) {
-- 
1.9.1

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drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall

[Sagar Arun Kamble]

v1: Updated tasks and frequency post reset.
    Added DFPS param update for MAX_FPS and FPS Stall.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/intel_slpc.c   | 30 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 +++++
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a8e4bb..f0474f1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1140,7 +1140,7 @@ static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
 	return ret;
 }
 
-static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
 				   enum slpc_param_id enable_id,
 				   enum slpc_param_id disable_id)
 {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 06e4a95..6883f44 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -299,8 +299,38 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	u64 val;
+
 	host2guc_slpc_reset(dev_priv);
 	dev_priv->guc.slpc.enabled = true;
+
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_GTPERF,
+				SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_BALANCER,
+				SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_DCC,
+				SLPC_PARAM_TASK_DISABLE_DCC);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
+			     1);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
+			     1);
+
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index e236d9d..a2161b0b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -184,4 +184,9 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
 void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
+
+/* i915_debugfs.c */
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+			    enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id);
 #endif
-- 
1.9.1

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drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

[Sagar Arun Kamble]

With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0c739c6..2a3381c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4982,7 +4982,13 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(GEN6_RP_CONTROL, 0);
+	uint32_t rp_ctl = 0;
+
+	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
+	if (i915.enable_slpc)
+		rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
+
+	I915_WRITE(GEN6_RP_CONTROL, rp_ctl);
 
 	dev_priv->rps.enabled = false;
 }
-- 
1.9.1

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drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC

[Sagar Arun Kamble]

v2: Checkpatch update.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 71 ++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_guc_loader.c | 12 +++---
 drivers/gpu/drm/i915/intel_slpc.c       | 27 +++++++-----
 drivers/gpu/drm/i915/intel_slpc.h       | 73 ++++++++++++++++++++++-----------
 4 files changed, 110 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f0474f1..83f26ef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1359,10 +1359,10 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 	struct page *page;
 	void *pv = NULL;
 	struct slpc_shared_data data;
+	struct slpc_task_state_data *task_data;
 	int i, value;
 	enum slpc_global_state global_state;
 	enum slpc_platform_sku platform_sku;
-	enum slpc_host_os host_os;
 	enum slpc_power_plan power_plan;
 	enum slpc_power_source power_source;
 
@@ -1379,11 +1379,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 		data = *(struct slpc_shared_data *) pv;
 		kunmap_atomic(pv);
 
-		seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
-			   data.slpc_version >> 16,
-			   (data.slpc_version >> 8) & 0xFF,
-			   data.slpc_version & 0xFF,
-			   data.slpc_version);
 		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
 
 		global_state = (enum slpc_global_state) data.global_state;
@@ -1442,20 +1437,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 		seq_printf(m, "slice count: %d\n",
 			   data.platform_info.slice_count);
 
-		host_os = (enum slpc_host_os) data.platform_info.host_os;
-		seq_printf(m, "host OS: %d (", host_os);
-		switch (host_os) {
-		case SLPC_HOST_OS_UNDEFINED:
-			seq_puts(m, "undefined)\n");
-			break;
-		case SLPC_HOST_OS_WINDOWS_8:
-			seq_puts(m, "Windows 8)\n");
-			break;
-		default:
-			seq_puts(m, "unknown)\n");
-			break;
-		}
-
 		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
 			   data.platform_info.power_plan_source);
 		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
@@ -1502,17 +1483,45 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 			   data.platform_info.P1_freq * 50,
 			   data.platform_info.Pe_freq * 50,
 			   data.platform_info.Pn_freq * 50);
-		seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
-			   data.platform_info.package_rapl_limit_high,
-			   data.platform_info.package_rapl_limit_low);
-		seq_printf(m, "task state data: 0x%08x\n",
-			   data.task_state_data);
-		seq_printf(m, "\tturbo active: %d\n",
-			   (data.task_state_data & 1));
-		seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
-			   (data.task_state_data & 2),
-			   (data.task_state_data & 4),
-			   (data.task_state_data >> 3) & 0xFF);
+		task_data = &data.task_state_data;
+		seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+			   task_data->bitfield1, task_data->bitfield2);
+
+		seq_printf(m, "\tgtperf task active: %s\n",
+			   yesno(task_data->gtperf_task_active));
+		seq_printf(m, "\tgtperf stall possible: %s\n",
+			   yesno(task_data->gtperf_stall_possible));
+		seq_printf(m, "\tgtperf gaming mode: %s\n",
+			   yesno(task_data->gtperf_gaming_mode));
+		seq_printf(m, "\tgtperf target fps: %d\n",
+			   task_data->gtperf_target_fps);
+
+		seq_printf(m, "\tdcc task active: %s\n",
+			   yesno(task_data->dcc_task_active));
+		seq_printf(m, "\tin dcc: %s\n",
+			   yesno(task_data->in_dcc));
+		seq_printf(m, "\tin dct: %s\n",
+			   yesno(task_data->in_dct));
+		seq_printf(m, "\tfreq switch active: %d\n",
+			   task_data->freq_switch_active);
+
+		seq_printf(m, "\tibc enabled: %s\n",
+			   yesno(task_data->ibc_enabled));
+		seq_printf(m, "\tibc active: %s\n",
+			   yesno(task_data->ibc_active));
+		seq_printf(m, "\tpg1 enabled: %s\n",
+			   yesno(task_data->pg1_enabled));
+		seq_printf(m, "\tpg1 active: %s\n",
+			   yesno(task_data->pg1_active));
+
+		seq_printf(m, "\tunslice max freq: %d\n",
+			   task_data->freq_unslice_max);
+		seq_printf(m, "\tunslice min freq: %d\n",
+			   task_data->freq_unslice_min);
+		seq_printf(m, "\tslice max freq: %d\n",
+			   task_data->freq_slice_max);
+		seq_printf(m, "\tslice min freq: %d\n",
+			   task_data->freq_slice_min);
 
 		seq_puts(m, "override parameter bitfield\n");
 		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 13ffd47..4ec5a4d 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -59,11 +59,11 @@
  *
  */
 
-#define SKL_FW_MAJOR 6
-#define SKL_FW_MINOR 1
+#define SKL_FW_MAJOR 9
+#define SKL_FW_MINOR 18
 
-#define BXT_FW_MAJOR 8
-#define BXT_FW_MINOR 7
+#define BXT_FW_MAJOR 9
+#define BXT_FW_MINOR 18
 
 #define KBL_FW_MAJOR 9
 #define KBL_FW_MINOR 14
@@ -164,8 +164,8 @@ static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
-	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
 		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
 	}
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 6883f44..5ab8362 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -229,14 +229,12 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
 		data = kmap_atomic(page);
 		memset(data, 0, sizeof(struct slpc_shared_data));
 
-		data->slpc_version = SLPC_VERSION;
 		data->shared_data_size = sizeof(struct slpc_shared_data);
 		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
 		data->platform_info.platform_sku =
 					(u8)slpc_get_platform_sku(dev_priv);
 		data->platform_info.slice_count =
 					(u8)slpc_get_slice_count(dev_priv);
-		data->platform_info.host_os = (u8)SLPC_HOST_OS_WINDOWS_8;
 		data->platform_info.power_plan_source =
 			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
 						    SLPC_POWER_SOURCE_AC);
@@ -246,10 +244,6 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
 		data->platform_info.P1_freq = (u8)(msr_value >> 8);
 		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
 		data->platform_info.Pn_freq = (u8)(msr_value >> 48);
-		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
-		data->platform_info.package_rapl_limit_high =
-							(u32)(msr_value >> 32);
-		data->platform_info.package_rapl_limit_low = (u32)msr_value;
 
 		kunmap_atomic(data);
 	}
@@ -320,17 +314,28 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 				SLPC_PARAM_TASK_DISABLE_DCC);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
-			     1);
+			     SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+			     0);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+			     SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
 			     0);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
-			     1);
+			     SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+			     0);
 
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			     0);
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a2161b0b..c773617 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,10 +24,6 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
-#define SLPC_MAJOR_VER 2
-#define SLPC_MINOR_VER 4
-#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
-
 enum slpc_status {
 	SLPC_STATUS_OK = 0,
 	SLPC_STATUS_ERROR = 1,
@@ -45,14 +41,13 @@ enum slpc_status {
 	SLPC_STATUS_VALUE_ALREADY_SET = 13,
 	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
 	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
-	SLPC_STATUS_MISMATCHING_VERSION = 16,
-	SLPC_STATUS_MEMIO_ERROR = 17,
-	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
-	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
-	SLPC_STATUS_NO_EVENT_QUEUED = 20,
-	SLPC_STATUS_OUT_OF_SPACE = 21,
-	SLPC_STATUS_TIMEOUT = 22,
-	SLPC_STATUS_NO_LOCK = 23,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
 };
 
 enum slpc_event_id {
@@ -80,13 +75,16 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
 	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
 	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
-	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
 	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
-	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
 	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
 	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
 	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
-	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
 };
 
 #define SLPC_PARAM_TASK_DEFAULT 0
@@ -103,11 +101,6 @@ enum slpc_global_state {
 	SLPC_GLOBAL_STATE_ERROR = 5
 };
 
-enum slpc_host_os {
-	SLPC_HOST_OS_UNDEFINED = 0,
-	SLPC_HOST_OS_WINDOWS_8 = 1,
-};
-
 enum slpc_platform_sku {
 	SLPC_PLATFORM_SKU_UNDEFINED = 0,
 	SLPC_PLATFORM_SKU_ULX = 1,
@@ -140,25 +133,55 @@ enum slpc_power_source {
 struct slpc_platform_info {
 	u8 platform_sku;
 	u8 slice_count;
-	u8 host_os;
+	u8 reserved;
 	u8 power_plan_source;
 	u8 P0_freq;
 	u8 P1_freq;
 	u8 Pe_freq;
 	u8 Pn_freq;
-	u32 package_rapl_limit_high;
-	u32 package_rapl_limit_low;
+	u32 reserved1;
+	u32 reserved2;
 } __packed;
 
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 freq_unslice_max:8;
+			u32 freq_unslice_min:8;
+			u32 freq_slice_max:8;
+			u32 freq_slice_min:8;
+		};
+	};
+};
+
 #define SLPC_MAX_OVERRIDE_PARAMETERS 192
 #define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
 
 struct slpc_shared_data {
-	u32 slpc_version;
+	u32 reserved;
 	u32 shared_data_size;
 	u32 global_state;
 	struct slpc_platform_info platform_info;
-	u32 task_state_data;
+	struct slpc_task_state_data task_state_data;
 	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
 	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
 } __packed;
-- 
1.9.1

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drm/i915/slpc: Update freq min/max softlimits

[Sagar Arun Kamble]

v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 5ab8362..7062d8b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -293,6 +293,10 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
 	u64 val;
 
 	host2guc_slpc_reset(dev_priv);
@@ -336,6 +340,25 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 	intel_slpc_set_param(dev_priv,
 			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			     0);
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	intel_slpc_query_task_state(dev_priv);
+
+	pv = kmap_atomic(i915_gem_object_get_page(obj, 0));
+	data = *(struct slpc_shared_data *) pv;
+	kunmap_atomic(pv);
+
+	/*
+	 * TODO: Define separate variables for slice and unslice
+	 *	 frequencies for driver state variable.
+	 */
+	dev_priv->rps.max_freq_softlimit =
+			data.task_state_data.freq_unslice_max;
+	dev_priv->rps.min_freq_softlimit =
+			data.task_state_data.freq_unslice_min;
+
+	dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+	dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: drm/i915/slpc: Update freq min/max softlimits

[Chris Wilson]

On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote:
> 
> 
> On 8/20/2016 1:32 PM, Chris Wilson wrote:
> >On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:
> >>+	obj = dev_priv->guc.slpc.vma->obj;
> >>+	if (obj) {
> >OOPS.
> Fixed in next series.
> >
> >>+		intel_slpc_query_task_state(dev_priv);
> >>+
> >>+		page = i915_gem_object_get_page(obj, 0);
> >>+		if (page)
> >>+			pv = kmap_atomic(page);
> >>+	}
> >>+
> >>+	if (pv) {
> >>+		data = *(struct slpc_shared_data *) pv;
> >>+		kunmap_atomic(pv);
> >Can kmap_atomic return zero?
> Fixed in next series.
> >
> >>+
> >>+		/*
> >>+		 * TODO: Define separate variables for slice and unslice
> >>+		 *	 frequencies for driver state variable.
> >>+		 */
> >>+		dev_priv->rps.max_freq_softlimit =
> >>+				data.task_state_data.freq_unslice_max;
> >>+		dev_priv->rps.min_freq_softlimit =
> >>+				data.task_state_data.freq_unslice_min;
> >These are user values, you do not get to arbitrarily rewrite them.
> >
> >You control dev_priv->rps.[min|max]_freq.
> With SLPC, GuC firmware SLPC S/W requested frequency be operated in
> the softlimits analogous to
> Host softlimits. Limits might be different with SLPC and can be
> controlled through regular interfaces.
> dev_priv->rps.[min|max]_freq are HW Min/Max.

Exactly. The soft limits are *only* set by the user. They are not to
modified by the driver. (The caveat would be a dynamic update of the hw
range, but that too should never be required.)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: drm/i915/slpc: Update freq min/max softlimits

[Kamble, Sagar A]

On 8/21/2016 2:09 PM, Chris Wilson wrote:
> On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote:
>>
>> On 8/20/2016 1:32 PM, Chris Wilson wrote:
>>> On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:
>>>> +	obj = dev_priv->guc.slpc.vma->obj;
>>>> +	if (obj) {
>>> OOPS.
>> Fixed in next series.
>>>> +		intel_slpc_query_task_state(dev_priv);
>>>> +
>>>> +		page = i915_gem_object_get_page(obj, 0);
>>>> +		if (page)
>>>> +			pv = kmap_atomic(page);
>>>> +	}
>>>> +
>>>> +	if (pv) {
>>>> +		data = *(struct slpc_shared_data *) pv;
>>>> +		kunmap_atomic(pv);
>>> Can kmap_atomic return zero?
>> Fixed in next series.
>>>> +
>>>> +		/*
>>>> +		 * TODO: Define separate variables for slice and unslice
>>>> +		 *	 frequencies for driver state variable.
>>>> +		 */
>>>> +		dev_priv->rps.max_freq_softlimit =
>>>> +				data.task_state_data.freq_unslice_max;
>>>> +		dev_priv->rps.min_freq_softlimit =
>>>> +				data.task_state_data.freq_unslice_min;
>>> These are user values, you do not get to arbitrarily rewrite them.
>>>
>>> You control dev_priv->rps.[min|max]_freq.
>> With SLPC, GuC firmware SLPC S/W requested frequency be operated in
>> the softlimits analogous to
>> Host softlimits. Limits might be different with SLPC and can be
>> controlled through regular interfaces.
>> dev_priv->rps.[min|max]_freq are HW Min/Max.
> Exactly. The soft limits are *only* set by the user. They are not to
> modified by the driver. (The caveat would be a dynamic update of the hw
> range, but that too should never be required.)
> -Chris
This initialization is similar to following from intel_init_gt_powersave
         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
I assume min_freq is hw min(RPn). With SLPC, min_freq(RPn) will not be 
requested.
SLPC operating range today is (>Rpe, Rp0) so I wanted user to know
the min_softlimit being initialized by SLPC by default.


>

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Re: drm/i915/slpc: Enable SLPC in guc if supported

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1751 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160819]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-Enable-SLPC-in-guc-if-supported/20160820-132618
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_guc_loader.c: In function 'set_guc_init_params':
>> drivers/gpu/drm/i915/intel_guc_loader.c:178:6: error: implicit declaration of function 'intel_slpc_enabled' [-Werror=implicit-function-declaration]
     if (intel_slpc_enabled())
         ^~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/intel_slpc_enabled +178 drivers/gpu/drm/i915/intel_guc_loader.c

   172	
   173		params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
   174	
   175		params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
   176				GUC_CTL_VCS2_ENABLED;
   177	
 > 178		if (intel_slpc_enabled())
   179			params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
   180	
   181		if (i915.guc_log_level >= 0) {

---
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[-- Attachment #2: .config.gz --]
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Re: drm/i915/slpc: Enable SLPC in guc if supported

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3025 bytes --]

Hi Tom,

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.8-rc3 next-20160819]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-Enable-SLPC-in-guc-if-supported/20160820-132618
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x009-201633 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/firmware.h:4,
                    from drivers/gpu/drm/i915/intel_guc_loader.c:29:
   drivers/gpu/drm/i915/intel_guc_loader.c: In function 'set_guc_init_params':
   drivers/gpu/drm/i915/intel_guc_loader.c:178:6: error: implicit declaration of function 'intel_slpc_enabled' [-Werror=implicit-function-declaration]
     if (intel_slpc_enabled())
         ^
   include/linux/compiler.h:151:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_guc_loader.c:178:2: note: in expansion of macro 'if'
     if (intel_slpc_enabled())
     ^~
   cc1: some warnings being treated as errors

vim +/if +178 drivers/gpu/drm/i915/intel_guc_loader.c

   162			(get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
   163			(get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
   164	
   165		/*
   166		 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
   167		 * second. This ARAR is calculated by:
   168		 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
   169		 */
   170		params[GUC_CTL_ARAT_HIGH] = 0;
   171		params[GUC_CTL_ARAT_LOW] = 100000000;
   172	
   173		params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
   174	
   175		params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
   176				GUC_CTL_VCS2_ENABLED;
   177	
 > 178		if (intel_slpc_enabled())
   179			params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
   180	
   181		if (i915.guc_log_level >= 0) {
   182			params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
   183			params[GUC_CTL_DEBUG] =
   184				i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
   185		}
   186	

---
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Re: drm/i915/slpc: Add SKL SLPC Support

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1597 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160819]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-Add-SKL-SLPC-Support/20160820-132820
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x013-201633 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/i915_pci.c:324:2: error: unknown field 'has_slpc' specified in initializer
     .has_slpc = 1,
     ^
   drivers/gpu/drm/i915/i915_pci.c:331:2: error: unknown field 'has_slpc' specified in initializer
     .has_slpc = 1,
     ^

vim +/has_slpc +324 drivers/gpu/drm/i915/i915_pci.c

   318	};
   319	
   320	static const struct intel_device_info intel_skylake_info = {
   321		BDW_FEATURES,
   322		.is_skylake = 1,
   323		.gen = 9,
 > 324		.has_slpc = 1,
   325	};
   326	
   327	static const struct intel_device_info intel_skylake_gt3_info = {

---
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Re: drm/i915/slpc: Add slpc support for max/min freq

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 7662 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160819]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-Add-slpc-support-for-max-min-freq/20160821-143422
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_sysfs.c: In function 'gt_max_freq_mhz_store':
>> drivers/gpu/drm/i915/i915_sysfs.c:385:6: error: implicit declaration of function 'intel_slpc_active' [-Werror=implicit-function-declaration]
     if (intel_slpc_active(dev_priv)) {
         ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_sysfs.c:386:3: error: implicit declaration of function 'intel_slpc_set_param' [-Werror=implicit-function-declaration]
      intel_slpc_set_param(dev_priv,
      ^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_sysfs.c:387:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_sysfs.c:387:10: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/i915_sysfs.c:390:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_sysfs.c: In function 'gt_min_freq_mhz_store':
>> drivers/gpu/drm/i915/i915_sysfs.c:460:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_sysfs.c:463:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu/drm/i915/i915_debugfs.c: In function 'i915_max_freq_set':
>> drivers/gpu/drm/i915/i915_debugfs.c:5004:6: error: implicit declaration of function 'intel_slpc_active' [-Werror=implicit-function-declaration]
     if (intel_slpc_active(dev_priv)) {
         ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_debugfs.c:5005:3: error: implicit declaration of function 'intel_slpc_set_param' [-Werror=implicit-function-declaration]
      intel_slpc_set_param(dev_priv,
      ^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_debugfs.c:5006:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_debugfs.c:5006:10: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/i915_debugfs.c:5009:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_debugfs.c: In function 'i915_min_freq_set':
>> drivers/gpu/drm/i915/i915_debugfs.c:5082:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_debugfs.c:5085:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/intel_slpc_active +385 drivers/gpu/drm/i915/i915_sysfs.c

   379		if (val > dev_priv->rps.rp0_freq)
   380			DRM_DEBUG("User requested overclocking to %d\n",
   381				  intel_gpu_freq(dev_priv, val));
   382	
   383		dev_priv->rps.max_freq_softlimit = val;
   384	
 > 385		if (intel_slpc_active(dev_priv)) {
 > 386			intel_slpc_set_param(dev_priv,
 > 387					     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
   388					     (u32) intel_gpu_freq(dev_priv, val));
   389			intel_slpc_set_param(dev_priv,
 > 390					     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
   391					     (u32) intel_gpu_freq(dev_priv, val));
   392		}
   393	
   394		val = clamp_t(int, dev_priv->rps.cur_freq,
   395			      dev_priv->rps.min_freq_softlimit,
   396			      dev_priv->rps.max_freq_softlimit);
   397	
   398		/* We still need *_set_rps to process the new max_delay and
   399		 * update the interrupt limits and PMINTRMSK even though
   400		 * frequency request may be unchanged. */
   401		intel_set_rps(dev_priv, val);
   402	
   403		mutex_unlock(&dev_priv->rps.hw_lock);
   404	
   405		intel_runtime_pm_put(dev_priv);
   406	
   407		return count;
   408	}
   409	
   410	static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
   411	{
   412		struct drm_minor *minor = dev_to_drm_minor(kdev);
   413		struct drm_device *dev = minor->dev;
   414		struct drm_i915_private *dev_priv = to_i915(dev);
   415		int ret;
   416	
   417		flush_delayed_work(&dev_priv->rps.delayed_resume_work);
   418	
   419		mutex_lock(&dev_priv->rps.hw_lock);
   420		ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
   421		mutex_unlock(&dev_priv->rps.hw_lock);
   422	
   423		return snprintf(buf, PAGE_SIZE, "%d\n", ret);
   424	}
   425	
   426	static ssize_t gt_min_freq_mhz_store(struct device *kdev,
   427					     struct device_attribute *attr,
   428					     const char *buf, size_t count)
   429	{
   430		struct drm_minor *minor = dev_to_drm_minor(kdev);
   431		struct drm_device *dev = minor->dev;
   432		struct drm_i915_private *dev_priv = to_i915(dev);
   433		u32 val;
   434		ssize_t ret;
   435	
   436		ret = kstrtou32(buf, 0, &val);
   437		if (ret)
   438			return ret;
   439	
   440		flush_delayed_work(&dev_priv->rps.delayed_resume_work);
   441	
   442		intel_runtime_pm_get(dev_priv);
   443	
   444		mutex_lock(&dev_priv->rps.hw_lock);
   445	
   446		val = intel_freq_opcode(dev_priv, val);
   447	
   448		if (val < dev_priv->rps.min_freq ||
   449		    val > dev_priv->rps.max_freq ||
   450		    val > dev_priv->rps.max_freq_softlimit) {
   451			mutex_unlock(&dev_priv->rps.hw_lock);
   452			intel_runtime_pm_put(dev_priv);
   453			return -EINVAL;
   454		}
   455	
   456		dev_priv->rps.min_freq_softlimit = val;
   457	
   458		if (intel_slpc_active(dev_priv)) {
   459			intel_slpc_set_param(dev_priv,
 > 460					     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
   461					     (u32) intel_gpu_freq(dev_priv, val));
   462			intel_slpc_set_param(dev_priv,
 > 463					     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
   464					     (u32) intel_gpu_freq(dev_priv, val));
   465		}
   466	

---
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Re: drm/i915/slpc: If using SLPC, do not set frequency

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1694 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160819]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-If-using-SLPC-do-not-set-frequency/20160821-142010
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_pm.c: In function 'intel_set_rps':
>> drivers/gpu/drm/i915/intel_pm.c:4944:6: error: implicit declaration of function 'intel_slpc_active' [-Werror=implicit-function-declaration]
     if (intel_slpc_active(dev_priv))
         ^~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/intel_slpc_active +4944 drivers/gpu/drm/i915/intel_pm.c

  4938		}
  4939		spin_unlock(&dev_priv->rps.client_lock);
  4940	}
  4941	
  4942	void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
  4943	{
> 4944		if (intel_slpc_active(dev_priv))
  4945			return;
  4946	
  4947		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
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Re: drm/i915/slpc: Add enable_slpc module parameter

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1753 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160819]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-Add-enable_slpc-module-parameter/20160820-131710
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x015-201633 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_guc_loader.c: In function 'sanitize_slpc_option':
>> drivers/gpu/drm/i915/intel_guc_loader.c:139:22: error: implicit declaration of function 'HAS_SLPC' [-Werror=implicit-function-declaration]
      i915.enable_slpc = HAS_SLPC(dev);
                         ^~~~~~~~
   cc1: some warnings being treated as errors

vim +/HAS_SLPC +139 drivers/gpu/drm/i915/intel_guc_loader.c

   133	}
   134	
   135	static void sanitize_slpc_option(struct drm_device *dev)
   136	{
   137		/* Handle default case */
   138		if (i915.enable_slpc < 0)
 > 139			i915.enable_slpc = HAS_SLPC(dev);
   140	
   141		/* slpc requires hardware support and compatible firmware */
   142		if (!HAS_SLPC(dev))

---
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Re: drm/i915/slpc: Add slpc support for max/min freq

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 7666 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160822]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-Add-slpc-support-for-max-min-freq/20160820-132319
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel-7.2 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_sysfs.c: In function 'gt_max_freq_mhz_store':
>> drivers/gpu/drm/i915/i915_sysfs.c:385:6: error: implicit declaration of function 'intel_slpc_active' [-Werror=implicit-function-declaration]
     if (intel_slpc_active(dev_priv)) {
         ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_sysfs.c:386:3: error: implicit declaration of function 'intel_slpc_set_param' [-Werror=implicit-function-declaration]
      intel_slpc_set_param(dev_priv,
      ^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_sysfs.c:387:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_sysfs.c:387:10: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/i915_sysfs.c:390:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_sysfs.c: In function 'gt_min_freq_mhz_store':
>> drivers/gpu/drm/i915/i915_sysfs.c:460:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_sysfs.c:463:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu/drm/i915/i915_debugfs.c: In function 'i915_max_freq_set':
>> drivers/gpu/drm/i915/i915_debugfs.c:5004:6: error: implicit declaration of function 'intel_slpc_active' [-Werror=implicit-function-declaration]
     if (intel_slpc_active(dev_priv)) {
         ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_debugfs.c:5005:3: error: implicit declaration of function 'intel_slpc_set_param' [-Werror=implicit-function-declaration]
      intel_slpc_set_param(dev_priv,
      ^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_debugfs.c:5006:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_debugfs.c:5006:10: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/i915_debugfs.c:5009:10: error: 'SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_debugfs.c: In function 'i915_min_freq_set':
>> drivers/gpu/drm/i915/i915_debugfs.c:5082:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_debugfs.c:5085:10: error: 'SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ' undeclared (first use in this function)
             SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/intel_slpc_active +385 drivers/gpu/drm/i915/i915_sysfs.c

   379		if (val > dev_priv->rps.rp0_freq)
   380			DRM_DEBUG("User requested overclocking to %d\n",
   381				  intel_gpu_freq(dev_priv, val));
   382	
   383		dev_priv->rps.max_freq_softlimit = val;
   384	
 > 385		if (intel_slpc_active(dev_priv)) {
 > 386			intel_slpc_set_param(dev_priv,
 > 387					     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
   388					     (u32) intel_gpu_freq(dev_priv, val));
   389			intel_slpc_set_param(dev_priv,
 > 390					     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
   391					     (u32) intel_gpu_freq(dev_priv, val));
   392		}
   393	
   394		val = clamp_t(int, dev_priv->rps.cur_freq,
   395			      dev_priv->rps.min_freq_softlimit,
   396			      dev_priv->rps.max_freq_softlimit);
   397	
   398		/* We still need *_set_rps to process the new max_delay and
   399		 * update the interrupt limits and PMINTRMSK even though
   400		 * frequency request may be unchanged. */
   401		intel_set_rps(dev_priv, val);
   402	
   403		mutex_unlock(&dev_priv->rps.hw_lock);
   404	
   405		intel_runtime_pm_put(dev_priv);
   406	
   407		return count;
   408	}
   409	
   410	static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
   411	{
   412		struct drm_minor *minor = dev_to_drm_minor(kdev);
   413		struct drm_device *dev = minor->dev;
   414		struct drm_i915_private *dev_priv = to_i915(dev);
   415		int ret;
   416	
   417		flush_delayed_work(&dev_priv->rps.delayed_resume_work);
   418	
   419		mutex_lock(&dev_priv->rps.hw_lock);
   420		ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
   421		mutex_unlock(&dev_priv->rps.hw_lock);
   422	
   423		return snprintf(buf, PAGE_SIZE, "%d\n", ret);
   424	}
   425	
   426	static ssize_t gt_min_freq_mhz_store(struct device *kdev,
   427					     struct device_attribute *attr,
   428					     const char *buf, size_t count)
   429	{
   430		struct drm_minor *minor = dev_to_drm_minor(kdev);
   431		struct drm_device *dev = minor->dev;
   432		struct drm_i915_private *dev_priv = to_i915(dev);
   433		u32 val;
   434		ssize_t ret;
   435	
   436		ret = kstrtou32(buf, 0, &val);
   437		if (ret)
   438			return ret;
   439	
   440		flush_delayed_work(&dev_priv->rps.delayed_resume_work);
   441	
   442		intel_runtime_pm_get(dev_priv);
   443	
   444		mutex_lock(&dev_priv->rps.hw_lock);
   445	
   446		val = intel_freq_opcode(dev_priv, val);
   447	
   448		if (val < dev_priv->rps.min_freq ||
   449		    val > dev_priv->rps.max_freq ||
   450		    val > dev_priv->rps.max_freq_softlimit) {
   451			mutex_unlock(&dev_priv->rps.hw_lock);
   452			intel_runtime_pm_put(dev_priv);
   453			return -EINVAL;
   454		}
   455	
   456		dev_priv->rps.min_freq_softlimit = val;
   457	
   458		if (intel_slpc_active(dev_priv)) {
   459			intel_slpc_set_param(dev_priv,
 > 460					     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
   461					     (u32) intel_gpu_freq(dev_priv, val));
   462			intel_slpc_set_param(dev_priv,
 > 463					     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
   464					     (u32) intel_gpu_freq(dev_priv, val));
   465		}
   466	

---
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Re: drm/i915/slpc: If using SLPC, do not set frequency

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1698 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160822]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-If-using-SLPC-do-not-set-frequency/20160820-131950
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel-7.2 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_pm.c: In function 'intel_set_rps':
>> drivers/gpu/drm/i915/intel_pm.c:4944:6: error: implicit declaration of function 'intel_slpc_active' [-Werror=implicit-function-declaration]
     if (intel_slpc_active(dev_priv))
         ^~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/intel_slpc_active +4944 drivers/gpu/drm/i915/intel_pm.c

  4938		}
  4939		spin_unlock(&dev_priv->rps.client_lock);
  4940	}
  4941	
  4942	void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
  4943	{
> 4944		if (intel_slpc_active(dev_priv))
  4945			return;
  4946	
  4947		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

---
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[PATCH v3 00/27] Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features.  The SLPC
implementation runs in firmware on GuC.

This series has been tested with SKL GuC firmware
version 9.18 which is yet to be released. Performance and
power testing with these patches and 9.18 firmware is at
parity and in some cases better than host solution today
on various Linux benchmarks.

The graphics power management features in SLPC in this
version are called GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate.  Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios.  BALANCER is only
active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.

The last series can be found in the archive at
"[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/094445.html

This series incorporates feedback from code reviews on
earlier series. It drops the display mode notification
patches as it is not needed for Turbo part of GTPERF.
This series also adds new interface changes for SLPC
support on 9.18 GuC Firmware which is not yet published.
Will like to get review started prior to firmware is published.

With SLPC disabled by default, this series (first 25 patches)
should be safe to merge now and it can be enabled once
9.18 firmware is released. 

v2: Addressed review comments on v1. Removed patch to
enable SLPC by default.

v3: Addressed WARNING in igt@drv_module_reload_basic
flagged by trybot BAT. Added change for sanitizing GT PM
during reset. Added separate patch for sysfs interface to
know HW requested frequency. Also, earlier patches did not
go as series hence were not correctly picked up by BAT.

VIZ-6773, VIZ-6889, VIZ-6890

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Beuchat, Marc <marc.beuchat@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>

Sagar Arun Kamble (9):
  drm/i915: Remove RPM suspend dependency on rps.enabled and related
    changes
  drm/i915: Add sysfs interface to know the HW requested frequency
  drm/i915: Check GuC load status for Host to GuC action and SLPC status
  drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
  drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS
    Stall
  drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
  drm/i915: Sanitize GT PM before reset
  drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC
  drm/i915/slpc: Update freq min/max softlimits

Tom O'Rourke (18):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize SLPC version
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Update sysfs/debugfs interfaces for frequency
    parameters
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add broxton support

 drivers/gpu/drm/i915/Makefile              |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 469 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c            |  23 +-
 drivers/gpu/drm/i915/i915_drv.h            |   2 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  20 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_pci.c            |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  49 +++
 drivers/gpu/drm/i915/intel_drv.h           |  13 +
 drivers/gpu/drm/i915/intel_guc.h           |  11 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  49 ++-
 drivers/gpu/drm/i915/intel_pm.c            | 131 +++++---
 drivers/gpu/drm/i915/intel_runtime_pm.c    |   2 +-
 drivers/gpu/drm/i915/intel_slpc.c          | 370 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 215 +++++++++++++
 16 files changed, 1312 insertions(+), 55 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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[PATCH v3 01/27] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[Sagar Arun Kamble]

For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM
Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other
GENs this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.

v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
    spacing changes. (David)
    and commit message update for checkpatch issues.

v3: Rebase.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 14 +++++++++++---
 drivers/gpu/drm/i915/intel_pm.c         | 20 ++++++++++++++++++--
 drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5a7c0c2..53b5968 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2293,10 +2293,18 @@ static int intel_runtime_suspend(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
 		return -ENODEV;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	/*
+	 * Once RC6 and RPS enabling is separated for non-GEN9 platforms
+	 * below check should be removed.
+	*/
+	if (!IS_GEN9(dev_priv))
+		if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+			return -ENODEV;
+
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Suspending device\n");
@@ -2400,7 +2408,7 @@ static int intel_runtime_resume(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret = 0;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5e3f170..9dad6df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5155,6 +5155,8 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -5162,11 +5164,15 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5178,6 +5184,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5395,6 +5403,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5538,6 +5548,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5634,6 +5646,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -6108,6 +6122,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6188,6 +6204,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6777,7 +6795,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		ironlake_disable_drps(dev_priv);
 	}
 
-	dev_priv->rps.enabled = false;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -6821,7 +6838,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168..9a7ff5e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2770,7 +2770,7 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 	 * so the driver's own RPM reference tracking asserts also work on
 	 * platforms without RPM support.
 	 */
-	if (!HAS_RUNTIME_PM(dev)) {
+	if (!HAS_RUNTIME_PM(dev_priv)) {
 		pm_runtime_dont_use_autosuspend(kdev);
 		pm_runtime_get_sync(kdev);
 	} else {
-- 
1.9.1

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[PATCH v3 02/27] drm/i915/slpc: Expose guc functions for use with SLPC

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

v1: Updated function names as they need to be made extern. (ChrisW)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_guc.h           |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index e436941..9a69bf1 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -47,7 +47,7 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
  *
  * Doorbells:
  * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 	return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	u32 status;
@@ -141,7 +141,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -152,7 +152,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -169,7 +169,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 		/* bit 0 and 1 are for Render and Media domain separately */
 		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 /*
@@ -621,7 +621,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
@@ -1067,7 +1067,7 @@ int intel_guc_suspend(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 
@@ -1092,5 +1092,5 @@ int intel_guc_resume(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c973262..9e6b948 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
 
-- 
1.9.1

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[PATCH v3 03/27] drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 41e4178..9f2f10a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -652,6 +652,7 @@ struct intel_csr {
 	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
+	func(has_slpc) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2791,6 +2792,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev)		(IS_GEN9(dev))
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
+#define HAS_SLPC(dev)		(INTEL_INFO(dev)->has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
-- 
1.9.1

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[PATCH v3 04/27] drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Move slpc_version_check to intel_guc_ucode_init.
    fix whitespace (Sagar)
    Moved version check to different patch as has_slpc
    should not be updated based on it. Instead module parameter
    should be updated based on version check. (Sagar)
    Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e678051 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,12 +322,14 @@ static const struct intel_device_info intel_skylake_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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[PATCH v3 05/27] drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
    Remove sanitize enable_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as
    part of slpc_enable_sanitize function in the next patch. (Sagar)
    Updated slpc option sanitize function call for platforms without
    GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_guc.h        |  6 ++++++
 drivers/gpu/drm/i915/intel_guc_loader.c | 30 ++++++++++++++++++++++++++----
 4 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
+	int enable_slpc;
 	int enable_psr;
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..bf7624f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
 	uint32_t last_seqno[I915_NUM_ENGINES];
 };
 
+static inline int intel_slpc_enabled(void)
+{
+	WARN_ON(i915.enable_slpc < 0);
+	return i915.enable_slpc;
+}
+
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_device *dev);
 extern int intel_guc_setup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index e67d8de..383f3b1 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+	/* Handle default case */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev_priv);
+
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev_priv))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc loaded */
+	if (!i915.enable_guc_loading)
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
 	/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -729,18 +748,21 @@ void intel_guc_init(struct drm_device *dev)
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 
-	/* Early (and silent) return if GuC loading is disabled */
+	/* Return if GuC loading is disabled sanitizing SLPC option */
 	if (!i915.enable_guc_loading)
-		return;
+		goto out;
 	if (fw_path == NULL)
-		return;
+		goto out;
 	if (*fw_path == '\0')
-		return;
+		goto out;
 
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 	guc_fw_fetch(dev, guc_fw);
 	/* status must now be FAIL or SUCCESS */
+
+out:
+	sanitize_slpc_option(dev_priv);
 }
 
 /**
-- 
1.9.1

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[PATCH v3 06/27] drm/i915/slpc: Sanitize SLPC version

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Updated with modified sanitize_slpc_option in earlier patch.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 383f3b1..03dc5af 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -146,6 +146,8 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 
 static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
 	/* Handle default case */
 	if (i915.enable_slpc < 0)
 		i915.enable_slpc = HAS_SLPC(dev_priv);
@@ -161,6 +163,9 @@ static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	/* slpc requires guc submission */
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
+
+	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+		i915.enable_slpc = 0;
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v3 07/27] drm/i915/slpc: Use intel_slpc_* functions if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  3 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_guc.h  |  1 +
 drivers/gpu/drm/i915/intel_pm.c   | 98 ++++++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_slpc.c | 50 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 35 ++++++++++++++
 6 files changed, 159 insertions(+), 32 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da246..229290d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,7 +52,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+	  i915_guc_submission.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 92c38d4..7ae4299 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1692,6 +1692,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 			  enum dpio_channel ch, bool override);
 
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
+{
+	return 0;
+}
 
 /* intel_pm.c */
 void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index bf7624f..6fdbac5 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9dad6df..72ea545 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5082,7 +5082,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	 * our rpm wakeref. And then disable the interrupts to stop any
 	 * futher RPS reclocking whilst we are asleep.
 	 */
-	gen6_disable_rps_interrupts(dev_priv);
+	if (!intel_slpc_active(dev_priv))
+		gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
@@ -6733,6 +6734,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 	/* Finally allow us to boost to max by default */
 	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
 
+	if (intel_slpc_enabled())
+		intel_slpc_init(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
@@ -6741,7 +6745,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (IS_VALLEYVIEW(dev_priv))
+	if (intel_slpc_enabled())
+		intel_slpc_cleanup(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
 	if (!i915.enable_rc6)
@@ -6761,28 +6767,42 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
+	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) {
+		if (intel_slpc_active(dev_priv))
+			intel_slpc_suspend(dev_priv);
 		intel_runtime_pm_put(dev_priv);
+	}
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
-	intel_disable_gt_powersave(dev_priv);
+	if (intel_slpc_enabled()) {
+		/* TODO: Set SLPC enabled forcefully */
+		intel_disable_gt_powersave(dev_priv);
+	} else {
+		dev_priv->rps.enabled = true; /* force disabling */
+		intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+		gen6_reset_rps_interrupts(dev_priv);
+	}
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (!intel_slpc_active(dev_priv))
+			return;
+	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_active(dev_priv)) {
+		gen9_disable_rc6(dev_priv);
+		intel_slpc_disable(dev_priv);
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_disable_rc6(dev_priv);
 		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
@@ -6803,7 +6823,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	/* Powersaving is controlled by the host when inside a VM */
@@ -6812,31 +6835,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (IS_CHERRYVIEW(dev_priv)) {
-		cherryview_enable_rps(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
-		valleyview_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_enabled()) {
 		gen9_enable_rc6(dev_priv);
-		gen9_enable_rps(dev_priv);
+		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		gen8_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
-		gen6_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (IS_IRONLAKE_M(dev_priv)) {
-		ironlake_enable_drps(dev_priv);
-		intel_init_emon(dev_priv);
-	}
+	} else {
+		if (IS_CHERRYVIEW(dev_priv)) {
+			cherryview_enable_rps(dev_priv);
+		} else if (IS_VALLEYVIEW(dev_priv)) {
+			valleyview_enable_rps(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 9) {
+			gen9_enable_rc6(dev_priv);
+			gen9_enable_rps(dev_priv);
+			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+				gen6_update_ring_freq(dev_priv);
+		} else if (IS_BROADWELL(dev_priv)) {
+			gen8_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 6) {
+			gen6_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (IS_IRONLAKE_M(dev_priv)) {
+			ironlake_enable_drps(dev_priv);
+			intel_init_emon(dev_priv);
+		}
 
-	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
 
-	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+	}
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
@@ -6848,7 +6878,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			goto out;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		goto out;
 
 	rcs = &dev_priv->engine[RCS];
@@ -6878,7 +6911,10 @@ out:
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..2e509a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_suspend(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_reset(struct drm_i915_private *dev_priv)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..ae52146
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_suspend(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+void intel_slpc_reset(struct drm_i915_private *dev_priv);
+
+#endif
-- 
1.9.1

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[PATCH v3 08/27] drm/i915/slpc: Enable SLPC in guc if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 03dc5af..6514141 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -211,6 +211,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (intel_slpc_enabled())
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	if (i915.guc_log_level >= 0) {
 		params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 		params[GUC_CTL_DEBUG] =
-- 
1.9.1

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[PATCH v3 09/27] drm/i915/slpc: If using SLPC, do not set frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 72ea545..3451437 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5141,6 +5141,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+	if (intel_slpc_active(dev_priv))
+		return;
+
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		valleyview_set_rps(dev_priv, val);
 	else
-- 
1.9.1

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[PATCH v3 10/27] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC shared data is used to pass information
to/from SLPC in GuC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v1: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
    change default host_os to "Windows"
    Spelling fixes (Sagar Kamble and Nick Hoath)
    Added WARN for checking if upper 32bits of GTT offset
    of shared object are zero. (ChrisW)
    Changed function call from gem_allocate/release_guc_obj to
    i915_guc_allocate/release_gem_obj. (Sagar)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE
    definition from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable
    to determine if it is active as it not just dependent on shared
    data setup.
    Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes. (David)
    Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
    with SLPC Enabled.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
 drivers/gpu/drm/i915/intel_guc.h  |  2 +
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
 drivers/gpu/drm/i915/intel_slpc.c | 94 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 78 ++++++++++++++++++++++++++++++++
 5 files changed, 184 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7ae4299..59125c2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,7 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
-	return 0;
+	int ret = 0;
+
+	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
+		ret = 1;
+
+	return ret;
 }
 
 /* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 6fdbac5..af4310c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -145,6 +145,8 @@ struct intel_guc {
 
 	uint64_t submissions[I915_NUM_ENGINES];
 	uint32_t last_seqno[I915_NUM_ENGINES];
+
+	struct intel_slpc slpc;
 };
 
 static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3451437..aaff409 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6748,7 +6748,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (intel_slpc_enabled())
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma)
 		intel_slpc_cleanup(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
@@ -6838,7 +6839,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (intel_slpc_enabled()) {
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma) {
 		gen9_enable_rc6(dev_priv);
 		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 2e509a7..ef29df1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,15 +22,109 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	WARN_ON(platform_sku > 0xFF);
+
+	return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+	unsigned int slice_count = 1;
+
+	if (IS_SKYLAKE(dev_priv))
+		slice_count = INTEL_INFO(dev_priv)->slice_total;
+
+	return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 msr_value;
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+
+	page = i915_gem_object_get_page(obj, 0);
+	if (page) {
+		data = kmap_atomic(page);
+		memset(data, 0, sizeof(struct slpc_shared_data));
+
+		data->slpc_version = SLPC_VERSION;
+		data->shared_data_size = sizeof(struct slpc_shared_data);
+		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
+		data->platform_info.platform_sku =
+					(u8)slpc_get_platform_sku(dev_priv);
+		data->platform_info.slice_count =
+					(u8)slpc_get_slice_count(dev_priv);
+		data->platform_info.host_os = (u8)SLPC_HOST_OS_WINDOWS_8;
+		data->platform_info.power_plan_source =
+			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+						    SLPC_POWER_SOURCE_AC);
+		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+		data->platform_info.P0_freq = (u8)msr_value;
+		rdmsrl(MSR_PLATFORM_INFO, msr_value);
+		data->platform_info.P1_freq = (u8)(msr_value >> 8);
+		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
+		data->platform_info.Pn_freq = (u8)(msr_value >> 48);
+		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
+		data->platform_info.package_rapl_limit_high =
+							(u32)(msr_value >> 32);
+		data->platform_info.package_rapl_limit_low = (u32)msr_value;
+
+		kunmap_atomic(data);
+	}
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+	struct i915_vma *vma;
+
+	/* Allocate shared data structure */
+	vma = dev_priv->guc.slpc.vma;
+	if (!vma) {
+		vma = guc_allocate_vma(guc,
+			       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		if (IS_ERR(vma)) {
+			DRM_ERROR("slpc_shared_data allocation failed\n");
+			i915.enable_slpc = 0;
+			return;
+		}
+
+		dev_priv->guc.slpc.vma = vma;
+	}
+
+	slpc_shared_data_init(dev_priv);
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+
+	/* Release shared data structure */
+	mutex_lock(&dev_priv->drm.struct_mutex);
+	i915_vma_unpin_and_release(&guc->slpc.vma);
+	mutex_unlock(&dev_priv->drm.struct_mutex);
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index ae52146..e951289 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,84 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+#define SLPC_MAJOR_VER 2
+#define SLPC_MINOR_VER 4
+#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_host_os {
+	SLPC_HOST_OS_UNDEFINED = 0,
+	SLPC_HOST_OS_WINDOWS_8 = 1,
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 host_os;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 package_rapl_limit_high;
+	u32 package_rapl_limit_low;
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 slpc_version;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	u32 task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+struct intel_slpc {
+	struct i915_vma *vma;
+	bool enabled;
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[PATCH v3 11/27] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLPC requested value needs to be made available to i915 without
reading RPNSWREQ.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
    Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
    don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
    for proper division of functionality. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7d7b4d9..d15ad6c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1106,6 +1106,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (intel_slpc_active(dev_priv))
+		seq_puts(m, "SLPC Active\n");
+
 	if (IS_GEN5(dev_priv)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2338,6 +2341,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_file *file;
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
 	seq_printf(m, "GPU busy? %s [%x]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2d482f6..cee5f07 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -299,6 +299,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	return snprintf(buf, PAGE_SIZE, "%d\n",
 			intel_gpu_freq(dev_priv,
 				       dev_priv->rps.cur_freq));
-- 
1.9.1

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[PATCH v3 12/27] drm/i915: Add sysfs interface to know the HW requested frequency

[Sagar Arun Kamble]

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index cee5f07..8ae7db8 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -307,6 +307,32 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 				       dev_priv->rps.cur_freq));
 }
 
+static ssize_t gt_req_freq_mhz_show(struct device *kdev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+	u32 reqf;
+
+	if (!intel_runtime_pm_get_if_in_use(dev_priv))
+		return -ENODEV;
+
+	reqf = I915_READ(GEN6_RPNSWREQ);
+	intel_runtime_pm_put(dev_priv);
+
+	if (IS_GEN9(dev_priv))
+		reqf >>= 23;
+	else {
+		reqf &= ~GEN6_TURBO_DISABLE;
+		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+			reqf >>= 24;
+		else
+			reqf >>= 25;
+	}
+	reqf = intel_gpu_freq(dev_priv, reqf);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", reqf);
+}
+
 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
@@ -463,6 +489,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
+static DEVICE_ATTR(gt_req_freq_mhz, S_IRUGO, gt_req_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
@@ -495,6 +522,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 static const struct attribute *gen6_attrs[] = {
 	&dev_attr_gt_act_freq_mhz.attr,
 	&dev_attr_gt_cur_freq_mhz.attr,
+	&dev_attr_gt_req_freq_mhz.attr,
 	&dev_attr_gt_boost_freq_mhz.attr,
 	&dev_attr_gt_max_freq_mhz.attr,
 	&dev_attr_gt_min_freq_mhz.attr,
-- 
1.9.1

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[PATCH v3 13/27] drm/i915/slpc: Send reset event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add host2guc SLPC reset event and send reset event
during enable.

v1: Extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 28 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index ef29df1..b9e76f8 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+	int ret = i915_guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= SLPC_EVENT_STATUS_MASK;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -137,6 +163,8 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_reset(dev_priv);
+	dev_priv->guc.slpc.enabled = true;
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index e951289..031e36b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK	0xFF
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH v3 14/27] drm/i915/slpc: Send shutdown event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b9e76f8..0687b21 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -155,10 +168,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
@@ -169,4 +186,6 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
-- 
1.9.1

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[PATCH v3 15/27] drm/i915/slpc: Add slpc_status enum values

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

v1: fix whitespace (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 031e36b..9fe9ae3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,33 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MISMATCHING_VERSION = 16,
+	SLPC_STATUS_MEMIO_ERROR = 17,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
+	SLPC_STATUS_NO_EVENT_QUEUED = 20,
+	SLPC_STATUS_OUT_OF_SPACE = 21,
+	SLPC_STATUS_TIMEOUT = 22,
+	SLPC_STATUS_NO_LOCK = 23,
+};
+
 enum slpc_event_id {
 	SLPC_EVENT_RESET = 0,
 	SLPC_EVENT_SHUTDOWN = 1,
-- 
1.9.1

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[PATCH v3 16/27] drm/i915/slpc: Add parameter unset/set/get functions

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add slpc_param_id enum values.
Add events for setting/unsetting parameters.

v1: Use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

v2: Checkpatch update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 102 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  29 ++++++++++-
 2 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 0687b21..af486ae 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,108 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+				    enum slpc_param_id id, u32 value)
+{
+	u32 data[4];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data[2] = (u32) id;
+	data[3] = value;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+				      enum slpc_param_id id)
+{
+	u32 data[3];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data[2] = (u32) id;
+
+	host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							&= (~(1 << (id % 32)));
+		data->override_parameters_values[id] = 0;
+		kunmap_atomic(data);
+
+		host2guc_slpc_unset_param(dev_priv, id);
+	}
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							|= (1 << (id % 32));
+		data->override_parameters_values[id] = value;
+		kunmap_atomic(data);
+
+		host2guc_slpc_set_param(dev_priv, id, value);
+	}
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		if (overriding) {
+			bits = data->override_parameters_set_bits[id >> 5];
+			*overriding = (0 != (bits & (1 << (id % 32))));
+		}
+		if (value)
+			*value = data->override_parameters_values[id];
+
+		kunmap_atomic(data);
+	}
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 9fe9ae3..018f772 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -69,6 +69,26 @@ enum slpc_event_id {
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 #define SLPC_EVENT_STATUS_MASK	0xFF
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -150,5 +170,12 @@ void intel_slpc_suspend(struct drm_i915_private *dev_priv);
 void intel_slpc_disable(struct drm_i915_private *dev_priv);
 void intel_slpc_enable(struct drm_i915_private *dev_priv);
 void intel_slpc_reset(struct drm_i915_private *dev_priv);
-
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value);
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value);
 #endif
-- 
1.9.1

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[PATCH v3 17/27] drm/i915/slpc: Add slpc support for max/min freq

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d15ad6c..b803cf0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4890,6 +4890,15 @@ i915_max_freq_set(void *data, u64 val)
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4945,6 +4954,15 @@ i915_min_freq_set(void *data, u64 val)
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 8ae7db8..c4479e1 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -417,6 +417,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
@@ -470,6 +479,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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[PATCH v3 18/27] drm/i915/slpc: Add enable/disable debugfs for slpc

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
    Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 252 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   5 +
 2 files changed, 257 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b803cf0..6d237c5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1098,6 +1098,255 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			i915_next_seqno_get, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+				     &value_disable);
+
+		/* set the output value:
+		* 0: default
+		* 1: enabled
+		* 2: disabled
+		* 3: unknown (should not happen)
+		*/
+		if (override_disable && (value_disable == 1))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (value_enable == 1))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		intel_slpc_unset_param(dev_priv, enable_id);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		intel_slpc_set_param(dev_priv, enable_id, 1);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		intel_slpc_set_param(dev_priv, disable_id, 1);
+		intel_slpc_unset_param(dev_priv, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = slpc_enable_disable_set(dev, val, enable_id, disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			       SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5339,6 +5588,9 @@ static const struct i915_debugfs_files {
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 018f772..aef8324 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -89,6 +89,11 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
 };
 
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH v3 19/27] drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
    Avoid magic numbers and use local variables (Jon Bloomfield)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Moved definition of power plan and power source to earlier
    patch in the series.
    drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
    (Akash)

v2-v3: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 184 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   |  19 ++++
 drivers/gpu/drm/i915/intel_slpc.h   |   1 +
 3 files changed, 204 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6d237c5..8d0171f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1347,6 +1347,189 @@ static const struct file_operations i915_slpc_dcc_fops = {
 	.llseek	 = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
+	int i, value;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	enum slpc_host_os host_os;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		intel_slpc_query_task_state(dev_priv);
+
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			pv = kmap_atomic(page);
+	}
+
+	if (pv) {
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
+			   data.slpc_version >> 16,
+			   (data.slpc_version >> 8) & 0xFF,
+			   data.slpc_version & 0xFF,
+			   data.slpc_version);
+		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+		global_state = (enum slpc_global_state) data.global_state;
+		seq_printf(m, "global state: %d (", global_state);
+		switch (global_state) {
+		case SLPC_GLOBAL_STATE_NOT_RUNNING:
+			seq_puts(m, "not running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_INITIALIZING:
+			seq_puts(m, "initializing)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RESETTING:
+			seq_puts(m, "resetting)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RUNNING:
+			seq_puts(m, "running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+			seq_puts(m, "shutting down)\n");
+			break;
+		case SLPC_GLOBAL_STATE_ERROR:
+			seq_puts(m, "error)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		platform_sku = (enum slpc_platform_sku)
+				data.platform_info.platform_sku;
+		seq_printf(m, "sku: %d (", platform_sku);
+		switch (platform_sku) {
+		case SLPC_PLATFORM_SKU_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULX:
+			seq_puts(m, "ULX)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULT:
+			seq_puts(m, "ULT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_T:
+			seq_puts(m, "T)\n");
+			break;
+		case SLPC_PLATFORM_SKU_MOBL:
+			seq_puts(m, "Mobile)\n");
+			break;
+		case SLPC_PLATFORM_SKU_DT:
+			seq_puts(m, "DT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_UNKNOWN:
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+		seq_printf(m, "slice count: %d\n",
+			   data.platform_info.slice_count);
+
+		host_os = (enum slpc_host_os) data.platform_info.host_os;
+		seq_printf(m, "host OS: %d (", host_os);
+		switch (host_os) {
+		case SLPC_HOST_OS_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_HOST_OS_WINDOWS_8:
+			seq_puts(m, "Windows 8)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+			   data.platform_info.power_plan_source);
+		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+					data.platform_info.power_plan_source);
+		power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+					data.platform_info.power_plan_source);
+		switch (power_plan) {
+		case SLPC_POWER_PLAN_UNDEFINED:
+			seq_puts(m, "undefined");
+			break;
+		case SLPC_POWER_PLAN_BATTERY_SAVER:
+			seq_puts(m, "battery saver");
+			break;
+		case SLPC_POWER_PLAN_BALANCED:
+			seq_puts(m, "balanced");
+			break;
+		case SLPC_POWER_PLAN_PERFORMANCE:
+			seq_puts(m, "performance");
+			break;
+		case SLPC_POWER_PLAN_UNKNOWN:
+		default:
+			seq_puts(m, "unknown");
+			break;
+		}
+		seq_puts(m, "\n\tsource:\t");
+		switch (power_source) {
+		case SLPC_POWER_SOURCE_UNDEFINED:
+			seq_puts(m, "undefined\n");
+			break;
+		case SLPC_POWER_SOURCE_AC:
+			seq_puts(m, "AC\n");
+			break;
+		case SLPC_POWER_SOURCE_DC:
+			seq_puts(m, "DC\n");
+			break;
+		case SLPC_POWER_SOURCE_UNKNOWN:
+		default:
+			seq_puts(m, "unknown\n");
+			break;
+		}
+
+		seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+			   data.platform_info.P0_freq * 50,
+			   data.platform_info.P1_freq * 50,
+			   data.platform_info.Pe_freq * 50,
+			   data.platform_info.Pn_freq * 50);
+		seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
+			   data.platform_info.package_rapl_limit_high,
+			   data.platform_info.package_rapl_limit_low);
+		seq_printf(m, "task state data: 0x%08x\n",
+			   data.task_state_data);
+		seq_printf(m, "\tturbo active: %d\n",
+			   (data.task_state_data & 1));
+		seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
+			   (data.task_state_data & 2),
+			   (data.task_state_data & 4),
+			   (data.task_state_data >> 3) & 0xFF);
+
+		seq_puts(m, "override parameter bitfield\n");
+		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+			seq_printf(m, "%d: 0x%08x\n", i,
+				   data.override_parameters_set_bits[i]);
+
+		seq_puts(m, "override parameters (only non-zero shown)\n");
+		for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+			value = data.override_parameters_values[i];
+			if (value)
+				seq_printf(m, "%d: 0x%8x\n", i, value);
+		}
+
+	} else {
+		seq_puts(m, "no SLPC info available\n");
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5546,6 +5729,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index af486ae..86037f9 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -167,6 +167,25 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	if (intel_slpc_active(dev_priv))
+		host2guc_slpc_query_task_state(dev_priv);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index aef8324..e236d9d 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -183,4 +183,5 @@ void intel_slpc_set_param(struct drm_i915_private *dev_priv,
 void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
 #endif
-- 
1.9.1

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[PATCH v3 20/27] drm/i915/slpc: Add broxton support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.

v1: Adjusted slpc version check for major version 8.
    Added message if version mismatch happens for easier debug. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c         | 1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e678051..60a5eb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -342,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
+	.has_slpc = 1,
 	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6514141..3943aed 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -164,8 +164,11 @@ static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
+	}
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v3 21/27] drm/i915: Check GuC load status for Host to GuC action and SLPC status

[Sagar Arun Kamble]

Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.

v2: Space and function return convention issues. (Deepak)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++++
 drivers/gpu/drm/i915/intel_drv.h           | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 9a69bf1..cc1d5e3 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -78,6 +78,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct intel_guc_fw *guc_fw = &guc->guc_fw;
 	u32 status;
 	int i;
 	int ret;
@@ -85,6 +86,9 @@ int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 	if (WARN_ON(len < 1 || len > 15))
 		return -EINVAL;
 
+	if (WARN_ON(guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS))
+		return -ENODEV;
+
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	dev_priv->guc.action_count += 1;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 59125c2..989c56b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,8 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int ret = 0;
 
+	if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+		return ret;
+
 	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
 		ret = 1;
 
-- 
1.9.1

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[PATCH v3 22/27] drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

[Sagar Arun Kamble]

This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 53b5968..0265adc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1637,6 +1637,7 @@ static int i915_drm_resume(struct drm_device *dev)
 static int i915_drm_resume_early(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	int ret;
 
@@ -1694,6 +1695,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 			  ret);
 
+	/*
+	 * Mark GuC FW load status as PENDING to avoid any Host to GuC actions
+	 * invoked till GuC gets loaded in i915_drm_resume.
+	*/
+	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+
 	intel_uncore_early_sanitize(dev_priv, true);
 
 	if (IS_BROXTON(dev_priv)) {
-- 
1.9.1

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[PATCH v3 23/27] drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall

[Sagar Arun Kamble]

v1: Updated tasks and frequency post reset.
    Added DFPS param update for MAX_FPS and FPS Stall.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/intel_slpc.c   | 30 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 +++++
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8d0171f..340a781 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1137,7 +1137,7 @@ static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
 	return ret;
 }
 
-static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
 				   enum slpc_param_id enable_id,
 				   enum slpc_param_id disable_id)
 {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 86037f9..fd409c2 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -301,8 +301,38 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	u64 val;
+
 	host2guc_slpc_reset(dev_priv);
 	dev_priv->guc.slpc.enabled = true;
+
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_GTPERF,
+				SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_BALANCER,
+				SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_DCC,
+				SLPC_PARAM_TASK_DISABLE_DCC);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
+			     1);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
+			     1);
+
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index e236d9d..a2161b0b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -184,4 +184,9 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
 void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
+
+/* i915_debugfs.c */
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+			    enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id);
 #endif
-- 
1.9.1

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[PATCH v3 24/27] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

[Sagar Arun Kamble]

With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aaff409..77384b9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5158,7 +5158,13 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(GEN6_RP_CONTROL, 0);
+	uint32_t rp_ctl = 0;
+
+	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
+	if (i915.enable_slpc)
+		rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
+
+	I915_WRITE(GEN6_RP_CONTROL, rp_ctl);
 
 	dev_priv->rps.enabled = false;
 }
-- 
1.9.1

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[PATCH v3 25/27] drm/i915: Sanitize GT PM before reset

[Sagar Arun Kamble]

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0265adc..a35dee5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1761,6 +1761,8 @@ int i915_reset(struct drm_i915_private *dev_priv)
 	unsigned reset_counter;
 	int ret;
 
+	intel_sanitize_gt_powersave(dev_priv);
+
 	mutex_lock(&dev->struct_mutex);
 
 	/* Clear any previous failed attempts at recovery. Time to try again. */
-- 
1.9.1

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[PATCH v3 26/27] drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC

[Sagar Arun Kamble]

v2: Checkpatch update.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 71 ++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_guc_loader.c | 12 +++---
 drivers/gpu/drm/i915/intel_slpc.c       | 27 +++++++-----
 drivers/gpu/drm/i915/intel_slpc.h       | 73 ++++++++++++++++++++++-----------
 4 files changed, 110 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 340a781..d68cf92 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1356,10 +1356,10 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 	struct page *page;
 	void *pv = NULL;
 	struct slpc_shared_data data;
+	struct slpc_task_state_data *task_data;
 	int i, value;
 	enum slpc_global_state global_state;
 	enum slpc_platform_sku platform_sku;
-	enum slpc_host_os host_os;
 	enum slpc_power_plan power_plan;
 	enum slpc_power_source power_source;
 
@@ -1376,11 +1376,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 		data = *(struct slpc_shared_data *) pv;
 		kunmap_atomic(pv);
 
-		seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
-			   data.slpc_version >> 16,
-			   (data.slpc_version >> 8) & 0xFF,
-			   data.slpc_version & 0xFF,
-			   data.slpc_version);
 		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
 
 		global_state = (enum slpc_global_state) data.global_state;
@@ -1439,20 +1434,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 		seq_printf(m, "slice count: %d\n",
 			   data.platform_info.slice_count);
 
-		host_os = (enum slpc_host_os) data.platform_info.host_os;
-		seq_printf(m, "host OS: %d (", host_os);
-		switch (host_os) {
-		case SLPC_HOST_OS_UNDEFINED:
-			seq_puts(m, "undefined)\n");
-			break;
-		case SLPC_HOST_OS_WINDOWS_8:
-			seq_puts(m, "Windows 8)\n");
-			break;
-		default:
-			seq_puts(m, "unknown)\n");
-			break;
-		}
-
 		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
 			   data.platform_info.power_plan_source);
 		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
@@ -1499,17 +1480,45 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 			   data.platform_info.P1_freq * 50,
 			   data.platform_info.Pe_freq * 50,
 			   data.platform_info.Pn_freq * 50);
-		seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
-			   data.platform_info.package_rapl_limit_high,
-			   data.platform_info.package_rapl_limit_low);
-		seq_printf(m, "task state data: 0x%08x\n",
-			   data.task_state_data);
-		seq_printf(m, "\tturbo active: %d\n",
-			   (data.task_state_data & 1));
-		seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
-			   (data.task_state_data & 2),
-			   (data.task_state_data & 4),
-			   (data.task_state_data >> 3) & 0xFF);
+		task_data = &data.task_state_data;
+		seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+			   task_data->bitfield1, task_data->bitfield2);
+
+		seq_printf(m, "\tgtperf task active: %s\n",
+			   yesno(task_data->gtperf_task_active));
+		seq_printf(m, "\tgtperf stall possible: %s\n",
+			   yesno(task_data->gtperf_stall_possible));
+		seq_printf(m, "\tgtperf gaming mode: %s\n",
+			   yesno(task_data->gtperf_gaming_mode));
+		seq_printf(m, "\tgtperf target fps: %d\n",
+			   task_data->gtperf_target_fps);
+
+		seq_printf(m, "\tdcc task active: %s\n",
+			   yesno(task_data->dcc_task_active));
+		seq_printf(m, "\tin dcc: %s\n",
+			   yesno(task_data->in_dcc));
+		seq_printf(m, "\tin dct: %s\n",
+			   yesno(task_data->in_dct));
+		seq_printf(m, "\tfreq switch active: %d\n",
+			   task_data->freq_switch_active);
+
+		seq_printf(m, "\tibc enabled: %s\n",
+			   yesno(task_data->ibc_enabled));
+		seq_printf(m, "\tibc active: %s\n",
+			   yesno(task_data->ibc_active));
+		seq_printf(m, "\tpg1 enabled: %s\n",
+			   yesno(task_data->pg1_enabled));
+		seq_printf(m, "\tpg1 active: %s\n",
+			   yesno(task_data->pg1_active));
+
+		seq_printf(m, "\tunslice max freq: %d\n",
+			   task_data->freq_unslice_max);
+		seq_printf(m, "\tunslice min freq: %d\n",
+			   task_data->freq_unslice_min);
+		seq_printf(m, "\tslice max freq: %d\n",
+			   task_data->freq_slice_max);
+		seq_printf(m, "\tslice min freq: %d\n",
+			   task_data->freq_slice_min);
 
 		seq_puts(m, "override parameter bitfield\n");
 		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 3943aed..b612b59 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -59,11 +59,11 @@
  *
  */
 
-#define SKL_FW_MAJOR 6
-#define SKL_FW_MINOR 1
+#define SKL_FW_MAJOR 9
+#define SKL_FW_MINOR 18
 
-#define BXT_FW_MAJOR 8
-#define BXT_FW_MINOR 7
+#define BXT_FW_MAJOR 9
+#define BXT_FW_MINOR 18
 
 #define KBL_FW_MAJOR 9
 #define KBL_FW_MINOR 14
@@ -164,8 +164,8 @@ static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
-	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
 		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
 	}
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index fd409c2..0cde40e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -229,14 +229,12 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
 		data = kmap_atomic(page);
 		memset(data, 0, sizeof(struct slpc_shared_data));
 
-		data->slpc_version = SLPC_VERSION;
 		data->shared_data_size = sizeof(struct slpc_shared_data);
 		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
 		data->platform_info.platform_sku =
 					(u8)slpc_get_platform_sku(dev_priv);
 		data->platform_info.slice_count =
 					(u8)slpc_get_slice_count(dev_priv);
-		data->platform_info.host_os = (u8)SLPC_HOST_OS_WINDOWS_8;
 		data->platform_info.power_plan_source =
 			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
 						    SLPC_POWER_SOURCE_AC);
@@ -246,10 +244,6 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
 		data->platform_info.P1_freq = (u8)(msr_value >> 8);
 		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
 		data->platform_info.Pn_freq = (u8)(msr_value >> 48);
-		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
-		data->platform_info.package_rapl_limit_high =
-							(u32)(msr_value >> 32);
-		data->platform_info.package_rapl_limit_low = (u32)msr_value;
 
 		kunmap_atomic(data);
 	}
@@ -322,17 +316,28 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 				SLPC_PARAM_TASK_DISABLE_DCC);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
-			     1);
+			     SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+			     0);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+			     SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
 			     0);
 
 	intel_slpc_set_param(dev_priv,
-			     SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
-			     1);
+			     SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+			     0);
 
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			     0);
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a2161b0b..c773617 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,10 +24,6 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
-#define SLPC_MAJOR_VER 2
-#define SLPC_MINOR_VER 4
-#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
-
 enum slpc_status {
 	SLPC_STATUS_OK = 0,
 	SLPC_STATUS_ERROR = 1,
@@ -45,14 +41,13 @@ enum slpc_status {
 	SLPC_STATUS_VALUE_ALREADY_SET = 13,
 	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
 	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
-	SLPC_STATUS_MISMATCHING_VERSION = 16,
-	SLPC_STATUS_MEMIO_ERROR = 17,
-	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
-	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
-	SLPC_STATUS_NO_EVENT_QUEUED = 20,
-	SLPC_STATUS_OUT_OF_SPACE = 21,
-	SLPC_STATUS_TIMEOUT = 22,
-	SLPC_STATUS_NO_LOCK = 23,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
 };
 
 enum slpc_event_id {
@@ -80,13 +75,16 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
 	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
 	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
-	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
 	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
-	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
 	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
 	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
 	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
-	SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
 };
 
 #define SLPC_PARAM_TASK_DEFAULT 0
@@ -103,11 +101,6 @@ enum slpc_global_state {
 	SLPC_GLOBAL_STATE_ERROR = 5
 };
 
-enum slpc_host_os {
-	SLPC_HOST_OS_UNDEFINED = 0,
-	SLPC_HOST_OS_WINDOWS_8 = 1,
-};
-
 enum slpc_platform_sku {
 	SLPC_PLATFORM_SKU_UNDEFINED = 0,
 	SLPC_PLATFORM_SKU_ULX = 1,
@@ -140,25 +133,55 @@ enum slpc_power_source {
 struct slpc_platform_info {
 	u8 platform_sku;
 	u8 slice_count;
-	u8 host_os;
+	u8 reserved;
 	u8 power_plan_source;
 	u8 P0_freq;
 	u8 P1_freq;
 	u8 Pe_freq;
 	u8 Pn_freq;
-	u32 package_rapl_limit_high;
-	u32 package_rapl_limit_low;
+	u32 reserved1;
+	u32 reserved2;
 } __packed;
 
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 freq_unslice_max:8;
+			u32 freq_unslice_min:8;
+			u32 freq_slice_max:8;
+			u32 freq_slice_min:8;
+		};
+	};
+};
+
 #define SLPC_MAX_OVERRIDE_PARAMETERS 192
 #define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
 
 struct slpc_shared_data {
-	u32 slpc_version;
+	u32 reserved;
 	u32 shared_data_size;
 	u32 global_state;
 	struct slpc_platform_info platform_info;
-	u32 task_state_data;
+	struct slpc_task_state_data task_state_data;
 	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
 	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
 } __packed;
-- 
1.9.1

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[PATCH v3 27/27] drm/i915/slpc: Update freq min/max softlimits

[Sagar Arun Kamble]

v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 0cde40e..a6a1021 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -295,6 +295,10 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
 	u64 val;
 
 	host2guc_slpc_reset(dev_priv);
@@ -338,6 +342,25 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 	intel_slpc_set_param(dev_priv,
 			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			     0);
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	intel_slpc_query_task_state(dev_priv);
+
+	pv = kmap_atomic(i915_gem_object_get_page(obj, 0));
+	data = *(struct slpc_shared_data *) pv;
+	kunmap_atomic(pv);
+
+	/*
+	 * TODO: Define separate variables for slice and unslice
+	 *	 frequencies for driver state variable.
+	 */
+	dev_priv->rps.max_freq_softlimit =
+			data.task_state_data.freq_unslice_max;
+	dev_priv->rps.min_freq_softlimit =
+			data.task_state_data.freq_unslice_min;
+
+	dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+	dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH v3 01/27] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3523 bytes --]

Hi Sagar,

[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v4.8-rc3 next-20160823]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160823-204034
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x016-201634 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_runtime_pm.c: In function 'intel_runtime_pm_enable':
>> drivers/gpu/drm/i915/intel_runtime_pm.c:2761:21: warning: unused variable 'dev' [-Wunused-variable]
     struct drm_device *dev = &dev_priv->drm;
                        ^~~

vim +/dev +2761 drivers/gpu/drm/i915/intel_runtime_pm.c

c49d13ee David Weinehall 2016-08-22  2745  	pm_runtime_put_autosuspend(kdev);
9c065a7d Daniel Vetter   2014-09-30  2746  }
9c065a7d Daniel Vetter   2014-09-30  2747  
e4e7684f Daniel Vetter   2014-09-30  2748  /**
e4e7684f Daniel Vetter   2014-09-30  2749   * intel_runtime_pm_enable - enable runtime pm
e4e7684f Daniel Vetter   2014-09-30  2750   * @dev_priv: i915 device instance
e4e7684f Daniel Vetter   2014-09-30  2751   *
e4e7684f Daniel Vetter   2014-09-30  2752   * This function enables runtime pm at the end of the driver load sequence.
e4e7684f Daniel Vetter   2014-09-30  2753   *
e4e7684f Daniel Vetter   2014-09-30  2754   * Note that this function does currently not enable runtime pm for the
e4e7684f Daniel Vetter   2014-09-30  2755   * subordinate display power domains. That is only done on the first modeset
e4e7684f Daniel Vetter   2014-09-30  2756   * using intel_display_set_init_power().
e4e7684f Daniel Vetter   2014-09-30  2757   */
f458ebbc Daniel Vetter   2014-09-30  2758  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d Daniel Vetter   2014-09-30  2759  {
52a05c30 David Weinehall 2016-08-22  2760  	struct pci_dev *pdev = dev_priv->drm.pdev;
91c8a326 Chris Wilson    2016-07-05 @2761  	struct drm_device *dev = &dev_priv->drm;
52a05c30 David Weinehall 2016-08-22  2762  	struct device *kdev = &pdev->dev;
9c065a7d Daniel Vetter   2014-09-30  2763  
c49d13ee David Weinehall 2016-08-22  2764  	pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
c49d13ee David Weinehall 2016-08-22  2765  	pm_runtime_mark_last_busy(kdev);
cbc68dc9 Imre Deak       2015-12-17  2766  
25b181b4 Imre Deak       2015-12-17  2767  	/*
25b181b4 Imre Deak       2015-12-17  2768  	 * Take a permanent reference to disable the RPM functionality and drop
25b181b4 Imre Deak       2015-12-17  2769  	 * it only when unloading the driver. Use the low level get/put helpers,

:::::: The code at line 2761 was first introduced by commit
:::::: 91c8a326a192117219d5b9b980244c3662e35404 drm/i915: Convert dev_priv->dev backpointers to dev_priv->drm

:::::: TO: Chris Wilson <chris@chris-wilson.co.uk>
:::::: CC: Chris Wilson <chris@chris-wilson.co.uk>

---
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Re: [PATCH v3 01/27] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2455 bytes --]

Hi Sagar,

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v4.8-rc3 next-20160823]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160823-204034
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x001-201634 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_runtime_pm.c: In function 'intel_runtime_pm_enable':
>> drivers/gpu/drm/i915/intel_runtime_pm.c:2761:21: error: unused variable 'dev' [-Werror=unused-variable]
     struct drm_device *dev = &dev_priv->drm;
                        ^~~
   cc1: all warnings being treated as errors

vim +/dev +2761 drivers/gpu/drm/i915/intel_runtime_pm.c

e4e7684f Daniel Vetter   2014-09-30  2755   * subordinate display power domains. That is only done on the first modeset
e4e7684f Daniel Vetter   2014-09-30  2756   * using intel_display_set_init_power().
e4e7684f Daniel Vetter   2014-09-30  2757   */
f458ebbc Daniel Vetter   2014-09-30  2758  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d Daniel Vetter   2014-09-30  2759  {
52a05c30 David Weinehall 2016-08-22  2760  	struct pci_dev *pdev = dev_priv->drm.pdev;
91c8a326 Chris Wilson    2016-07-05 @2761  	struct drm_device *dev = &dev_priv->drm;
52a05c30 David Weinehall 2016-08-22  2762  	struct device *kdev = &pdev->dev;
9c065a7d Daniel Vetter   2014-09-30  2763  
c49d13ee David Weinehall 2016-08-22  2764  	pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */

:::::: The code at line 2761 was first introduced by commit
:::::: 91c8a326a192117219d5b9b980244c3662e35404 drm/i915: Convert dev_priv->dev backpointers to dev_priv->drm

:::::: TO: Chris Wilson <chris@chris-wilson.co.uk>
:::::: CC: Chris Wilson <chris@chris-wilson.co.uk>

---
0-DAY kernel test infrastructure                Open Source Technology Center
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Re: [PATCH v3 27/27] drm/i915/slpc: Update freq min/max softlimits

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2012 bytes --]

Hi Sagar,

[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v4.8-rc3 next-20160823]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160823-204034
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_slpc.c: In function 'intel_slpc_enable':
>> drivers/gpu/drm/i915/intel_slpc.c:299:15: warning: unused variable 'page' [-Wunused-variable]
     struct page *page;
                  ^~~~

vim +/page +299 drivers/gpu/drm/i915/intel_slpc.c

   283	
   284	void intel_slpc_suspend(struct drm_i915_private *dev_priv)
   285	{
   286		host2guc_slpc_shutdown(dev_priv);
   287		dev_priv->guc.slpc.enabled = false;
   288	}
   289	
   290	void intel_slpc_disable(struct drm_i915_private *dev_priv)
   291	{
   292		host2guc_slpc_shutdown(dev_priv);
   293		dev_priv->guc.slpc.enabled = false;
   294	}
   295	
   296	void intel_slpc_enable(struct drm_i915_private *dev_priv)
   297	{
   298		struct drm_i915_gem_object *obj;
 > 299		struct page *page;
   300		void *pv = NULL;
   301		struct slpc_shared_data data;
   302		u64 val;
   303	
   304		host2guc_slpc_reset(dev_priv);
   305		dev_priv->guc.slpc.enabled = true;
   306	
   307		/* Enable only GTPERF task, Disable others */

---
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✗ Fi.CI.BAT: warning for series starting with [v3,01/27] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/27] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes
URL   : https://patchwork.freedesktop.org/series/11461/
State : warning

== Summary ==

Series 11461v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/11461/revisions/1/mbox/

Test drv_hangman:
        Subgroup error-state-basic:
                pass       -> DMESG-WARN (fi-snb-2600)
Test gem_basic:
        Subgroup bad-close:
                pass       -> DMESG-WARN (fi-snb-2520m)
Test gem_ringfill:
        Subgroup basic-default-forked:
                pass       -> DMESG-WARN (fi-snb-2600)
        Subgroup basic-default-hang:
                pass       -> DMESG-WARN (fi-snb-2520m)
Test kms_cursor_legacy:
        Subgroup basic-flip-vs-cursor-varying-size:
                fail       -> PASS       (fi-hsw-4770k)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-snb-2600)
                pass       -> DMESG-WARN (fi-snb-2520m)
        Subgroup hang-read-crc-pipe-b:
                skip       -> PASS       (fi-skl-6260u)
                pass       -> DMESG-WARN (fi-snb-2600)
                pass       -> DMESG-WARN (fi-snb-2520m)

fi-bdw-5557u     total:249  pass:232  dwarn:0   dfail:0   fail:1   skip:16 
fi-bsw-n3050     total:249  pass:202  dwarn:0   dfail:0   fail:3   skip:44 
fi-byt-n2820     total:249  pass:204  dwarn:0   dfail:0   fail:4   skip:41 
fi-hsw-4770k     total:249  pass:220  dwarn:6   dfail:0   fail:1   skip:22 
fi-hsw-4770r     total:249  pass:221  dwarn:0   dfail:0   fail:2   skip:26 
fi-ivb-3520m     total:249  pass:217  dwarn:0   dfail:0   fail:1   skip:31 
fi-skl-6260u     total:249  pass:234  dwarn:0   dfail:0   fail:1   skip:14 
fi-skl-6700k     total:249  pass:214  dwarn:4   dfail:0   fail:3   skip:28 
fi-snb-2520m     total:249  pass:197  dwarn:8   dfail:0   fail:2   skip:42 
fi-snb-2600      total:249  pass:198  dwarn:8   dfail:0   fail:1   skip:42 

Results at /archive/results/CI_IGT_test/Patchwork_2406/

5a8708ec5c5bbc8eacf1f5b9cb815e6064e9737b drm-intel-nightly: 2016y-08m-23d-12h-12m-19s UTC integration manifest
cdf6f4e drm/i915/slpc: Update freq min/max softlimits
3c60f17 drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC
0e3e59f drm/i915: Sanitize GT PM before reset
03c1058 drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
58d8793 drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall
bd518e4 drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
36be1aa drm/i915: Check GuC load status for Host to GuC action and SLPC status
28e9513 drm/i915/slpc: Add broxton support
ebc79b5 drm/i915/slpc: Add i915_slpc_info to debugfs
5daaf83 drm/i915/slpc: Add enable/disable debugfs for slpc
1cccd78 drm/i915/slpc: Add slpc support for max/min freq
b086b52 drm/i915/slpc: Add parameter unset/set/get functions
700487e drm/i915/slpc: Add slpc_status enum values
d9fa858 drm/i915/slpc: Send shutdown event
a9dac14 drm/i915/slpc: Send reset event
b1e6d41 drm/i915: Add sysfs interface to know the HW requested frequency
db28c6a drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters
f22abbe drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
488d086 drm/i915/slpc: If using SLPC, do not set frequency
f75ddcd drm/i915/slpc: Enable SLPC in guc if supported
a2794ff drm/i915/slpc: Use intel_slpc_* functions if supported
71a703d drm/i915/slpc: Sanitize SLPC version
19483f6 drm/i915/slpc: Add enable_slpc module parameter
44686ae drm/i915/slpc: Add SKL SLPC Support
a567d72 drm/i915/slpc: Add has_slpc capability flag
a207589 drm/i915/slpc: Expose guc functions for use with SLPC
ade0a96 drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

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Re: [PATCH v3 27/27] drm/i915/slpc: Update freq min/max softlimits

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1619 bytes --]

Hi Sagar,

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v4.8-rc3 next-20160823]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160823-204034
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x009-201634 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_slpc.c: In function 'intel_slpc_enable':
>> drivers/gpu/drm/i915/intel_slpc.c:299:15: error: unused variable 'page' [-Werror=unused-variable]
     struct page *page;
                  ^~~~
   cc1: all warnings being treated as errors

vim +/page +299 drivers/gpu/drm/i915/intel_slpc.c

   293		dev_priv->guc.slpc.enabled = false;
   294	}
   295	
   296	void intel_slpc_enable(struct drm_i915_private *dev_priv)
   297	{
   298		struct drm_i915_gem_object *obj;
 > 299		struct page *page;
   300		void *pv = NULL;
   301		struct slpc_shared_data data;
   302		u64 val;

---
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Re: drm/i915/slpc: Update freq min/max softlimits

[Chris Wilson]

On Sun, Aug 21, 2016 at 09:39:17PM +0530, Kamble, Sagar A wrote:
> 
> 
> On 8/21/2016 2:09 PM, Chris Wilson wrote:
> >On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote:
> >>
> >>On 8/20/2016 1:32 PM, Chris Wilson wrote:
> >>>On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:
> >>>>+	obj = dev_priv->guc.slpc.vma->obj;
> >>>>+	if (obj) {
> >>>OOPS.
> >>Fixed in next series.
> >>>>+		intel_slpc_query_task_state(dev_priv);
> >>>>+
> >>>>+		page = i915_gem_object_get_page(obj, 0);
> >>>>+		if (page)
> >>>>+			pv = kmap_atomic(page);
> >>>>+	}
> >>>>+
> >>>>+	if (pv) {
> >>>>+		data = *(struct slpc_shared_data *) pv;
> >>>>+		kunmap_atomic(pv);
> >>>Can kmap_atomic return zero?
> >>Fixed in next series.
> >>>>+
> >>>>+		/*
> >>>>+		 * TODO: Define separate variables for slice and unslice
> >>>>+		 *	 frequencies for driver state variable.
> >>>>+		 */
> >>>>+		dev_priv->rps.max_freq_softlimit =
> >>>>+				data.task_state_data.freq_unslice_max;
> >>>>+		dev_priv->rps.min_freq_softlimit =
> >>>>+				data.task_state_data.freq_unslice_min;
> >>>These are user values, you do not get to arbitrarily rewrite them.
> >>>
> >>>You control dev_priv->rps.[min|max]_freq.
> >>With SLPC, GuC firmware SLPC S/W requested frequency be operated in
> >>the softlimits analogous to
> >>Host softlimits. Limits might be different with SLPC and can be
> >>controlled through regular interfaces.
> >>dev_priv->rps.[min|max]_freq are HW Min/Max.
> >Exactly. The soft limits are *only* set by the user. They are not to
> >modified by the driver. (The caveat would be a dynamic update of the hw
> >range, but that too should never be required.)
> >-Chris
> This initialization is similar to following from intel_init_gt_powersave
>         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
>         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
> I assume min_freq is hw min(RPn). With SLPC, min_freq(RPn) will not
> be requested.
> SLPC operating range today is (>Rpe, Rp0) so I wanted user to know
> the min_softlimit being initialized by SLPC by default.

Hmm, my mistake here was thinking this was more than a one off. Setting
the initial soft (user) range on startup is fine. Continually changing
them after userspace registration is not. (The value the user writes
into the limit is what should be read back - without very good reason,
such as the hard limits changing).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: drm/i915/slpc: Update freq min/max softlimits

[Kamble, Sagar A]

On 8/24/2016 2:07 PM, Chris Wilson wrote:
> On Sun, Aug 21, 2016 at 09:39:17PM +0530, Kamble, Sagar A wrote:
>>
>> On 8/21/2016 2:09 PM, Chris Wilson wrote:
>>> On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote:
>>>> On 8/20/2016 1:32 PM, Chris Wilson wrote:
>>>>> On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:
>>>>>> +	obj = dev_priv->guc.slpc.vma->obj;
>>>>>> +	if (obj) {
>>>>> OOPS.
>>>> Fixed in next series.
>>>>>> +		intel_slpc_query_task_state(dev_priv);
>>>>>> +
>>>>>> +		page = i915_gem_object_get_page(obj, 0);
>>>>>> +		if (page)
>>>>>> +			pv = kmap_atomic(page);
>>>>>> +	}
>>>>>> +
>>>>>> +	if (pv) {
>>>>>> +		data = *(struct slpc_shared_data *) pv;
>>>>>> +		kunmap_atomic(pv);
>>>>> Can kmap_atomic return zero?
>>>> Fixed in next series.
>>>>>> +
>>>>>> +		/*
>>>>>> +		 * TODO: Define separate variables for slice and unslice
>>>>>> +		 *	 frequencies for driver state variable.
>>>>>> +		 */
>>>>>> +		dev_priv->rps.max_freq_softlimit =
>>>>>> +				data.task_state_data.freq_unslice_max;
>>>>>> +		dev_priv->rps.min_freq_softlimit =
>>>>>> +				data.task_state_data.freq_unslice_min;
>>>>> These are user values, you do not get to arbitrarily rewrite them.
>>>>>
>>>>> You control dev_priv->rps.[min|max]_freq.
>>>> With SLPC, GuC firmware SLPC S/W requested frequency be operated in
>>>> the softlimits analogous to
>>>> Host softlimits. Limits might be different with SLPC and can be
>>>> controlled through regular interfaces.
>>>> dev_priv->rps.[min|max]_freq are HW Min/Max.
>>> Exactly. The soft limits are *only* set by the user. They are not to
>>> modified by the driver. (The caveat would be a dynamic update of the hw
>>> range, but that too should never be required.)
>>> -Chris
>> This initialization is similar to following from intel_init_gt_powersave
>>          dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
>>          dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
>> I assume min_freq is hw min(RPn). With SLPC, min_freq(RPn) will not
>> be requested.
>> SLPC operating range today is (>Rpe, Rp0) so I wanted user to know
>> the min_softlimit being initialized by SLPC by default.
> Hmm, my mistake here was thinking this was more than a one off. Setting
> the initial soft (user) range on startup is fine. Continually changing
> them after userspace registration is not. (The value the user writes
> into the limit is what should be read back - without very good reason,
> such as the hard limits changing).
> -Chris
I interpreted the rewrite differently, thinking SLPC should not write it 
post init_gt_powersave.
As discussed, I will change this to make sure SLPC init does not touch 
these values once it is
initialized in the load path.
>

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Re: [PATCH v3 08/27] drm/i915/slpc: Enable SLPC in guc if supported

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1607 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc4 next-20160825]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/drm-i915-slpc-Enable-SLPC-in-guc-if-supported/20160821-143205
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-b0-09040633 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8) 4.4.7
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_guc_loader.c: In function 'set_guc_init_params':
>> drivers/gpu/drm/i915/intel_guc_loader.c:178: error: implicit declaration of function 'intel_slpc_enabled'

vim +/intel_slpc_enabled +178 drivers/gpu/drm/i915/intel_guc_loader.c

   172	
   173		params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
   174	
   175		params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
   176				GUC_CTL_VCS2_ENABLED;
   177	
 > 178		if (intel_slpc_enabled())
   179			params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
   180	
   181		if (i915.guc_log_level >= 0) {

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 25190 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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[PATCH v4 00/25] Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features.  The SLPC
implementation runs in firmware on GuC.

This series has been tested with SKL GuC firmware
version 9.18 which is yet to be released. Performance and
power testing with these patches and 9.18 firmware is at
parity and in some cases better than host solution today
on various Linux benchmarks.

The graphics power management features in SLPC in this
version are called GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate.  Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios.  BALANCER is only
active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.

The last series can be found in the archive at
"[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/094445.html

This series incorporates feedback from code reviews on
earlier series. It drops the display mode notification
patches as it is not needed for Turbo part of GTPERF.
This series also adds new interface changes for SLPC
support on 9.18 GuC Firmware which is not yet published.
Will like to get review started prior to firmware is published.

With SLPC disabled by default, this series
should be safe to merge now and it can be enabled once
9.18 firmware is released. 

v2: Addressed review comments on v1. Removed patch to
enable SLPC by default.

v3: Addressed WARNING in igt@drv_module_reload_basic
flagged by trybot BAT. Added change for sanitizing GT PM
during reset. Added separate patch for sysfs interface to
know HW requested frequency. Also, earlier patches did not
go as series hence were not correctly picked up by BAT.

v4: Changes to multiple patches. CI BAT is passing.
Performance run on SKL GT2 done and shows perf at parity with
Host Turbo. For BXT, SLPC improves performance when GuC is
enabled compared to Host Turbo. This series keeps only support
of 9.18 firmware for better readability. If needed, other
SLPC interfaces for different GuC version will be added later.

VIZ-6773, VIZ-6889, VIZ-6890

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Beuchat, Marc <marc.beuchat@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>

Sagar Arun Kamble (7):
  drm/i915: Remove RPM suspend dependency on rps.enabled and related
    changes
  drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS
    Stall
  drm/i915/slpc: Update freq min/max softlimits
  drm/i915/slpc: Check GuC load status in SLPC active check
  drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
  drm/i915: Add sysfs interface to know the HW requested frequency
  drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

Tom O'Rourke (18):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize SLPC version
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Update sysfs/debugfs interfaces for frequency
    parameters
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add Broxton SLPC support

 drivers/gpu/drm/i915/Makefile              |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 491 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.c            |  21 +-
 drivers/gpu/drm/i915/i915_drv.h            |   4 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  16 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_pci.c            |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  49 +++
 drivers/gpu/drm/i915/intel_drv.h           |  13 +
 drivers/gpu/drm/i915/intel_guc.h           |  12 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  30 ++
 drivers/gpu/drm/i915/intel_pm.c            | 133 ++++++--
 drivers/gpu/drm/i915/intel_runtime_pm.c    |   3 +-
 drivers/gpu/drm/i915/intel_slpc.c          | 389 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 215 +++++++++++++
 16 files changed, 1335 insertions(+), 54 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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[PATCH v4 01/25] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[Sagar Arun Kamble]

For Gen9, RPM suspend is dependent on rps.enabled. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM
Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other
GENs this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.

v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
    spacing changes. (David)
    and commit message update for checkpatch issues.

v3: Rebase.

v4: Commit message update.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 14 +++++++++++---
 drivers/gpu/drm/i915/intel_pm.c         | 20 ++++++++++++++++++--
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
 3 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 02c34d6..1f677a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2284,10 +2284,18 @@ static int intel_runtime_suspend(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
 		return -ENODEV;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	/*
+	 * Once RC6 and RPS enabling is separated for non-GEN9 platforms
+	 * below check should be removed.
+	*/
+	if (!IS_GEN9(dev_priv))
+		if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+			return -ENODEV;
+
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Suspending device\n");
@@ -2391,7 +2399,7 @@ static int intel_runtime_resume(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret = 0;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f833a0..b9c460c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5061,6 +5061,8 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -5068,11 +5070,15 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5084,6 +5090,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5301,6 +5309,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5444,6 +5454,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5540,6 +5552,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -6014,6 +6028,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6094,6 +6110,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6683,7 +6701,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		ironlake_disable_drps(dev_priv);
 	}
 
-	dev_priv->rps.enabled = false;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -6727,7 +6744,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168..ed1faf1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2758,7 +2758,6 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 {
 	struct pci_dev *pdev = dev_priv->drm.pdev;
-	struct drm_device *dev = &dev_priv->drm;
 	struct device *kdev = &pdev->dev;
 
 	pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
@@ -2770,7 +2769,7 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 	 * so the driver's own RPM reference tracking asserts also work on
 	 * platforms without RPM support.
 	 */
-	if (!HAS_RUNTIME_PM(dev)) {
+	if (!HAS_RUNTIME_PM(dev_priv)) {
 		pm_runtime_dont_use_autosuspend(kdev);
 		pm_runtime_get_sync(kdev);
 	} else {
-- 
1.9.1

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[PATCH v4 02/25] drm/i915/slpc: Expose guc functions for use with SLPC

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

v1: Updated function names as they need to be made extern. (ChrisW)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_guc.h           |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 77526d7..5f80751 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -47,7 +47,7 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
  *
  * Doorbells:
  * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 	return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	u32 status;
@@ -139,7 +139,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -150,7 +150,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -167,7 +167,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 		/* bit 0 and 1 are for Render and Media domain separately */
 		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 /*
@@ -620,7 +620,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
@@ -1064,7 +1064,7 @@ int intel_guc_suspend(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 
@@ -1089,5 +1089,5 @@ int intel_guc_resume(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c973262..9e6b948 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
 
-- 
1.9.1

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[PATCH v4 03/25] drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ecfd8e9..b86f658 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -664,7 +664,8 @@ struct intel_csr {
 	func(has_snoop) sep \
 	func(has_ddi) sep \
 	func(has_fpga_dbg) sep \
-	func(has_pooled_eu)
+	func(has_pooled_eu) sep \
+	func(has_slpc)
 
 #define DEFINE_FLAG(name) u8 name:1
 #define SEP_SEMICOLON ;
@@ -2804,6 +2805,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev)		(IS_GEN9(dev))
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
+#define HAS_SLPC(dev)		(INTEL_INFO(dev)->has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
-- 
1.9.1

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[PATCH v4 04/25] drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Move slpc_version_check to intel_guc_ucode_init.
    fix whitespace (Sagar)
    Moved version check to different patch as has_slpc
    should not be updated based on it. Instead module parameter
    should be updated based on version check. (Sagar)
    Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e678051 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,12 +322,14 @@ static const struct intel_device_info intel_skylake_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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[PATCH v4 05/25] drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
    Remove sanitize enable_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as
    part of slpc_enable_sanitize function in the next patch. (Sagar)
    Updated slpc option sanitize function call for platforms without
    GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_guc.h        |  7 +++++++
 drivers/gpu/drm/i915/intel_guc_loader.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.c         |  2 ++
 5 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
+	int enable_slpc;
 	int enable_psr;
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..d73e4ed 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
 	uint32_t last_seqno[I915_NUM_ENGINES];
 };
 
+static inline int intel_slpc_enabled(void)
+{
+	WARN_ON(i915.enable_slpc < 0);
+	return i915.enable_slpc;
+}
+
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_device *dev);
 extern int intel_guc_setup(struct drm_device *dev);
@@ -153,6 +159,7 @@ extern void intel_guc_fini(struct drm_device *dev);
 extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
 extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
+extern void sanitize_slpc_option(struct drm_i915_private *dev_priv);
 
 /* i915_guc_submission.c */
 int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 853928f..fb38018 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	}
 }
 
+void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+	/* Handle default case */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev_priv);
+
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev_priv))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc loaded */
+	if (!i915.enable_guc_loading)
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
 	/* XXX: GT type based on PCI device ID? field seems unused by fw */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9c460c..56bde62 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6598,6 +6598,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_get(dev_priv);
 	}
 
+	sanitize_slpc_option(dev_priv);
+
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-- 
1.9.1

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[PATCH v4 06/25] drm/i915/slpc: Sanitize SLPC version

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v9 is supported.  Other
platforms and versions can be added here later.

v1: Updated with modified sanitize_slpc_option in earlier patch.

v2-v3: Rebase.

v4: Updated support for GuC firmware v9.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index fb38018..500b0b6 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -146,6 +146,8 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 
 void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
 	/* Handle default case */
 	if (i915.enable_slpc < 0)
 		i915.enable_slpc = HAS_SLPC(dev_priv);
@@ -161,6 +163,9 @@ void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	/* slpc requires guc submission */
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
+
+	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+		i915.enable_slpc = 0;
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v4 07/25] drm/i915/slpc: Use intel_slpc_* functions if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
    (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  3 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_guc.h  |  1 +
 drivers/gpu/drm/i915/intel_pm.c   | 96 +++++++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_slpc.c | 46 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 34 ++++++++++++++
 6 files changed, 153 insertions(+), 31 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da246..229290d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,7 +52,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+	  i915_guc_submission.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 570a7ca..6f9480b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1712,6 +1712,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 			  enum dpio_channel ch, bool override);
 
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
+{
+	return 0;
+}
 
 /* intel_pm.c */
 void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index d73e4ed..83dec66 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 56bde62..db5c4ef 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,7 +4988,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	 * our rpm wakeref. And then disable the interrupts to stop any
 	 * futher RPS reclocking whilst we are asleep.
 	 */
-	gen6_disable_rps_interrupts(dev_priv);
+	if (!intel_slpc_active(dev_priv))
+		gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
@@ -6641,6 +6642,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 	/* Finally allow us to boost to max by default */
 	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
 
+	if (intel_slpc_enabled())
+		intel_slpc_init(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
@@ -6649,7 +6653,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (IS_VALLEYVIEW(dev_priv))
+	if (intel_slpc_enabled())
+		intel_slpc_cleanup(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
 	if (!i915.enable_rc6)
@@ -6673,24 +6679,38 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_put(dev_priv);
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
+
+	if (intel_slpc_active(dev_priv))
+		intel_slpc_suspend(dev_priv);
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
-	intel_disable_gt_powersave(dev_priv);
+	if (intel_slpc_enabled()) {
+		/* TODO: Set SLPC enabled forcefully */
+		intel_disable_gt_powersave(dev_priv);
+	} else {
+		dev_priv->rps.enabled = true; /* force disabling */
+		intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+		gen6_reset_rps_interrupts(dev_priv);
+	}
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (!intel_slpc_active(dev_priv))
+			return;
+	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_active(dev_priv)) {
+		gen9_disable_rc6(dev_priv);
+		intel_slpc_disable(dev_priv);
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_disable_rc6(dev_priv);
 		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
@@ -6711,7 +6731,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	/* Powersaving is controlled by the host when inside a VM */
@@ -6720,31 +6743,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (IS_CHERRYVIEW(dev_priv)) {
-		cherryview_enable_rps(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
-		valleyview_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_enabled()) {
 		gen9_enable_rc6(dev_priv);
-		gen9_enable_rps(dev_priv);
+		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		gen8_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
-		gen6_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (IS_IRONLAKE_M(dev_priv)) {
-		ironlake_enable_drps(dev_priv);
-		intel_init_emon(dev_priv);
-	}
+	} else {
+		if (IS_CHERRYVIEW(dev_priv)) {
+			cherryview_enable_rps(dev_priv);
+		} else if (IS_VALLEYVIEW(dev_priv)) {
+			valleyview_enable_rps(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 9) {
+			gen9_enable_rc6(dev_priv);
+			gen9_enable_rps(dev_priv);
+			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+				gen6_update_ring_freq(dev_priv);
+		} else if (IS_BROADWELL(dev_priv)) {
+			gen8_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 6) {
+			gen6_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (IS_IRONLAKE_M(dev_priv)) {
+			ironlake_enable_drps(dev_priv);
+			intel_init_emon(dev_priv);
+		}
 
-	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
 
-	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+	}
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
@@ -6756,7 +6786,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			goto out;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		goto out;
 
 	rcs = &dev_priv->engine[RCS];
@@ -6786,7 +6819,10 @@ out:
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..be9e84c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_suspend(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..28296f1
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_suspend(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+
+#endif
-- 
1.9.1

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[PATCH v4 08/25] drm/i915/slpc: Enable SLPC in guc if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 500b0b6..2dda771 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -213,6 +213,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (intel_slpc_enabled())
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	if (i915.guc_log_level >= 0) {
 		params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 		params[GUC_CTL_DEBUG] =
-- 
1.9.1

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[PATCH v4 09/25] drm/i915/slpc: If using SLPC, do not set frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index db5c4ef..d187066 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5047,6 +5047,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+	if (intel_slpc_active(dev_priv))
+		return;
+
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		valleyview_set_rps(dev_priv, val);
 	else
-- 
1.9.1

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[PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC shared data is used to pass information
to/from SLPC in GuC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v1: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
    change default host_os to "Windows"
    Spelling fixes (Sagar Kamble and Nick Hoath)
    Added WARN for checking if upper 32bits of GTT offset
    of shared object are zero. (ChrisW)
    Changed function call from gem_allocate/release_guc_obj to
    i915_guc_allocate/release_gem_obj. (Sagar)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE
    definition from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable
    to determine if it is active as it not just dependent on shared
    data setup.
    Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes. (David)
    Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
    with SLPC Enabled.

v4: Updated support for GuC v9.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
 drivers/gpu/drm/i915/intel_guc.h  |  2 +
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
 drivers/gpu/drm/i915/intel_slpc.c | 88 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 99 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 199 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6f9480b..99b19ae 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1714,7 +1714,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
-	return 0;
+	int ret = 0;
+
+	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
+		ret = 1;
+
+	return ret;
 }
 
 /* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 83dec66..6e24e60 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -145,6 +145,8 @@ struct intel_guc {
 
 	uint64_t submissions[I915_NUM_ENGINES];
 	uint32_t last_seqno[I915_NUM_ENGINES];
+
+	struct intel_slpc slpc;
 };
 
 static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d187066..2211f7b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6656,7 +6656,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (intel_slpc_enabled())
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma)
 		intel_slpc_cleanup(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
@@ -6746,7 +6747,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (intel_slpc_enabled()) {
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma) {
 		gen9_enable_rc6(dev_priv);
 		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index be9e84c..67236a1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,15 +22,103 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	WARN_ON(platform_sku > 0xFF);
+
+	return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+	unsigned int slice_count = 1;
+
+	if (IS_SKYLAKE(dev_priv))
+		slice_count = INTEL_INFO(dev_priv)->slice_total;
+
+	return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 msr_value;
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+
+	page = i915_gem_object_get_page(obj, 0);
+	if (page) {
+		data = kmap_atomic(page);
+		memset(data, 0, sizeof(struct slpc_shared_data));
+
+		data->shared_data_size = sizeof(struct slpc_shared_data);
+		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
+		data->platform_info.platform_sku =
+					(u8)slpc_get_platform_sku(dev_priv);
+		data->platform_info.slice_count =
+					(u8)slpc_get_slice_count(dev_priv);
+		data->platform_info.power_plan_source =
+			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+						    SLPC_POWER_SOURCE_AC);
+		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+		data->platform_info.P0_freq = (u8)msr_value;
+		rdmsrl(MSR_PLATFORM_INFO, msr_value);
+		data->platform_info.P1_freq = (u8)(msr_value >> 8);
+		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
+		data->platform_info.Pn_freq = (u8)(msr_value >> 48);
+
+		kunmap_atomic(data);
+	}
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+	struct i915_vma *vma;
+
+	/* Allocate shared data structure */
+	vma = dev_priv->guc.slpc.vma;
+	if (!vma) {
+		vma = guc_allocate_vma(guc,
+			       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		if (IS_ERR(vma)) {
+			DRM_ERROR("slpc_shared_data allocation failed\n");
+			i915.enable_slpc = 0;
+			return;
+		}
+
+		dev_priv->guc.slpc.vma = vma;
+	}
+
+	slpc_shared_data_init(dev_priv);
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+
+	/* Release shared data structure */
+	mutex_lock(&dev_priv->drm.struct_mutex);
+	i915_vma_unpin_and_release(&guc->slpc.vma);
+	mutex_unlock(&dev_priv->drm.struct_mutex);
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 28296f1..6cdbc96 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,105 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 reserved;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 reserved1;
+	u32 reserved2;
+} __packed;
+
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 freq_unslice_max:8;
+			u32 freq_unslice_min:8;
+			u32 freq_slice_max:8;
+			u32 freq_slice_min:8;
+		};
+	};
+};
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 reserved;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	struct slpc_task_state_data task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+struct intel_slpc {
+	struct i915_vma *vma;
+	bool enabled;
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[PATCH v4 11/25] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLPC requested value needs to be made available to i915 without
reading RPNSWREQ.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
    Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
    don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
    for proper division of functionality. (Sagar)

v4: idle_freq, boost_freq are also not used with SLPC.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++------
 drivers/gpu/drm/i915/i915_sysfs.c   |  3 +++
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3fde507..7641778 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1083,6 +1083,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (intel_slpc_active(dev_priv))
+		seq_puts(m, "SLPC Active\n");
+
 	if (IS_GEN5(dev_priv)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -1250,15 +1253,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Max overclocked frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
 
-		seq_printf(m, "Current freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+		if (!intel_slpc_active(dev_priv)) {
+			seq_printf(m, "Current freq: %d MHz\n",
+				   intel_gpu_freq(dev_priv,
+						  dev_priv->rps.cur_freq));
+			seq_printf(m, "Idle freq: %d MHz\n",
+				   intel_gpu_freq(dev_priv,
+						  dev_priv->rps.idle_freq));
+			seq_printf(m, "Boost freq: %d MHz\n",
+				   intel_gpu_freq(dev_priv,
+						  dev_priv->rps.boost_freq));
+		}
+
 		seq_printf(m, "Actual freq: %d MHz\n", cagf);
-		seq_printf(m, "Idle freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
 		seq_printf(m, "Min freq: %d MHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
-		seq_printf(m, "Boost freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
 		seq_printf(m, "Max freq: %d MHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
 		seq_printf(m,
@@ -2315,6 +2324,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_file *file;
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
 	seq_printf(m, "GPU busy? %s [%x]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 1012eee..020d64e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -299,6 +299,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	return snprintf(buf, PAGE_SIZE, "%d\n",
 			intel_gpu_freq(dev_priv,
 				       dev_priv->rps.cur_freq));
-- 
1.9.1

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[PATCH v4 12/25] drm/i915/slpc: Send reset event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add host2guc SLPC reset event and send reset event
during enable.

v1: Extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

v3: Rebase.

v4: Added DRM_INFO message when SLPC is enabled.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 67236a1..eb3358a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+	int ret = i915_guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= SLPC_EVENT_STATUS_MASK;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -131,4 +157,7 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_reset(dev_priv);
+	DRM_INFO("SLPC Enabled\n");
+	dev_priv->guc.slpc.enabled = true;
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 6cdbc96..a96f365 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,20 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK	0xFF
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH v4 13/25] drm/i915/slpc: Send shutdown event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++++--
 drivers/gpu/drm/i915/intel_slpc.c | 17 +++++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2211f7b..70e08d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6691,7 +6691,7 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	if (intel_slpc_enabled()) {
-		/* TODO: Set SLPC enabled forcefully */
+		dev_priv->guc.slpc.enabled = true;
 		intel_disable_gt_powersave(dev_priv);
 	} else {
 		dev_priv->rps.enabled = true; /* force disabling */
@@ -6704,8 +6704,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	if (intel_slpc_enabled()) {
-		if (!intel_slpc_active(dev_priv))
+		if (!intel_slpc_active(dev_priv)) {
+			dev_priv->guc.slpc.enabled = false;
 			return;
+		}
 	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index eb3358a..f9d32c1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -149,10 +162,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v4 14/25] drm/i915/slpc: Add slpc_status enum values

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.h | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a96f365..4838e1e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,32 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
+};
+
 enum slpc_event_id {
 	SLPC_EVENT_RESET = 0,
 	SLPC_EVENT_SHUTDOWN = 1,
-- 
1.9.1

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[PATCH v4 15/25] drm/i915/slpc: Add parameter unset/set/get functions

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add slpc_param_id enum values.
Add events for setting/unsetting parameters.

v1: Use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

v2: Checkpatch update.

v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 102 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  32 +++++++++++-
 2 files changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index f9d32c1..8ab5d9f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,108 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+				    enum slpc_param_id id, u32 value)
+{
+	u32 data[4];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data[2] = (u32) id;
+	data[3] = value;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+				      enum slpc_param_id id)
+{
+	u32 data[3];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data[2] = (u32) id;
+
+	host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							&= (~(1 << (id % 32)));
+		data->override_parameters_values[id] = 0;
+		kunmap_atomic(data);
+
+		host2guc_slpc_unset_param(dev_priv, id);
+	}
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							|= (1 << (id % 32));
+		data->override_parameters_values[id] = value;
+		kunmap_atomic(data);
+
+		host2guc_slpc_set_param(dev_priv, id, value);
+	}
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		if (overriding) {
+			bits = data->override_parameters_set_bits[id >> 5];
+			*overriding = (0 != (bits & (1 << (id % 32))));
+		}
+		if (value)
+			*value = data->override_parameters_values[id];
+
+		kunmap_atomic(data);
+	}
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 4838e1e..b0a627d 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -64,6 +64,29 @@ enum slpc_event_id {
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 #define SLPC_EVENT_STATUS_MASK	0xFF
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -169,5 +192,12 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
 void intel_slpc_suspend(struct drm_i915_private *dev_priv);
 void intel_slpc_disable(struct drm_i915_private *dev_priv);
 void intel_slpc_enable(struct drm_i915_private *dev_priv);
-
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value);
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value);
 #endif
-- 
1.9.1

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[PATCH v4 16/25] drm/i915/slpc: Add slpc support for max/min freq

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7641778..c8aa525 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4873,6 +4873,15 @@ i915_max_freq_set(void *data, u64 val)
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4928,6 +4937,15 @@ i915_min_freq_set(void *data, u64 val)
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 020d64e..ab161ca 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -391,6 +391,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
@@ -444,6 +453,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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[PATCH v4 17/25] drm/i915/slpc: Add enable/disable debugfs for slpc

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
    Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 252 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   5 +
 2 files changed, 257 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c8aa525..a51fee3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1075,6 +1075,255 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			i915_next_seqno_get, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+				     &value_disable);
+
+		/* set the output value:
+		* 0: default
+		* 1: enabled
+		* 2: disabled
+		* 3: unknown (should not happen)
+		*/
+		if (override_disable && (value_disable == 1))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (value_enable == 1))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		intel_slpc_unset_param(dev_priv, enable_id);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		intel_slpc_set_param(dev_priv, enable_id, 1);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		intel_slpc_set_param(dev_priv, disable_id, 1);
+		intel_slpc_unset_param(dev_priv, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = slpc_enable_disable_set(dev, val, enable_id, disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			       SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5319,6 +5568,9 @@ static const struct i915_debugfs_files {
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index b0a627d..3a134e2 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -87,6 +87,11 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
 };
 
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH v4 18/25] drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
    Avoid magic numbers and use local variables (Jon Bloomfield)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Moved definition of power plan and power source to earlier
    patch in the series.
    drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
    (Akash)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 197 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   |  19 ++++
 drivers/gpu/drm/i915/intel_slpc.h   |   1 +
 3 files changed, 217 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a51fee3..9efae32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1324,6 +1324,202 @@ static const struct file_operations i915_slpc_dcc_fops = {
 	.llseek	 = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
+	struct slpc_task_state_data *task_data;
+	int i, value;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	if (!intel_slpc_active(dev_priv))
+		return -ENODEV;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		intel_slpc_query_task_state(dev_priv);
+
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			pv = kmap_atomic(page);
+	}
+
+	if (pv) {
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+		global_state = (enum slpc_global_state) data.global_state;
+		seq_printf(m, "global state: %d (", global_state);
+		switch (global_state) {
+		case SLPC_GLOBAL_STATE_NOT_RUNNING:
+			seq_puts(m, "not running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_INITIALIZING:
+			seq_puts(m, "initializing)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RESETTING:
+			seq_puts(m, "resetting)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RUNNING:
+			seq_puts(m, "running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+			seq_puts(m, "shutting down)\n");
+			break;
+		case SLPC_GLOBAL_STATE_ERROR:
+			seq_puts(m, "error)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		platform_sku = (enum slpc_platform_sku)
+				data.platform_info.platform_sku;
+		seq_printf(m, "sku: %d (", platform_sku);
+		switch (platform_sku) {
+		case SLPC_PLATFORM_SKU_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULX:
+			seq_puts(m, "ULX)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULT:
+			seq_puts(m, "ULT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_T:
+			seq_puts(m, "T)\n");
+			break;
+		case SLPC_PLATFORM_SKU_MOBL:
+			seq_puts(m, "Mobile)\n");
+			break;
+		case SLPC_PLATFORM_SKU_DT:
+			seq_puts(m, "DT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_UNKNOWN:
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+		seq_printf(m, "slice count: %d\n",
+			   data.platform_info.slice_count);
+
+		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+			   data.platform_info.power_plan_source);
+		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+					data.platform_info.power_plan_source);
+		power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+					data.platform_info.power_plan_source);
+		switch (power_plan) {
+		case SLPC_POWER_PLAN_UNDEFINED:
+			seq_puts(m, "undefined");
+			break;
+		case SLPC_POWER_PLAN_BATTERY_SAVER:
+			seq_puts(m, "battery saver");
+			break;
+		case SLPC_POWER_PLAN_BALANCED:
+			seq_puts(m, "balanced");
+			break;
+		case SLPC_POWER_PLAN_PERFORMANCE:
+			seq_puts(m, "performance");
+			break;
+		case SLPC_POWER_PLAN_UNKNOWN:
+		default:
+			seq_puts(m, "unknown");
+			break;
+		}
+		seq_puts(m, "\n\tsource:\t");
+		switch (power_source) {
+		case SLPC_POWER_SOURCE_UNDEFINED:
+			seq_puts(m, "undefined\n");
+			break;
+		case SLPC_POWER_SOURCE_AC:
+			seq_puts(m, "AC\n");
+			break;
+		case SLPC_POWER_SOURCE_DC:
+			seq_puts(m, "DC\n");
+			break;
+		case SLPC_POWER_SOURCE_UNKNOWN:
+		default:
+			seq_puts(m, "unknown\n");
+			break;
+		}
+
+		seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+			   data.platform_info.P0_freq * 50,
+			   data.platform_info.P1_freq * 50,
+			   data.platform_info.Pe_freq * 50,
+			   data.platform_info.Pn_freq * 50);
+
+		task_data = &data.task_state_data;
+		seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+			   task_data->bitfield1, task_data->bitfield2);
+
+		seq_printf(m, "\tgtperf task active: %s\n",
+			   yesno(task_data->gtperf_task_active));
+		seq_printf(m, "\tgtperf stall possible: %s\n",
+			   yesno(task_data->gtperf_stall_possible));
+		seq_printf(m, "\tgtperf gaming mode: %s\n",
+			   yesno(task_data->gtperf_gaming_mode));
+		seq_printf(m, "\tgtperf target fps: %d\n",
+			   task_data->gtperf_target_fps);
+
+		seq_printf(m, "\tdcc task active: %s\n",
+			   yesno(task_data->dcc_task_active));
+		seq_printf(m, "\tin dcc: %s\n",
+			   yesno(task_data->in_dcc));
+		seq_printf(m, "\tin dct: %s\n",
+			   yesno(task_data->in_dct));
+		seq_printf(m, "\tfreq switch active: %d\n",
+			   task_data->freq_switch_active);
+
+		seq_printf(m, "\tibc enabled: %s\n",
+			   yesno(task_data->ibc_enabled));
+		seq_printf(m, "\tibc active: %s\n",
+			   yesno(task_data->ibc_active));
+		seq_printf(m, "\tpg1 enabled: %s\n",
+			   yesno(task_data->pg1_enabled));
+		seq_printf(m, "\tpg1 active: %s\n",
+			   yesno(task_data->pg1_active));
+
+		seq_printf(m, "\tunslice max freq: %d\n",
+			   task_data->freq_unslice_max);
+		seq_printf(m, "\tunslice min freq: %d\n",
+			   task_data->freq_unslice_min);
+		seq_printf(m, "\tslice max freq: %d\n",
+			   task_data->freq_slice_max);
+		seq_printf(m, "\tslice min freq: %d\n",
+			   task_data->freq_slice_min);
+
+		seq_puts(m, "override parameter bitfield\n");
+		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+			seq_printf(m, "%d: 0x%08x\n", i,
+				   data.override_parameters_set_bits[i]);
+
+		seq_puts(m, "override parameters (only non-zero shown)\n");
+		for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+			value = data.override_parameters_values[i];
+			if (value)
+				seq_printf(m, "%d: 0x%8x\n", i, value);
+		}
+
+	} else {
+		seq_puts(m, "no SLPC info available\n");
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5526,6 +5722,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 8ab5d9f..4683294 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -167,6 +167,25 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	if (intel_slpc_active(dev_priv))
+		host2guc_slpc_query_task_state(dev_priv);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 3a134e2..cc43194 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -205,4 +205,5 @@ void intel_slpc_set_param(struct drm_i915_private *dev_priv,
 void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
 #endif
-- 
1.9.1

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[PATCH v4 19/25] drm/i915/slpc: Add Broxton SLPC support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.

v1: Adjusted slpc version check for major version 8.
    Added message if version mismatch happens for easier debug. (Sagar)

v2-v3: Rebase.

v4: Commit message update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c         | 1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e678051..60a5eb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -342,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
+	.has_slpc = 1,
 	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2dda771..f0101a8 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -164,8 +164,11 @@ void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
+		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
+	}
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v4 20/25] drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall

[Sagar Arun Kamble]

v1: Updated tasks and frequency post reset.
    Added DFPS param update for MAX_FPS and FPS Stall.

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/intel_slpc.c   | 41 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 +++++
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9efae32..522e49d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1114,7 +1114,7 @@ static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
 	return ret;
 }
 
-static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
 				   enum slpc_param_id enable_id,
 				   enum slpc_param_id disable_id)
 {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 4683294..60b3aaf 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -295,7 +295,48 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	u64 val;
+
 	host2guc_slpc_reset(dev_priv);
 	DRM_INFO("SLPC Enabled\n");
 	dev_priv->guc.slpc.enabled = true;
+
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_GTPERF,
+				SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_BALANCER,
+				SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_DCC,
+				SLPC_PARAM_TASK_DISABLE_DCC);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			     0);
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index cc43194..8436965 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -206,4 +206,9 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
 void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
+
+/* i915_debugfs.c */
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+			    enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id);
 #endif
-- 
1.9.1

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[PATCH v4 21/25] drm/i915/slpc: Update freq min/max softlimits

[Sagar Arun Kamble]

v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

v3: Rebase.

v4: Updated to make sure SLPC enable keeps min/max freq softlimits
    unchanged after initializing once. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 47 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 60b3aaf..1a3a515 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -269,6 +269,7 @@ void intel_slpc_init(struct drm_i915_private *dev_priv)
 	}
 
 	slpc_shared_data_init(dev_priv);
+	dev_priv->guc.slpc.first_enable = false;
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
@@ -279,6 +280,8 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	i915_vma_unpin_and_release(&guc->slpc.vma);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
+
+	dev_priv->guc.slpc.first_enable = false;
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
@@ -339,4 +342,48 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 	intel_slpc_set_param(dev_priv,
 			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			     0);
+
+	if (!dev_priv->guc.slpc.first_enable) {
+		struct drm_i915_gem_object *obj;
+		void *pv = NULL;
+		struct slpc_shared_data data;
+
+		obj = dev_priv->guc.slpc.vma->obj;
+		intel_slpc_query_task_state(dev_priv);
+
+		pv = kmap_atomic(i915_gem_object_get_page(obj, 0));
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		/*
+		 * TODO: Define separate variables for slice and unslice
+		 *	 frequencies for driver state variable.
+		 */
+		dev_priv->rps.max_freq_softlimit =
+				data.task_state_data.freq_unslice_max;
+		dev_priv->rps.min_freq_softlimit =
+				data.task_state_data.freq_unslice_min;
+
+		dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->guc.slpc.first_enable = true;
+	} else {
+		/* Ask SLPC to operate within min/max freq softlimits */
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+	}
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 8436965..9a8602a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -189,6 +189,7 @@ struct slpc_shared_data {
 struct intel_slpc {
 	struct i915_vma *vma;
 	bool enabled;
+	bool first_enable;
 };
 
 /* intel_slpc.c */
-- 
1.9.1

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[PATCH v4 22/25] drm/i915/slpc: Check GuC load status in SLPC active check

[Sagar Arun Kamble]

SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.

v2: Space and function return convention issues. (Deepak)

v3: Rebase.

v4: Limiting the check for SLPC actions.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 99b19ae..64950bc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1714,8 +1714,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int ret = 0;
 
+	if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+		return ret;
+
 	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
 		ret = 1;
 
-- 
1.9.1

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[PATCH v4 23/25] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

[Sagar Arun Kamble]

With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70e08d9..d06c9bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5064,7 +5064,13 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(GEN6_RP_CONTROL, 0);
+	uint32_t rp_ctl = 0;
+
+	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
+	if (i915.enable_slpc)
+		rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
+
+	I915_WRITE(GEN6_RP_CONTROL, rp_ctl);
 
 	dev_priv->rps.enabled = false;
 }
-- 
1.9.1

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[PATCH v4 24/25] drm/i915: Add sysfs interface to know the HW requested frequency

[Sagar Arun Kamble]

With SLPC, user can read this value to know SLPC requested frequency.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index ab161ca..7bff742 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -307,6 +307,32 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 				       dev_priv->rps.cur_freq));
 }
 
+static ssize_t gt_req_freq_mhz_show(struct device *kdev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+	u32 reqf;
+
+	if (!intel_runtime_pm_get_if_in_use(dev_priv))
+		return -ENODEV;
+
+	reqf = I915_READ(GEN6_RPNSWREQ);
+	intel_runtime_pm_put(dev_priv);
+
+	if (IS_GEN9(dev_priv))
+		reqf >>= 23;
+	else {
+		reqf &= ~GEN6_TURBO_DISABLE;
+		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+			reqf >>= 24;
+		else
+			reqf >>= 25;
+	}
+	reqf = intel_gpu_freq(dev_priv, reqf);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", reqf);
+}
+
 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
@@ -481,6 +507,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
+static DEVICE_ATTR(gt_req_freq_mhz, S_IRUGO, gt_req_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
@@ -513,6 +540,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 static const struct attribute *gen6_attrs[] = {
 	&dev_attr_gt_act_freq_mhz.attr,
 	&dev_attr_gt_cur_freq_mhz.attr,
+	&dev_attr_gt_req_freq_mhz.attr,
 	&dev_attr_gt_boost_freq_mhz.attr,
 	&dev_attr_gt_max_freq_mhz.attr,
 	&dev_attr_gt_min_freq_mhz.attr,
-- 
1.9.1

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[PATCH v4 25/25] drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

[Sagar Arun Kamble]

This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1f677a9..aeb97ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1627,6 +1627,7 @@ static int i915_drm_resume(struct drm_device *dev)
 static int i915_drm_resume_early(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	int ret;
 
@@ -1684,6 +1685,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 			  ret);
 
+	/*
+	 * Mark GuC FW load status as PENDING to avoid any Host to GuC actions
+	 * invoked till GuC gets loaded in i915_drm_resume.
+	*/
+	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+
 	intel_uncore_early_sanitize(dev_priv, true);
 
 	if (IS_BROXTON(dev_priv)) {
-- 
1.9.1

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Re: [PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1645 bytes --]

Hi Tom,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20160907]
[cannot apply to v4.8-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160907-201335
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_slpc.c: In function 'slpc_get_slice_count':
>> drivers/gpu/drm/i915/intel_slpc.c:50:37: error: 'const struct intel_device_info' has no member named 'slice_total'
      slice_count = INTEL_INFO(dev_priv)->slice_total;
                                        ^~

vim +50 drivers/gpu/drm/i915/intel_slpc.c

    44	
    45	static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
    46	{
    47		unsigned int slice_count = 1;
    48	
    49		if (IS_SKYLAKE(dev_priv))
  > 50			slice_count = INTEL_INFO(dev_priv)->slice_total;
    51	
    52		return slice_count;
    53	}

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 25029 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Dave Gordon]

On 07/09/16 14:52, kbuild test robot wrote:
> Hi Tom,
>
> [auto build test ERROR on drm-intel/for-linux-next]
> [also build test ERROR on next-20160907]
> [cannot apply to v4.8-rc5]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
> [Check https://git-scm.com/docs/git-format-patch for more information]
>
> url:    https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160907-201335
> base:   git://anongit.freedesktop.org/drm-intel for-linux-next
> config: i386-defconfig (attached as .config)
> compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
> reproduce:
>         # save the attached .config to linux build tree
>         make ARCH=i386
>
> All errors (new ones prefixed by >>):
>
>    drivers/gpu/drm/i915/intel_slpc.c: In function 'slpc_get_slice_count':
>>> drivers/gpu/drm/i915/intel_slpc.c:50:37: error: 'const struct intel_device_info' has no member named 'slice_total'
>       slice_count = INTEL_INFO(dev_priv)->slice_total;
>                                         ^~
>
> vim +50 drivers/gpu/drm/i915/intel_slpc.c
>
>     44	
>     45	static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
>     46	{
>     47		unsigned int slice_count = 1;
>     48	
>     49		if (IS_SKYLAKE(dev_priv))
>   > 50			slice_count = INTEL_INFO(dev_priv)->slice_total;
>     51	
>     52		return slice_count;
>     53	}
>
> ---
> 0-DAY kernel test infrastructure                Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
>
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Is this the right fix?

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 1a3a515..77a316e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -207,7 +207,7 @@ static unsigned int slpc_get_slice_count(struct 
drm_i915_private *dev_priv)
         unsigned int slice_count = 1;

         if (IS_SKYLAKE(dev_priv))
-               slice_count = INTEL_INFO(dev_priv)->slice_total;
+               slice_count = 
hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);

         return slice_count;
  }

.Dave.
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Re: [PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Kamble, Sagar A]

On 9/7/2016 8:26 PM, Dave Gordon wrote:
> On 07/09/16 14:52, kbuild test robot wrote:
>> Hi Tom,
>>
>> [auto build test ERROR on drm-intel/for-linux-next]
>> [also build test ERROR on next-20160907]
>> [cannot apply to v4.8-rc5]
>> [if your patch is applied to the wrong git tree, please drop us a 
>> note to help improve the system]
>> [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or 
>> --base=auto for convenience) to record what (public, well-known) 
>> commit your patch series was built on]
>> [Check https://git-scm.com/docs/git-format-patch for more information]
>>
>> url: 
>> https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160907-201335
>> base:   git://anongit.freedesktop.org/drm-intel for-linux-next
>> config: i386-defconfig (attached as .config)
>> compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
>> reproduce:
>>         # save the attached .config to linux build tree
>>         make ARCH=i386
>>
>> All errors (new ones prefixed by >>):
>>
>>    drivers/gpu/drm/i915/intel_slpc.c: In function 
>> 'slpc_get_slice_count':
>>>> drivers/gpu/drm/i915/intel_slpc.c:50:37: error: 'const struct 
>>>> intel_device_info' has no member named 'slice_total'
>>       slice_count = INTEL_INFO(dev_priv)->slice_total;
>>                                         ^~
>>
>> vim +50 drivers/gpu/drm/i915/intel_slpc.c
>>
>>     44
>>     45    static unsigned int slpc_get_slice_count(struct 
>> drm_i915_private *dev_priv)
>>     46    {
>>     47        unsigned int slice_count = 1;
>>     48
>>     49        if (IS_SKYLAKE(dev_priv))
>>   > 50            slice_count = INTEL_INFO(dev_priv)->slice_total;
>>     51
>>     52        return slice_count;
>>     53    }
>>
>> ---
>> 0-DAY kernel test infrastructure                Open Source 
>> Technology Center
>> https://lists.01.org/pipermail/kbuild-all Intel Corporation
>>
>>
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> Is this the right fix?
Yes. I forgot to rebase. Thanks.
Will be sending new series as v4 as earlier one did not go as 
series(went as individual patches - i had done "git format-patch -k ")
>
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
> b/drivers/gpu/drm/i915/intel_slpc.c
> index 1a3a515..77a316e 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -207,7 +207,7 @@ static unsigned int slpc_get_slice_count(struct 
> drm_i915_private *dev_priv)
>         unsigned int slice_count = 1;
>
>         if (IS_SKYLAKE(dev_priv))
> -               slice_count = INTEL_INFO(dev_priv)->slice_total;
> +               slice_count = 
> hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
>
>         return slice_count;
>  }
>
> .Dave.

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