[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Jerome Brunet]

This patch series adds the necessary pins, clocks and device tree nodes to
enable the spifc controller on the GXBB family. I had to add the nand pins
in pintctrl as the pinmux setting left by u-boot was conflicting with the
spifc pinmux during my test on the P200.

Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbrunet@baylibre.com
 * Omit patches :
  - dt-bindings: spi-meson: Add GXBB Compatible string
  - spi: meson: Add GXBB compatible
  Sent as dedicated series
 * Omit patch:
  - clk: gxbb: expose spifc clock
  Already applied
 * Rename SPI flash controller pins from spifc_* to nor_* to keep the
   name aligned with the datasheet

Jerome Brunet (3):
  pinctrl: amlogic: gxbb: add spi nor pins
  pinctrl: amlogic: gxbb: add nand pins
  ARM64: dts: amlogic: add spi nor pins

Neil Armstrong (1):
  ARM64: dts: meson-gxbb: Add SPIFC node

 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 37 +++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

-- 
2.7.4

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Jerome Brunet]

This patch series adds the necessary pins, clocks and device tree nodes to
enable the spifc controller on the GXBB family. I had to add the nand pins
in pintctrl as the pinmux setting left by u-boot was conflicting with the
spifc pinmux during my test on the P200.

Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbrunet at baylibre.com
 * Omit patches :
  - dt-bindings: spi-meson: Add GXBB Compatible string
  - spi: meson: Add GXBB compatible
  Sent as dedicated series
 * Omit patch:
  - clk: gxbb: expose spifc clock
  Already applied
 * Rename SPI flash controller pins from spifc_* to nor_* to keep the
   name aligned with the datasheet

Jerome Brunet (3):
  pinctrl: amlogic: gxbb: add spi nor pins
  pinctrl: amlogic: gxbb: add nand pins
  ARM64: dts: amlogic: add spi nor pins

Neil Armstrong (1):
  ARM64: dts: meson-gxbb: Add SPIFC node

 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 37 +++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

-- 
2.7.4

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Jerome Brunet]

This patch series adds the necessary pins, clocks and device tree nodes to
enable the spifc controller on the GXBB family. I had to add the nand pins
in pintctrl as the pinmux setting left by u-boot was conflicting with the
spifc pinmux during my test on the P200.

Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbrunet at baylibre.com
 * Omit patches :
  - dt-bindings: spi-meson: Add GXBB Compatible string
  - spi: meson: Add GXBB compatible
  Sent as dedicated series
 * Omit patch:
  - clk: gxbb: expose spifc clock
  Already applied
 * Rename SPI flash controller pins from spifc_* to nor_* to keep the
   name aligned with the datasheet

Jerome Brunet (3):
  pinctrl: amlogic: gxbb: add spi nor pins
  pinctrl: amlogic: gxbb: add nand pins
  ARM64: dts: amlogic: add spi nor pins

Neil Armstrong (1):
  ARM64: dts: meson-gxbb: Add SPIFC node

 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 37 +++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

-- 
2.7.4

[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Jerome Brunet]

Add EE domains pins for the SPI flash controller

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index cb4d6ad30530..f74dbd5d350b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
 
+static const unsigned int nor_d_pins[]		= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nor_q_pins[]		= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nor_c_pins[]		= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nor_cs_pins[]		= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
 static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
 static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -393,6 +398,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(emmc_clk,		4,	18),
 	GROUP(emmc_cmd,		4,	19),
 	GROUP(emmc_ds,		4,	31),
+	GROUP(nor_d,		5,	1),
+	GROUP(nor_q,		5,	3),
+	GROUP(nor_c,		5,	2),
+	GROUP(nor_cs,		5,	0),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -475,6 +484,10 @@ static const char * const emmc_groups[] = {
 	"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
 };
 
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+};
+
 static const char * const sdcard_groups[] = {
 	"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
 	"sdcard_cmd", "sdcard_clk",
@@ -524,6 +537,7 @@ static const char * const i2c_slave_ao_groups[] = {
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
+	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
-- 
2.7.4

[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Jerome Brunet]

Add EE domains pins for the SPI flash controller

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index cb4d6ad30530..f74dbd5d350b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
 
+static const unsigned int nor_d_pins[]		= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nor_q_pins[]		= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nor_c_pins[]		= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nor_cs_pins[]		= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
 static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
 static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -393,6 +398,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(emmc_clk,		4,	18),
 	GROUP(emmc_cmd,		4,	19),
 	GROUP(emmc_ds,		4,	31),
+	GROUP(nor_d,		5,	1),
+	GROUP(nor_q,		5,	3),
+	GROUP(nor_c,		5,	2),
+	GROUP(nor_cs,		5,	0),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -475,6 +484,10 @@ static const char * const emmc_groups[] = {
 	"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
 };
 
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+};
+
 static const char * const sdcard_groups[] = {
 	"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
 	"sdcard_cmd", "sdcard_clk",
@@ -524,6 +537,7 @@ static const char * const i2c_slave_ao_groups[] = {
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
+	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
-- 
2.7.4

[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Jerome Brunet]

Add EE domains pins for the SPI flash controller

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index cb4d6ad30530..f74dbd5d350b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
 
+static const unsigned int nor_d_pins[]		= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nor_q_pins[]		= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nor_c_pins[]		= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nor_cs_pins[]		= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
 static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
 static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -393,6 +398,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(emmc_clk,		4,	18),
 	GROUP(emmc_cmd,		4,	19),
 	GROUP(emmc_ds,		4,	31),
+	GROUP(nor_d,		5,	1),
+	GROUP(nor_q,		5,	3),
+	GROUP(nor_c,		5,	2),
+	GROUP(nor_cs,		5,	0),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -475,6 +484,10 @@ static const char * const emmc_groups[] = {
 	"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
 };
 
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+};
+
 static const char * const sdcard_groups[] = {
 	"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
 	"sdcard_cmd", "sdcard_clk",
@@ -524,6 +537,7 @@ static const char * const i2c_slave_ao_groups[] = {
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
+	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
-- 
2.7.4

[PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Jerome Brunet]

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f74dbd5d350b..699f93c51040 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -168,6 +168,15 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
 static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
 static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
 
+static const unsigned int nand_ce0_pins[]	= { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[]	= { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[]	= { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[]	= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[]	= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[]	= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[]	= { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[]	= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
 static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
@@ -402,6 +411,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(nor_q,		5,	3),
 	GROUP(nor_c,		5,	2),
 	GROUP(nor_cs,		5,	0),
+	GROUP(nand_ce0,		4,	26),
+	GROUP(nand_ce1,		4,	27),
+	GROUP(nand_rb0,		4,	25),
+	GROUP(nand_ale,		4,	24),
+	GROUP(nand_cle,		4,	23),
+	GROUP(nand_wen_clk,	4,	22),
+	GROUP(nand_ren_wr,	4,	21),
+	GROUP(nand_dqs,		4,	20),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -493,6 +510,11 @@ static const char * const sdcard_groups[] = {
 	"sdcard_cmd", "sdcard_clk",
 };
 
+static const char * const nand_groups[] = {
+	"nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
 static const char * const uart_a_groups[] = {
 	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
 };
@@ -539,6 +561,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(emmc),
 	FUNCTION(nor),
 	FUNCTION(sdcard),
+	FUNCTION(nand),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
-- 
2.7.4

[PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Jerome Brunet]

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f74dbd5d350b..699f93c51040 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -168,6 +168,15 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
 static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
 static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
 
+static const unsigned int nand_ce0_pins[]	= { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[]	= { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[]	= { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[]	= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[]	= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[]	= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[]	= { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[]	= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
 static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
@@ -402,6 +411,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(nor_q,		5,	3),
 	GROUP(nor_c,		5,	2),
 	GROUP(nor_cs,		5,	0),
+	GROUP(nand_ce0,		4,	26),
+	GROUP(nand_ce1,		4,	27),
+	GROUP(nand_rb0,		4,	25),
+	GROUP(nand_ale,		4,	24),
+	GROUP(nand_cle,		4,	23),
+	GROUP(nand_wen_clk,	4,	22),
+	GROUP(nand_ren_wr,	4,	21),
+	GROUP(nand_dqs,		4,	20),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -493,6 +510,11 @@ static const char * const sdcard_groups[] = {
 	"sdcard_cmd", "sdcard_clk",
 };
 
+static const char * const nand_groups[] = {
+	"nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
 static const char * const uart_a_groups[] = {
 	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
 };
@@ -539,6 +561,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(emmc),
 	FUNCTION(nor),
 	FUNCTION(sdcard),
+	FUNCTION(nand),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
-- 
2.7.4

[PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Jerome Brunet]

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f74dbd5d350b..699f93c51040 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -168,6 +168,15 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
 static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
 static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
 
+static const unsigned int nand_ce0_pins[]	= { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[]	= { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[]	= { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[]	= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[]	= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[]	= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[]	= { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[]	= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
 static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
@@ -402,6 +411,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(nor_q,		5,	3),
 	GROUP(nor_c,		5,	2),
 	GROUP(nor_cs,		5,	0),
+	GROUP(nand_ce0,		4,	26),
+	GROUP(nand_ce1,		4,	27),
+	GROUP(nand_rb0,		4,	25),
+	GROUP(nand_ale,		4,	24),
+	GROUP(nand_cle,		4,	23),
+	GROUP(nand_wen_clk,	4,	22),
+	GROUP(nand_ren_wr,	4,	21),
+	GROUP(nand_dqs,		4,	20),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -493,6 +510,11 @@ static const char * const sdcard_groups[] = {
 	"sdcard_cmd", "sdcard_clk",
 };
 
+static const char * const nand_groups[] = {
+	"nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
 static const char * const uart_a_groups[] = {
 	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
 };
@@ -539,6 +561,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(emmc),
 	FUNCTION(nor),
 	FUNCTION(sdcard),
+	FUNCTION(nand),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
-- 
2.7.4

[PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Jerome Brunet]

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f74dbd5d350b..699f93c51040 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -168,6 +168,15 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
 static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
 static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
 
+static const unsigned int nand_ce0_pins[]	= { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[]	= { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[]	= { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[]	= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[]	= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[]	= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[]	= { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[]	= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
 static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
@@ -402,6 +411,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(nor_q,		5,	3),
 	GROUP(nor_c,		5,	2),
 	GROUP(nor_cs,		5,	0),
+	GROUP(nand_ce0,		4,	26),
+	GROUP(nand_ce1,		4,	27),
+	GROUP(nand_rb0,		4,	25),
+	GROUP(nand_ale,		4,	24),
+	GROUP(nand_cle,		4,	23),
+	GROUP(nand_wen_clk,	4,	22),
+	GROUP(nand_ren_wr,	4,	21),
+	GROUP(nand_dqs,		4,	20),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -493,6 +510,11 @@ static const char * const sdcard_groups[] = {
 	"sdcard_cmd", "sdcard_clk",
 };
 
+static const char * const nand_groups[] = {
+	"nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
 static const char * const uart_a_groups[] = {
 	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
 };
@@ -539,6 +561,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(emmc),
 	FUNCTION(nor),
 	FUNCTION(sdcard),
+	FUNCTION(nand),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
-- 
2.7.4

[PATCH v2 3/4] ARM64: dts: amlogic: add spi nor pins

[Jerome Brunet]

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 762f3681a49c..49e803e42e10 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -333,6 +333,16 @@
 					};
 				};
 
+				nor_pins: nor {
+					mux {
+						groups = "nor_d",
+						       "nor_q",
+						       "nor_c",
+						       "nor_cs";
+						function = "nor";
+					};
+				};
+
 				sdcard_pins: sdcard {
 					mux {
 						groups = "sdcard_d0",
-- 
2.7.4

[PATCH v2 3/4] ARM64: dts: amlogic: add spi nor pins

[Jerome Brunet]

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 762f3681a49c..49e803e42e10 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -333,6 +333,16 @@
 					};
 				};
 
+				nor_pins: nor {
+					mux {
+						groups = "nor_d",
+						       "nor_q",
+						       "nor_c",
+						       "nor_cs";
+						function = "nor";
+					};
+				};
+
 				sdcard_pins: sdcard {
 					mux {
 						groups = "sdcard_d0",
-- 
2.7.4

[PATCH v2 3/4] ARM64: dts: amlogic: add spi nor pins

[Jerome Brunet]

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 762f3681a49c..49e803e42e10 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -333,6 +333,16 @@
 					};
 				};
 
+				nor_pins: nor {
+					mux {
+						groups = "nor_d",
+						       "nor_q",
+						       "nor_c",
+						       "nor_cs";
+						function = "nor";
+					};
+				};
+
 				sdcard_pins: sdcard {
 					mux {
 						groups = "sdcard_d0",
-- 
2.7.4

[PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node

[Jerome Brunet]

From: Neil Armstrong <narmstrong@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 49e803e42e10..8d3bf3c7345e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -193,6 +193,15 @@
 				reg = <0x0 0x098d0 0x0 0x10>;
 				clocks = <&xtal>;
 			};
+
+			spifc: spi@8c80 {
+				compatible = "amlogic,meson-gxbb-spifc";
+				reg = <0x0 0x08c80 0x0 0x80>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clkc CLKID_SPI>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@c4301000 {
-- 
2.7.4

[PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node

[Jerome Brunet]

From: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>

Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Signed-off-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 49e803e42e10..8d3bf3c7345e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -193,6 +193,15 @@
 				reg = <0x0 0x098d0 0x0 0x10>;
 				clocks = <&xtal>;
 			};
+
+			spifc: spi@8c80 {
+				compatible = "amlogic,meson-gxbb-spifc";
+				reg = <0x0 0x08c80 0x0 0x80>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clkc CLKID_SPI>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@c4301000 {
-- 
2.7.4

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[PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node

[Jerome Brunet]

From: Neil Armstrong <narmstrong@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 49e803e42e10..8d3bf3c7345e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -193,6 +193,15 @@
 				reg = <0x0 0x098d0 0x0 0x10>;
 				clocks = <&xtal>;
 			};
+
+			spifc: spi at 8c80 {
+				compatible = "amlogic,meson-gxbb-spifc";
+				reg = <0x0 0x08c80 0x0 0x80>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clkc CLKID_SPI>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller at c4301000 {
-- 
2.7.4

[PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node

[Jerome Brunet]

From: Neil Armstrong <narmstrong@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 49e803e42e10..8d3bf3c7345e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -193,6 +193,15 @@
 				reg = <0x0 0x098d0 0x0 0x10>;
 				clocks = <&xtal>;
 			};
+
+			spifc: spi at 8c80 {
+				compatible = "amlogic,meson-gxbb-spifc";
+				reg = <0x0 0x08c80 0x0 0x80>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clkc CLKID_SPI>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller at c4301000 {
-- 
2.7.4

Re: [PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Acked-by: Kevin Hilman <khilman@baylibre.com>

[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Acked-by: Kevin Hilman <khilman@baylibre.com>

[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Acked-by: Kevin Hilman <khilman@baylibre.com>

Re: [PATCH v2 3/4] ARM64: dts: amlogic: add spi nor pins

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Applied.

Kevin

[PATCH v2 3/4] ARM64: dts: amlogic: add spi nor pins

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Applied.

Kevin

[PATCH v2 3/4] ARM64: dts: amlogic: add spi nor pins

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Applied.

Kevin

Re: [PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> From: Neil Armstrong <narmstrong@baylibre.com>
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Applied,

Kevin

[PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> From: Neil Armstrong <narmstrong@baylibre.com>
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Applied,

Kevin

[PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> From: Neil Armstrong <narmstrong@baylibre.com>
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Applied,

Kevin

Re: [PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> This patch series adds the necessary pins, clocks and device tree nodes to
> enable the spifc controller on the GXBB family. I had to add the nand pins
> in pintctrl as the pinmux setting left by u-boot was conflicting with the
> spifc pinmux during my test on the P200.

This series seems to be missing a patch which enables the SPIfc on the
P200 board for use with the on-board NOR flash.

Kevin

> Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbrunet@baylibre.com
>  * Omit patches :
>   - dt-bindings: spi-meson: Add GXBB Compatible string
>   - spi: meson: Add GXBB compatible
>   Sent as dedicated series
>  * Omit patch:
>   - clk: gxbb: expose spifc clock
>   Already applied
>  * Rename SPI flash controller pins from spifc_* to nor_* to keep the
>    name aligned with the datasheet
>
> Jerome Brunet (3):
>   pinctrl: amlogic: gxbb: add spi nor pins
>   pinctrl: amlogic: gxbb: add nand pins
>   ARM64: dts: amlogic: add spi nor pins
>
> Neil Armstrong (1):
>   ARM64: dts: meson-gxbb: Add SPIFC node
>
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
>  drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 37 +++++++++++++++++++++++++++++
>  2 files changed, 56 insertions(+)

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> This patch series adds the necessary pins, clocks and device tree nodes to
> enable the spifc controller on the GXBB family. I had to add the nand pins
> in pintctrl as the pinmux setting left by u-boot was conflicting with the
> spifc pinmux during my test on the P200.

This series seems to be missing a patch which enables the SPIfc on the
P200 board for use with the on-board NOR flash.

Kevin

> Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbrunet at baylibre.com
>  * Omit patches :
>   - dt-bindings: spi-meson: Add GXBB Compatible string
>   - spi: meson: Add GXBB compatible
>   Sent as dedicated series
>  * Omit patch:
>   - clk: gxbb: expose spifc clock
>   Already applied
>  * Rename SPI flash controller pins from spifc_* to nor_* to keep the
>    name aligned with the datasheet
>
> Jerome Brunet (3):
>   pinctrl: amlogic: gxbb: add spi nor pins
>   pinctrl: amlogic: gxbb: add nand pins
>   ARM64: dts: amlogic: add spi nor pins
>
> Neil Armstrong (1):
>   ARM64: dts: meson-gxbb: Add SPIFC node
>
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
>  drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 37 +++++++++++++++++++++++++++++
>  2 files changed, 56 insertions(+)

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> This patch series adds the necessary pins, clocks and device tree nodes to
> enable the spifc controller on the GXBB family. I had to add the nand pins
> in pintctrl as the pinmux setting left by u-boot was conflicting with the
> spifc pinmux during my test on the P200.

This series seems to be missing a patch which enables the SPIfc on the
P200 board for use with the on-board NOR flash.

Kevin

> Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbrunet at baylibre.com
>  * Omit patches :
>   - dt-bindings: spi-meson: Add GXBB Compatible string
>   - spi: meson: Add GXBB compatible
>   Sent as dedicated series
>  * Omit patch:
>   - clk: gxbb: expose spifc clock
>   Already applied
>  * Rename SPI flash controller pins from spifc_* to nor_* to keep the
>    name aligned with the datasheet
>
> Jerome Brunet (3):
>   pinctrl: amlogic: gxbb: add spi nor pins
>   pinctrl: amlogic: gxbb: add nand pins
>   ARM64: dts: amlogic: add spi nor pins
>
> Neil Armstrong (1):
>   ARM64: dts: meson-gxbb: Add SPIFC node
>
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
>  drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 37 +++++++++++++++++++++++++++++
>  2 files changed, 56 insertions(+)

Re: [PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[jbrunet]

On Mon, 2016-09-12 at 13:38 -0700, Kevin Hilman wrote:
> Jerome Brunet <jbrunet@baylibre.com> writes:
> 
> > 
> > This patch series adds the necessary pins, clocks and device tree
> > nodes to
> > enable the spifc controller on the GXBB family. I had to add the
> > nand pins
> > in pintctrl as the pinmux setting left by u-boot was conflicting
> > with the
> > spifc pinmux during my test on the P200.
> 
> This series seems to be missing a patch which enables the SPIfc on
> the
> P200 board for use with the on-board NOR flash.
> 
> Kevin
> 

Indeed, I did not provide this patch, on purpose.
The SPI-NOR at 4U2 on the P200 schematics was not present on the board
I have. I assumed this was the case for all other P200 as well.

In addition, to enable the SPI-NOR, you would also need to solder
something at 4R3 (SPI_CS signal disconnected by default)

Finally, all the SPIfc lines are shared with the NAND controller which,
like the SPI-NOR, appears on the schematics (4CCN1) but is not soldered
on the actual hardware.

Of course, I can share such patch for testing purposes if you would
like me to.

Jerome.

> > 
> > Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-g
> > it-send-email-jbrunet@baylibre.com
> >  * Omit patches :
> >   - dt-bindings: spi-meson: Add GXBB Compatible string
> >   - spi: meson: Add GXBB compatible
> >   Sent as dedicated series
> >  * Omit patch:
> >   - clk: gxbb: expose spifc clock
> >   Already applied
> >  * Rename SPI flash controller pins from spifc_* to nor_* to keep
> > the
> >    name aligned with the datasheet
> > 
> > Jerome Brunet (3):
> >   pinctrl: amlogic: gxbb: add spi nor pins
> >   pinctrl: amlogic: gxbb: add nand pins
> >   ARM64: dts: amlogic: add spi nor pins
> > 
> > Neil Armstrong (1):
> >   ARM64: dts: meson-gxbb: Add SPIFC node
> > 
> >  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
> >  drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 37
> > +++++++++++++++++++++++++++++
> >  2 files changed, 56 insertions(+)

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[jbrunet]

On Mon, 2016-09-12 at 13:38 -0700, Kevin Hilman wrote:
> Jerome Brunet <jbrunet@baylibre.com> writes:
> 
> > 
> > This patch series adds the necessary pins, clocks and device tree
> > nodes to
> > enable the spifc controller on the GXBB family. I had to add the
> > nand pins
> > in pintctrl as the pinmux setting left by u-boot was conflicting
> > with the
> > spifc pinmux during my test on the P200.
> 
> This series seems to be missing a patch which enables the SPIfc on
> the
> P200 board for use with the on-board NOR flash.
> 
> Kevin
> 

Indeed, I did not provide this patch, on purpose.
The SPI-NOR at 4U2 on the P200 schematics was not present on the board
I have. I assumed this was the case for all other P200 as well.

In addition, to enable the SPI-NOR, you would also need to solder
something at 4R3 (SPI_CS signal disconnected by default)

Finally, all the SPIfc lines are shared with the NAND controller which,
like the SPI-NOR, appears on the schematics (4CCN1) but is not soldered
on the actual hardware.

Of course, I can share such patch for testing purposes if you would
like me to.

Jerome.

> > 
> > Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-g
> > it-send-email-jbrunet at baylibre.com
> > ?* Omit patches :
> > ? - dt-bindings: spi-meson: Add GXBB Compatible string
> > ? - spi: meson: Add GXBB compatible
> > ? Sent as dedicated series
> > ?* Omit patch:
> > ? - clk: gxbb: expose spifc clock
> > ? Already applied
> > ?* Rename SPI flash controller pins from spifc_* to nor_* to keep
> > the
> > ???name aligned with the datasheet
> > 
> > Jerome Brunet (3):
> > ? pinctrl: amlogic: gxbb: add spi nor pins
> > ? pinctrl: amlogic: gxbb: add nand pins
> > ? ARM64: dts: amlogic: add spi nor pins
> > 
> > Neil Armstrong (1):
> > ? ARM64: dts: meson-gxbb: Add SPIFC node
> > 
> > ?arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
> > ?drivers/pinctrl/meson/pinctrl-meson-gxbb.c??| 37
> > +++++++++++++++++++++++++++++
> > ?2 files changed, 56 insertions(+)

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[jbrunet]

On Mon, 2016-09-12 at 13:38 -0700, Kevin Hilman wrote:
> Jerome Brunet <jbrunet@baylibre.com> writes:
> 
> > 
> > This patch series adds the necessary pins, clocks and device tree
> > nodes to
> > enable the spifc controller on the GXBB family. I had to add the
> > nand pins
> > in pintctrl as the pinmux setting left by u-boot was conflicting
> > with the
> > spifc pinmux during my test on the P200.
> 
> This series seems to be missing a patch which enables the SPIfc on
> the
> P200 board for use with the on-board NOR flash.
> 
> Kevin
> 

Indeed, I did not provide this patch, on purpose.
The SPI-NOR at 4U2 on the P200 schematics was not present on the board
I have. I assumed this was the case for all other P200 as well.

In addition, to enable the SPI-NOR, you would also need to solder
something at 4R3 (SPI_CS signal disconnected by default)

Finally, all the SPIfc lines are shared with the NAND controller which,
like the SPI-NOR, appears on the schematics (4CCN1) but is not soldered
on the actual hardware.

Of course, I can share such patch for testing purposes if you would
like me to.

Jerome.

> > 
> > Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-g
> > it-send-email-jbrunet at baylibre.com
> > ?* Omit patches :
> > ? - dt-bindings: spi-meson: Add GXBB Compatible string
> > ? - spi: meson: Add GXBB compatible
> > ? Sent as dedicated series
> > ?* Omit patch:
> > ? - clk: gxbb: expose spifc clock
> > ? Already applied
> > ?* Rename SPI flash controller pins from spifc_* to nor_* to keep
> > the
> > ???name aligned with the datasheet
> > 
> > Jerome Brunet (3):
> > ? pinctrl: amlogic: gxbb: add spi nor pins
> > ? pinctrl: amlogic: gxbb: add nand pins
> > ? ARM64: dts: amlogic: add spi nor pins
> > 
> > Neil Armstrong (1):
> > ? ARM64: dts: meson-gxbb: Add SPIFC node
> > 
> > ?arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++
> > ?drivers/pinctrl/meson/pinctrl-meson-gxbb.c??| 37
> > +++++++++++++++++++++++++++++
> > ?2 files changed, 56 insertions(+)

Re: [PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Linus Walleij]

On Fri, Sep 9, 2016 at 10:28 AM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

This patch does not apply on the latest pinctrl devel
branch:
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

Please rebase, include Kevin's ACK and resend.

Goes for all pinctrl portions of the patch series.

Yours,
Linus Walleij

Re: [PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Linus Walleij]

On Fri, Sep 9, 2016 at 10:28 AM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

This patch does not apply on the latest pinctrl devel
branch:
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

Please rebase, include Kevin's ACK and resend.

Goes for all pinctrl portions of the patch series.

Yours,
Linus Walleij

[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Linus Walleij]

On Fri, Sep 9, 2016 at 10:28 AM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

This patch does not apply on the latest pinctrl devel
branch:
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

Please rebase, include Kevin's ACK and resend.

Goes for all pinctrl portions of the patch series.

Yours,
Linus Walleij

[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Linus Walleij]

On Fri, Sep 9, 2016 at 10:28 AM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

This patch does not apply on the latest pinctrl devel
branch:
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

Please rebase, include Kevin's ACK and resend.

Goes for all pinctrl portions of the patch series.

Yours,
Linus Walleij

Re: [PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Kevin Hilman]

jbrunet <jbrunet@baylibre.com> writes:

> On Mon, 2016-09-12 at 13:38 -0700, Kevin Hilman wrote:
>> Jerome Brunet <jbrunet@baylibre.com> writes:
>> 
>> > 
>> > This patch series adds the necessary pins, clocks and device tree
>> > nodes to
>> > enable the spifc controller on the GXBB family. I had to add the
>> > nand pins
>> > in pintctrl as the pinmux setting left by u-boot was conflicting
>> > with the
>> > spifc pinmux during my test on the P200.
>> 
>> This series seems to be missing a patch which enables the SPIfc on
>> the
>> P200 board for use with the on-board NOR flash.
>> 
>
> Indeed, I did not provide this patch, on purpose.
> The SPI-NOR at 4U2 on the P200 schematics was not present on the board
> I have. I assumed this was the case for all other P200 as well.
>
> In addition, to enable the SPI-NOR, you would also need to solder
> something at 4R3 (SPI_CS signal disconnected by default)

OK, that makes seense.  I thought the NOR was on the board by default.

> Finally, all the SPIfc lines are shared with the NAND controller which,
> like the SPI-NOR, appears on the schematics (4CCN1) but is not soldered
> on the actual hardware.
>
> Of course, I can share such patch for testing purposes if you would
> like me to.

Yeah, having a testing patch in the list archives would be useful.

Thanks,

Kevin

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Kevin Hilman]

jbrunet <jbrunet@baylibre.com> writes:

> On Mon, 2016-09-12 at 13:38 -0700, Kevin Hilman wrote:
>> Jerome Brunet <jbrunet@baylibre.com> writes:
>> 
>> > 
>> > This patch series adds the necessary pins, clocks and device tree
>> > nodes to
>> > enable the spifc controller on the GXBB family. I had to add the
>> > nand pins
>> > in pintctrl as the pinmux setting left by u-boot was conflicting
>> > with the
>> > spifc pinmux during my test on the P200.
>> 
>> This series seems to be missing a patch which enables the SPIfc on
>> the
>> P200 board for use with the on-board NOR flash.
>> 
>
> Indeed, I did not provide this patch, on purpose.
> The SPI-NOR at 4U2 on the P200 schematics was not present on the board
> I have. I assumed this was the case for all other P200 as well.
>
> In addition, to enable the SPI-NOR, you would also need to solder
> something at 4R3 (SPI_CS signal disconnected by default)

OK, that makes seense.  I thought the NOR was on the board by default.

> Finally, all the SPIfc lines are shared with the NAND controller which,
> like the SPI-NOR, appears on the schematics (4CCN1) but is not soldered
> on the actual hardware.
>
> Of course, I can share such patch for testing purposes if you would
> like me to.

Yeah, having a testing patch in the list archives would be useful.

Thanks,

Kevin

[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family

[Kevin Hilman]

jbrunet <jbrunet@baylibre.com> writes:

> On Mon, 2016-09-12 at 13:38 -0700, Kevin Hilman wrote:
>> Jerome Brunet <jbrunet@baylibre.com> writes:
>> 
>> > 
>> > This patch series adds the necessary pins, clocks and device tree
>> > nodes to
>> > enable the spifc controller on the GXBB family. I had to add the
>> > nand pins
>> > in pintctrl as the pinmux setting left by u-boot was conflicting
>> > with the
>> > spifc pinmux during my test on the P200.
>> 
>> This series seems to be missing a patch which enables the SPIfc on
>> the
>> P200 board for use with the on-board NOR flash.
>> 
>
> Indeed, I did not provide this patch, on purpose.
> The SPI-NOR at 4U2 on the P200 schematics was not present on the board
> I have. I assumed this was the case for all other P200 as well.
>
> In addition, to enable the SPI-NOR, you would also need to solder
> something at 4R3 (SPI_CS signal disconnected by default)

OK, that makes seense.  I thought the NOR was on the board by default.

> Finally, all the SPIfc lines are shared with the NAND controller which,
> like the SPI-NOR, appears on the schematics (4CCN1) but is not soldered
> on the actual hardware.
>
> Of course, I can share such patch for testing purposes if you would
> like me to.

Yeah, having a testing patch in the list archives would be useful.

Thanks,

Kevin

[RESEND PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Jerome Brunet]

Add EE domains pins for the SPI flash controller

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f115638e8699..573901887cee 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
 
+static const unsigned int nor_d_pins[]		= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nor_q_pins[]		= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nor_c_pins[]		= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nor_cs_pins[]		= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
 static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
 static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -430,6 +435,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(emmc_clk,		4,	18),
 	GROUP(emmc_cmd,		4,	19),
 	GROUP(emmc_ds,		4,	31),
+	GROUP(nor_d,		5,	1),
+	GROUP(nor_q,		5,	3),
+	GROUP(nor_c,		5,	2),
+	GROUP(nor_cs,		5,	0),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -517,6 +526,10 @@ static const char * const emmc_groups[] = {
 	"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
 };
 
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+};
+
 static const char * const sdcard_groups[] = {
 	"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
 	"sdcard_cmd", "sdcard_clk",
@@ -619,6 +632,7 @@ static const char * const pwm_ao_b_groups[] = {
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
+	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(sdio),
 	FUNCTION(uart_a),
-- 
2.7.4

[RESEND PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Jerome Brunet]

Add EE domains pins for the SPI flash controller

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f115638e8699..573901887cee 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
 
+static const unsigned int nor_d_pins[]		= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nor_q_pins[]		= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nor_c_pins[]		= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nor_cs_pins[]		= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
 static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
 static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -430,6 +435,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(emmc_clk,		4,	18),
 	GROUP(emmc_cmd,		4,	19),
 	GROUP(emmc_ds,		4,	31),
+	GROUP(nor_d,		5,	1),
+	GROUP(nor_q,		5,	3),
+	GROUP(nor_c,		5,	2),
+	GROUP(nor_cs,		5,	0),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -517,6 +526,10 @@ static const char * const emmc_groups[] = {
 	"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
 };
 
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+};
+
 static const char * const sdcard_groups[] = {
 	"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
 	"sdcard_cmd", "sdcard_clk",
@@ -619,6 +632,7 @@ static const char * const pwm_ao_b_groups[] = {
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
+	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(sdio),
 	FUNCTION(uart_a),
-- 
2.7.4

[RESEND PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Jerome Brunet]

Add EE domains pins for the SPI flash controller

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f115638e8699..573901887cee 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
 
+static const unsigned int nor_d_pins[]		= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nor_q_pins[]		= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nor_c_pins[]		= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nor_cs_pins[]		= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
 static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
 static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -430,6 +435,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(emmc_clk,		4,	18),
 	GROUP(emmc_cmd,		4,	19),
 	GROUP(emmc_ds,		4,	31),
+	GROUP(nor_d,		5,	1),
+	GROUP(nor_q,		5,	3),
+	GROUP(nor_c,		5,	2),
+	GROUP(nor_cs,		5,	0),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -517,6 +526,10 @@ static const char * const emmc_groups[] = {
 	"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
 };
 
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+};
+
 static const char * const sdcard_groups[] = {
 	"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
 	"sdcard_cmd", "sdcard_clk",
@@ -619,6 +632,7 @@ static const char * const pwm_ao_b_groups[] = {
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
+	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(sdio),
 	FUNCTION(uart_a),
-- 
2.7.4

[RESEND PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Jerome Brunet]

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 573901887cee..b06cc12f2500 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -176,6 +176,15 @@ static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) };
 static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) };
 static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) };
 
+static const unsigned int nand_ce0_pins[]	= { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[]	= { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[]	= { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[]	= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[]	= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[]	= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[]	= { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[]	= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
 static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
@@ -439,6 +448,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(nor_q,		5,	3),
 	GROUP(nor_c,		5,	2),
 	GROUP(nor_cs,		5,	0),
+	GROUP(nand_ce0,		4,	26),
+	GROUP(nand_ce1,		4,	27),
+	GROUP(nand_rb0,		4,	25),
+	GROUP(nand_ale,		4,	24),
+	GROUP(nand_cle,		4,	23),
+	GROUP(nand_wen_clk,	4,	22),
+	GROUP(nand_ren_wr,	4,	21),
+	GROUP(nand_dqs,		4,	20),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -540,6 +557,11 @@ static const char * const sdio_groups[] = {
 	"sdio_cmd", "sdio_clk", "sdio_irq",
 };
 
+static const char * const nand_groups[] = {
+	"nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
 static const char * const uart_a_groups[] = {
 	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
 };
@@ -635,6 +657,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(sdio),
+	FUNCTION(nand),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
-- 
2.7.4

[RESEND PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Jerome Brunet]

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 573901887cee..b06cc12f2500 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -176,6 +176,15 @@ static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) };
 static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) };
 static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) };
 
+static const unsigned int nand_ce0_pins[]	= { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[]	= { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[]	= { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[]	= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[]	= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[]	= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[]	= { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[]	= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
 static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
@@ -439,6 +448,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(nor_q,		5,	3),
 	GROUP(nor_c,		5,	2),
 	GROUP(nor_cs,		5,	0),
+	GROUP(nand_ce0,		4,	26),
+	GROUP(nand_ce1,		4,	27),
+	GROUP(nand_rb0,		4,	25),
+	GROUP(nand_ale,		4,	24),
+	GROUP(nand_cle,		4,	23),
+	GROUP(nand_wen_clk,	4,	22),
+	GROUP(nand_ren_wr,	4,	21),
+	GROUP(nand_dqs,		4,	20),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -540,6 +557,11 @@ static const char * const sdio_groups[] = {
 	"sdio_cmd", "sdio_clk", "sdio_irq",
 };
 
+static const char * const nand_groups[] = {
+	"nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
 static const char * const uart_a_groups[] = {
 	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
 };
@@ -635,6 +657,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(sdio),
+	FUNCTION(nand),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
-- 
2.7.4

[RESEND PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Jerome Brunet]

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 573901887cee..b06cc12f2500 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -176,6 +176,15 @@ static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) };
 static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) };
 static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) };
 
+static const unsigned int nand_ce0_pins[]	= { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[]	= { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[]	= { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[]	= { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[]	= { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[]	= { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[]	= { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[]	= { PIN(BOOT_15, EE_OFF) };
+
 static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
 static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
@@ -439,6 +448,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(nor_q,		5,	3),
 	GROUP(nor_c,		5,	2),
 	GROUP(nor_cs,		5,	0),
+	GROUP(nand_ce0,		4,	26),
+	GROUP(nand_ce1,		4,	27),
+	GROUP(nand_rb0,		4,	25),
+	GROUP(nand_ale,		4,	24),
+	GROUP(nand_cle,		4,	23),
+	GROUP(nand_wen_clk,	4,	22),
+	GROUP(nand_ren_wr,	4,	21),
+	GROUP(nand_dqs,		4,	20),
 
 	/* Bank CARD */
 	GROUP(sdcard_d1,	2,	14),
@@ -540,6 +557,11 @@ static const char * const sdio_groups[] = {
 	"sdio_cmd", "sdio_clk", "sdio_irq",
 };
 
+static const char * const nand_groups[] = {
+	"nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
 static const char * const uart_a_groups[] = {
 	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
 };
@@ -635,6 +657,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(nor),
 	FUNCTION(sdcard),
 	FUNCTION(sdio),
+	FUNCTION(nand),
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
-- 
2.7.4

[RFT] ARM64: dts: gxbb: add spifc device

[Jerome Brunet]

Enable the spifc controller on the gxbb p200 and add spi nor device on
it. By default, the spi nor shown on the schematics is not present on
the actual hardware. Same goes for the resistor 4R3 which needs to be
soldered in order to connect the NOR_CS signal to the SPI device.

Keep in mind that the spifc lines are shared with the NAND controller.

This patch is not intended to be upstreamed and is provided here for
testing purpose.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 0eaca7277cfd..116cbc91c8e2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -77,3 +77,17 @@
 	pinctrl-0 = <&remote_input_ao_pins>;
 	pinctrl-names = "default";
 };
+
+&spifc {
+	status = "okay";
+	pinctrl-0 = <&nor_pins>;
+	pinctrl-names = "default";
+
+	spi-flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+	};
+};
-- 
2.7.4

Re: [RESEND PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Linus Walleij]

On Tue, Sep 13, 2016 at 5:12 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the SPI flash controller
>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Patch applied.

Yours,
Linus Walleij

[RESEND PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Linus Walleij]

On Tue, Sep 13, 2016 at 5:12 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the SPI flash controller
>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Patch applied.

Yours,
Linus Walleij

[RESEND PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins

[Linus Walleij]

On Tue, Sep 13, 2016 at 5:12 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the SPI flash controller
>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Patch applied.

Yours,
Linus Walleij

Re: [RESEND PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Linus Walleij]

On Tue, Sep 13, 2016 at 5:12 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the NAND flash controller.
> Even tough we have no driver for the NAND flash controller yet, we need
> to have these pins in pinctrl as the actual pin are shared with the spifc
> controller. The bootloader on the S905-P200 setup pinmux for the NAND
> controller so we need the kernel to properly deactivate this if necessary.
>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Patch applied.

Yours,
Linus Walleij

[RESEND PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Linus Walleij]

On Tue, Sep 13, 2016 at 5:12 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the NAND flash controller.
> Even tough we have no driver for the NAND flash controller yet, we need
> to have these pins in pinctrl as the actual pin are shared with the spifc
> controller. The bootloader on the S905-P200 setup pinmux for the NAND
> controller so we need the kernel to properly deactivate this if necessary.
>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Patch applied.

Yours,
Linus Walleij

[RESEND PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins

[Linus Walleij]

On Tue, Sep 13, 2016 at 5:12 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Add EE domains pins for the NAND flash controller.
> Even tough we have no driver for the NAND flash controller yet, we need
> to have these pins in pinctrl as the actual pin are shared with the spifc
> controller. The bootloader on the S905-P200 setup pinmux for the NAND
> controller so we need the kernel to properly deactivate this if necessary.
>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Patch applied.

Yours,
Linus Walleij