* [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc.
@ 2016-09-23 0:34 Xo Wang
2016-09-23 0:34 ` [PATCH v2 2/2] ARM: dts: aspeed: Add Ingrasys Zaius BMC DTS Xo Wang
2016-09-23 4:46 ` [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc Joel Stanley
0 siblings, 2 replies; 4+ messages in thread
From: Xo Wang @ 2016-09-23 0:34 UTC (permalink / raw)
To: openbmc
Ingrasys designs and manufactures cloud hardware and is part of Foxconn
business group F: http://www.ingrasys.com/
Signed-off-by: Xo Wang <xow@google.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 2c2500d..54e9182 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -130,6 +130,7 @@ iom Iomega Corporation
img Imagination Technologies Ltd.
inforce Inforce Computing
ingenic Ingenic Semiconductor
+ingrasys Ingrasys Technology Inc.
innolux Innolux Corporation
intel Intel Corporation
intercontrol Inter Control Group
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] ARM: dts: aspeed: Add Ingrasys Zaius BMC DTS
2016-09-23 0:34 [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc Xo Wang
@ 2016-09-23 0:34 ` Xo Wang
2016-09-23 4:54 ` Joel Stanley
2016-09-23 4:46 ` [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc Joel Stanley
1 sibling, 1 reply; 4+ messages in thread
From: Xo Wang @ 2016-09-23 0:34 UTC (permalink / raw)
To: openbmc
Zaius is a POWER9 platform announced at OpenPOWER Summit 2016. This adds
basic DTS support for its AST2500 BMC. This includes bringup stage
hardware like flash, UART, and networking.
Additional work is needed to enable GPIOs and route I2C through muxes.
Signed-off-by: Xo Wang <xow@google.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 210 +++++++++++++++++++++++++++++
2 files changed, 211 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 495ca3d..b9541c6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -895,6 +895,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-firestone.dtb \
aspeed-bmc-opp-garrison.dtb \
aspeed-bmc-opp-witherspoon.dtb \
+ aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-facebook-cmm.dtb \
aspeed-ast2500-evb.dtb
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
new file mode 100644
index 0000000..4c4754b
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -0,0 +1,210 @@
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+
+/ {
+ model = "Zaius BMC";
+ compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ ahb {
+ bmc_pnor: fmc@1e620000 {
+ reg = < 0x1e620000 0xc4
+ 0x20000000 0x04000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-fmc";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+ };
+ };
+
+ host_pnor: spi@1e630000 {
+ reg = < 0x1e630000 0xc4
+ 0x30000000 0x04000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-smc";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ label = "pnor";
+ };
+ };
+
+ data_pnor: spi@1e631000 {
+ reg = < 0x1e631000 0xc4
+ 0x38000000 0x00800000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-smc";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ };
+ };
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+
+ /* Power sequencer UCD90160 PMBUS @64h
+ * FRU AT24C64D @50h
+ * RTC PCF8523 @68h
+ * Clock buffer 9DBL04 @6dh
+ */
+};
+
+&i2c1 {
+ status = "disabled";
+
+ /* MUX1 PCA9546A @71h
+ * PCIe 0
+ * PCIe 1
+ * PCIe 2
+ * TPM header
+ */
+};
+
+&i2c2 {
+ status = "disabled";
+
+ /* OCP Mezz Connector A (OOB SMBUS) */
+};
+
+&i2c3 {
+ status = "disabled";
+
+ /* OCP Mezz Connector A (PCIe slot SMBUS) */
+};
+
+&i2c4 {
+ status = "disabled";
+
+ /* MUX1 PCA9546A @71h
+ * PCIe 3
+ * PCIe 4
+ */
+};
+
+
+&i2c5 {
+ status = "disabled";
+
+ /* CPU0 PRM 0.7V */
+ /* CPU0 PRM 1.2V CH03 */
+ /* CPU0 PRM 0.8V */
+ /* CPU0 PRM 1.2V CH47 */
+};
+
+&i2c6 {
+ status = "disabled";
+
+ /* CPU1 PRM 0.7V */
+ /* CPU1 PRM 1.2V CH03 */
+ /* CPU1 PRM 0.8V */
+ /* CPU1 PRM 1.2V CH47 */
+};
+
+&i2c7 {
+ status = "disabled";
+
+ /* MUX PCA9541A (other master: CPU0 PCIe 1)
+ * ADM1272 PMBUS @10h
+ */
+ /* 12V SMPS Q54SH12050NNDH @61h */
+ /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
+ /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
+ /* CPU0 VR ISL68137 0.8V PMBUS @60h */
+ /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
+ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
+};
+
+&i2c8 {
+ status = "disabled";
+
+ /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
+ /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
+ /* CPU1 VR ISL68137 0.8V PMBUS @61h */
+ /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
+ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
+};
+
+
+&i2c9 {
+ status = "disabled";
+
+ /* Fan board */
+};
+
+&i2c10 {
+ status = "disabled";
+};
+
+&i2c11 {
+ status = "disabled";
+
+ /* GPU sideband */
+};
+
+&i2c12 {
+ status = "disabled";
+};
+
+&i2c13 {
+ status = "disabled";
+
+ /* MUX PI3USB102
+ * CPU0 debug
+ * CPU1 debug
+ */
+};
+
+&vuart {
+ status = "okay";
+};
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc.
2016-09-23 0:34 [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc Xo Wang
2016-09-23 0:34 ` [PATCH v2 2/2] ARM: dts: aspeed: Add Ingrasys Zaius BMC DTS Xo Wang
@ 2016-09-23 4:46 ` Joel Stanley
1 sibling, 0 replies; 4+ messages in thread
From: Joel Stanley @ 2016-09-23 4:46 UTC (permalink / raw)
To: Xo Wang; +Cc: OpenBMC Maillist
On Fri, Sep 23, 2016 at 10:04 AM, Xo Wang <xow@google.com> wrote:
> Ingrasys designs and manufactures cloud hardware and is part of Foxconn
> business group F: http://www.ingrasys.com/
Thanks, applied to dev-4.7 as 5df6ef640e58ec87fde655e466f1cbfc4cb68f56.
>
> Signed-off-by: Xo Wang <xow@google.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 2c2500d..54e9182 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -130,6 +130,7 @@ iom Iomega Corporation
> img Imagination Technologies Ltd.
> inforce Inforce Computing
> ingenic Ingenic Semiconductor
> +ingrasys Ingrasys Technology Inc.
> innolux Innolux Corporation
> intel Intel Corporation
> intercontrol Inter Control Group
> --
> 2.8.0.rc3.226.g39d4020
>
> _______________________________________________
> openbmc mailing list
> openbmc@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/openbmc
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] ARM: dts: aspeed: Add Ingrasys Zaius BMC DTS
2016-09-23 0:34 ` [PATCH v2 2/2] ARM: dts: aspeed: Add Ingrasys Zaius BMC DTS Xo Wang
@ 2016-09-23 4:54 ` Joel Stanley
0 siblings, 0 replies; 4+ messages in thread
From: Joel Stanley @ 2016-09-23 4:54 UTC (permalink / raw)
To: Xo Wang; +Cc: OpenBMC Maillist
On Fri, Sep 23, 2016 at 10:04 AM, Xo Wang <xow@google.com> wrote:
> Zaius is a POWER9 platform announced at OpenPOWER Summit 2016. This adds
> basic DTS support for its AST2500 BMC. This includes bringup stage
> hardware like flash, UART, and networking.
>
> Additional work is needed to enable GPIOs and route I2C through muxes.
>
> Signed-off-by: Xo Wang <xow@google.com>
Thanks, applied to dev-4.7 as 31491101bab1f11b01fd880d7d34dd36d26cf8fb.
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 210 +++++++++++++++++++++++++++++
> 2 files changed, 211 insertions(+)
> create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 495ca3d..b9541c6 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -895,6 +895,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
> aspeed-bmc-opp-firestone.dtb \
> aspeed-bmc-opp-garrison.dtb \
> aspeed-bmc-opp-witherspoon.dtb \
> + aspeed-bmc-opp-zaius.dtb \
> aspeed-bmc-facebook-cmm.dtb \
> aspeed-ast2500-evb.dtb
> endif
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> new file mode 100644
> index 0000000..4c4754b
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> @@ -0,0 +1,210 @@
> +/dts-v1/;
> +
> +#include "aspeed-g5.dtsi"
> +
> +/ {
> + model = "Zaius BMC";
> + compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
> +
> + aliases {
> + serial4 = &uart5;
> + };
> +
> + chosen {
> + stdout-path = &uart5;
> + bootargs = "console=ttyS4,115200 earlyprintk";
> + };
> +
> + memory {
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + ahb {
> + bmc_pnor: fmc@1e620000 {
> + reg = < 0x1e620000 0xc4
> + 0x20000000 0x04000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2500-fmc";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor" ;
> +#include "aspeed-bmc-opp-flash-layout.dtsi"
> + };
> + };
> +
> + host_pnor: spi@1e630000 {
> + reg = < 0x1e630000 0xc4
> + 0x30000000 0x04000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2500-smc";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor" ;
> + label = "pnor";
> + };
> + };
> +
> + data_pnor: spi@1e631000 {
> + reg = < 0x1e631000 0xc4
> + 0x38000000 0x00800000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2500-smc";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor" ;
> + };
> + };
> + };
> +};
> +
> +&uart5 {
> + status = "okay";
> +};
> +
> +&mac0 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgmii1_default>;
> + use-ncsi;
> +};
> +
> +&mac1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgmii2_default>;
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + eeprom@50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + pagesize = <32>;
> + };
> +
> + rtc@68 {
> + compatible = "nxp,pcf8523";
> + reg = <0x68>;
> + };
> +
> + /* Power sequencer UCD90160 PMBUS @64h
> + * FRU AT24C64D @50h
> + * RTC PCF8523 @68h
> + * Clock buffer 9DBL04 @6dh
> + */
> +};
> +
> +&i2c1 {
> + status = "disabled";
> +
> + /* MUX1 PCA9546A @71h
> + * PCIe 0
> + * PCIe 1
> + * PCIe 2
> + * TPM header
> + */
> +};
> +
> +&i2c2 {
> + status = "disabled";
> +
> + /* OCP Mezz Connector A (OOB SMBUS) */
> +};
> +
> +&i2c3 {
> + status = "disabled";
> +
> + /* OCP Mezz Connector A (PCIe slot SMBUS) */
> +};
> +
> +&i2c4 {
> + status = "disabled";
> +
> + /* MUX1 PCA9546A @71h
> + * PCIe 3
> + * PCIe 4
> + */
> +};
> +
> +
> +&i2c5 {
> + status = "disabled";
> +
> + /* CPU0 PRM 0.7V */
> + /* CPU0 PRM 1.2V CH03 */
> + /* CPU0 PRM 0.8V */
> + /* CPU0 PRM 1.2V CH47 */
> +};
> +
> +&i2c6 {
> + status = "disabled";
> +
> + /* CPU1 PRM 0.7V */
> + /* CPU1 PRM 1.2V CH03 */
> + /* CPU1 PRM 0.8V */
> + /* CPU1 PRM 1.2V CH47 */
> +};
> +
> +&i2c7 {
> + status = "disabled";
> +
> + /* MUX PCA9541A (other master: CPU0 PCIe 1)
> + * ADM1272 PMBUS @10h
> + */
> + /* 12V SMPS Q54SH12050NNDH @61h */
> + /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
> + /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
> + /* CPU0 VR ISL68137 0.8V PMBUS @60h */
> + /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
> + /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
> +};
> +
> +&i2c8 {
> + status = "disabled";
> +
> + /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
> + /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
> + /* CPU1 VR ISL68137 0.8V PMBUS @61h */
> + /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
> + /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
> +};
> +
> +
> +&i2c9 {
> + status = "disabled";
> +
> + /* Fan board */
> +};
> +
> +&i2c10 {
> + status = "disabled";
> +};
> +
> +&i2c11 {
> + status = "disabled";
> +
> + /* GPU sideband */
> +};
> +
> +&i2c12 {
> + status = "disabled";
> +};
> +
> +&i2c13 {
> + status = "disabled";
> +
> + /* MUX PI3USB102
> + * CPU0 debug
> + * CPU1 debug
> + */
> +};
> +
> +&vuart {
> + status = "okay";
> +};
> --
> 2.8.0.rc3.226.g39d4020
>
> _______________________________________________
> openbmc mailing list
> openbmc@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/openbmc
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-09-23 4:54 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2016-09-23 0:34 [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc Xo Wang
2016-09-23 0:34 ` [PATCH v2 2/2] ARM: dts: aspeed: Add Ingrasys Zaius BMC DTS Xo Wang
2016-09-23 4:54 ` Joel Stanley
2016-09-23 4:46 ` [PATCH v2 1/2] dt-bindings: Add Ingrasys Technology, Inc Joel Stanley
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