[PATCH 0/5] arm64: dts: hisilicon: Hip06 fix and support Hip07 D05 board

[PATCH 0/5] arm64: dts: hisilicon: Hip06 fix and support Hip07 D05 board

[Kefeng Wang]

1) DTs
- Fix Hip06 ehci/ohci interrupt pin number.
- Add initial support for Hip07 D05 board.

2) PL011
- The sbsa uart is used on Hip07 SoC, the interrupt is connected to mbigen,
  but the uart probe(arch_init) is earlier than mbigen(module_init), so
  don't complain on -EPROBE_DEFER when no irq.
- Add earlycon support for SBSA UART.

Kefeng Wang (5):
  arm64: dts: hip06: Correct hardware pin number of usb node
  Documentation: arm64: Add Hisilicon Hip07 D05 dts binding
  arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
  tty: amba-pl011: Don't complain on -EPROBE_DEFER when no irq
  tty: amba-pl011: Add earlycon support for SBSA UART

 .../bindings/arm/hisilicon/hisilicon.txt           |    4 +
 arch/arm64/boot/dts/hisilicon/Makefile             |    1 +
 arch/arm64/boot/dts/hisilicon/hip06.dtsi           |    4 +-
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts        |   66 ++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi           | 1059 ++++++++++++++++++++
 drivers/tty/serial/amba-pl011.c                    |    4 +-
 6 files changed, 1135 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07-d05.dts
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07.dtsi

-- 
1.7.12.4

[PATCH 0/5] arm64: dts: hisilicon: Hip06 fix and support Hip07 D05 board

[Kefeng Wang]

1) DTs
- Fix Hip06 ehci/ohci interrupt pin number.
- Add initial support for Hip07 D05 board.

2) PL011
- The sbsa uart is used on Hip07 SoC, the interrupt is connected to mbigen,
  but the uart probe(arch_init) is earlier than mbigen(module_init), so
  don't complain on -EPROBE_DEFER when no irq.
- Add earlycon support for SBSA UART.

Kefeng Wang (5):
  arm64: dts: hip06: Correct hardware pin number of usb node
  Documentation: arm64: Add Hisilicon Hip07 D05 dts binding
  arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
  tty: amba-pl011: Don't complain on -EPROBE_DEFER when no irq
  tty: amba-pl011: Add earlycon support for SBSA UART

 .../bindings/arm/hisilicon/hisilicon.txt           |    4 +
 arch/arm64/boot/dts/hisilicon/Makefile             |    1 +
 arch/arm64/boot/dts/hisilicon/hip06.dtsi           |    4 +-
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts        |   66 ++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi           | 1059 ++++++++++++++++++++
 drivers/tty/serial/amba-pl011.c                    |    4 +-
 6 files changed, 1135 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07-d05.dts
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07.dtsi

-- 
1.7.12.4

[PATCH 1/5] arm64: dts: hip06: Correct hardware pin number of usb node

[Kefeng Wang]

The ohci/ehci hardware pin number should be 640/641, correct them.

Fixes: commit aa8d3e74f54d ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board")
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 66b1bbf..be76f7d 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -322,7 +322,7 @@
 			compatible = "generic-ohci";
 			reg = <0x0 0xa7030000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
-			interrupts = <64 4>;
+			interrupts = <640 4>;
 			dma-coherent;
 			status = "disabled";
 		};
@@ -331,7 +331,7 @@
 			compatible = "generic-ehci";
 			reg = <0x0 0xa7020000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
-			interrupts = <65 4>;
+			interrupts = <641 4>;
 			dma-coherent;
 			status = "disabled";
 		};
-- 
1.7.12.4

[PATCH 1/5] arm64: dts: hip06: Correct hardware pin number of usb node

[Kefeng Wang]

The ohci/ehci hardware pin number should be 640/641, correct them.

Fixes: commit aa8d3e74f54d ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board")
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 66b1bbf..be76f7d 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -322,7 +322,7 @@
 			compatible = "generic-ohci";
 			reg = <0x0 0xa7030000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
-			interrupts = <64 4>;
+			interrupts = <640 4>;
 			dma-coherent;
 			status = "disabled";
 		};
@@ -331,7 +331,7 @@
 			compatible = "generic-ehci";
 			reg = <0x0 0xa7020000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
-			interrupts = <65 4>;
+			interrupts = <641 4>;
 			dma-coherent;
 			status = "disabled";
 		};
-- 
1.7.12.4

[PATCH 2/5] Documentation: arm64: Add Hisilicon Hip07 D05 dts binding

[Kefeng Wang]

This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip07 D05 board.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3f81575..7df79a7 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -28,6 +28,10 @@ HiP06 D03 Board
 Required root node properties:
 	- compatible = "hisilicon,hip06-d03";
 
+HiP07 D05 Board
+Required root node properties:
+	- compatible = "hisilicon,hip07-d05";
+
 Hisilicon system controller
 
 Required properties:
-- 
1.7.12.4

[PATCH 2/5] Documentation: arm64: Add Hisilicon Hip07 D05 dts binding

[Kefeng Wang]

This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip07 D05 board.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3f81575..7df79a7 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -28,6 +28,10 @@ HiP06 D03 Board
 Required root node properties:
 	- compatible = "hisilicon,hip06-d03";
 
+HiP07 D05 Board
+Required root node properties:
+	- compatible = "hisilicon,hip07-d05";
+
 Hisilicon system controller
 
 Required properties:
-- 
1.7.12.4

[PATCH 3/5] arm64: dts: hisilicon: Add initial dts for Hip07 D05 board

[Kefeng Wang]

Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.

Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/Makefile      |    1 +
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts |   66 ++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 1059 +++++++++++++++++++++++++++
 3 files changed, 1126 insertions(+)
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07-d05.dts
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07.dtsi

diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index d5f43a0..c8b8f80 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
 dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
 dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
+dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
 
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
new file mode 100644
index 0000000..e058442
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
@@ -0,0 +1,66 @@
+/**
+ * dts file for Hisilicon D05 Development Board
+ *
+ * Copyright (C) 2016 Hisilicon Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include "hip07.dtsi"
+
+/ {
+	model = "Hisilicon Hip07 D05 Development Board";
+	compatible = "hisilicon,hip07-d05";
+
+	/* the mem node will be updated by UEFI. */
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x0 0x40000000>;
+		numa-node-id = <0>;
+	};
+
+	distance-map {
+		compatible = "numa-distance-map-v1";
+		distance-matrix = <0 0 10>,
+				  <0 1 15>,
+				  <0 2 20>,
+				  <0 3 25>,
+				  <1 0 15>,
+				  <1 1 10>,
+				  <1 2 25>,
+				  <1 3 30>,
+				  <2 0 20>,
+				  <2 1 25>,
+				  <2 2 10>,
+				  <2 3 15>,
+				  <3 0 25>,
+				  <3 1 30>,
+				  <3 2 15>,
+				  <3 3 10>;
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "ok";
+};
+
+&usb_ohci {
+	status = "ok";
+};
+
+&usb_ehci {
+	status = "ok";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
new file mode 100644
index 0000000..5144eb1
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -0,0 +1,1059 @@
+/**
+ * dts file for Hisilicon D05 Development Board
+ *
+ * Copyright (C) 2016 Hisilicon Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "hisilicon,hip07-d05";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&cpu8>;
+				};
+				core1 {
+					cpu = <&cpu9>;
+				};
+				core2 {
+					cpu = <&cpu10>;
+				};
+				core3 {
+					cpu = <&cpu11>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&cpu12>;
+				};
+				core1 {
+					cpu = <&cpu13>;
+				};
+				core2 {
+					cpu = <&cpu14>;
+				};
+				core3 {
+					cpu = <&cpu15>;
+				};
+			};
+
+			cluster4 {
+				core0 {
+					cpu = <&cpu16>;
+				};
+				core1 {
+					cpu = <&cpu17>;
+				};
+				core2 {
+					cpu = <&cpu18>;
+				};
+				core3 {
+					cpu = <&cpu19>;
+				};
+			};
+
+			cluster5 {
+				core0 {
+					cpu = <&cpu20>;
+				};
+				core1 {
+					cpu = <&cpu21>;
+				};
+				core2 {
+					cpu = <&cpu22>;
+				};
+				core3 {
+					cpu = <&cpu23>;
+				};
+			};
+
+			cluster6 {
+				core0 {
+					cpu = <&cpu24>;
+				};
+				core1 {
+					cpu = <&cpu25>;
+				};
+				core2 {
+					cpu = <&cpu26>;
+				};
+				core3 {
+					cpu = <&cpu27>;
+				};
+			};
+
+			cluster7 {
+				core0 {
+					cpu = <&cpu28>;
+				};
+				core1 {
+					cpu = <&cpu29>;
+				};
+				core2 {
+					cpu = <&cpu30>;
+				};
+				core3 {
+					cpu = <&cpu31>;
+				};
+			};
+
+			cluster8 {
+				core0 {
+					cpu = <&cpu32>;
+				};
+				core1 {
+					cpu = <&cpu33>;
+				};
+				core2 {
+					cpu = <&cpu34>;
+				};
+				core3 {
+					cpu = <&cpu35>;
+				};
+			};
+
+			cluster9 {
+				core0 {
+					cpu = <&cpu36>;
+				};
+				core1 {
+					cpu = <&cpu37>;
+				};
+				core2 {
+					cpu = <&cpu38>;
+				};
+				core3 {
+					cpu = <&cpu39>;
+				};
+			};
+
+			cluster10 {
+				core0 {
+					cpu = <&cpu40>;
+				};
+				core1 {
+					cpu = <&cpu41>;
+				};
+				core2 {
+					cpu = <&cpu42>;
+				};
+				core3 {
+					cpu = <&cpu43>;
+				};
+			};
+
+			cluster11 {
+				core0 {
+					cpu = <&cpu44>;
+				};
+				core1 {
+					cpu = <&cpu45>;
+				};
+				core2 {
+					cpu = <&cpu46>;
+				};
+				core3 {
+					cpu = <&cpu47>;
+				};
+			};
+
+			cluster12 {
+				core0 {
+					cpu = <&cpu48>;
+				};
+				core1 {
+					cpu = <&cpu49>;
+				};
+				core2 {
+					cpu = <&cpu50>;
+				};
+				core3 {
+					cpu = <&cpu51>;
+				};
+			};
+
+			cluster13 {
+				core0 {
+					cpu = <&cpu52>;
+				};
+				core1 {
+					cpu = <&cpu53>;
+				};
+				core2 {
+					cpu = <&cpu54>;
+				};
+				core3 {
+					cpu = <&cpu55>;
+				};
+			};
+
+			cluster14 {
+				core0 {
+					cpu = <&cpu56>;
+				};
+				core1 {
+					cpu = <&cpu57>;
+				};
+				core2 {
+					cpu = <&cpu58>;
+				};
+				core3 {
+					cpu = <&cpu59>;
+				};
+			};
+
+			cluster15 {
+				core0 {
+					cpu = <&cpu60>;
+				};
+				core1 {
+					cpu = <&cpu61>;
+				};
+				core2 {
+					cpu = <&cpu62>;
+				};
+				core3 {
+					cpu = <&cpu63>;
+				};
+			};
+		};
+
+		cpu0: cpu@10000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu1: cpu@10001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu2: cpu@10002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu3: cpu@10003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu4: cpu@10100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu5: cpu@10101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu6: cpu@10102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu7: cpu@10103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu8: cpu@10200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu9: cpu@10201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu10: cpu@10202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu11: cpu@10203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu12: cpu@10300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu13: cpu@10301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu14: cpu@10302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu15: cpu@10303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu16: cpu@30000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu17: cpu@30001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu18: cpu@30002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu19: cpu@30003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu20: cpu@30100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu21: cpu@30101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu22: cpu@30102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu23: cpu@30103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu24: cpu@30200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu25: cpu@30201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu26: cpu@30202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu27: cpu@30203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu28: cpu@30300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu29: cpu@30301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu30: cpu@30302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu31: cpu@30303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu32: cpu@50000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu33: cpu@50001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu34: cpu@50002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu35: cpu@50003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu36: cpu@50100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu37: cpu@50101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu38: cpu@50102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu39: cpu@50103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu40: cpu@50200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu41: cpu@50201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu42: cpu@50202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu43: cpu@50203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu44: cpu@50300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu45: cpu@50301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu46: cpu@50302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu47: cpu@50303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu48: cpu@70000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu49: cpu@70001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu50: cpu@70002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu51: cpu@70003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu52: cpu@70100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu53: cpu@70101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu54: cpu@70102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu55: cpu@70103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu56: cpu@70200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu57: cpu@70201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu58: cpu@70202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu59: cpu@70203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu60: cpu@70300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu61: cpu@70301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu62: cpu@70302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu63: cpu@70303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cluster0_l2: l2-cache0 {
+			compatible = "cache";
+		};
+
+		cluster1_l2: l2-cache1 {
+			compatible = "cache";
+		};
+
+		cluster2_l2: l2-cache2 {
+			compatible = "cache";
+		};
+
+		cluster3_l2: l2-cache3 {
+			compatible = "cache";
+		};
+
+		cluster4_l2: l2-cache4 {
+			compatible = "cache";
+		};
+
+		cluster5_l2: l2-cache5 {
+			compatible = "cache";
+		};
+
+		cluster6_l2: l2-cache6 {
+			compatible = "cache";
+		};
+
+		cluster7_l2: l2-cache7 {
+			compatible = "cache";
+		};
+
+		cluster8_l2: l2-cache8 {
+			compatible = "cache";
+		};
+
+		cluster9_l2: l2-cache9 {
+			compatible = "cache";
+		};
+
+		cluster10_l2: l2-cache10 {
+			compatible = "cache";
+		};
+
+		cluster11_l2: l2-cache11 {
+			compatible = "cache";
+		};
+
+		cluster12_l2: l2-cache12 {
+			compatible = "cache";
+		};
+
+		cluster13_l2: l2-cache13 {
+			compatible = "cache";
+		};
+
+		cluster14_l2: l2-cache14 {
+			compatible = "cache";
+		};
+
+		cluster15_l2: l2-cache15 {
+			compatible = "cache";
+		};
+	};
+
+	gic: interrupt-controller@4d000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+		#redistributor-regions = <4>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x0 0x4d000000 0x0 0x10000>,	/* GICD */
+		      <0x0 0x4d100000 0x0 0x400000>,	/* p0 GICR node 0 */
+		      <0x0 0x6d100000 0x0 0x400000>,	/* p0 GICR node 1 */
+		      <0x400 0x4d100000 0x0 0x400000>,	/* p1 GICR node 2 */
+		      <0x400 0x6d100000 0x0 0x400000>,	/* p1 GICR node 3 */
+		      <0x0 0xfe000000 0x0 0x10000>,	/* GICC */
+		      <0x0 0xfe010000 0x0 0x10000>,	/* GICH */
+		      <0x0 0xfe020000 0x0 0x10000>;	/* GICV */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		p0_its_peri_a: interrupt-controller@4c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0x4c000000 0x0 0x40000>;
+		};
+
+		p0_its_peri_b: interrupt-controller@6c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0x6c000000 0x0 0x40000>;
+		};
+
+		p0_its_dsa_a: interrupt-controller@c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0xc6000000 0x0 0x40000>;
+		};
+
+		p0_its_dsa_b: interrupt-controller@8,c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x8 0xc6000000 0x0 0x40000>;
+		};
+
+		p1_its_peri_a: interrupt-controller@400,4c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x400 0x4c000000 0x0 0x40000>;
+		};
+
+		p1_its_peri_b: interrupt-controller@400,6c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x400 0x6c000000 0x0 0x40000>;
+		};
+
+		p1_its_dsa_a: interrupt-controller@400,c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x400 0xc6000000 0x0 0x40000>;
+		};
+
+		p1_its_dsa_b: interrupt-controller@408,c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x408 0xc6000000 0x0 0x40000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a72-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	p0_mbigen_peri_b: interrupt-controller@60080000 {
+		compatible = "hisilicon,mbigen-v2";
+		reg = <0x0 0x60080000 0x0 0x10000>;
+
+		mbigen_uart: uart_intc {
+			msi-parent = <&p0_its_peri_b 0x120c7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			num-pins = <1>;
+		};
+	};
+
+	p0_mbigen_pcie_a: interrupt-controller@a0080000 {
+		compatible = "hisilicon,mbigen-v2";
+		reg = <0x0 0xa0080000 0x0 0x10000>;
+
+		mbigen_usb: intc_usb {
+			msi-parent = <&p0_its_dsa_a 0x40080>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			num-pins = <2>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		uart0: uart@602b0000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0x0 0x602b0000 0x0 0x1000>;
+			interrupt-parent = <&mbigen_uart>;
+			interrupts = <807 4>;
+			current-speed = <115200>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		usb_ohci: ohci@a7030000 {
+			compatible = "generic-ohci";
+			reg = <0x0 0xa7030000 0x0 0x10000>;
+			interrupt-parent = <&mbigen_usb>;
+			interrupts = <640 4>;
+			dma-coherent;
+			status = "disabled";
+		};
+
+		usb_ehci: ehci@a7020000 {
+			compatible = "generic-ehci";
+			reg = <0x0 0xa7020000 0x0 0x10000>;
+			interrupt-parent = <&mbigen_usb>;
+			interrupts = <641 4>;
+			dma-coherent;
+			status = "disabled";
+		};
+	};
+};
-- 
1.7.12.4

[PATCH 3/5] arm64: dts: hisilicon: Add initial dts for Hip07 D05 board

[Kefeng Wang]

Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.

Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/Makefile      |    1 +
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts |   66 ++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 1059 +++++++++++++++++++++++++++
 3 files changed, 1126 insertions(+)
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07-d05.dts
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip07.dtsi

diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index d5f43a0..c8b8f80 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
 dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
 dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
+dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
 
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
new file mode 100644
index 0000000..e058442
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
@@ -0,0 +1,66 @@
+/**
+ * dts file for Hisilicon D05 Development Board
+ *
+ * Copyright (C) 2016 Hisilicon Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include "hip07.dtsi"
+
+/ {
+	model = "Hisilicon Hip07 D05 Development Board";
+	compatible = "hisilicon,hip07-d05";
+
+	/* the mem node will be updated by UEFI. */
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x0 0x40000000>;
+		numa-node-id = <0>;
+	};
+
+	distance-map {
+		compatible = "numa-distance-map-v1";
+		distance-matrix = <0 0 10>,
+				  <0 1 15>,
+				  <0 2 20>,
+				  <0 3 25>,
+				  <1 0 15>,
+				  <1 1 10>,
+				  <1 2 25>,
+				  <1 3 30>,
+				  <2 0 20>,
+				  <2 1 25>,
+				  <2 2 10>,
+				  <2 3 15>,
+				  <3 0 25>,
+				  <3 1 30>,
+				  <3 2 15>,
+				  <3 3 10>;
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "ok";
+};
+
+&usb_ohci {
+	status = "ok";
+};
+
+&usb_ehci {
+	status = "ok";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
new file mode 100644
index 0000000..5144eb1
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -0,0 +1,1059 @@
+/**
+ * dts file for Hisilicon D05 Development Board
+ *
+ * Copyright (C) 2016 Hisilicon Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "hisilicon,hip07-d05";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&cpu8>;
+				};
+				core1 {
+					cpu = <&cpu9>;
+				};
+				core2 {
+					cpu = <&cpu10>;
+				};
+				core3 {
+					cpu = <&cpu11>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&cpu12>;
+				};
+				core1 {
+					cpu = <&cpu13>;
+				};
+				core2 {
+					cpu = <&cpu14>;
+				};
+				core3 {
+					cpu = <&cpu15>;
+				};
+			};
+
+			cluster4 {
+				core0 {
+					cpu = <&cpu16>;
+				};
+				core1 {
+					cpu = <&cpu17>;
+				};
+				core2 {
+					cpu = <&cpu18>;
+				};
+				core3 {
+					cpu = <&cpu19>;
+				};
+			};
+
+			cluster5 {
+				core0 {
+					cpu = <&cpu20>;
+				};
+				core1 {
+					cpu = <&cpu21>;
+				};
+				core2 {
+					cpu = <&cpu22>;
+				};
+				core3 {
+					cpu = <&cpu23>;
+				};
+			};
+
+			cluster6 {
+				core0 {
+					cpu = <&cpu24>;
+				};
+				core1 {
+					cpu = <&cpu25>;
+				};
+				core2 {
+					cpu = <&cpu26>;
+				};
+				core3 {
+					cpu = <&cpu27>;
+				};
+			};
+
+			cluster7 {
+				core0 {
+					cpu = <&cpu28>;
+				};
+				core1 {
+					cpu = <&cpu29>;
+				};
+				core2 {
+					cpu = <&cpu30>;
+				};
+				core3 {
+					cpu = <&cpu31>;
+				};
+			};
+
+			cluster8 {
+				core0 {
+					cpu = <&cpu32>;
+				};
+				core1 {
+					cpu = <&cpu33>;
+				};
+				core2 {
+					cpu = <&cpu34>;
+				};
+				core3 {
+					cpu = <&cpu35>;
+				};
+			};
+
+			cluster9 {
+				core0 {
+					cpu = <&cpu36>;
+				};
+				core1 {
+					cpu = <&cpu37>;
+				};
+				core2 {
+					cpu = <&cpu38>;
+				};
+				core3 {
+					cpu = <&cpu39>;
+				};
+			};
+
+			cluster10 {
+				core0 {
+					cpu = <&cpu40>;
+				};
+				core1 {
+					cpu = <&cpu41>;
+				};
+				core2 {
+					cpu = <&cpu42>;
+				};
+				core3 {
+					cpu = <&cpu43>;
+				};
+			};
+
+			cluster11 {
+				core0 {
+					cpu = <&cpu44>;
+				};
+				core1 {
+					cpu = <&cpu45>;
+				};
+				core2 {
+					cpu = <&cpu46>;
+				};
+				core3 {
+					cpu = <&cpu47>;
+				};
+			};
+
+			cluster12 {
+				core0 {
+					cpu = <&cpu48>;
+				};
+				core1 {
+					cpu = <&cpu49>;
+				};
+				core2 {
+					cpu = <&cpu50>;
+				};
+				core3 {
+					cpu = <&cpu51>;
+				};
+			};
+
+			cluster13 {
+				core0 {
+					cpu = <&cpu52>;
+				};
+				core1 {
+					cpu = <&cpu53>;
+				};
+				core2 {
+					cpu = <&cpu54>;
+				};
+				core3 {
+					cpu = <&cpu55>;
+				};
+			};
+
+			cluster14 {
+				core0 {
+					cpu = <&cpu56>;
+				};
+				core1 {
+					cpu = <&cpu57>;
+				};
+				core2 {
+					cpu = <&cpu58>;
+				};
+				core3 {
+					cpu = <&cpu59>;
+				};
+			};
+
+			cluster15 {
+				core0 {
+					cpu = <&cpu60>;
+				};
+				core1 {
+					cpu = <&cpu61>;
+				};
+				core2 {
+					cpu = <&cpu62>;
+				};
+				core3 {
+					cpu = <&cpu63>;
+				};
+			};
+		};
+
+		cpu0: cpu at 10000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu1: cpu at 10001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu2: cpu at 10002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu3: cpu at 10003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu4: cpu at 10100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu5: cpu at 10101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu6: cpu at 10102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu7: cpu at 10103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu8: cpu at 10200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu9: cpu at 10201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu10: cpu at 10202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu11: cpu at 10203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu12: cpu at 10300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu13: cpu at 10301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu14: cpu at 10302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu15: cpu at 10303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x10303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+			numa-node-id = <0>;
+		};
+
+		cpu16: cpu at 30000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu17: cpu at 30001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu18: cpu at 30002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu19: cpu at 30003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster4_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu20: cpu at 30100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu21: cpu at 30101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu22: cpu at 30102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu23: cpu at 30103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster5_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu24: cpu at 30200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu25: cpu at 30201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu26: cpu at 30202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu27: cpu at 30203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster6_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu28: cpu at 30300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu29: cpu at 30301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu30: cpu at 30302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu31: cpu at 30303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x30303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster7_l2>;
+			numa-node-id = <1>;
+		};
+
+		cpu32: cpu at 50000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu33: cpu at 50001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu34: cpu at 50002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu35: cpu at 50003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster8_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu36: cpu at 50100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu37: cpu at 50101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu38: cpu at 50102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu39: cpu at 50103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster9_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu40: cpu at 50200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu41: cpu at 50201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu42: cpu at 50202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu43: cpu at 50203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster10_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu44: cpu at 50300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu45: cpu at 50301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu46: cpu at 50302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu47: cpu at 50303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x50303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster11_l2>;
+			numa-node-id = <2>;
+		};
+
+		cpu48: cpu at 70000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70000>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu49: cpu at 70001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70001>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu50: cpu at 70002 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70002>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu51: cpu at 70003 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70003>;
+			enable-method = "psci";
+			next-level-cache = <&cluster12_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu52: cpu at 70100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70100>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu53: cpu at 70101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70101>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu54: cpu at 70102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70102>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu55: cpu at 70103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70103>;
+			enable-method = "psci";
+			next-level-cache = <&cluster13_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu56: cpu at 70200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70200>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu57: cpu at 70201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70201>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu58: cpu at 70202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70202>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu59: cpu at 70203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70203>;
+			enable-method = "psci";
+			next-level-cache = <&cluster14_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu60: cpu at 70300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70300>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu61: cpu at 70301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70301>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu62: cpu at 70302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70302>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cpu63: cpu at 70303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x70303>;
+			enable-method = "psci";
+			next-level-cache = <&cluster15_l2>;
+			numa-node-id = <3>;
+		};
+
+		cluster0_l2: l2-cache0 {
+			compatible = "cache";
+		};
+
+		cluster1_l2: l2-cache1 {
+			compatible = "cache";
+		};
+
+		cluster2_l2: l2-cache2 {
+			compatible = "cache";
+		};
+
+		cluster3_l2: l2-cache3 {
+			compatible = "cache";
+		};
+
+		cluster4_l2: l2-cache4 {
+			compatible = "cache";
+		};
+
+		cluster5_l2: l2-cache5 {
+			compatible = "cache";
+		};
+
+		cluster6_l2: l2-cache6 {
+			compatible = "cache";
+		};
+
+		cluster7_l2: l2-cache7 {
+			compatible = "cache";
+		};
+
+		cluster8_l2: l2-cache8 {
+			compatible = "cache";
+		};
+
+		cluster9_l2: l2-cache9 {
+			compatible = "cache";
+		};
+
+		cluster10_l2: l2-cache10 {
+			compatible = "cache";
+		};
+
+		cluster11_l2: l2-cache11 {
+			compatible = "cache";
+		};
+
+		cluster12_l2: l2-cache12 {
+			compatible = "cache";
+		};
+
+		cluster13_l2: l2-cache13 {
+			compatible = "cache";
+		};
+
+		cluster14_l2: l2-cache14 {
+			compatible = "cache";
+		};
+
+		cluster15_l2: l2-cache15 {
+			compatible = "cache";
+		};
+	};
+
+	gic: interrupt-controller at 4d000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+		#redistributor-regions = <4>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x0 0x4d000000 0x0 0x10000>,	/* GICD */
+		      <0x0 0x4d100000 0x0 0x400000>,	/* p0 GICR node 0 */
+		      <0x0 0x6d100000 0x0 0x400000>,	/* p0 GICR node 1 */
+		      <0x400 0x4d100000 0x0 0x400000>,	/* p1 GICR node 2 */
+		      <0x400 0x6d100000 0x0 0x400000>,	/* p1 GICR node 3 */
+		      <0x0 0xfe000000 0x0 0x10000>,	/* GICC */
+		      <0x0 0xfe010000 0x0 0x10000>,	/* GICH */
+		      <0x0 0xfe020000 0x0 0x10000>;	/* GICV */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		p0_its_peri_a: interrupt-controller at 4c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0x4c000000 0x0 0x40000>;
+		};
+
+		p0_its_peri_b: interrupt-controller at 6c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0x6c000000 0x0 0x40000>;
+		};
+
+		p0_its_dsa_a: interrupt-controller at c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0xc6000000 0x0 0x40000>;
+		};
+
+		p0_its_dsa_b: interrupt-controller at 8,c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x8 0xc6000000 0x0 0x40000>;
+		};
+
+		p1_its_peri_a: interrupt-controller at 400,4c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x400 0x4c000000 0x0 0x40000>;
+		};
+
+		p1_its_peri_b: interrupt-controller at 400,6c000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x400 0x6c000000 0x0 0x40000>;
+		};
+
+		p1_its_dsa_a: interrupt-controller at 400,c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x400 0xc6000000 0x0 0x40000>;
+		};
+
+		p1_its_dsa_b: interrupt-controller at 408,c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x408 0xc6000000 0x0 0x40000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a72-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	p0_mbigen_peri_b: interrupt-controller at 60080000 {
+		compatible = "hisilicon,mbigen-v2";
+		reg = <0x0 0x60080000 0x0 0x10000>;
+
+		mbigen_uart: uart_intc {
+			msi-parent = <&p0_its_peri_b 0x120c7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			num-pins = <1>;
+		};
+	};
+
+	p0_mbigen_pcie_a: interrupt-controller at a0080000 {
+		compatible = "hisilicon,mbigen-v2";
+		reg = <0x0 0xa0080000 0x0 0x10000>;
+
+		mbigen_usb: intc_usb {
+			msi-parent = <&p0_its_dsa_a 0x40080>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			num-pins = <2>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		uart0: uart at 602b0000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0x0 0x602b0000 0x0 0x1000>;
+			interrupt-parent = <&mbigen_uart>;
+			interrupts = <807 4>;
+			current-speed = <115200>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		usb_ohci: ohci at a7030000 {
+			compatible = "generic-ohci";
+			reg = <0x0 0xa7030000 0x0 0x10000>;
+			interrupt-parent = <&mbigen_usb>;
+			interrupts = <640 4>;
+			dma-coherent;
+			status = "disabled";
+		};
+
+		usb_ehci: ehci at a7020000 {
+			compatible = "generic-ehci";
+			reg = <0x0 0xa7020000 0x0 0x10000>;
+			interrupt-parent = <&mbigen_usb>;
+			interrupts = <641 4>;
+			dma-coherent;
+			status = "disabled";
+		};
+	};
+};
-- 
1.7.12.4

[PATCH 4/5] tty: amba-pl011: Don't complain on -EPROBE_DEFER when no irq

[Kefeng Wang]

Don't complain on -EPROBE_DEFER when attempting to get the irq.
the driver probe will be retried later.

Cc: Russell King <linux@armlinux.org.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/tty/serial/amba-pl011.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 8a9e213..7d9b291 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2555,7 +2555,8 @@ static int sbsa_uart_probe(struct platform_device *pdev)
 
 	ret = platform_get_irq(pdev, 0);
 	if (ret < 0) {
-		dev_err(&pdev->dev, "cannot obtain irq\n");
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "cannot obtain irq\n");
 		return ret;
 	}
 	uap->port.irq	= ret;
-- 
1.7.12.4

[PATCH 4/5] tty: amba-pl011: Don't complain on -EPROBE_DEFER when no irq

[Kefeng Wang]

Don't complain on -EPROBE_DEFER when attempting to get the irq.
the driver probe will be retried later.

Cc: Russell King <linux@armlinux.org.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/tty/serial/amba-pl011.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 8a9e213..7d9b291 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2555,7 +2555,8 @@ static int sbsa_uart_probe(struct platform_device *pdev)
 
 	ret = platform_get_irq(pdev, 0);
 	if (ret < 0) {
-		dev_err(&pdev->dev, "cannot obtain irq\n");
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "cannot obtain irq\n");
 		return ret;
 	}
 	uap->port.irq	= ret;
-- 
1.7.12.4

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

Declare an OF early console for SBSA UART so that the early console device
can be specified via the "stdout-path" property in device-tree.

Cc: Russell King <linux@armlinux.org.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/tty/serial/amba-pl011.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 7d9b291..3688d3b 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
 	return 0;
 }
 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
+OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
 
 #else
 #define AMBA_CONSOLE	NULL
-- 
1.7.12.4

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

Declare an OF early console for SBSA UART so that the early console device
can be specified via the "stdout-path" property in device-tree.

Cc: Russell King <linux@armlinux.org.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/tty/serial/amba-pl011.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 7d9b291..3688d3b 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
 	return 0;
 }
 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
+OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
 
 #else
 #define AMBA_CONSOLE	NULL
-- 
1.7.12.4

Re: [PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Greg Kroah-Hartman]

On Sat, Sep 24, 2016 at 05:14:25PM +0800, Kefeng Wang wrote:
> Declare an OF early console for SBSA UART so that the early console device
> can be specified via the "stdout-path" property in device-tree.
> 
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  drivers/tty/serial/amba-pl011.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index 7d9b291..3688d3b 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
>  	return 0;
>  }
>  OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
> +OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);

Why do you need another option for the same thing?

confused,

greg k-h

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Greg Kroah-Hartman]

On Sat, Sep 24, 2016 at 05:14:25PM +0800, Kefeng Wang wrote:
> Declare an OF early console for SBSA UART so that the early console device
> can be specified via the "stdout-path" property in device-tree.
> 
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  drivers/tty/serial/amba-pl011.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index 7d9b291..3688d3b 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
>  	return 0;
>  }
>  OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
> +OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);

Why do you need another option for the same thing?

confused,

greg k-h

Re: [PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

On 2016/9/27 18:57, Greg Kroah-Hartman wrote:
> On Sat, Sep 24, 2016 at 05:14:25PM +0800, Kefeng Wang wrote:
>> Declare an OF early console for SBSA UART so that the early console device
>> can be specified via the "stdout-path" property in device-tree.
>>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>>  drivers/tty/serial/amba-pl011.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
>> index 7d9b291..3688d3b 100644
>> --- a/drivers/tty/serial/amba-pl011.c
>> +++ b/drivers/tty/serial/amba-pl011.c
>> @@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
>>  	return 0;
>>  }
>>  OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
>> +OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
> 
> Why do you need another option for the same thing?


It is used to support earlycon(without option) for sbsa-uart in bootargs.

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon"
	};

	uart0: uart@602b0000 {
		compatible = "arm,sbsa-uart";
		reg = <0x0 0x602b0000 0x0 0x1000>;
		...
	};

We setup a unique struct with compatible name by OF_EARLYCON_DECLARE,
#define OF_EARLYCON_DECLARE(_name, compat, fn)				\
	static const struct earlycon_id __UNIQUE_ID(__earlycon_##_name)	\
	     __used __section(__earlycon_table)				\
		= { .name = __stringify(_name),				\
		    .compatible = compat,				\
		    .setup = fn  }

if without this patch(see drivers/of/fdt.c),

early_init_dt_scan_chosen_serial()
 - for (match = __earlycon_table; match < __earlycon_table_end; match++)
  -- if (fdt_node_check_compatible(fdt, offset, match->compatible))
	countinue;
  -- of_setup_earlycon(match, offset, options); // will never touch here.

Thanks,
Kefeng

> 
> confused,
> 
> greg k-h
> 
> .
> 

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

On 2016/9/27 18:57, Greg Kroah-Hartman wrote:
> On Sat, Sep 24, 2016 at 05:14:25PM +0800, Kefeng Wang wrote:
>> Declare an OF early console for SBSA UART so that the early console device
>> can be specified via the "stdout-path" property in device-tree.
>>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>>  drivers/tty/serial/amba-pl011.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
>> index 7d9b291..3688d3b 100644
>> --- a/drivers/tty/serial/amba-pl011.c
>> +++ b/drivers/tty/serial/amba-pl011.c
>> @@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
>>  	return 0;
>>  }
>>  OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
>> +OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
> 
> Why do you need another option for the same thing?


It is used to support earlycon(without option) for sbsa-uart in bootargs.

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon"
	};

	uart0: uart at 602b0000 {
		compatible = "arm,sbsa-uart";
		reg = <0x0 0x602b0000 0x0 0x1000>;
		...
	};

We setup a unique struct with compatible name by OF_EARLYCON_DECLARE,
#define OF_EARLYCON_DECLARE(_name, compat, fn)				\
	static const struct earlycon_id __UNIQUE_ID(__earlycon_##_name)	\
	     __used __section(__earlycon_table)				\
		= { .name = __stringify(_name),				\
		    .compatible = compat,				\
		    .setup = fn  }

if without this patch(see drivers/of/fdt.c),

early_init_dt_scan_chosen_serial()
 - for (match = __earlycon_table; match < __earlycon_table_end; match++)
  -- if (fdt_node_check_compatible(fdt, offset, match->compatible))
	countinue;
  -- of_setup_earlycon(match, offset, options); // will never touch here.

Thanks,
Kefeng

> 
> confused,
> 
> greg k-h
> 
> .
> 

[PATCH] arm64: dts: hip06: Fix no reg property warning

[Kefeng Wang]

Warning (unit_address_vs_reg): Node /soc/ethernet at 4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/ethernet at 5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/ethernet at 0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/ethernet at 1 has a unit name, but no reg property

Fix warning when build with W=1.

Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index b548763..f66c51b 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -508,7 +508,7 @@
 			};
 		};
 
-		eth0: ethernet at 4{
+		eth0: ethernet-4{
 			compatible = "hisilicon,hns-nic-v2";
 			ae-handle = <&dsaf0>;
 			port-idx-in-ae = <4>;
@@ -517,7 +517,7 @@
 			dma-coherent;
 		};
 
-		eth1: ethernet at 5{
+		eth1: ethernet-5{
 			compatible = "hisilicon,hns-nic-v2";
 			ae-handle = <&dsaf0>;
 			port-idx-in-ae = <5>;
@@ -526,7 +526,7 @@
 			dma-coherent;
 		};
 
-		eth2: ethernet at 0{
+		eth2: ethernet-0{
 			compatible = "hisilicon,hns-nic-v2";
 			ae-handle = <&dsaf0>;
 			port-idx-in-ae = <0>;
@@ -535,7 +535,7 @@
 			dma-coherent;
 		};
 
-		eth3: ethernet at 1{
+		eth3: ethernet-1{
 			compatible = "hisilicon,hns-nic-v2";
 			ae-handle = <&dsaf0>;
 			port-idx-in-ae = <1>;
-- 
1.7.12.4

Re: [PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

Hi Greg, any more comments, thanks.

On 2016/9/27 21:15, Kefeng Wang wrote:
> 
> 
> On 2016/9/27 18:57, Greg Kroah-Hartman wrote:
>> On Sat, Sep 24, 2016 at 05:14:25PM +0800, Kefeng Wang wrote:
>>> Declare an OF early console for SBSA UART so that the early console device
>>> can be specified via the "stdout-path" property in device-tree.
>>>
>>> Cc: Russell King <linux@armlinux.org.uk>
>>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>> ---
>>>  drivers/tty/serial/amba-pl011.c | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
>>> index 7d9b291..3688d3b 100644
>>> --- a/drivers/tty/serial/amba-pl011.c
>>> +++ b/drivers/tty/serial/amba-pl011.c
>>> @@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
>>>  	return 0;
>>>  }
>>>  OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
>>> +OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
>>
>> Why do you need another option for the same thing?
> 
> 
> It is used to support earlycon(without option) for sbsa-uart in bootargs.
> 
> 	chosen {
> 		stdout-path = "serial0:115200n8";
> 		bootargs = "earlycon"
> 	};
> 
> 	uart0: uart@602b0000 {
> 		compatible = "arm,sbsa-uart";
> 		reg = <0x0 0x602b0000 0x0 0x1000>;
> 		...
> 	};
> 
> We setup a unique struct with compatible name by OF_EARLYCON_DECLARE,
> #define OF_EARLYCON_DECLARE(_name, compat, fn)				\
> 	static const struct earlycon_id __UNIQUE_ID(__earlycon_##_name)	\
> 	     __used __section(__earlycon_table)				\
> 		= { .name = __stringify(_name),				\
> 		    .compatible = compat,				\
> 		    .setup = fn  }
> 
> if without this patch(see drivers/of/fdt.c),
> 
> early_init_dt_scan_chosen_serial()
>  - for (match = __earlycon_table; match < __earlycon_table_end; match++)
>   -- if (fdt_node_check_compatible(fdt, offset, match->compatible))
> 	countinue;
>   -- of_setup_earlycon(match, offset, options); // will never touch here.
> 
> Thanks,
> Kefeng
> 
>>
>> confused,
>>
>> greg k-h
>>
>> .
>>
> 
> 
> .
> 

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

Hi Greg, any more comments, thanks.

On 2016/9/27 21:15, Kefeng Wang wrote:
> 
> 
> On 2016/9/27 18:57, Greg Kroah-Hartman wrote:
>> On Sat, Sep 24, 2016 at 05:14:25PM +0800, Kefeng Wang wrote:
>>> Declare an OF early console for SBSA UART so that the early console device
>>> can be specified via the "stdout-path" property in device-tree.
>>>
>>> Cc: Russell King <linux@armlinux.org.uk>
>>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>> ---
>>>  drivers/tty/serial/amba-pl011.c | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
>>> index 7d9b291..3688d3b 100644
>>> --- a/drivers/tty/serial/amba-pl011.c
>>> +++ b/drivers/tty/serial/amba-pl011.c
>>> @@ -2330,6 +2330,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
>>>  	return 0;
>>>  }
>>>  OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
>>> +OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
>>
>> Why do you need another option for the same thing?
> 
> 
> It is used to support earlycon(without option) for sbsa-uart in bootargs.
> 
> 	chosen {
> 		stdout-path = "serial0:115200n8";
> 		bootargs = "earlycon"
> 	};
> 
> 	uart0: uart at 602b0000 {
> 		compatible = "arm,sbsa-uart";
> 		reg = <0x0 0x602b0000 0x0 0x1000>;
> 		...
> 	};
> 
> We setup a unique struct with compatible name by OF_EARLYCON_DECLARE,
> #define OF_EARLYCON_DECLARE(_name, compat, fn)				\
> 	static const struct earlycon_id __UNIQUE_ID(__earlycon_##_name)	\
> 	     __used __section(__earlycon_table)				\
> 		= { .name = __stringify(_name),				\
> 		    .compatible = compat,				\
> 		    .setup = fn  }
> 
> if without this patch(see drivers/of/fdt.c),
> 
> early_init_dt_scan_chosen_serial()
>  - for (match = __earlycon_table; match < __earlycon_table_end; match++)
>   -- if (fdt_node_check_compatible(fdt, offset, match->compatible))
> 	countinue;
>   -- of_setup_earlycon(match, offset, options); // will never touch here.
> 
> Thanks,
> Kefeng
> 
>>
>> confused,
>>
>> greg k-h
>>
>> .
>>
> 
> 
> .
> 

Re: [PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Greg Kroah-Hartman]

On Mon, Oct 24, 2016 at 11:59:20AM +0800, Kefeng Wang wrote:
> Hi Greg, any more comments, thanks.

Never wait, just resend if you have comments and you know you have to
fix them up...

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Greg Kroah-Hartman]

On Mon, Oct 24, 2016 at 11:59:20AM +0800, Kefeng Wang wrote:
> Hi Greg, any more comments, thanks.

Never wait, just resend if you have comments and you know you have to
fix them up...

Re: [PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

On 2016/10/27 23:18, Greg Kroah-Hartman wrote:
> On Mon, Oct 24, 2016 at 11:59:20AM +0800, Kefeng Wang wrote:
>> Hi Greg, any more comments, thanks.
> 
> Never wait, just resend if you have comments and you know you have to
> fix them up...
> 

Hi Greg, as I mentioned in previous mail, compatible "arm,sbsa-uart" need
be provided by adding a new OF_EARLYCON_DECLARE(), this is the patch's point.

And I no further update, could this patch be acceptable and be picked up?

Thanks,
Kefeng

> .
> 

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

On 2016/10/27 23:18, Greg Kroah-Hartman wrote:
> On Mon, Oct 24, 2016 at 11:59:20AM +0800, Kefeng Wang wrote:
>> Hi Greg, any more comments, thanks.
> 
> Never wait, just resend if you have comments and you know you have to
> fix them up...
> 

Hi Greg, as I mentioned in previous mail, compatible "arm,sbsa-uart" need
be provided by adding a new OF_EARLYCON_DECLARE(), this is the patch's point.

And I no further update, could this patch be acceptable and be picked up?

Thanks,
Kefeng

> .
> 

Re: [PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Greg Kroah-Hartman]

On Sun, Oct 30, 2016 at 04:49:30PM +0800, Kefeng Wang wrote:
> 
> 
> On 2016/10/27 23:18, Greg Kroah-Hartman wrote:
> > On Mon, Oct 24, 2016 at 11:59:20AM +0800, Kefeng Wang wrote:
> >> Hi Greg, any more comments, thanks.
> > 
> > Never wait, just resend if you have comments and you know you have to
> > fix them up...
> > 
> 
> Hi Greg, as I mentioned in previous mail, compatible "arm,sbsa-uart" need
> be provided by adding a new OF_EARLYCON_DECLARE(), this is the patch's point.
> 
> And I no further update, could this patch be acceptable and be picked up?

It's long gone from my queue, please resend it if you think it should be
applied.

thanks,

greg k-h

[PATCH 5/5] tty: amba-pl011: Add earlycon support for SBSA UART

[Greg Kroah-Hartman]

On Sun, Oct 30, 2016 at 04:49:30PM +0800, Kefeng Wang wrote:
> 
> 
> On 2016/10/27 23:18, Greg Kroah-Hartman wrote:
> > On Mon, Oct 24, 2016 at 11:59:20AM +0800, Kefeng Wang wrote:
> >> Hi Greg, any more comments, thanks.
> > 
> > Never wait, just resend if you have comments and you know you have to
> > fix them up...
> > 
> 
> Hi Greg, as I mentioned in previous mail, compatible "arm,sbsa-uart" need
> be provided by adding a new OF_EARLYCON_DECLARE(), this is the patch's point.
> 
> And I no further update, could this patch be acceptable and be picked up?

It's long gone from my queue, please resend it if you think it should be
applied.

thanks,

greg k-h

[PATCH RESEND] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

Declare an OF early console for SBSA UART so that the early console device
can be specified via the "stdout-path" property in device-tree.

Cc: Russell King <linux@armlinux.org.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/tty/serial/amba-pl011.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index e2c33b9..a4a0b3d 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2357,6 +2357,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
 	return 0;
 }
 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
+OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
 
 #else
 #define AMBA_CONSOLE	NULL
-- 
1.7.12.4

[PATCH RESEND] tty: amba-pl011: Add earlycon support for SBSA UART

[Kefeng Wang]

Declare an OF early console for SBSA UART so that the early console device
can be specified via the "stdout-path" property in device-tree.

Cc: Russell King <linux@armlinux.org.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/tty/serial/amba-pl011.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index e2c33b9..a4a0b3d 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2357,6 +2357,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
 	return 0;
 }
 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
+OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
 
 #else
 #define AMBA_CONSOLE	NULL
-- 
1.7.12.4

[PATCH] arm64: dts: hip06: Fix no reg property warning

[Wei Xu]

Hi Kefeng,

On 2016/10/24 4:40, Kefeng Wang wrote:
> Warning (unit_address_vs_reg): Node /soc/ethernet at 4 has a unit name, but no reg property
> Warning (unit_address_vs_reg): Node /soc/ethernet at 5 has a unit name, but no reg property
> Warning (unit_address_vs_reg): Node /soc/ethernet at 0 has a unit name, but no reg property
> Warning (unit_address_vs_reg): Node /soc/ethernet at 1 has a unit name, but no reg property
> 
> Fix warning when build with W=1.
> 
> Cc: Kejian Yan <yankejian@huawei.com>
> Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---

Applied to the hisilicon soc tree.
Thanks!

Best Regards,
Wei

>  arch/arm64/boot/dts/hisilicon/hip06.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> index b548763..f66c51b 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> @@ -508,7 +508,7 @@
>  			};
>  		};
>  
> -		eth0: ethernet at 4{
> +		eth0: ethernet-4{
>  			compatible = "hisilicon,hns-nic-v2";
>  			ae-handle = <&dsaf0>;
>  			port-idx-in-ae = <4>;
> @@ -517,7 +517,7 @@
>  			dma-coherent;
>  		};
>  
> -		eth1: ethernet at 5{
> +		eth1: ethernet-5{
>  			compatible = "hisilicon,hns-nic-v2";
>  			ae-handle = <&dsaf0>;
>  			port-idx-in-ae = <5>;
> @@ -526,7 +526,7 @@
>  			dma-coherent;
>  		};
>  
> -		eth2: ethernet at 0{
> +		eth2: ethernet-0{
>  			compatible = "hisilicon,hns-nic-v2";
>  			ae-handle = <&dsaf0>;
>  			port-idx-in-ae = <0>;
> @@ -535,7 +535,7 @@
>  			dma-coherent;
>  		};
>  
> -		eth3: ethernet at 1{
> +		eth3: ethernet-1{
>  			compatible = "hisilicon,hns-nic-v2";
>  			ae-handle = <&dsaf0>;
>  			port-idx-in-ae = <1>;
> 

Re: [PATCH 1/5] arm64: dts: hip06: Correct hardware pin number of usb node

[Wei Xu]

Hi Kefeng,

On 2016/9/24 10:14, Kefeng Wang wrote:
> The ohci/ehci hardware pin number should be 640/641, correct them.
> 
> Fixes: commit aa8d3e74f54d ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board")
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---

Applied to the hisilicon soc tree.
Thanks!

Best Regards,
Wei

>  arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> index 66b1bbf..be76f7d 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> @@ -322,7 +322,7 @@
>  			compatible = "generic-ohci";
>  			reg = <0x0 0xa7030000 0x0 0x10000>;
>  			interrupt-parent = <&mbigen_usb>;
> -			interrupts = <64 4>;
> +			interrupts = <640 4>;
>  			dma-coherent;
>  			status = "disabled";
>  		};
> @@ -331,7 +331,7 @@
>  			compatible = "generic-ehci";
>  			reg = <0x0 0xa7020000 0x0 0x10000>;
>  			interrupt-parent = <&mbigen_usb>;
> -			interrupts = <65 4>;
> +			interrupts = <641 4>;
>  			dma-coherent;
>  			status = "disabled";
>  		};
> 

[PATCH 1/5] arm64: dts: hip06: Correct hardware pin number of usb node

[Wei Xu]

Hi Kefeng,

On 2016/9/24 10:14, Kefeng Wang wrote:
> The ohci/ehci hardware pin number should be 640/641, correct them.
> 
> Fixes: commit aa8d3e74f54d ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board")
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---

Applied to the hisilicon soc tree.
Thanks!

Best Regards,
Wei

>  arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> index 66b1bbf..be76f7d 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> @@ -322,7 +322,7 @@
>  			compatible = "generic-ohci";
>  			reg = <0x0 0xa7030000 0x0 0x10000>;
>  			interrupt-parent = <&mbigen_usb>;
> -			interrupts = <64 4>;
> +			interrupts = <640 4>;
>  			dma-coherent;
>  			status = "disabled";
>  		};
> @@ -331,7 +331,7 @@
>  			compatible = "generic-ehci";
>  			reg = <0x0 0xa7020000 0x0 0x10000>;
>  			interrupt-parent = <&mbigen_usb>;
> -			interrupts = <65 4>;
> +			interrupts = <641 4>;
>  			dma-coherent;
>  			status = "disabled";
>  		};
> 

Re: [PATCH 2/5] Documentation: arm64: Add Hisilicon Hip07 D05 dts binding

[Wei Xu]

Hi Kefeng,

On 2016/9/24 10:14, Kefeng Wang wrote:
> This patch adds documentation for the devicetree bindings used by
> the DT files of Hisilicon Hip07 D05 board.
> 
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---

Applied to the hisilicon soc tree.
Thanks!

Best Regards,
Wei

>  Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> index 3f81575..7df79a7 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> @@ -28,6 +28,10 @@ HiP06 D03 Board
>  Required root node properties:
>  	- compatible = "hisilicon,hip06-d03";
>  
> +HiP07 D05 Board
> +Required root node properties:
> +	- compatible = "hisilicon,hip07-d05";
> +
>  Hisilicon system controller
>  
>  Required properties:
> 

[PATCH 2/5] Documentation: arm64: Add Hisilicon Hip07 D05 dts binding

[Wei Xu]

Hi Kefeng,

On 2016/9/24 10:14, Kefeng Wang wrote:
> This patch adds documentation for the devicetree bindings used by
> the DT files of Hisilicon Hip07 D05 board.
> 
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---

Applied to the hisilicon soc tree.
Thanks!

Best Regards,
Wei

>  Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> index 3f81575..7df79a7 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> @@ -28,6 +28,10 @@ HiP06 D03 Board
>  Required root node properties:
>  	- compatible = "hisilicon,hip06-d03";
>  
> +HiP07 D05 Board
> +Required root node properties:
> +	- compatible = "hisilicon,hip07-d05";
> +
>  Hisilicon system controller
>  
>  Required properties:
> 

Re: [PATCH 3/5] arm64: dts: hisilicon: Add initial dts for Hip07 D05 board

[Wei Xu]

Hi Kefeng,

On 2016/9/24 10:14, Kefeng Wang wrote:
> Adding initial dt file for Hip07 D05 board, it is with dual socket
> and each socket has two SCCLs(supper cpu cluster), one SCCL contains
> four clusters and each cluster has quard Cortex-A72.
> 
> Since each SCCL has their own DDR controller, it could be treated as
> a separate numa node. Thus, there are four numa nodes(one node with
> sixteen core) on Hip07 SoC.
> 
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---

Applied to the hisilicon soc tree.
Thanks!

Best Regards,
Wei

>  arch/arm64/boot/dts/hisilicon/Makefile      |    1 +
>  arch/arm64/boot/dts/hisilicon/hip07-d05.dts |   66 ++
>  arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 1059 +++++++++++++++++++++++++++
>  3 files changed, 1126 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/hisilicon/hip07-d05.dts
>  create mode 100644 arch/arm64/boot/dts/hisilicon/hip07.dtsi
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
> index d5f43a0..c8b8f80 100644
> --- a/arch/arm64/boot/dts/hisilicon/Makefile
> +++ b/arch/arm64/boot/dts/hisilicon/Makefile
> @@ -1,6 +1,7 @@
>  dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
>  dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
>  dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
> +dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
>  
>  always		:= $(dtb-y)
>  subdir-y	:= $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> new file mode 100644
> index 0000000..e058442
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> @@ -0,0 +1,66 @@
> +/**
> + * dts file for Hisilicon D05 Development Board
> + *
> + * Copyright (C) 2016 Hisilicon Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "hip07.dtsi"
> +
> +/ {
> +	model = "Hisilicon Hip07 D05 Development Board";
> +	compatible = "hisilicon,hip07-d05";
> +
> +	/* the mem node will be updated by UEFI. */
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x0 0x00000000 0x0 0x40000000>;
> +		numa-node-id = <0>;
> +	};
> +
> +	distance-map {
> +		compatible = "numa-distance-map-v1";
> +		distance-matrix = <0 0 10>,
> +				  <0 1 15>,
> +				  <0 2 20>,
> +				  <0 3 25>,
> +				  <1 0 15>,
> +				  <1 1 10>,
> +				  <1 2 25>,
> +				  <1 3 30>,
> +				  <2 0 20>,
> +				  <2 1 25>,
> +				  <2 2 10>,
> +				  <2 3 15>,
> +				  <3 0 25>,
> +				  <3 1 30>,
> +				  <3 2 15>,
> +				  <3 3 10>;
> +	};
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "ok";
> +};
> +
> +&usb_ohci {
> +	status = "ok";
> +};
> +
> +&usb_ehci {
> +	status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> new file mode 100644
> index 0000000..5144eb1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> @@ -0,0 +1,1059 @@
> +/**
> + * dts file for Hisilicon D05 Development Board
> + *
> + * Copyright (C) 2016 Hisilicon Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "hisilicon,hip07-d05";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +				core2 {
> +					cpu = <&cpu6>;
> +				};
> +				core3 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +
> +			cluster2 {
> +				core0 {
> +					cpu = <&cpu8>;
> +				};
> +				core1 {
> +					cpu = <&cpu9>;
> +				};
> +				core2 {
> +					cpu = <&cpu10>;
> +				};
> +				core3 {
> +					cpu = <&cpu11>;
> +				};
> +			};
> +
> +			cluster3 {
> +				core0 {
> +					cpu = <&cpu12>;
> +				};
> +				core1 {
> +					cpu = <&cpu13>;
> +				};
> +				core2 {
> +					cpu = <&cpu14>;
> +				};
> +				core3 {
> +					cpu = <&cpu15>;
> +				};
> +			};
> +
> +			cluster4 {
> +				core0 {
> +					cpu = <&cpu16>;
> +				};
> +				core1 {
> +					cpu = <&cpu17>;
> +				};
> +				core2 {
> +					cpu = <&cpu18>;
> +				};
> +				core3 {
> +					cpu = <&cpu19>;
> +				};
> +			};
> +
> +			cluster5 {
> +				core0 {
> +					cpu = <&cpu20>;
> +				};
> +				core1 {
> +					cpu = <&cpu21>;
> +				};
> +				core2 {
> +					cpu = <&cpu22>;
> +				};
> +				core3 {
> +					cpu = <&cpu23>;
> +				};
> +			};
> +
> +			cluster6 {
> +				core0 {
> +					cpu = <&cpu24>;
> +				};
> +				core1 {
> +					cpu = <&cpu25>;
> +				};
> +				core2 {
> +					cpu = <&cpu26>;
> +				};
> +				core3 {
> +					cpu = <&cpu27>;
> +				};
> +			};
> +
> +			cluster7 {
> +				core0 {
> +					cpu = <&cpu28>;
> +				};
> +				core1 {
> +					cpu = <&cpu29>;
> +				};
> +				core2 {
> +					cpu = <&cpu30>;
> +				};
> +				core3 {
> +					cpu = <&cpu31>;
> +				};
> +			};
> +
> +			cluster8 {
> +				core0 {
> +					cpu = <&cpu32>;
> +				};
> +				core1 {
> +					cpu = <&cpu33>;
> +				};
> +				core2 {
> +					cpu = <&cpu34>;
> +				};
> +				core3 {
> +					cpu = <&cpu35>;
> +				};
> +			};
> +
> +			cluster9 {
> +				core0 {
> +					cpu = <&cpu36>;
> +				};
> +				core1 {
> +					cpu = <&cpu37>;
> +				};
> +				core2 {
> +					cpu = <&cpu38>;
> +				};
> +				core3 {
> +					cpu = <&cpu39>;
> +				};
> +			};
> +
> +			cluster10 {
> +				core0 {
> +					cpu = <&cpu40>;
> +				};
> +				core1 {
> +					cpu = <&cpu41>;
> +				};
> +				core2 {
> +					cpu = <&cpu42>;
> +				};
> +				core3 {
> +					cpu = <&cpu43>;
> +				};
> +			};
> +
> +			cluster11 {
> +				core0 {
> +					cpu = <&cpu44>;
> +				};
> +				core1 {
> +					cpu = <&cpu45>;
> +				};
> +				core2 {
> +					cpu = <&cpu46>;
> +				};
> +				core3 {
> +					cpu = <&cpu47>;
> +				};
> +			};
> +
> +			cluster12 {
> +				core0 {
> +					cpu = <&cpu48>;
> +				};
> +				core1 {
> +					cpu = <&cpu49>;
> +				};
> +				core2 {
> +					cpu = <&cpu50>;
> +				};
> +				core3 {
> +					cpu = <&cpu51>;
> +				};
> +			};
> +
> +			cluster13 {
> +				core0 {
> +					cpu = <&cpu52>;
> +				};
> +				core1 {
> +					cpu = <&cpu53>;
> +				};
> +				core2 {
> +					cpu = <&cpu54>;
> +				};
> +				core3 {
> +					cpu = <&cpu55>;
> +				};
> +			};
> +
> +			cluster14 {
> +				core0 {
> +					cpu = <&cpu56>;
> +				};
> +				core1 {
> +					cpu = <&cpu57>;
> +				};
> +				core2 {
> +					cpu = <&cpu58>;
> +				};
> +				core3 {
> +					cpu = <&cpu59>;
> +				};
> +			};
> +
> +			cluster15 {
> +				core0 {
> +					cpu = <&cpu60>;
> +				};
> +				core1 {
> +					cpu = <&cpu61>;
> +				};
> +				core2 {
> +					cpu = <&cpu62>;
> +				};
> +				core3 {
> +					cpu = <&cpu63>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@10000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu1: cpu@10001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu2: cpu@10002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu3: cpu@10003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu4: cpu@10100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu5: cpu@10101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu6: cpu@10102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu7: cpu@10103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu8: cpu@10200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu9: cpu@10201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu10: cpu@10202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu11: cpu@10203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu12: cpu@10300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu13: cpu@10301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu14: cpu@10302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu15: cpu@10303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu16: cpu@30000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu17: cpu@30001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu18: cpu@30002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu19: cpu@30003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu20: cpu@30100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu21: cpu@30101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu22: cpu@30102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu23: cpu@30103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu24: cpu@30200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu25: cpu@30201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu26: cpu@30202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu27: cpu@30203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu28: cpu@30300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu29: cpu@30301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu30: cpu@30302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu31: cpu@30303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu32: cpu@50000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu33: cpu@50001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu34: cpu@50002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu35: cpu@50003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu36: cpu@50100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu37: cpu@50101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu38: cpu@50102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu39: cpu@50103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu40: cpu@50200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu41: cpu@50201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu42: cpu@50202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu43: cpu@50203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu44: cpu@50300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu45: cpu@50301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu46: cpu@50302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu47: cpu@50303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu48: cpu@70000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu49: cpu@70001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu50: cpu@70002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu51: cpu@70003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu52: cpu@70100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu53: cpu@70101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu54: cpu@70102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu55: cpu@70103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu56: cpu@70200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu57: cpu@70201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu58: cpu@70202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu59: cpu@70203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu60: cpu@70300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu61: cpu@70301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu62: cpu@70302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu63: cpu@70303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cluster0_l2: l2-cache0 {
> +			compatible = "cache";
> +		};
> +
> +		cluster1_l2: l2-cache1 {
> +			compatible = "cache";
> +		};
> +
> +		cluster2_l2: l2-cache2 {
> +			compatible = "cache";
> +		};
> +
> +		cluster3_l2: l2-cache3 {
> +			compatible = "cache";
> +		};
> +
> +		cluster4_l2: l2-cache4 {
> +			compatible = "cache";
> +		};
> +
> +		cluster5_l2: l2-cache5 {
> +			compatible = "cache";
> +		};
> +
> +		cluster6_l2: l2-cache6 {
> +			compatible = "cache";
> +		};
> +
> +		cluster7_l2: l2-cache7 {
> +			compatible = "cache";
> +		};
> +
> +		cluster8_l2: l2-cache8 {
> +			compatible = "cache";
> +		};
> +
> +		cluster9_l2: l2-cache9 {
> +			compatible = "cache";
> +		};
> +
> +		cluster10_l2: l2-cache10 {
> +			compatible = "cache";
> +		};
> +
> +		cluster11_l2: l2-cache11 {
> +			compatible = "cache";
> +		};
> +
> +		cluster12_l2: l2-cache12 {
> +			compatible = "cache";
> +		};
> +
> +		cluster13_l2: l2-cache13 {
> +			compatible = "cache";
> +		};
> +
> +		cluster14_l2: l2-cache14 {
> +			compatible = "cache";
> +		};
> +
> +		cluster15_l2: l2-cache15 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	gic: interrupt-controller@4d000000 {
> +		compatible = "arm,gic-v3";
> +		#interrupt-cells = <3>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		interrupt-controller;
> +		#redistributor-regions = <4>;
> +		redistributor-stride = <0x0 0x40000>;
> +		reg = <0x0 0x4d000000 0x0 0x10000>,	/* GICD */
> +		      <0x0 0x4d100000 0x0 0x400000>,	/* p0 GICR node 0 */
> +		      <0x0 0x6d100000 0x0 0x400000>,	/* p0 GICR node 1 */
> +		      <0x400 0x4d100000 0x0 0x400000>,	/* p1 GICR node 2 */
> +		      <0x400 0x6d100000 0x0 0x400000>,	/* p1 GICR node 3 */
> +		      <0x0 0xfe000000 0x0 0x10000>,	/* GICC */
> +		      <0x0 0xfe010000 0x0 0x10000>,	/* GICH */
> +		      <0x0 0xfe020000 0x0 0x10000>;	/* GICV */
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		p0_its_peri_a: interrupt-controller@4c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x0 0x4c000000 0x0 0x40000>;
> +		};
> +
> +		p0_its_peri_b: interrupt-controller@6c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x0 0x6c000000 0x0 0x40000>;
> +		};
> +
> +		p0_its_dsa_a: interrupt-controller@c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x0 0xc6000000 0x0 0x40000>;
> +		};
> +
> +		p0_its_dsa_b: interrupt-controller@8,c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x8 0xc6000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_peri_a: interrupt-controller@400,4c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x400 0x4c000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_peri_b: interrupt-controller@400,6c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x400 0x6c000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_dsa_a: interrupt-controller@400,c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x400 0xc6000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_dsa_b: interrupt-controller@408,c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x408 0xc6000000 0x0 0x40000>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a72-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	p0_mbigen_peri_b: interrupt-controller@60080000 {
> +		compatible = "hisilicon,mbigen-v2";
> +		reg = <0x0 0x60080000 0x0 0x10000>;
> +
> +		mbigen_uart: uart_intc {
> +			msi-parent = <&p0_its_peri_b 0x120c7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			num-pins = <1>;
> +		};
> +	};
> +
> +	p0_mbigen_pcie_a: interrupt-controller@a0080000 {
> +		compatible = "hisilicon,mbigen-v2";
> +		reg = <0x0 0xa0080000 0x0 0x10000>;
> +
> +		mbigen_usb: intc_usb {
> +			msi-parent = <&p0_its_dsa_a 0x40080>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			num-pins = <2>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		uart0: uart@602b0000 {
> +			compatible = "arm,sbsa-uart";
> +			reg = <0x0 0x602b0000 0x0 0x1000>;
> +			interrupt-parent = <&mbigen_uart>;
> +			interrupts = <807 4>;
> +			current-speed = <115200>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		usb_ohci: ohci@a7030000 {
> +			compatible = "generic-ohci";
> +			reg = <0x0 0xa7030000 0x0 0x10000>;
> +			interrupt-parent = <&mbigen_usb>;
> +			interrupts = <640 4>;
> +			dma-coherent;
> +			status = "disabled";
> +		};
> +
> +		usb_ehci: ehci@a7020000 {
> +			compatible = "generic-ehci";
> +			reg = <0x0 0xa7020000 0x0 0x10000>;
> +			interrupt-parent = <&mbigen_usb>;
> +			interrupts = <641 4>;
> +			dma-coherent;
> +			status = "disabled";
> +		};
> +	};
> +};
> 

[PATCH 3/5] arm64: dts: hisilicon: Add initial dts for Hip07 D05 board

[Wei Xu]

Hi Kefeng,

On 2016/9/24 10:14, Kefeng Wang wrote:
> Adding initial dt file for Hip07 D05 board, it is with dual socket
> and each socket has two SCCLs(supper cpu cluster), one SCCL contains
> four clusters and each cluster has quard Cortex-A72.
> 
> Since each SCCL has their own DDR controller, it could be treated as
> a separate numa node. Thus, there are four numa nodes(one node with
> sixteen core) on Hip07 SoC.
> 
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---

Applied to the hisilicon soc tree.
Thanks!

Best Regards,
Wei

>  arch/arm64/boot/dts/hisilicon/Makefile      |    1 +
>  arch/arm64/boot/dts/hisilicon/hip07-d05.dts |   66 ++
>  arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 1059 +++++++++++++++++++++++++++
>  3 files changed, 1126 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/hisilicon/hip07-d05.dts
>  create mode 100644 arch/arm64/boot/dts/hisilicon/hip07.dtsi
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
> index d5f43a0..c8b8f80 100644
> --- a/arch/arm64/boot/dts/hisilicon/Makefile
> +++ b/arch/arm64/boot/dts/hisilicon/Makefile
> @@ -1,6 +1,7 @@
>  dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
>  dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
>  dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
> +dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
>  
>  always		:= $(dtb-y)
>  subdir-y	:= $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> new file mode 100644
> index 0000000..e058442
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> @@ -0,0 +1,66 @@
> +/**
> + * dts file for Hisilicon D05 Development Board
> + *
> + * Copyright (C) 2016 Hisilicon Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "hip07.dtsi"
> +
> +/ {
> +	model = "Hisilicon Hip07 D05 Development Board";
> +	compatible = "hisilicon,hip07-d05";
> +
> +	/* the mem node will be updated by UEFI. */
> +	memory at 0 {
> +		device_type = "memory";
> +		reg = <0x0 0x00000000 0x0 0x40000000>;
> +		numa-node-id = <0>;
> +	};
> +
> +	distance-map {
> +		compatible = "numa-distance-map-v1";
> +		distance-matrix = <0 0 10>,
> +				  <0 1 15>,
> +				  <0 2 20>,
> +				  <0 3 25>,
> +				  <1 0 15>,
> +				  <1 1 10>,
> +				  <1 2 25>,
> +				  <1 3 30>,
> +				  <2 0 20>,
> +				  <2 1 25>,
> +				  <2 2 10>,
> +				  <2 3 15>,
> +				  <3 0 25>,
> +				  <3 1 30>,
> +				  <3 2 15>,
> +				  <3 3 10>;
> +	};
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "ok";
> +};
> +
> +&usb_ohci {
> +	status = "ok";
> +};
> +
> +&usb_ehci {
> +	status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> new file mode 100644
> index 0000000..5144eb1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> @@ -0,0 +1,1059 @@
> +/**
> + * dts file for Hisilicon D05 Development Board
> + *
> + * Copyright (C) 2016 Hisilicon Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "hisilicon,hip07-d05";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +				core2 {
> +					cpu = <&cpu6>;
> +				};
> +				core3 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +
> +			cluster2 {
> +				core0 {
> +					cpu = <&cpu8>;
> +				};
> +				core1 {
> +					cpu = <&cpu9>;
> +				};
> +				core2 {
> +					cpu = <&cpu10>;
> +				};
> +				core3 {
> +					cpu = <&cpu11>;
> +				};
> +			};
> +
> +			cluster3 {
> +				core0 {
> +					cpu = <&cpu12>;
> +				};
> +				core1 {
> +					cpu = <&cpu13>;
> +				};
> +				core2 {
> +					cpu = <&cpu14>;
> +				};
> +				core3 {
> +					cpu = <&cpu15>;
> +				};
> +			};
> +
> +			cluster4 {
> +				core0 {
> +					cpu = <&cpu16>;
> +				};
> +				core1 {
> +					cpu = <&cpu17>;
> +				};
> +				core2 {
> +					cpu = <&cpu18>;
> +				};
> +				core3 {
> +					cpu = <&cpu19>;
> +				};
> +			};
> +
> +			cluster5 {
> +				core0 {
> +					cpu = <&cpu20>;
> +				};
> +				core1 {
> +					cpu = <&cpu21>;
> +				};
> +				core2 {
> +					cpu = <&cpu22>;
> +				};
> +				core3 {
> +					cpu = <&cpu23>;
> +				};
> +			};
> +
> +			cluster6 {
> +				core0 {
> +					cpu = <&cpu24>;
> +				};
> +				core1 {
> +					cpu = <&cpu25>;
> +				};
> +				core2 {
> +					cpu = <&cpu26>;
> +				};
> +				core3 {
> +					cpu = <&cpu27>;
> +				};
> +			};
> +
> +			cluster7 {
> +				core0 {
> +					cpu = <&cpu28>;
> +				};
> +				core1 {
> +					cpu = <&cpu29>;
> +				};
> +				core2 {
> +					cpu = <&cpu30>;
> +				};
> +				core3 {
> +					cpu = <&cpu31>;
> +				};
> +			};
> +
> +			cluster8 {
> +				core0 {
> +					cpu = <&cpu32>;
> +				};
> +				core1 {
> +					cpu = <&cpu33>;
> +				};
> +				core2 {
> +					cpu = <&cpu34>;
> +				};
> +				core3 {
> +					cpu = <&cpu35>;
> +				};
> +			};
> +
> +			cluster9 {
> +				core0 {
> +					cpu = <&cpu36>;
> +				};
> +				core1 {
> +					cpu = <&cpu37>;
> +				};
> +				core2 {
> +					cpu = <&cpu38>;
> +				};
> +				core3 {
> +					cpu = <&cpu39>;
> +				};
> +			};
> +
> +			cluster10 {
> +				core0 {
> +					cpu = <&cpu40>;
> +				};
> +				core1 {
> +					cpu = <&cpu41>;
> +				};
> +				core2 {
> +					cpu = <&cpu42>;
> +				};
> +				core3 {
> +					cpu = <&cpu43>;
> +				};
> +			};
> +
> +			cluster11 {
> +				core0 {
> +					cpu = <&cpu44>;
> +				};
> +				core1 {
> +					cpu = <&cpu45>;
> +				};
> +				core2 {
> +					cpu = <&cpu46>;
> +				};
> +				core3 {
> +					cpu = <&cpu47>;
> +				};
> +			};
> +
> +			cluster12 {
> +				core0 {
> +					cpu = <&cpu48>;
> +				};
> +				core1 {
> +					cpu = <&cpu49>;
> +				};
> +				core2 {
> +					cpu = <&cpu50>;
> +				};
> +				core3 {
> +					cpu = <&cpu51>;
> +				};
> +			};
> +
> +			cluster13 {
> +				core0 {
> +					cpu = <&cpu52>;
> +				};
> +				core1 {
> +					cpu = <&cpu53>;
> +				};
> +				core2 {
> +					cpu = <&cpu54>;
> +				};
> +				core3 {
> +					cpu = <&cpu55>;
> +				};
> +			};
> +
> +			cluster14 {
> +				core0 {
> +					cpu = <&cpu56>;
> +				};
> +				core1 {
> +					cpu = <&cpu57>;
> +				};
> +				core2 {
> +					cpu = <&cpu58>;
> +				};
> +				core3 {
> +					cpu = <&cpu59>;
> +				};
> +			};
> +
> +			cluster15 {
> +				core0 {
> +					cpu = <&cpu60>;
> +				};
> +				core1 {
> +					cpu = <&cpu61>;
> +				};
> +				core2 {
> +					cpu = <&cpu62>;
> +				};
> +				core3 {
> +					cpu = <&cpu63>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu at 10000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu1: cpu at 10001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu2: cpu at 10002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu3: cpu at 10003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster0_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu4: cpu at 10100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu5: cpu at 10101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu6: cpu at 10102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu7: cpu at 10103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster1_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu8: cpu at 10200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu9: cpu at 10201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu10: cpu at 10202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu11: cpu at 10203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster2_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu12: cpu at 10300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu13: cpu at 10301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu14: cpu at 10302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu15: cpu at 10303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x10303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster3_l2>;
> +			numa-node-id = <0>;
> +		};
> +
> +		cpu16: cpu at 30000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu17: cpu at 30001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu18: cpu at 30002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu19: cpu at 30003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster4_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu20: cpu at 30100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu21: cpu at 30101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu22: cpu at 30102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu23: cpu at 30103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster5_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu24: cpu at 30200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu25: cpu at 30201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu26: cpu at 30202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu27: cpu at 30203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster6_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu28: cpu at 30300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu29: cpu at 30301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu30: cpu at 30302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu31: cpu at 30303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x30303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster7_l2>;
> +			numa-node-id = <1>;
> +		};
> +
> +		cpu32: cpu at 50000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu33: cpu at 50001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu34: cpu at 50002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu35: cpu at 50003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster8_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu36: cpu at 50100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu37: cpu at 50101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu38: cpu at 50102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu39: cpu at 50103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster9_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu40: cpu at 50200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu41: cpu at 50201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu42: cpu at 50202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu43: cpu at 50203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster10_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu44: cpu at 50300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu45: cpu at 50301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu46: cpu at 50302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu47: cpu at 50303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x50303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster11_l2>;
> +			numa-node-id = <2>;
> +		};
> +
> +		cpu48: cpu at 70000 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70000>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu49: cpu at 70001 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70001>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu50: cpu at 70002 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70002>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu51: cpu at 70003 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70003>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster12_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu52: cpu at 70100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70100>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu53: cpu at 70101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70101>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu54: cpu at 70102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70102>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu55: cpu at 70103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70103>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster13_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu56: cpu at 70200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70200>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu57: cpu at 70201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70201>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu58: cpu at 70202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70202>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu59: cpu at 70203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70203>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster14_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu60: cpu at 70300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70300>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu61: cpu at 70301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70301>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu62: cpu at 70302 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70302>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cpu63: cpu at 70303 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72", "arm,armv8";
> +			reg = <0x70303>;
> +			enable-method = "psci";
> +			next-level-cache = <&cluster15_l2>;
> +			numa-node-id = <3>;
> +		};
> +
> +		cluster0_l2: l2-cache0 {
> +			compatible = "cache";
> +		};
> +
> +		cluster1_l2: l2-cache1 {
> +			compatible = "cache";
> +		};
> +
> +		cluster2_l2: l2-cache2 {
> +			compatible = "cache";
> +		};
> +
> +		cluster3_l2: l2-cache3 {
> +			compatible = "cache";
> +		};
> +
> +		cluster4_l2: l2-cache4 {
> +			compatible = "cache";
> +		};
> +
> +		cluster5_l2: l2-cache5 {
> +			compatible = "cache";
> +		};
> +
> +		cluster6_l2: l2-cache6 {
> +			compatible = "cache";
> +		};
> +
> +		cluster7_l2: l2-cache7 {
> +			compatible = "cache";
> +		};
> +
> +		cluster8_l2: l2-cache8 {
> +			compatible = "cache";
> +		};
> +
> +		cluster9_l2: l2-cache9 {
> +			compatible = "cache";
> +		};
> +
> +		cluster10_l2: l2-cache10 {
> +			compatible = "cache";
> +		};
> +
> +		cluster11_l2: l2-cache11 {
> +			compatible = "cache";
> +		};
> +
> +		cluster12_l2: l2-cache12 {
> +			compatible = "cache";
> +		};
> +
> +		cluster13_l2: l2-cache13 {
> +			compatible = "cache";
> +		};
> +
> +		cluster14_l2: l2-cache14 {
> +			compatible = "cache";
> +		};
> +
> +		cluster15_l2: l2-cache15 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	gic: interrupt-controller at 4d000000 {
> +		compatible = "arm,gic-v3";
> +		#interrupt-cells = <3>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		interrupt-controller;
> +		#redistributor-regions = <4>;
> +		redistributor-stride = <0x0 0x40000>;
> +		reg = <0x0 0x4d000000 0x0 0x10000>,	/* GICD */
> +		      <0x0 0x4d100000 0x0 0x400000>,	/* p0 GICR node 0 */
> +		      <0x0 0x6d100000 0x0 0x400000>,	/* p0 GICR node 1 */
> +		      <0x400 0x4d100000 0x0 0x400000>,	/* p1 GICR node 2 */
> +		      <0x400 0x6d100000 0x0 0x400000>,	/* p1 GICR node 3 */
> +		      <0x0 0xfe000000 0x0 0x10000>,	/* GICC */
> +		      <0x0 0xfe010000 0x0 0x10000>,	/* GICH */
> +		      <0x0 0xfe020000 0x0 0x10000>;	/* GICV */
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		p0_its_peri_a: interrupt-controller at 4c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x0 0x4c000000 0x0 0x40000>;
> +		};
> +
> +		p0_its_peri_b: interrupt-controller at 6c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x0 0x6c000000 0x0 0x40000>;
> +		};
> +
> +		p0_its_dsa_a: interrupt-controller at c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x0 0xc6000000 0x0 0x40000>;
> +		};
> +
> +		p0_its_dsa_b: interrupt-controller at 8,c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x8 0xc6000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_peri_a: interrupt-controller at 400,4c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x400 0x4c000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_peri_b: interrupt-controller at 400,6c000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x400 0x6c000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_dsa_a: interrupt-controller at 400,c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x400 0xc6000000 0x0 0x40000>;
> +		};
> +
> +		p1_its_dsa_b: interrupt-controller at 408,c6000000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			#msi-cells = <1>;
> +			reg = <0x408 0xc6000000 0x0 0x40000>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a72-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	p0_mbigen_peri_b: interrupt-controller at 60080000 {
> +		compatible = "hisilicon,mbigen-v2";
> +		reg = <0x0 0x60080000 0x0 0x10000>;
> +
> +		mbigen_uart: uart_intc {
> +			msi-parent = <&p0_its_peri_b 0x120c7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			num-pins = <1>;
> +		};
> +	};
> +
> +	p0_mbigen_pcie_a: interrupt-controller at a0080000 {
> +		compatible = "hisilicon,mbigen-v2";
> +		reg = <0x0 0xa0080000 0x0 0x10000>;
> +
> +		mbigen_usb: intc_usb {
> +			msi-parent = <&p0_its_dsa_a 0x40080>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			num-pins = <2>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		uart0: uart at 602b0000 {
> +			compatible = "arm,sbsa-uart";
> +			reg = <0x0 0x602b0000 0x0 0x1000>;
> +			interrupt-parent = <&mbigen_uart>;
> +			interrupts = <807 4>;
> +			current-speed = <115200>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		usb_ohci: ohci at a7030000 {
> +			compatible = "generic-ohci";
> +			reg = <0x0 0xa7030000 0x0 0x10000>;
> +			interrupt-parent = <&mbigen_usb>;
> +			interrupts = <640 4>;
> +			dma-coherent;
> +			status = "disabled";
> +		};
> +
> +		usb_ehci: ehci at a7020000 {
> +			compatible = "generic-ehci";
> +			reg = <0x0 0xa7020000 0x0 0x10000>;
> +			interrupt-parent = <&mbigen_usb>;
> +			interrupts = <641 4>;
> +			dma-coherent;
> +			status = "disabled";
> +		};
> +	};
> +};
>