[PATCH 1/4] drm/amdgpu/virtual_dce: drop empty function

[PATCH 1/4] drm/amdgpu/virtual_dce: drop empty function

[Alex Deucher]

No need to ack non-existent interrupts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 23ff9f2..7c889d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -697,15 +697,6 @@ static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
 	return 0;
 }
 
-static void dce_virtual_crtc_vblank_int_ack(struct amdgpu_device *adev,
-					  int crtc)
-{
-	if (crtc >= adev->mode_info.num_crtc) {
-		DRM_DEBUG("invalid crtc %d\n", crtc);
-		return;
-	}
-}
-
 static int dce_virtual_crtc_irq(struct amdgpu_device *adev,
 			      struct amdgpu_irq_src *source,
 			      struct amdgpu_iv_entry *entry)
@@ -713,8 +704,6 @@ static int dce_virtual_crtc_irq(struct amdgpu_device *adev,
 	unsigned crtc = 0;
 	unsigned irq_type = AMDGPU_CRTC_IRQ_VBLANK1;
 
-	dce_virtual_crtc_vblank_int_ack(adev, crtc);
-
 	if (amdgpu_irq_enabled(adev, source, irq_type)) {
 		drm_handle_vblank(adev->ddev, crtc);
 	}
-- 
2.5.5

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[PATCH 2/4] drm/amdgpu/virtual_dce: adjust config ifdef

[Alex Deucher]

Include the CIK asics in the ifdef.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 7c889d3..5ba97a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -99,15 +99,15 @@ static void dce_virtual_stop_mc_access(struct amdgpu_device *adev,
 			      struct amdgpu_mode_mc_save *save)
 {
 	switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_CIK
 	case CHIP_BONAIRE:
 	case CHIP_HAWAII:
 	case CHIP_KAVERI:
 	case CHIP_KABINI:
 	case CHIP_MULLINS:
-#ifdef CONFIG_DRM_AMDGPU_CIK
 		dce_v8_0_disable_dce(adev);
-#endif
 		break;
+#endif
 	case CHIP_FIJI:
 	case CHIP_TONGA:
 		dce_v10_0_disable_dce(adev);
-- 
2.5.5

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[PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce

[Alex Deucher]

Needed for virtual dce support

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 50 ++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.h |  2 ++
 2 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 0a6e3b1..502e979 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -490,12 +490,55 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
 					  bool render)
 {
-	if (!render) 
+	if (!render)
 		WREG32(R_000300_VGA_RENDER_CONTROL,
 			RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 
 }
 
+static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
+{
+	int num_crtc = 0;
+
+	switch (adev->asic_type) {
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+	case CHIP_VERDE:
+		num_crtc = 6;
+		break;
+	case CHIP_OLAND:
+		num_crtc = 2;
+		break;
+	default:
+		num_crtc = 0;
+	}
+	return num_crtc;
+}
+
+void dce_v6_0_disable_dce(struct amdgpu_device *adev)
+{
+	/*Disable VGA render and enabled crtc, if has DCE engine*/
+	if (amdgpu_atombios_has_dce_engine_info(adev)) {
+		u32 tmp;
+		int crtc_enabled, i;
+
+		dce_v6_0_set_vga_render_state(adev, false);
+
+		/*Disable crtc*/
+		for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
+			crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
+				EVERGREEN_CRTC_MASTER_EN;
+			if (crtc_enabled) {
+				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+				tmp &= ~EVERGREEN_CRTC_MASTER_EN;
+				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
+				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+			}
+		}
+	}
+}
+
 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
 {
 
@@ -2217,21 +2260,20 @@ static int dce_v6_0_early_init(void *handle)
 	dce_v6_0_set_display_funcs(adev);
 	dce_v6_0_set_irq_funcs(adev);
 
+	adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
+
 	switch (adev->asic_type) {
 	case CHIP_TAHITI:
 	case CHIP_PITCAIRN:
 	case CHIP_VERDE:
-		adev->mode_info.num_crtc = 6;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
 	case CHIP_OLAND:
-		adev->mode_info.num_crtc = 2;
 		adev->mode_info.num_hpd = 2;
 		adev->mode_info.num_dig = 2;
 		break;
 	default:
-		/* FIXME: not supported yet */
 		return -EINVAL;
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
index 6a55281..4c6cd18 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
@@ -26,4 +26,6 @@
 
 extern const struct amd_ip_funcs dce_v6_0_ip_funcs;
 
+void dce_v6_0_disable_dce(struct amdgpu_device *adev);
+
 #endif
-- 
2.5.5

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[PATCH 4/4] drm/amdgpu/virtual_dce: add dce6 support

[Alex Deucher]

disable the real dce hw if the asic supports dce.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 5ba97a7..359fe56 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -27,6 +27,9 @@
 #include "atom.h"
 #include "amdgpu_pll.h"
 #include "amdgpu_connectors.h"
+#ifdef CONFIG_DRM_AMDGPU_SI
+#include "dce_v6_0.h"
+#endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
 #include "dce_v8_0.h"
 #endif
@@ -99,6 +102,14 @@ static void dce_virtual_stop_mc_access(struct amdgpu_device *adev,
 			      struct amdgpu_mode_mc_save *save)
 {
 	switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+	case CHIP_VERDE:
+	case CHIP_OLAND:
+		dce_v6_0_disable_dce(adev);
+		break;
+#endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
 	case CHIP_BONAIRE:
 	case CHIP_HAWAII:
@@ -119,6 +130,9 @@ static void dce_virtual_stop_mc_access(struct amdgpu_device *adev,
 		dce_v11_0_disable_dce(adev);
 		break;
 	case CHIP_TOPAZ:
+#ifdef CONFIG_DRM_AMDGPU_SI
+	case CHIP_HAINAN:
+#endif
 		/* no DCE */
 		return;
 	default:
-- 
2.5.5

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RE: [PATCH 1/4] drm/amdgpu/virtual_dce: drop empty function

[Deng, Emily]

Reviewed-By: Emily Deng <Emily.Deng@amd.com>

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Alex Deucher
> Sent: Friday, September 30, 2016 12:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 1/4] drm/amdgpu/virtual_dce: drop empty function
> 
> No need to ack non-existent interrupts.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 11 -----------
>  1 file changed, 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 23ff9f2..7c889d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -697,15 +697,6 @@ static int dce_virtual_set_crtc_irq_state(struct
> amdgpu_device *adev,
>  	return 0;
>  }
> 
> -static void dce_virtual_crtc_vblank_int_ack(struct amdgpu_device *adev,
> -					  int crtc)
> -{
> -	if (crtc >= adev->mode_info.num_crtc) {
> -		DRM_DEBUG("invalid crtc %d\n", crtc);
> -		return;
> -	}
> -}
> -
>  static int dce_virtual_crtc_irq(struct amdgpu_device *adev,
>  			      struct amdgpu_irq_src *source,
>  			      struct amdgpu_iv_entry *entry) @@ -713,8
> +704,6 @@ static int dce_virtual_crtc_irq(struct amdgpu_device *adev,
>  	unsigned crtc = 0;
>  	unsigned irq_type = AMDGPU_CRTC_IRQ_VBLANK1;
> 
> -	dce_virtual_crtc_vblank_int_ack(adev, crtc);
> -
>  	if (amdgpu_irq_enabled(adev, source, irq_type)) {
>  		drm_handle_vblank(adev->ddev, crtc);
>  	}
> --
> 2.5.5
> 
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RE: [PATCH 2/4] drm/amdgpu/virtual_dce: adjust config ifdef

[Deng, Emily]

Reviewed-By: Emily Deng <Emily.Deng@amd.com>

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Alex Deucher
> Sent: Friday, September 30, 2016 12:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 2/4] drm/amdgpu/virtual_dce: adjust config ifdef
> 
> Include the CIK asics in the ifdef.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 7c889d3..5ba97a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -99,15 +99,15 @@ static void dce_virtual_stop_mc_access(struct
> amdgpu_device *adev,
>  			      struct amdgpu_mode_mc_save *save)  {
>  	switch (adev->asic_type) {
> +#ifdef CONFIG_DRM_AMDGPU_CIK
>  	case CHIP_BONAIRE:
>  	case CHIP_HAWAII:
>  	case CHIP_KAVERI:
>  	case CHIP_KABINI:
>  	case CHIP_MULLINS:
> -#ifdef CONFIG_DRM_AMDGPU_CIK
>  		dce_v8_0_disable_dce(adev);
> -#endif
>  		break;
> +#endif
>  	case CHIP_FIJI:
>  	case CHIP_TONGA:
>  		dce_v10_0_disable_dce(adev);
> --
> 2.5.5
> 
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RE: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce

[Deng, Emily]

Hi Alex,
    It seems hasn't support virtual display for dce_v6_0 asic?

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Alex Deucher
> Sent: Friday, September 30, 2016 12:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
> 
> Needed for virtual dce support
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 50
> ++++++++++++++++++++++++++++++++---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.h |  2 ++
>  2 files changed, 48 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 0a6e3b1..502e979 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -490,12 +490,55 @@ static void dce_v6_0_resume_mc_access(struct
> amdgpu_device *adev,  static void dce_v6_0_set_vga_render_state(struct
> amdgpu_device *adev,
>  					  bool render)
>  {
> -	if (!render)
> +	if (!render)
>  		WREG32(R_000300_VGA_RENDER_CONTROL,
>  			RREG32(R_000300_VGA_RENDER_CONTROL) &
> C_000300_VGA_VSTATUS_CNTL);
> 
>  }
> 
> +static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) {
> +	int num_crtc = 0;
> +
> +	switch (adev->asic_type) {
> +	case CHIP_TAHITI:
> +	case CHIP_PITCAIRN:
> +	case CHIP_VERDE:
> +		num_crtc = 6;
> +		break;
> +	case CHIP_OLAND:
> +		num_crtc = 2;
> +		break;
> +	default:
> +		num_crtc = 0;
> +	}
> +	return num_crtc;
> +}
> +
> +void dce_v6_0_disable_dce(struct amdgpu_device *adev) {
> +	/*Disable VGA render and enabled crtc, if has DCE engine*/
> +	if (amdgpu_atombios_has_dce_engine_info(adev)) {
> +		u32 tmp;
> +		int crtc_enabled, i;
> +
> +		dce_v6_0_set_vga_render_state(adev, false);
> +
> +		/*Disable crtc*/
> +		for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
> +			crtc_enabled =
> RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
> +				EVERGREEN_CRTC_MASTER_EN;
> +			if (crtc_enabled) {
> +				WREG32(EVERGREEN_CRTC_UPDATE_LOCK
> + crtc_offsets[i], 1);
> +				tmp = RREG32(EVERGREEN_CRTC_CONTROL
> + crtc_offsets[i]);
> +				tmp &= ~EVERGREEN_CRTC_MASTER_EN;
> +				WREG32(EVERGREEN_CRTC_CONTROL +
> crtc_offsets[i], tmp);
> +				WREG32(EVERGREEN_CRTC_UPDATE_LOCK
> + crtc_offsets[i], 0);
> +			}
> +		}
> +	}
> +}
> +
>  static void dce_v6_0_program_fmt(struct drm_encoder *encoder)  {
> 
> @@ -2217,21 +2260,20 @@ static int dce_v6_0_early_init(void *handle)
>  	dce_v6_0_set_display_funcs(adev);
>  	dce_v6_0_set_irq_funcs(adev);
> 
> +	adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
> +
>  	switch (adev->asic_type) {
>  	case CHIP_TAHITI:
>  	case CHIP_PITCAIRN:
>  	case CHIP_VERDE:
> -		adev->mode_info.num_crtc = 6;
>  		adev->mode_info.num_hpd = 6;
>  		adev->mode_info.num_dig = 6;
>  		break;
>  	case CHIP_OLAND:
> -		adev->mode_info.num_crtc = 2;
>  		adev->mode_info.num_hpd = 2;
>  		adev->mode_info.num_dig = 2;
>  		break;
>  	default:
> -		/* FIXME: not supported yet */
>  		return -EINVAL;
>  	}
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> index 6a55281..4c6cd18 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> @@ -26,4 +26,6 @@
> 
>  extern const struct amd_ip_funcs dce_v6_0_ip_funcs;
> 
> +void dce_v6_0_disable_dce(struct amdgpu_device *adev);
> +
>  #endif
> --
> 2.5.5
> 
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RE: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce

[Deucher, Alexander]

> -----Original Message-----
> From: Deng, Emily
> Sent: Friday, September 30, 2016 3:21 AM
> To: Alex Deucher; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: RE: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
> 
> Hi Alex,
>     It seems hasn't support virtual display for dce_v6_0 asic?

SI support was developed in parallel and landed after your virtual dce patches went in.

Alex

> 
> > -----Original Message-----
> > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of Alex Deucher
> > Sent: Friday, September 30, 2016 12:14 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> > Subject: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
> >
> > Needed for virtual dce support
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 50
> > ++++++++++++++++++++++++++++++++---
> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.h |  2 ++
> >  2 files changed, 48 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > index 0a6e3b1..502e979 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > @@ -490,12 +490,55 @@ static void dce_v6_0_resume_mc_access(struct
> > amdgpu_device *adev,  static void dce_v6_0_set_vga_render_state(struct
> > amdgpu_device *adev,
> >  					  bool render)
> >  {
> > -	if (!render)
> > +	if (!render)
> >  		WREG32(R_000300_VGA_RENDER_CONTROL,
> >  			RREG32(R_000300_VGA_RENDER_CONTROL) &
> > C_000300_VGA_VSTATUS_CNTL);
> >
> >  }
> >
> > +static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) {
> > +	int num_crtc = 0;
> > +
> > +	switch (adev->asic_type) {
> > +	case CHIP_TAHITI:
> > +	case CHIP_PITCAIRN:
> > +	case CHIP_VERDE:
> > +		num_crtc = 6;
> > +		break;
> > +	case CHIP_OLAND:
> > +		num_crtc = 2;
> > +		break;
> > +	default:
> > +		num_crtc = 0;
> > +	}
> > +	return num_crtc;
> > +}
> > +
> > +void dce_v6_0_disable_dce(struct amdgpu_device *adev) {
> > +	/*Disable VGA render and enabled crtc, if has DCE engine*/
> > +	if (amdgpu_atombios_has_dce_engine_info(adev)) {
> > +		u32 tmp;
> > +		int crtc_enabled, i;
> > +
> > +		dce_v6_0_set_vga_render_state(adev, false);
> > +
> > +		/*Disable crtc*/
> > +		for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
> > +			crtc_enabled =
> > RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
> > +				EVERGREEN_CRTC_MASTER_EN;
> > +			if (crtc_enabled) {
> > +				WREG32(EVERGREEN_CRTC_UPDATE_LOCK
> > + crtc_offsets[i], 1);
> > +				tmp = RREG32(EVERGREEN_CRTC_CONTROL
> > + crtc_offsets[i]);
> > +				tmp &= ~EVERGREEN_CRTC_MASTER_EN;
> > +				WREG32(EVERGREEN_CRTC_CONTROL +
> > crtc_offsets[i], tmp);
> > +				WREG32(EVERGREEN_CRTC_UPDATE_LOCK
> > + crtc_offsets[i], 0);
> > +			}
> > +		}
> > +	}
> > +}
> > +
> >  static void dce_v6_0_program_fmt(struct drm_encoder *encoder)  {
> >
> > @@ -2217,21 +2260,20 @@ static int dce_v6_0_early_init(void *handle)
> >  	dce_v6_0_set_display_funcs(adev);
> >  	dce_v6_0_set_irq_funcs(adev);
> >
> > +	adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
> > +
> >  	switch (adev->asic_type) {
> >  	case CHIP_TAHITI:
> >  	case CHIP_PITCAIRN:
> >  	case CHIP_VERDE:
> > -		adev->mode_info.num_crtc = 6;
> >  		adev->mode_info.num_hpd = 6;
> >  		adev->mode_info.num_dig = 6;
> >  		break;
> >  	case CHIP_OLAND:
> > -		adev->mode_info.num_crtc = 2;
> >  		adev->mode_info.num_hpd = 2;
> >  		adev->mode_info.num_dig = 2;
> >  		break;
> >  	default:
> > -		/* FIXME: not supported yet */
> >  		return -EINVAL;
> >  	}
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > index 6a55281..4c6cd18 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > @@ -26,4 +26,6 @@
> >
> >  extern const struct amd_ip_funcs dce_v6_0_ip_funcs;
> >
> > +void dce_v6_0_disable_dce(struct amdgpu_device *adev);
> > +
> >  #endif
> > --
> > 2.5.5
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce

[Alex Deucher]

On Fri, Sep 30, 2016 at 9:19 AM, Deucher, Alexander
<Alexander.Deucher@amd.com> wrote:
>> -----Original Message-----
>> From: Deng, Emily
>> Sent: Friday, September 30, 2016 3:21 AM
>> To: Alex Deucher; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander
>> Subject: RE: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
>>
>> Hi Alex,
>>     It seems hasn't support virtual display for dce_v6_0 asic?
>
> SI support was developed in parallel and landed after your virtual dce patches went in.

Ping on this series.

Alex

>
> Alex
>
>>
>> > -----Original Message-----
>> > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>> > Of Alex Deucher
>> > Sent: Friday, September 30, 2016 12:14 PM
>> > To: amd-gfx@lists.freedesktop.org
>> > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
>> > Subject: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
>> >
>> > Needed for virtual dce support
>> >
>> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> > ---
>> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 50
>> > ++++++++++++++++++++++++++++++++---
>> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.h |  2 ++
>> >  2 files changed, 48 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> > index 0a6e3b1..502e979 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> > @@ -490,12 +490,55 @@ static void dce_v6_0_resume_mc_access(struct
>> > amdgpu_device *adev,  static void dce_v6_0_set_vga_render_state(struct
>> > amdgpu_device *adev,
>> >                                       bool render)
>> >  {
>> > -   if (!render)
>> > +   if (!render)
>> >             WREG32(R_000300_VGA_RENDER_CONTROL,
>> >                     RREG32(R_000300_VGA_RENDER_CONTROL) &
>> > C_000300_VGA_VSTATUS_CNTL);
>> >
>> >  }
>> >
>> > +static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) {
>> > +   int num_crtc = 0;
>> > +
>> > +   switch (adev->asic_type) {
>> > +   case CHIP_TAHITI:
>> > +   case CHIP_PITCAIRN:
>> > +   case CHIP_VERDE:
>> > +           num_crtc = 6;
>> > +           break;
>> > +   case CHIP_OLAND:
>> > +           num_crtc = 2;
>> > +           break;
>> > +   default:
>> > +           num_crtc = 0;
>> > +   }
>> > +   return num_crtc;
>> > +}
>> > +
>> > +void dce_v6_0_disable_dce(struct amdgpu_device *adev) {
>> > +   /*Disable VGA render and enabled crtc, if has DCE engine*/
>> > +   if (amdgpu_atombios_has_dce_engine_info(adev)) {
>> > +           u32 tmp;
>> > +           int crtc_enabled, i;
>> > +
>> > +           dce_v6_0_set_vga_render_state(adev, false);
>> > +
>> > +           /*Disable crtc*/
>> > +           for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
>> > +                   crtc_enabled =
>> > RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
>> > +                           EVERGREEN_CRTC_MASTER_EN;
>> > +                   if (crtc_enabled) {
>> > +                           WREG32(EVERGREEN_CRTC_UPDATE_LOCK
>> > + crtc_offsets[i], 1);
>> > +                           tmp = RREG32(EVERGREEN_CRTC_CONTROL
>> > + crtc_offsets[i]);
>> > +                           tmp &= ~EVERGREEN_CRTC_MASTER_EN;
>> > +                           WREG32(EVERGREEN_CRTC_CONTROL +
>> > crtc_offsets[i], tmp);
>> > +                           WREG32(EVERGREEN_CRTC_UPDATE_LOCK
>> > + crtc_offsets[i], 0);
>> > +                   }
>> > +           }
>> > +   }
>> > +}
>> > +
>> >  static void dce_v6_0_program_fmt(struct drm_encoder *encoder)  {
>> >
>> > @@ -2217,21 +2260,20 @@ static int dce_v6_0_early_init(void *handle)
>> >     dce_v6_0_set_display_funcs(adev);
>> >     dce_v6_0_set_irq_funcs(adev);
>> >
>> > +   adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
>> > +
>> >     switch (adev->asic_type) {
>> >     case CHIP_TAHITI:
>> >     case CHIP_PITCAIRN:
>> >     case CHIP_VERDE:
>> > -           adev->mode_info.num_crtc = 6;
>> >             adev->mode_info.num_hpd = 6;
>> >             adev->mode_info.num_dig = 6;
>> >             break;
>> >     case CHIP_OLAND:
>> > -           adev->mode_info.num_crtc = 2;
>> >             adev->mode_info.num_hpd = 2;
>> >             adev->mode_info.num_dig = 2;
>> >             break;
>> >     default:
>> > -           /* FIXME: not supported yet */
>> >             return -EINVAL;
>> >     }
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
>> > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
>> > index 6a55281..4c6cd18 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
>> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
>> > @@ -26,4 +26,6 @@
>> >
>> >  extern const struct amd_ip_funcs dce_v6_0_ip_funcs;
>> >
>> > +void dce_v6_0_disable_dce(struct amdgpu_device *adev);
>> > +
>> >  #endif
>> > --
>> > 2.5.5
>> >
>> > _______________________________________________
>> > amd-gfx mailing list
>> > amd-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce

[Deng, Emily]

Reviewed-By: Emily Deng <Emily.Deng@amd.com>

> -----Original Message-----
> From: Deucher, Alexander
> Sent: Friday, September 30, 2016 9:19 PM
> To: Deng, Emily <Emily.Deng@amd.com>; Alex Deucher
> <alexdeucher@gmail.com>; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
> 
> > -----Original Message-----
> > From: Deng, Emily
> > Sent: Friday, September 30, 2016 3:21 AM
> > To: Alex Deucher; amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander
> > Subject: RE: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
> >
> > Hi Alex,
> >     It seems hasn't support virtual display for dce_v6_0 asic?
> 
> SI support was developed in parallel and landed after your virtual dce patches
> went in.
> 
> Alex
> 
> >
> > > -----Original Message-----
> > > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On
> > > Behalf Of Alex Deucher
> > > Sent: Friday, September 30, 2016 12:14 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> > > Subject: [PATCH 3/4] drm/amdgpu/dce6: add dce_v6_0_disable_dce
> > >
> > > Needed for virtual dce support
> > >
> > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 50
> > > ++++++++++++++++++++++++++++++++---
> > >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.h |  2 ++
> > >  2 files changed, 48 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > index 0a6e3b1..502e979 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > @@ -490,12 +490,55 @@ static void
> dce_v6_0_resume_mc_access(struct
> > > amdgpu_device *adev,  static void
> > > dce_v6_0_set_vga_render_state(struct
> > > amdgpu_device *adev,
> > >  					  bool render)
> > >  {
> > > -	if (!render)
> > > +	if (!render)
> > >  		WREG32(R_000300_VGA_RENDER_CONTROL,
> > >  			RREG32(R_000300_VGA_RENDER_CONTROL) &
> > > C_000300_VGA_VSTATUS_CNTL);
> > >
> > >  }
> > >
> > > +static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) {
> > > +	int num_crtc = 0;
> > > +
> > > +	switch (adev->asic_type) {
> > > +	case CHIP_TAHITI:
> > > +	case CHIP_PITCAIRN:
> > > +	case CHIP_VERDE:
> > > +		num_crtc = 6;
> > > +		break;
> > > +	case CHIP_OLAND:
> > > +		num_crtc = 2;
> > > +		break;
> > > +	default:
> > > +		num_crtc = 0;
> > > +	}
> > > +	return num_crtc;
> > > +}
> > > +
> > > +void dce_v6_0_disable_dce(struct amdgpu_device *adev) {
> > > +	/*Disable VGA render and enabled crtc, if has DCE engine*/
> > > +	if (amdgpu_atombios_has_dce_engine_info(adev)) {
> > > +		u32 tmp;
> > > +		int crtc_enabled, i;
> > > +
> > > +		dce_v6_0_set_vga_render_state(adev, false);
> > > +
> > > +		/*Disable crtc*/
> > > +		for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
> > > +			crtc_enabled =
> > > RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
> > > +				EVERGREEN_CRTC_MASTER_EN;
> > > +			if (crtc_enabled) {
> > > +				WREG32(EVERGREEN_CRTC_UPDATE_LOCK
> crtc_offsets[i], 1);
> > > +				tmp = RREG32(EVERGREEN_CRTC_CONTROL
> crtc_offsets[i]);
> > > +				tmp &= ~EVERGREEN_CRTC_MASTER_EN;
> > > +				WREG32(EVERGREEN_CRTC_CONTROL +
> > > crtc_offsets[i], tmp);
> > > +				WREG32(EVERGREEN_CRTC_UPDATE_LOCK
> crtc_offsets[i], 0);
> > > +			}
> > > +		}
> > > +	}
> > > +}
> > > +
> > >  static void dce_v6_0_program_fmt(struct drm_encoder *encoder)  {
> > >
> > > @@ -2217,21 +2260,20 @@ static int dce_v6_0_early_init(void *handle)
> > >  	dce_v6_0_set_display_funcs(adev);
> > >  	dce_v6_0_set_irq_funcs(adev);
> > >
> > > +	adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
> > > +
> > >  	switch (adev->asic_type) {
> > >  	case CHIP_TAHITI:
> > >  	case CHIP_PITCAIRN:
> > >  	case CHIP_VERDE:
> > > -		adev->mode_info.num_crtc = 6;
> > >  		adev->mode_info.num_hpd = 6;
> > >  		adev->mode_info.num_dig = 6;
> > >  		break;
> > >  	case CHIP_OLAND:
> > > -		adev->mode_info.num_crtc = 2;
> > >  		adev->mode_info.num_hpd = 2;
> > >  		adev->mode_info.num_dig = 2;
> > >  		break;
> > >  	default:
> > > -		/* FIXME: not supported yet */
> > >  		return -EINVAL;
> > >  	}
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > > index 6a55281..4c6cd18 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> > > @@ -26,4 +26,6 @@
> > >
> > >  extern const struct amd_ip_funcs dce_v6_0_ip_funcs;
> > >
> > > +void dce_v6_0_disable_dce(struct amdgpu_device *adev);
> > > +
> > >  #endif
> > > --
> > > 2.5.5
> > >
> > > _______________________________________________
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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