* [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support
@ 2016-10-06 13:21 Peter Maydell
2016-10-06 13:21 ` [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 Peter Maydell
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Peter Maydell @ 2016-10-06 13:21 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: patches, Edgar E. Iglesias
This set of three straightforward patches is a preliminary
for adding virtualization support to the GICv3 emulation:
* add a (nop implementation of) MDCCINT_EL1, since KVM
will read/write it on worldswitch
* fix some bugs in the GICv3 trace events
* add trace events for the generic timers
(which I have been using for debugging)
I actually have almost all of the GICv3 virt code written,
but it currently has bugs which mean that a guest kernel
under KVM won't boot. Debugging in progress...
thanks
-- PMM
Peter Maydell (3):
target-arm: Implement dummy MDCCINT_EL1
target-arm: Add trace events for the generic timers
hw/intc/arm_gicv3: Fix ICC register tracepoints
Makefile.objs | 1 +
hw/intc/arm_gicv3_cpuif.c | 23 +++++++++++++++--------
hw/intc/trace-events | 14 +++++++-------
target-arm/helper.c | 28 ++++++++++++++++++++++++----
4 files changed, 47 insertions(+), 19 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
@ 2016-10-06 13:21 ` Peter Maydell
2016-10-06 16:55 ` Edgar E. Iglesias
2016-10-06 13:21 ` [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers Peter Maydell
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2016-10-06 13:21 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: patches, Edgar E. Iglesias
MDCCINT_EL1 is part of the DCC debugger communication
channel between the CPU and an attached external debugger.
QEMU doesn't implement this, but since Linux may try
to access this register we need to provide at least
a dummy implementation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 25f612d..23792ab 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
+ /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
+ * Channel but Linux may try to access this register. The 32-bit
+ * alias is DBGDCCINT.
+ */
+ { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .accessfn = access_tda,
+ .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
2016-10-06 13:21 ` [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 Peter Maydell
@ 2016-10-06 13:21 ` Peter Maydell
2016-10-06 16:55 ` Edgar E. Iglesias
2016-10-06 13:21 ` [Qemu-devel] [PATCH 3/3] hw/intc/arm_gicv3: Fix ICC register tracepoints Peter Maydell
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2016-10-06 13:21 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: patches, Edgar E. Iglesias
Add some useful trace events for the ARM generic timers (notably
the various register writes and the resulting IRQ line state).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Makefile.objs | 1 +
target-arm/helper.c | 20 ++++++++++++++++----
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 02fb8e7..69fdd48 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -155,6 +155,7 @@ trace-events-y += hw/alpha/trace-events
trace-events-y += ui/trace-events
trace-events-y += audio/trace-events
trace-events-y += net/trace-events
+trace-events-y += target-arm/trace-events
trace-events-y += target-i386/trace-events
trace-events-y += target-sparc/trace-events
trace-events-y += target-s390x/trace-events
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 23792ab..5fcdc2b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1,4 +1,5 @@
#include "qemu/osdep.h"
+#include "trace.h"
#include "cpu.h"
#include "internals.h"
#include "exec/gdbstub.h"
@@ -1560,10 +1561,13 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
/* Note that this must be unsigned 64 bit arithmetic: */
int istatus = count - offset >= gt->cval;
uint64_t nexttick;
+ int irqstate;
gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
- qemu_set_irq(cpu->gt_timer_outputs[timeridx],
- (istatus && !(gt->ctl & 2)));
+
+ irqstate = (istatus && !(gt->ctl & 2));
+ qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
+
if (istatus) {
/* Next transition is when count rolls back over to zero */
nexttick = UINT64_MAX;
@@ -1580,11 +1584,13 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
nexttick = INT64_MAX / GTIMER_SCALE;
}
timer_mod(cpu->gt_timer[timeridx], nexttick);
+ trace_arm_gt_recalc(timeridx, irqstate, nexttick);
} else {
/* Timer disabled: ISTATUS and timer output always clear */
gt->ctl &= ~4;
qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
timer_del(cpu->gt_timer[timeridx]);
+ trace_arm_gt_recalc_disabled(timeridx);
}
}
@@ -1610,6 +1616,7 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx,
uint64_t value)
{
+ trace_arm_gt_cval_write(timeridx, value);
env->cp15.c14_timer[timeridx].cval = value;
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}
@@ -1629,6 +1636,7 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
+ trace_arm_gt_tval_write(timeridx, value);
env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
sextract64(value, 0, 32);
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
@@ -1641,6 +1649,7 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
+ trace_arm_gt_ctl_write(timeridx, value);
env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
if ((oldval ^ value) & 1) {
/* Enable toggled */
@@ -1649,8 +1658,10 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* IMASK toggled: don't need to recalculate,
* just set the interrupt line based on ISTATUS
*/
- qemu_set_irq(cpu->gt_timer_outputs[timeridx],
- (oldval & 4) && !(value & 2));
+ int irqstate = (oldval & 4) && !(value & 2);
+
+ trace_arm_gt_imask_toggle(timeridx, irqstate);
+ qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
}
}
@@ -1715,6 +1726,7 @@ static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
ARMCPU *cpu = arm_env_get_cpu(env);
+ trace_arm_gt_cntvoff_write(value);
raw_write(env, ri, value);
gt_recalc_timer(cpu, GTIMER_VIRT);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 3/3] hw/intc/arm_gicv3: Fix ICC register tracepoints
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
2016-10-06 13:21 ` [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 Peter Maydell
2016-10-06 13:21 ` [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers Peter Maydell
@ 2016-10-06 13:21 ` Peter Maydell
2016-10-06 16:59 ` [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Edgar E. Iglesias
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2016-10-06 13:21 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: patches, Edgar E. Iglesias
Fix some problems with the tracepoints for ICC register reads
and writes:
* tracepoints for ICC_BPR<n>, ICC_AP<n>R<x>, ICC_IGRPEN<n>,
ICC_EIOR<n> were not printing the <n> that indicated whether
the access was to the group 0 or 1 register
* the ICC_IGREPEN1_EL3 read function was not actually calling
the associated tracepoint
* the ICC_BPR<n> write function was incorrectly calling the
tracepoint for ICC_PMR writes
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_cpuif.c | 23 +++++++++++++++--------
hw/intc/trace-events | 14 +++++++-------
2 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 4633172..bca30c4 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -454,7 +454,8 @@ static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
int irq = value & 0xffffff;
int grp;
- trace_gicv3_icc_eoir_write(gicv3_redist_affid(cs), value);
+ trace_gicv3_icc_eoir_write(ri->crm == 8 ? 0 : 1,
+ gicv3_redist_affid(cs), value);
if (ri->crm == 8) {
/* EOIR0 */
@@ -542,7 +543,7 @@ static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
bpr = MIN(bpr, 7);
}
- trace_gicv3_icc_bpr_read(gicv3_redist_affid(cs), bpr);
+ trace_gicv3_icc_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr);
return bpr;
}
@@ -553,7 +554,8 @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
GICv3CPUState *cs = icc_cs_from_env(env);
int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
- trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
+ trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1,
+ gicv3_redist_affid(cs), value);
if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
grp = GICV3_G1NS;
@@ -591,7 +593,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
value = cs->icc_apr[grp][regno];
- trace_gicv3_icc_ap_read(regno, gicv3_redist_affid(cs), value);
+ trace_gicv3_icc_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
return value;
}
@@ -603,7 +605,7 @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
int regno = ri->opc2 & 3;
int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
- trace_gicv3_icc_ap_write(regno, gicv3_redist_affid(cs), value);
+ trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
grp = GICV3_G1NS;
@@ -820,7 +822,8 @@ static uint64_t icc_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri)
}
value = cs->icc_igrpen[grp];
- trace_gicv3_icc_igrpen_read(gicv3_redist_affid(cs), value);
+ trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0,
+ gicv3_redist_affid(cs), value);
return value;
}
@@ -830,7 +833,8 @@ static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
GICv3CPUState *cs = icc_cs_from_env(env);
int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0;
- trace_gicv3_icc_igrpen_write(gicv3_redist_affid(cs), value);
+ trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0,
+ gicv3_redist_affid(cs), value);
if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
grp = GICV3_G1NS;
@@ -843,9 +847,12 @@ static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
static uint64_t icc_igrpen1_el3_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
+ uint64_t value;
/* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */
- return cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1);
+ value = cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1);
+ trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs), value);
+ return value;
}
static void icc_igrpen1_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index f12192c..4a23848 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -84,12 +84,12 @@ gic_acknowledge_irq(int cpu, int irq) "cpu %d acknowledged irq %d"
# hw/intc/arm_gicv3_cpuif.c
gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu %x value 0x%" PRIx64
gicv3_icc_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR write cpu %x value 0x%" PRIx64
-gicv3_icc_bpr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_BPR read cpu %x value 0x%" PRIx64
-gicv3_icc_bpr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_BPR write cpu %x value 0x%" PRIx64
-gicv3_icc_ap_read(int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR read cpu %x value 0x%" PRIx64
-gicv3_icc_ap_write(int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR write cpu %x value 0x%" PRIx64
-gicv3_icc_igrpen_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN read cpu %x value 0x%" PRIx64
-gicv3_icc_igrpen_write(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN write cpu %x value 0x%" PRIx64
+gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d read cpu %x value 0x%" PRIx64
+gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d write cpu %x value 0x%" PRIx64
+gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR%d read cpu %x value 0x%" PRIx64
+gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR%d write cpu %x value 0x%" PRIx64
+gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN%d read cpu %x value 0x%" PRIx64
+gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN%d write cpu %x value 0x%" PRIx64
gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_EL3 read cpu %x value 0x%" PRIx64
gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_EL3 write cpu %x value 0x%" PRIx64
gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR read cpu %x value 0x%" PRIx64
@@ -101,7 +101,7 @@ gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f
gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist) "GICv3 CPU i/f %x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x"
gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu %x value 0x%" PRIx64
gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu %x value 0x%" PRIx64
-gicv3_icc_eoir_write(uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR write cpu %x value 0x%" PRIx64
+gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR%d write cpu %x value 0x%" PRIx64
gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read cpu %x value 0x%" PRIx64
gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read cpu %x value 0x%" PRIx64
gicv3_icc_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICC_DIR write cpu %x value 0x%" PRIx64
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1
2016-10-06 13:21 ` [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 Peter Maydell
@ 2016-10-06 16:55 ` Edgar E. Iglesias
0 siblings, 0 replies; 11+ messages in thread
From: Edgar E. Iglesias @ 2016-10-06 16:55 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, patches
On Thu, Oct 06, 2016 at 02:21:05PM +0100, Peter Maydell wrote:
> MDCCINT_EL1 is part of the DCC debugger communication
> channel between the CPU and an attached external debugger.
> QEMU doesn't implement this, but since Linux may try
> to access this register we need to provide at least
> a dummy implementation.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target-arm/helper.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 25f612d..23792ab 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
> .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
> .access = PL1_RW, .accessfn = access_tda,
> .type = ARM_CP_NOP },
> + /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
> + * Channel but Linux may try to access this register. The 32-bit
> + * alias is DBGDCCINT.
> + */
> + { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
> + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
> + .access = PL1_RW, .accessfn = access_tda,
> + .type = ARM_CP_NOP },
> REGINFO_SENTINEL
> };
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers
2016-10-06 13:21 ` [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers Peter Maydell
@ 2016-10-06 16:55 ` Edgar E. Iglesias
0 siblings, 0 replies; 11+ messages in thread
From: Edgar E. Iglesias @ 2016-10-06 16:55 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, patches
On Thu, Oct 06, 2016 at 02:21:06PM +0100, Peter Maydell wrote:
> Add some useful trace events for the ARM generic timers (notably
> the various register writes and the resulting IRQ line state).
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Makefile.objs | 1 +
> target-arm/helper.c | 20 ++++++++++++++++----
> 2 files changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/Makefile.objs b/Makefile.objs
> index 02fb8e7..69fdd48 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -155,6 +155,7 @@ trace-events-y += hw/alpha/trace-events
> trace-events-y += ui/trace-events
> trace-events-y += audio/trace-events
> trace-events-y += net/trace-events
> +trace-events-y += target-arm/trace-events
> trace-events-y += target-i386/trace-events
> trace-events-y += target-sparc/trace-events
> trace-events-y += target-s390x/trace-events
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 23792ab..5fcdc2b 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1,4 +1,5 @@
> #include "qemu/osdep.h"
> +#include "trace.h"
> #include "cpu.h"
> #include "internals.h"
> #include "exec/gdbstub.h"
> @@ -1560,10 +1561,13 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
> /* Note that this must be unsigned 64 bit arithmetic: */
> int istatus = count - offset >= gt->cval;
> uint64_t nexttick;
> + int irqstate;
>
> gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
> - qemu_set_irq(cpu->gt_timer_outputs[timeridx],
> - (istatus && !(gt->ctl & 2)));
> +
> + irqstate = (istatus && !(gt->ctl & 2));
> + qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
> +
> if (istatus) {
> /* Next transition is when count rolls back over to zero */
> nexttick = UINT64_MAX;
> @@ -1580,11 +1584,13 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
> nexttick = INT64_MAX / GTIMER_SCALE;
> }
> timer_mod(cpu->gt_timer[timeridx], nexttick);
> + trace_arm_gt_recalc(timeridx, irqstate, nexttick);
> } else {
> /* Timer disabled: ISTATUS and timer output always clear */
> gt->ctl &= ~4;
> qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
> timer_del(cpu->gt_timer[timeridx]);
> + trace_arm_gt_recalc_disabled(timeridx);
> }
> }
>
> @@ -1610,6 +1616,7 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
> int timeridx,
> uint64_t value)
> {
> + trace_arm_gt_cval_write(timeridx, value);
> env->cp15.c14_timer[timeridx].cval = value;
> gt_recalc_timer(arm_env_get_cpu(env), timeridx);
> }
> @@ -1629,6 +1636,7 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
> {
> uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
>
> + trace_arm_gt_tval_write(timeridx, value);
> env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
> sextract64(value, 0, 32);
> gt_recalc_timer(arm_env_get_cpu(env), timeridx);
> @@ -1641,6 +1649,7 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> ARMCPU *cpu = arm_env_get_cpu(env);
> uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
>
> + trace_arm_gt_ctl_write(timeridx, value);
> env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
> if ((oldval ^ value) & 1) {
> /* Enable toggled */
> @@ -1649,8 +1658,10 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> /* IMASK toggled: don't need to recalculate,
> * just set the interrupt line based on ISTATUS
> */
> - qemu_set_irq(cpu->gt_timer_outputs[timeridx],
> - (oldval & 4) && !(value & 2));
> + int irqstate = (oldval & 4) && !(value & 2);
> +
> + trace_arm_gt_imask_toggle(timeridx, irqstate);
> + qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
> }
> }
>
> @@ -1715,6 +1726,7 @@ static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
> {
> ARMCPU *cpu = arm_env_get_cpu(env);
>
> + trace_arm_gt_cntvoff_write(value);
> raw_write(env, ri, value);
> gt_recalc_timer(cpu, GTIMER_VIRT);
> }
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
` (2 preceding siblings ...)
2016-10-06 13:21 ` [Qemu-devel] [PATCH 3/3] hw/intc/arm_gicv3: Fix ICC register tracepoints Peter Maydell
@ 2016-10-06 16:59 ` Edgar E. Iglesias
2016-10-06 17:48 ` Peter Maydell
2016-10-11 9:15 ` no-reply
2016-10-11 9:19 ` Peter Maydell
5 siblings, 1 reply; 11+ messages in thread
From: Edgar E. Iglesias @ 2016-10-06 16:59 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, patches
On Thu, Oct 06, 2016 at 02:21:04PM +0100, Peter Maydell wrote:
> This set of three straightforward patches is a preliminary
> for adding virtualization support to the GICv3 emulation:
> * add a (nop implementation of) MDCCINT_EL1, since KVM
> will read/write it on worldswitch
> * fix some bugs in the GICv3 trace events
> * add trace events for the generic timers
> (which I have been using for debugging)
>
> I actually have almost all of the GICv3 virt code written,
> but it currently has bugs which mean that a guest kernel
> under KVM won't boot. Debugging in progress...
That is very cool, we could soon enable EL2 :-)
What kind of issues are you seeing?
FWIW with our out of tree GICv2 virt models we've got issues
with SMP Xen were things go nuts some times with virtual
timer interrupts. Some times they take for ever to hit,
like if we loose events.
Last time I looked at it, I noticed that our GICv2 virt
implementation of the APR regs and EOIR stuff seems totally
bogus (my bad).
Cheers,
Edgar
>
> thanks
> -- PMM
>
> Peter Maydell (3):
> target-arm: Implement dummy MDCCINT_EL1
> target-arm: Add trace events for the generic timers
> hw/intc/arm_gicv3: Fix ICC register tracepoints
>
> Makefile.objs | 1 +
> hw/intc/arm_gicv3_cpuif.c | 23 +++++++++++++++--------
> hw/intc/trace-events | 14 +++++++-------
> target-arm/helper.c | 28 ++++++++++++++++++++++++----
> 4 files changed, 47 insertions(+), 19 deletions(-)
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support
2016-10-06 16:59 ` [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Edgar E. Iglesias
@ 2016-10-06 17:48 ` Peter Maydell
2016-10-06 17:59 ` Peter Maydell
0 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2016-10-06 17:48 UTC (permalink / raw)
To: Edgar E. Iglesias; +Cc: qemu-arm, QEMU Developers, Patch Tracking
On 6 October 2016 at 17:59, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> On Thu, Oct 06, 2016 at 02:21:04PM +0100, Peter Maydell wrote:
>> This set of three straightforward patches is a preliminary
>> for adding virtualization support to the GICv3 emulation:
>> * add a (nop implementation of) MDCCINT_EL1, since KVM
>> will read/write it on worldswitch
>> * fix some bugs in the GICv3 trace events
>> * add trace events for the generic timers
>> (which I have been using for debugging)
>>
>> I actually have almost all of the GICv3 virt code written,
>> but it currently has bugs which mean that a guest kernel
>> under KVM won't boot. Debugging in progress...
>
>
> That is very cool, we could soon enable EL2 :-)
>
> What kind of issues are you seeing?
The guest kernel just sits there like a lemon without printing
anything. Trying the kvm-unit-tests, the simple 'setup' test
works OK, but the one which tries to PSCI boot other SMP cores
fails.
> FWIW with our out of tree GICv2 virt models we've got issues
> with SMP Xen were things go nuts some times with virtual
> timer interrupts. Some times they take for ever to hit,
> like if we loose events.
Have you tried undoing the broken bit of virt.c that
marks the timer interrupts as edge triggered ?
(see 'hw/arm/virt: Don't incorrectly claim architectural timer
to be edge-triggered' in the branch below).
> Last time I looked at it, I noticed that our GICv2 virt
> implementation of the APR regs and EOIR stuff seems totally
> bogus (my bad).
Those were dodgy in original GICv2 for a long time...
https://git.linaro.org/people/peter.maydell/qemu-arm.git gicv3-virt
if you're interested in looking at my work-in-progress, though
as I say it is clearly badly broken right now.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support
2016-10-06 17:48 ` Peter Maydell
@ 2016-10-06 17:59 ` Peter Maydell
0 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2016-10-06 17:59 UTC (permalink / raw)
To: Edgar E. Iglesias; +Cc: qemu-arm, QEMU Developers, Patch Tracking
On 6 October 2016 at 18:48, Peter Maydell <peter.maydell@linaro.org> wrote:
> Trying the kvm-unit-tests, the simple 'setup' test
> works OK, but the one which tries to PSCI boot other SMP cores
> fails.
This is probably because the outer QEMU is intercepting those
PSCI calls and executing them itself rather than allowing the
EL2 guest to do the work...
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
` (3 preceding siblings ...)
2016-10-06 16:59 ` [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Edgar E. Iglesias
@ 2016-10-11 9:15 ` no-reply
2016-10-11 9:19 ` Peter Maydell
5 siblings, 0 replies; 11+ messages in thread
From: no-reply @ 2016-10-11 9:15 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-arm, qemu-devel, edgar.iglesias, patches
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Message-id: 1475760067-25756-1-git-send-email-peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
make J=8 docker-test-quick@centos6
make J=8 docker-test-mingw@fedora
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
467ec98 hw/intc/arm_gicv3: Fix ICC register tracepoints
b348ced target-arm: Add trace events for the generic timers
0608753 target-arm: Implement dummy MDCCINT_EL1
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '65cc4d2748a2c2e6f27f1cf39e07a5dbabd80ebf'
BUILD centos6
ARCHIVE qemu.tgz
ARCHIVE dtc.tgz
COPY RUNNER
RUN test-quick in centos6
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
ccache-3.1.6-2.el6.x86_64
epel-release-6-8.noarch
gcc-4.4.7-17.el6.x86_64
git-1.7.1-4.el6_7.1.x86_64
glib2-devel-2.28.8-5.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
make-3.81-23.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
tar-1.23-15.el6_8.x86_64
zlib-devel-1.2.3-29.el6.x86_64
Environment variables:
PACKAGES=libfdt-devel ccache tar git make gcc g++ zlib-devel glib2-devel SDL-devel pixman-devel epel-release
HOSTNAME=371ec705fdba
TERM=xterm
MAKEFLAGS= -j8
HISTSIZE=1000
J=8
USER=root
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
MAIL=/var/spool/mail/root
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
LANG=en_US.UTF-8
TARGET_LIST=
HISTCONTROL=ignoredups
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
LOGNAME=root
LESSOPEN=||/usr/bin/lesspipe.sh %s
FEATURES= dtc
DEBUG=
G_BROKEN_FILENAMES=1
CCACHE_HASHDIR=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install
No C++ compiler available; disabling C++ specific optional code
Install prefix /var/tmp/qemu-build/install
BIOS directory /var/tmp/qemu-build/install/share/qemu
binary directory /var/tmp/qemu-build/install/bin
library directory /var/tmp/qemu-build/install/lib
module directory /var/tmp/qemu-build/install/lib/qemu
libexec directory /var/tmp/qemu-build/install/libexec
include directory /var/tmp/qemu-build/install/include
config directory /var/tmp/qemu-build/install/etc
local state directory /var/tmp/qemu-build/install/var
Manual directory /var/tmp/qemu-build/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /tmp/qemu-test/src
C compiler cc
Host C compiler cc
C++ compiler
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wmissing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all
LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
tcg debug enabled no
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
pixman system
SDL support yes (1.2.14)
GTK support no
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support no
GNUTLS rnd no
libgcrypt no
libgcrypt kdf no
nettle no
nettle kdf no
libtasn1 no
curses support no
virgl support no
curl support no
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
VNC support yes
VNC SASL support no
VNC JPEG support no
VNC PNG support no
xen support no
brlapi support no
bluez support no
Documentation no
PIE yes
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support yes
Install blobs yes
KVM support yes
RDMA support no
TCG interpreter no
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support no
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
Trace backends log
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
GlusterFS support no
Archipelago support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough yes
QOM debugging yes
lzo support no
snappy support no
bzip2 support no
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
GEN x86_64-softmmu/config-devices.mak.tmp
GEN aarch64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN x86_64-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN qmp-introspect.h
make: *** No rule to make target `/tmp/qemu-test/src/target-arm/trace-events', needed by `/var/tmp/qemu-build/trace-events-all'. Stop.
make: *** Waiting for unfinished jobs....
tests/docker/Makefile.include:107: recipe for target 'docker-run-test-quick@centos6' failed
make: *** [docker-run-test-quick@centos6] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
` (4 preceding siblings ...)
2016-10-11 9:15 ` no-reply
@ 2016-10-11 9:19 ` Peter Maydell
5 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2016-10-11 9:19 UTC (permalink / raw)
To: qemu-arm, QEMU Developers; +Cc: Edgar E. Iglesias, Patch Tracking
On 6 October 2016 at 14:21, Peter Maydell <peter.maydell@linaro.org> wrote:
> This set of three straightforward patches is a preliminary
> for adding virtualization support to the GICv3 emulation:
> * add a (nop implementation of) MDCCINT_EL1, since KVM
> will read/write it on worldswitch
> * fix some bugs in the GICv3 trace events
> * add trace events for the generic timers
> (which I have been using for debugging)
>
> I actually have almost all of the GICv3 virt code written,
> but it currently has bugs which mean that a guest kernel
> under KVM won't boot. Debugging in progress...
>
> thanks
> -- PMM
>
> Peter Maydell (3):
> target-arm: Implement dummy MDCCINT_EL1
> target-arm: Add trace events for the generic timers
> hw/intc/arm_gicv3: Fix ICC register tracepoints
>
> Makefile.objs | 1 +
> hw/intc/arm_gicv3_cpuif.c | 23 +++++++++++++++--------
> hw/intc/trace-events | 14 +++++++-------
> target-arm/helper.c | 28 ++++++++++++++++++++++++----
> 4 files changed, 47 insertions(+), 19 deletions(-)
Patchew points out that I forgot to git-add target-arm/trace-events.
Will resend shortly.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-10-11 11:01 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
2016-10-06 13:21 ` [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 Peter Maydell
2016-10-06 16:55 ` Edgar E. Iglesias
2016-10-06 13:21 ` [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers Peter Maydell
2016-10-06 16:55 ` Edgar E. Iglesias
2016-10-06 13:21 ` [Qemu-devel] [PATCH 3/3] hw/intc/arm_gicv3: Fix ICC register tracepoints Peter Maydell
2016-10-06 16:59 ` [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Edgar E. Iglesias
2016-10-06 17:48 ` Peter Maydell
2016-10-06 17:59 ` Peter Maydell
2016-10-11 9:15 ` no-reply
2016-10-11 9:19 ` Peter Maydell
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