[Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6

[Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6

[Nikunj A Dadhania]

This series contains 15 new instructions for POWER9 ISA3.0
   Vector Extend Sign
   Vector Integer Negate 
   VSX Scalar Compare
   Vector Byte-Reverse

Patches:
01:
    vextsb2w: Vector Extend Sign Byte To Word
    vextsh2w: Vector Extend Sign Halfword To Word
    vextsb2d: Vector Extend Sign Byte To Doubleword
    vextsh2d: Vector Extend Sign Halfword To Doubleword
    vextsw2d: Vector Extend Sign Word To Doubleword
02:
    vnegw: Vector Negate Word
    vnegd: Vector Negate Doubleword
03:
    xxbrh: VSX Vector Byte-Reverse Halfword
    xxbrw: VSX Vector Byte-Reverse Word
    xxbrd: VSX Vector Byte-Reverse Doubleword
    xxbrq: VSX Vector Byte-Reverse Quadword
04:
    xscmpeqdp: VSX Scalar Compare Equal Double-Precision
    xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision
    xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision
    xscmpnedp: VSX Scalar Compare Not Equal Double-Precision

Nikunj A Dadhania (3):
  target-ppc: implement vexts[bh]2w and vexts[bhw]2d
  target-ppc: implement vnegw/d instructions
  target-ppc: implement xxbr[qdwh] instruction

Sandipan Das (1):
  target-ppc: Add xscmp[eq,gt,ge,ne]dp instructions

 target-ppc/fpu_helper.c             | 48 +++++++++++++++++++++++
 target-ppc/helper.h                 | 11 ++++++
 target-ppc/int_helper.c             | 27 +++++++++++++
 target-ppc/translate.c              | 32 +++++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  7 ++++
 target-ppc/translate/vmx-ops.inc.c  |  7 ++++
 target-ppc/translate/vsx-impl.inc.c | 78 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  | 12 ++++++
 8 files changed, 222 insertions(+)

-- 
2.7.4

[Qemu-devel] [PATCH 1/4] target-ppc: implement vexts[bh]2w and vexts[bhw]2d

[Nikunj A Dadhania]

Vector Extend Sign Instructions:

vextsb2w: Vector Extend Sign Byte To Word
vextsh2w: Vector Extend Sign Halfword To Word
vextsb2d: Vector Extend Sign Byte To Doubleword
vextsh2d: Vector Extend Sign Halfword To Doubleword
vextsw2d: Vector Extend Sign Word To Doubleword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  5 +++++
 target-ppc/int_helper.c             | 15 +++++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  5 +++++
 target-ppc/translate/vmx-ops.inc.c  |  5 +++++
 4 files changed, 30 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 796ad45..04c6421 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -267,6 +267,11 @@ DEF_HELPER_3(vinsertb, void, avr, avr, i32)
 DEF_HELPER_3(vinserth, void, avr, avr, i32)
 DEF_HELPER_3(vinsertw, void, avr, avr, i32)
 DEF_HELPER_3(vinsertd, void, avr, avr, i32)
+DEF_HELPER_2(vextsb2w, void, avr, avr)
+DEF_HELPER_2(vextsh2w, void, avr, avr)
+DEF_HELPER_2(vextsb2d, void, avr, avr)
+DEF_HELPER_2(vextsh2d, void, avr, avr)
+DEF_HELPER_2(vextsw2d, void, avr, avr)
 DEF_HELPER_2(vupkhpx, void, avr, avr)
 DEF_HELPER_2(vupklpx, void, avr, avr)
 DEF_HELPER_2(vupkhsb, void, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 202854f..b393c30 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1934,6 +1934,21 @@ VEXTRACT(uw, u32)
 VEXTRACT(d, u64)
 #undef VEXTRACT
 
+#define VEXT_SIGNED(name, element, mask, cast, recast)              \
+void helper_##name(ppc_avr_t *r, ppc_avr_t *b)                      \
+{                                                                   \
+    int i;                                                          \
+    VECTOR_FOR_INORDER_I(i, element) {                              \
+        r->element[i] = (recast)((cast)(b->element[i] & mask));     \
+    }                                                               \
+}
+VEXT_SIGNED(vextsb2w, s32, UINT8_MAX, char, int32_t)
+VEXT_SIGNED(vextsb2d, s64, UINT8_MAX, char, int64_t)
+VEXT_SIGNED(vextsh2w, s32, UINT16_MAX, int16_t, int32_t)
+VEXT_SIGNED(vextsh2d, s64, UINT16_MAX, int16_t, int64_t)
+VEXT_SIGNED(vextsw2d, s64, UINT32_MAX, int32_t, int64_t)
+#undef VEXT_SIGNED
+
 #define VSPLTI(suffix, element, splat_type)                     \
     void helper_vspltis##suffix(ppc_avr_t *r, uint32_t splat)   \
     {                                                           \
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index 25cd073..c8998f3 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -815,6 +815,11 @@ GEN_VXFORM_NOA(vclzb, 1, 28)
 GEN_VXFORM_NOA(vclzh, 1, 29)
 GEN_VXFORM_NOA(vclzw, 1, 30)
 GEN_VXFORM_NOA(vclzd, 1, 31)
+GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
+GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
+GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
+GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
+GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
 GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
 GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
 GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index ac1dc9b..68cba3e 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -215,6 +215,11 @@ GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
 GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
                                                PPC_ALTIVEC),
 GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
+GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
+GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11),
+GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18),
+GEN_VXFORM_300_EO(vextsh2d, 0x01, 0x18, 0x19),
+GEN_VXFORM_300_EO(vextsw2d, 0x01, 0x18, 0x1A),
 GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
 GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
 GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
-- 
2.7.4

[Qemu-devel] [PATCH 2/4] target-ppc: implement vnegw/d instructions

[Nikunj A Dadhania]

Vector Integer Negate Instructions:

vnegw: Vector Negate Word
vnegd: Vector Negate Doubleword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  2 ++
 target-ppc/int_helper.c             | 12 ++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  2 ++
 target-ppc/translate/vmx-ops.inc.c  |  2 ++
 4 files changed, 18 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 04c6421..5fcc546 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -272,6 +272,8 @@ DEF_HELPER_2(vextsh2w, void, avr, avr)
 DEF_HELPER_2(vextsb2d, void, avr, avr)
 DEF_HELPER_2(vextsh2d, void, avr, avr)
 DEF_HELPER_2(vextsw2d, void, avr, avr)
+DEF_HELPER_2(vnegw, void, avr, avr)
+DEF_HELPER_2(vnegd, void, avr, avr)
 DEF_HELPER_2(vupkhpx, void, avr, avr)
 DEF_HELPER_2(vupklpx, void, avr, avr)
 DEF_HELPER_2(vupkhsb, void, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index b393c30..76cf9b8 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1949,6 +1949,18 @@ VEXT_SIGNED(vextsh2d, s64, UINT16_MAX, int16_t, int64_t)
 VEXT_SIGNED(vextsw2d, s64, UINT32_MAX, int32_t, int64_t)
 #undef VEXT_SIGNED
 
+#define VNEG(name, element, mask)                                   \
+void helper_##name(ppc_avr_t *r, ppc_avr_t *b)                      \
+{                                                                   \
+    int i;                                                          \
+    VECTOR_FOR_INORDER_I(i, element) {                              \
+        r->element[i] = (~(b->element[i]) + 1) & mask;              \
+    }                                                               \
+}
+VNEG(vnegw, s32, UINT32_MAX)
+VNEG(vnegd, s64, UINT64_MAX)
+#undef VNEG
+
 #define VSPLTI(suffix, element, splat_type)                     \
     void helper_vspltis##suffix(ppc_avr_t *r, uint32_t splat)   \
     {                                                           \
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index c8998f3..563f101 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -815,6 +815,8 @@ GEN_VXFORM_NOA(vclzb, 1, 28)
 GEN_VXFORM_NOA(vclzh, 1, 29)
 GEN_VXFORM_NOA(vclzw, 1, 30)
 GEN_VXFORM_NOA(vclzd, 1, 31)
+GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
+GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
 GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
 GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
 GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index 68cba3e..ab64ab2 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -215,6 +215,8 @@ GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
 GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
                                                PPC_ALTIVEC),
 GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
+GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
+GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
 GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
 GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11),
 GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18),
-- 
2.7.4

[Qemu-devel] [PATCH 3/4] target-ppc: implement xxbr[qdwh] instruction

[Nikunj A Dadhania]

Add required helpers (GEN_XX2FORM_EO) for supporting this instruction.

xxbrh: VSX Vector Byte-Reverse Halfword
xxbrw: VSX Vector Byte-Reverse Word
xxbrd: VSX Vector Byte-Reverse Doubleword
xxbrq: VSX Vector Byte-Reverse Quadword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c              | 32 ++++++++++++++++
 target-ppc/translate/vsx-impl.inc.c | 74 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  |  8 ++++
 3 files changed, 114 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index dab8f19..94989b2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -376,6 +376,9 @@ GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2)     \
 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
 
+#define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
+GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
+
 typedef struct opcode_t {
     unsigned char opc1, opc2, opc3, opc4;
 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
@@ -662,6 +665,21 @@ EXTRACT_HELPER(IMM8, 11, 8);
     },                                                                        \
     .oname = stringify(name),                                                 \
 }
+#define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
+{                                                                             \
+    .opc1 = op1,                                                              \
+    .opc2 = op2,                                                              \
+    .opc3 = op3,                                                              \
+    .opc4 = op4,                                                              \
+    .handler = {                                                              \
+        .inval1  = invl,                                                      \
+        .type = _typ,                                                         \
+        .type2 = _typ2,                                                       \
+        .handler = &gen_##name,                                               \
+        .oname = onam,                                                        \
+    },                                                                        \
+    .oname = onam,                                                            \
+}
 #else
 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
 {                                                                             \
@@ -720,6 +738,20 @@ EXTRACT_HELPER(IMM8, 11, 8);
     },                                                                        \
     .oname = stringify(name),                                                 \
 }
+#define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
+{                                                                             \
+    .opc1 = op1,                                                              \
+    .opc2 = op2,                                                              \
+    .opc3 = op3,                                                              \
+    .opc4 = op4,                                                              \
+    .handler = {                                                              \
+        .inval1  = invl,                                                      \
+        .type = _typ,                                                         \
+        .type2 = _typ2,                                                       \
+        .handler = &gen_##name,                                               \
+    },                                                                        \
+    .oname = onam,                                                            \
+}
 #endif
 
 /* SPR load/store helpers */
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 23ec1e1..d510842 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -132,6 +132,22 @@ static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
     tcg_temp_free_i64(mask);
 }
 
+static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl,
+                          TCGv_i64 inh, TCGv_i64 inl)
+{
+    TCGv_i64 hi = tcg_temp_new_i64();
+    TCGv_i64 lo = tcg_temp_new_i64();
+
+    tcg_gen_bswap64_i64(hi, inh);
+    tcg_gen_bswap64_i64(lo, inl);
+    tcg_gen_shri_i64(outh, hi, 32);
+    tcg_gen_deposit_i64(outh, outh, hi, 32, 32);
+    tcg_gen_shri_i64(outl, lo, 32);
+    tcg_gen_deposit_i64(outl, outl, lo, 32, 32);
+
+    tcg_temp_free_i64(hi);
+    tcg_temp_free_i64(lo);
+}
 static void gen_lxvh8x(DisasContext *ctx)
 {
     TCGv EA;
@@ -717,6 +733,64 @@ GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
 
+static void gen_xxbrd(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    tcg_gen_bswap64_i64(xth, xbh);
+    tcg_gen_bswap64_i64(xtl, xbl);
+}
+
+static void gen_xxbrh(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_bswap16x8(xth, xtl, xbh, xbl);
+}
+
+static void gen_xxbrq(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    tcg_gen_bswap64_i64(xth, xbl);
+    tcg_gen_bswap64_i64(xtl, xbh);
+}
+
+static void gen_xxbrw(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_bswap32x4(xth, xtl, xbh, xbl);
+}
+
 #define VSX_LOGICAL(name, tcg_op)                                    \
 static void glue(gen_, name)(DisasContext * ctx)                     \
     {                                                                \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 10eb4b9..af0d27e 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -39,6 +39,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
 
+#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2)                          \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
+
 #define GEN_XX3FORM(name, opc2, opc3, fl2)                           \
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
@@ -222,6 +226,10 @@ GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
+GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300),
 
 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
 GEN_XX3FORM(name, opc2, opc3, fl2)
-- 
2.7.4

[Qemu-devel] [PATCH 4/4] target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions

[Nikunj A Dadhania]

From: Sandipan Das <sandipandas1990@gmail.com>

xscmpeqdp: VSX Scalar Compare Equal Double-Precision
xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision
xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision
xscmpnedp: VSX Scalar Compare Not Equal Double-Precision

Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
[ Fix LE case using msr_le ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/fpu_helper.c             | 48 +++++++++++++++++++++++++++++++++++++
 target-ppc/helper.h                 |  4 ++++
 target-ppc/translate/vsx-impl.inc.c |  4 ++++
 target-ppc/translate/vsx-ops.inc.c  |  4 ++++
 4 files changed, 60 insertions(+)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index b0760f0..87c17d9 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2362,6 +2362,54 @@ VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0)
 VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0)
 VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0)
 
+/* VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
+ *   op    - instruction mnemonic
+ *   cmp   - comparison operation
+ *   exp   - expected result of comparison
+ *   svxvc - set VXVC bit
+ */
+#define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc)                                \
+void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
+{                                                                             \
+    ppc_vsr_t xt, xa, xb;                                                     \
+                                                                              \
+    getVSR(xA(opcode), &xa, env);                                             \
+    getVSR(xB(opcode), &xb, env);                                             \
+    getVSR(xT(opcode), &xt, env);                                             \
+                                                                              \
+    if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||                            \
+                 float64_is_any_nan(xb.VsrD(0)))) {                           \
+        if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) ||          \
+            float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) {          \
+            float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
+        }                                                                     \
+        if (svxvc) {                                                          \
+            float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);              \
+        }                                                                     \
+    } else {                                                                  \
+        if (float64_##cmp(xb.VsrD(0), xa.VsrD(0), &env->fp_status) == exp) {  \
+            if (msr_le) {                                                     \
+                xt.VsrD(0) = 0;                                               \
+                xt.VsrD(1) = -1;                                              \
+            } else {                                                          \
+                xt.VsrD(0) = -1;                                              \
+                xt.VsrD(1) = 0;                                               \
+            }                                                                 \
+        } else {                                                              \
+            xt.VsrD(0) = 0;                                                   \
+            xt.VsrD(1) = 0;                                                   \
+        }                                                                     \
+    }                                                                         \
+                                                                              \
+    putVSR(xT(opcode), &xt, env);                                             \
+    helper_float_check_status(env);                                           \
+}
+
+VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
+VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
+VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
+VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
+
 #define VSX_SCALAR_CMP(op, ordered)                                      \
 void helper_##op(CPUPPCState *env, uint32_t opcode)                      \
 {                                                                        \
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5fcc546..0337292 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -389,6 +389,10 @@ DEF_HELPER_2(xsnmaddadp, void, env, i32)
 DEF_HELPER_2(xsnmaddmdp, void, env, i32)
 DEF_HELPER_2(xsnmsubadp, void, env, i32)
 DEF_HELPER_2(xsnmsubmdp, void, env, i32)
+DEF_HELPER_2(xscmpeqdp, void, env, i32)
+DEF_HELPER_2(xscmpgtdp, void, env, i32)
+DEF_HELPER_2(xscmpgedp, void, env, i32)
+DEF_HELPER_2(xscmpnedp, void, env, i32)
 DEF_HELPER_2(xscmpodp, void, env, i32)
 DEF_HELPER_2(xscmpudp, void, env, i32)
 DEF_HELPER_2(xsmaxdp, void, env, i32)
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index d510842..3ee20b4 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -620,6 +620,10 @@ GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)
 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index af0d27e..202c557 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -114,6 +114,10 @@ GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
+GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
+GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
+GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
+GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300),
 GEN_XX2IFORM(xscmpodp,  0x0C, 0x05, PPC2_VSX),
 GEN_XX2IFORM(xscmpudp,  0x0C, 0x04, PPC2_VSX),
 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
-- 
2.7.4

Re: [Qemu-devel] [PATCH 1/4] target-ppc: implement vexts[bh]2w and vexts[bhw]2d

[Richard Henderson]

On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
> +VEXT_SIGNED(vextsb2w, s32, UINT8_MAX, char, int32_t)
> +VEXT_SIGNED(vextsb2d, s64, UINT8_MAX, char, int64_t)

char has target-dependent sign.  Use int8_t.


r~

Re: [Qemu-devel] [PATCH 2/4] target-ppc: implement vnegw/d instructions

[Richard Henderson]

On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
> +        r->element[i] = (~(b->element[i]) + 1) & mask;              \

Any reason you're not writing this as a proper negate?


r~

Re: [Qemu-devel] [PATCH 1/4] target-ppc: implement vexts[bh]2w and vexts[bhw]2d

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
>> +VEXT_SIGNED(vextsb2w, s32, UINT8_MAX, char, int32_t)
>> +VEXT_SIGNED(vextsb2d, s64, UINT8_MAX, char, int64_t)
>
> char has target-dependent sign.  Use int8_t.

Sure. will change.

Regards
Nikunj

Re: [Qemu-devel] [PATCH 2/4] target-ppc: implement vnegw/d instructions

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
>> +        r->element[i] = (~(b->element[i]) + 1) & mask;              \
>
> Any reason you're not writing this as a proper negate?

No particular reason, I was just trying to mimic the pseudo code in the
ISA.

r->element[i] = -b->element[i];

Should be fine as well. 

Regards,
Nikunj

Re: [Qemu-devel] [PATCH 3/4] target-ppc: implement xxbr[qdwh] instruction

[Richard Henderson]

On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
> +static void gen_xxbrq(DisasContext *ctx)
> +{
> +    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
> +    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
> +    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
> +    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
> +
> +    if (unlikely(!ctx->vsx_enabled)) {
> +        gen_exception(ctx, POWERPC_EXCP_VSXU);
> +        return;
> +    }
> +    tcg_gen_bswap64_i64(xth, xbl);
> +    tcg_gen_bswap64_i64(xtl, xbh);
> +}

You need a temporary for the case of T==B.  You don't want to overwrite XBH 
with XTH before you consume the input.


r~

Re: [Qemu-devel] [PATCH 3/4] target-ppc: implement xxbr[qdwh] instruction

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
>> +static void gen_xxbrq(DisasContext *ctx)
>> +{
>> +    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
>> +    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
>> +    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
>> +    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
>> +
>> +    if (unlikely(!ctx->vsx_enabled)) {
>> +        gen_exception(ctx, POWERPC_EXCP_VSXU);
>> +        return;
>> +    }
>> +    tcg_gen_bswap64_i64(xth, xbl);
>> +    tcg_gen_bswap64_i64(xtl, xbh);
>> +}
>
> You need a temporary for the case of T==B.  You don't want to overwrite XBH 
> with XTH before you consume the input.

Ah.. right. Sure will change.

Regards,
Nikunj

Re: [Qemu-devel] [PATCH 4/4] target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions

[Richard Henderson]

On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
> +#define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc)                                \
> +void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
> +{                                                                             \
> +    ppc_vsr_t xt, xa, xb;                                                     \
> +                                                                              \
> +    getVSR(xA(opcode), &xa, env);                                             \
> +    getVSR(xB(opcode), &xb, env);                                             \
> +    getVSR(xT(opcode), &xt, env);                                             \
> +                                                                              \
> +    if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||                            \
> +                 float64_is_any_nan(xb.VsrD(0)))) {                           \
> +        if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) ||          \
> +            float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) {          \
> +            float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
> +        }                                                                     \
> +        if (svxvc) {                                                          \
> +            float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);              \
> +        }                                                                     \
> +    } else {                                                                  \
> +        if (float64_##cmp(xb.VsrD(0), xa.VsrD(0), &env->fp_status) == exp) {  \
> +            if (msr_le) {                                                     \
> +                xt.VsrD(0) = 0;                                               \
> +                xt.VsrD(1) = -1;                                              \
> +            } else {                                                          \
> +                xt.VsrD(0) = -1;                                              \
> +                xt.VsrD(1) = 0;                                               \
> +            }                                                                 \
> +        } else {                                                              \
> +            xt.VsrD(0) = 0;                                                   \
> +            xt.VsrD(1) = 0;                                                   \
> +        }                                                                     \
> +    }                                                                         \
> +                                                                              \
> +    putVSR(xT(opcode), &xt, env);                                             \
> +    helper_float_check_status(env);                                           \
> +}

I think you should be checking for NaN after the compare, and seeing that 
env->fp_status.float_exception_flags is non-zero.  C.f. FPU_FCTI.  Or in 
general, the coding structure used by target-tricore:

   result = float*op(args...)
   flags = get_float_exception_flags(&env->fp_status);
   if (unlikely(flags)) {
     set_float_exception_flags(&env->fp_status, 0);
     // special cases for nans, sometimes modifying result
     float_check_status(env, flags, GETPC())
   }
   return result // or putVSR as appropriate

Of course, the same can be said for other places in fpu_helper.c, where this 
detail has been previously missed.

And, unrelated, but a reminder for future cleanup: the fmadd, fmsub, fnmadd, 
and fnmsub helpers should be rewritten to use float64_muladd.  To be fair, I 
think these were written before we had proper fused multiply-add support within 
softfloat.


r~

Re: [Qemu-devel] [PATCH 4/4] target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
>> +#define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc)                                \
>> +void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
>> +{                                                                             \
>> +    ppc_vsr_t xt, xa, xb;                                                     \
>> +                                                                              \
>> +    getVSR(xA(opcode), &xa, env);                                             \
>> +    getVSR(xB(opcode), &xb, env);                                             \
>> +    getVSR(xT(opcode), &xt, env);                                             \
>> +                                                                              \
>> +    if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||                            \
>> +                 float64_is_any_nan(xb.VsrD(0)))) {                           \
>> +        if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) ||          \
>> +            float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) {          \
>> +            float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
>> +        }                                                                     \
>> +        if (svxvc) {                                                          \
>> +            float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);              \
>> +        }                                                                     \
>> +    } else {                                                                  \
>> +        if (float64_##cmp(xb.VsrD(0), xa.VsrD(0), &env->fp_status) == exp) {  \
>> +            if (msr_le) {                                                     \
>> +                xt.VsrD(0) = 0;                                               \
>> +                xt.VsrD(1) = -1;                                              \
>> +            } else {                                                          \
>> +                xt.VsrD(0) = -1;                                              \
>> +                xt.VsrD(1) = 0;                                               \
>> +            }                                                                 \
>> +        } else {                                                              \
>> +            xt.VsrD(0) = 0;                                                   \
>> +            xt.VsrD(1) = 0;                                                   \
>> +        }                                                                     \
>> +    }                                                                         \
>> +                                                                              \
>> +    putVSR(xT(opcode), &xt, env);                                             \
>> +    helper_float_check_status(env);                                           \
>> +}
>
> I think you should be checking for NaN after the compare, and seeing that 
> env->fp_status.float_exception_flags is non-zero.  C.f. FPU_FCTI.  Or in 
> general, the coding structure used by target-tricore:
>
>    result = float*op(args...)
>    flags = get_float_exception_flags(&env->fp_status);
>    if (unlikely(flags)) {
>      set_float_exception_flags(&env->fp_status, 0);
>      // special cases for nans, sometimes modifying result
>      float_check_status(env, flags, GETPC())
>    }
>    return result // or putVSR as appropriate
>
> Of course, the same can be said for other places in fpu_helper.c, where this 
> detail has been previously missed.

Yes, I had noticed that, but didn't want to change the behaviour as I am
not expert here. I will update and send a new revision.

> And, unrelated, but a reminder for future cleanup: the fmadd, fmsub, fnmadd, 
> and fnmsub helpers should be rewritten to use float64_muladd.  To be fair, I 
> think these were written before we had proper fused multiply-add support within 
> softfloat.

Sure. Will add that to my todo list.

Regards
Nikunj

Re: [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6

[no-reply]

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6
Message-id: 1475866623-16841-1-git-send-email-nikunj@linux.vnet.ibm.com
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
15c00cc target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions
8ef222f target-ppc: implement xxbr[qdwh] instruction
534bb80 target-ppc: implement vnegw/d instructions
e761e8d target-ppc: implement vexts[bh]2w and vexts[bhw]2d

=== OUTPUT BEGIN ===
Checking PATCH 1/4: target-ppc: implement vexts[bh]2w and vexts[bhw]2d...
Checking PATCH 2/4: target-ppc: implement vnegw/d instructions...
Checking PATCH 3/4: target-ppc: implement xxbr[qdwh] instruction...
ERROR: Macros with complex values should be enclosed in parenthesis
#173: FILE: target-ppc/translate/vsx-ops.inc.c:42:
+#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2)                          \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)

total: 1 errors, 0 warnings, 156 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 4/4: target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org

Re: [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6

[Nikunj A Dadhania]

no-reply@patchew.org writes:
> Checking PATCH 3/4: target-ppc: implement xxbr[qdwh] instruction...
> ERROR: Macros with complex values should be enclosed in parenthesis
> #173: FILE: target-ppc/translate/vsx-ops.inc.c:42:
> +#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2)                          \
> +GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
> +GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
>

Check patch doesn't like

#define FOO(x) \
BAR(x), \
BAR(x+1)

If I get rid of the "," the error goes away, which is not correct
for this use case. It is a false positive.

> total: 1 errors, 0 warnings, 156 lines checked
>
> Your patch has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
>
> Checking PATCH 4/4: target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions...
> === OUTPUT END ===
>
> Test command exited with code: 1
>

Regards
Nikunj