* [PATCH v3 1/3] PCI: rockchip: Provide captured slot power limit and scale
@ 2016-10-12 2:05 ` Shawn Lin
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Lin @ 2016-10-12 2:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, linux-rockchip, Rajat Jain, Wenrui Li, Brian Norris,
Shawn Lin
If vpcie3v3 is available, we could provide these information
via RC's configure register to make EP able to know the power
limit.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v3:
- rebase the code since it isn't cleanly applied again.
Changes in v2:
- rebase the code since it isn't cleanly applied after Bjorn's cleanup
drivers/pci/host/pcie-rockchip.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index db917c7..a67ff9e 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -135,6 +135,10 @@
#define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
#define PCIE_RC_CONFIG_SCC_SHIFT 16
+#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
+#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
@@ -398,6 +402,40 @@ static struct pci_ops rockchip_pcie_ops = {
.write = rockchip_pcie_wr_conf,
};
+static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip_pcie)
+{
+ u32 status, curr, scale, power;
+
+ if (IS_ERR(rockchip_pcie->vpcie3v3))
+ return;
+
+ /*
+ * Set RC's captured slot power limit and scale if
+ * vpcie3v3 available. The default values are both zero
+ * which means the software should set these two according
+ * to the actual power supply.
+ */
+ curr = regulator_get_current_limit(rockchip_pcie->vpcie3v3);
+ if (curr > 0) {
+ scale = 3; /* 0.001x */
+ curr = curr / 1000; /* convert to mA */
+ power = (curr * 3300) / 1000; /* milliwatt */
+ while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
+ if (!scale) {
+ dev_warn(rockchip_pcie->dev, "invalid power supply\n");
+ return;
+ }
+ scale--;
+ power = power / 10;
+ }
+
+ status = rockchip_pcie_readl(rockchip_pcie, PCIE_RC_CONFIG_DCR);
+ status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
+ (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
+ rockchip_pcie_writel(rockchip_pcie, PCIE_RC_CONFIG_DCR, status);
+ }
+}
+
/**
* rockchip_pcie_init_port - Initialize hardware
* @rockchip_pcie: PCIe port information
@@ -500,6 +538,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip_pcie)
(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
rockchip_pcie_writel(rockchip_pcie, PCIE_CORE_CTRL_PLC1, status);
+ rockchip_pcie_set_power_limit(rockchip_pcie);
+
/* Enable Gen1 training */
rockchip_pcie_writel(rockchip_pcie, PCIE_CLIENT_CONFIG,
PCIE_CLIENT_LINK_TRAIN_ENABLE);
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 1/3] PCI: rockchip: Provide captured slot power limit and scale
@ 2016-10-12 2:05 ` Shawn Lin
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Lin @ 2016-10-12 2:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Wenrui Li, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin,
Brian Norris, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rajat Jain
If vpcie3v3 is available, we could provide these information
via RC's configure register to make EP able to know the power
limit.
Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v3:
- rebase the code since it isn't cleanly applied again.
Changes in v2:
- rebase the code since it isn't cleanly applied after Bjorn's cleanup
drivers/pci/host/pcie-rockchip.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index db917c7..a67ff9e 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -135,6 +135,10 @@
#define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
#define PCIE_RC_CONFIG_SCC_SHIFT 16
+#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
+#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
@@ -398,6 +402,40 @@ static struct pci_ops rockchip_pcie_ops = {
.write = rockchip_pcie_wr_conf,
};
+static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip_pcie)
+{
+ u32 status, curr, scale, power;
+
+ if (IS_ERR(rockchip_pcie->vpcie3v3))
+ return;
+
+ /*
+ * Set RC's captured slot power limit and scale if
+ * vpcie3v3 available. The default values are both zero
+ * which means the software should set these two according
+ * to the actual power supply.
+ */
+ curr = regulator_get_current_limit(rockchip_pcie->vpcie3v3);
+ if (curr > 0) {
+ scale = 3; /* 0.001x */
+ curr = curr / 1000; /* convert to mA */
+ power = (curr * 3300) / 1000; /* milliwatt */
+ while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
+ if (!scale) {
+ dev_warn(rockchip_pcie->dev, "invalid power supply\n");
+ return;
+ }
+ scale--;
+ power = power / 10;
+ }
+
+ status = rockchip_pcie_readl(rockchip_pcie, PCIE_RC_CONFIG_DCR);
+ status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
+ (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
+ rockchip_pcie_writel(rockchip_pcie, PCIE_RC_CONFIG_DCR, status);
+ }
+}
+
/**
* rockchip_pcie_init_port - Initialize hardware
* @rockchip_pcie: PCIe port information
@@ -500,6 +538,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip_pcie)
(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
rockchip_pcie_writel(rockchip_pcie, PCIE_CORE_CTRL_PLC1, status);
+ rockchip_pcie_set_power_limit(rockchip_pcie);
+
/* Enable Gen1 training */
rockchip_pcie_writel(rockchip_pcie, PCIE_CLIENT_CONFIG,
PCIE_CLIENT_LINK_TRAIN_ENABLE);
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/3] PCI: rockchip: Mark RC as common clock architecture
@ 2016-10-12 2:05 ` Shawn Lin
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Lin @ 2016-10-12 2:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, linux-rockchip, Rajat Jain, Wenrui Li, Brian Norris,
Shawn Lin
The default value of common clock configuration is
zero indicating Rockchip's RC is using asynchronous
clock architecture but actually we are using common
clock. This will confuses some EP drivers if they
need some different settings referring to this value.
So let's fix it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v3:
- rebase the code since it isn't cleanly applied again
Changes in v2:
- rebase the code since it isn't cleanly applied after Bjorn's cleanup
drivers/pci/host/pcie-rockchip.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a67ff9e..d51afe6 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -141,6 +141,7 @@
#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
+#define PCIE_RC_CONFIG_LCS_CCC BIT(6)
#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
#define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
#define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
@@ -540,6 +541,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip_pcie)
rockchip_pcie_set_power_limit(rockchip_pcie);
+ /* Set RC's clock architecture as common clock */
+ status = rockchip_pcie_readl(rockchip_pcie, PCIE_RC_CONFIG_LCS);
+ status |= PCIE_RC_CONFIG_LCS_CCC;
+ rockchip_pcie_writel(rockchip_pcie, PCIE_RC_CONFIG_LCS, status);
+
/* Enable Gen1 training */
rockchip_pcie_writel(rockchip_pcie, PCIE_CLIENT_CONFIG,
PCIE_CLIENT_LINK_TRAIN_ENABLE);
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/3] PCI: rockchip: Mark RC as common clock architecture
@ 2016-10-12 2:05 ` Shawn Lin
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Lin @ 2016-10-12 2:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Wenrui Li, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin,
Brian Norris, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rajat Jain
The default value of common clock configuration is
zero indicating Rockchip's RC is using asynchronous
clock architecture but actually we are using common
clock. This will confuses some EP drivers if they
need some different settings referring to this value.
So let's fix it.
Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v3:
- rebase the code since it isn't cleanly applied again
Changes in v2:
- rebase the code since it isn't cleanly applied after Bjorn's cleanup
drivers/pci/host/pcie-rockchip.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a67ff9e..d51afe6 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -141,6 +141,7 @@
#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
+#define PCIE_RC_CONFIG_LCS_CCC BIT(6)
#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
#define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
#define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
@@ -540,6 +541,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip_pcie)
rockchip_pcie_set_power_limit(rockchip_pcie);
+ /* Set RC's clock architecture as common clock */
+ status = rockchip_pcie_readl(rockchip_pcie, PCIE_RC_CONFIG_LCS);
+ status |= PCIE_RC_CONFIG_LCS_CCC;
+ rockchip_pcie_writel(rockchip_pcie, PCIE_RC_CONFIG_LCS, status);
+
/* Enable Gen1 training */
rockchip_pcie_writel(rockchip_pcie, PCIE_CLIENT_CONFIG,
PCIE_CLIENT_LINK_TRAIN_ENABLE);
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/3] PCI: rockchip: add COMPILE_TEST for Kconfig
@ 2016-10-12 2:05 ` Shawn Lin
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Lin @ 2016-10-12 2:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, linux-rockchip, Rajat Jain, Wenrui Li, Brian Norris,
Shawn Lin
Add this could help build the driver if we enable
CONFIG_COMPILE_TEST.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
drivers/pci/host/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d7e7c0a..096440e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -276,7 +276,7 @@ config PCIE_ARTPEC6
config PCIE_ROCKCHIP
bool "Rockchip PCIe controller"
- depends on ARCH_ROCKCHIP
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
select MFD_SYSCON
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/3] PCI: rockchip: add COMPILE_TEST for Kconfig
@ 2016-10-12 2:05 ` Shawn Lin
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Lin @ 2016-10-12 2:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Wenrui Li, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin,
Brian Norris, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rajat Jain
Add this could help build the driver if we enable
CONFIG_COMPILE_TEST.
Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v3: None
Changes in v2: None
drivers/pci/host/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d7e7c0a..096440e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -276,7 +276,7 @@ config PCIE_ARTPEC6
config PCIE_ROCKCHIP
bool "Rockchip PCIe controller"
- depends on ARCH_ROCKCHIP
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
select MFD_SYSCON
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-10-12 2:10 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2016-10-12 2:05 [PATCH v3 1/3] PCI: rockchip: Provide captured slot power limit and scale Shawn Lin
2016-10-12 2:05 ` Shawn Lin
2016-10-12 2:05 ` [PATCH v3 2/3] PCI: rockchip: Mark RC as common clock architecture Shawn Lin
2016-10-12 2:05 ` Shawn Lin
2016-10-12 2:05 ` [PATCH v3 3/3] PCI: rockchip: add COMPILE_TEST for Kconfig Shawn Lin
2016-10-12 2:05 ` Shawn Lin
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