From: Priyanka Jain <priyanka.jain@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 0/5] Update LS2080A SoC code to support LS2088A SoC
Date: Wed, 19 Oct 2016 15:06:37 +0530 [thread overview]
Message-ID: <1476869802-30528-1-git-send-email-priyanka.jain@nxp.com> (raw)
From: Priyanka Jain <Priyanka.Jain@freescale.com>
LS2088A is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)Process to release secondary cores is different
4)LS2088A SoC has TZASC controller
In preparation of using same binary for LS2088A and LS2080A as both
are using same development boards. code is update to detect difference
based on SVR at runtime
Priyanka Jain (5):
armv8: lsch3: Use SVR based timer base address detection
armv8: fsl-layerscape: Update TZASC registers type
armv8: fsl-layerscape : Check SVR for initializing TZASC
armv8: fsl-layerscape: Add NXP LS2088A SoC support
armv8/fsl-lsch3: Update code to release secondary cores
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 16 +++++-
arch/arm/cpu/armv8/fsl-layerscape/cpu.h | 1 +
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 +++++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 47 +++++++++++-----
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 59 ++++++++++++++++++-
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +-
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 7 ++-
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 10 +++
board/freescale/ls2080a/MAINTAINERS | 2 +-
board/freescale/ls2080aqds/MAINTAINERS | 2 +-
board/freescale/ls2080aqds/README | 12 ++--
board/freescale/ls2080ardb/MAINTAINERS | 2 +-
board/freescale/ls2080ardb/README | 8 +-
15 files changed, 198 insertions(+), 37 deletions(-)
--
1.7.4.1
next reply other threads:[~2016-10-19 9:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-19 9:36 Priyanka Jain [this message]
2016-10-19 9:36 ` [U-Boot] [PATCH 1/5] armv8: lsch3: Use SVR based timer base address detection Priyanka Jain
2016-10-20 3:28 ` Prabhakar Kushwaha
2016-10-20 5:15 ` york sun
2016-10-24 6:29 ` Priyanka Jain
2016-10-24 15:24 ` york sun
2016-10-19 9:36 ` [U-Boot] [PATCH 2/5] armv8: fsl-layerscape: Update TZASC registers type Priyanka Jain
2016-10-19 9:36 ` [U-Boot] [PATCH 3/5] armv8: fsl-layerscape : Check SVR for initializing TZASC Priyanka Jain
2016-10-19 9:36 ` [U-Boot] [PATCH 4/5] armv8: fsl-layerscape: Add NXP LS2088A SoC support Priyanka Jain
2016-10-20 3:33 ` Prabhakar Kushwaha
2016-10-24 6:25 ` Priyanka Jain
2016-10-19 9:36 ` [U-Boot] [PATCH 5/5] armv8/fsl-lsch3: Update code to release secondary cores Priyanka Jain
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