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From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/5] armv8: lsch3: Use SVR based timer base address detection
Date: Thu, 20 Oct 2016 03:28:00 +0000	[thread overview]
Message-ID: <DB5PR0401MB1958F6858E8A63B561FFAD5497D50@DB5PR0401MB1958.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1476869802-30528-2-git-send-email-priyanka.jain@nxp.com>

Hi York

> -----Original Message-----
> From: Priyanka Jain [mailto:priyanka.jain at nxp.com]
> Sent: Wednesday, October 19, 2016 3:07 PM
> To: u-boot at lists.denx.de
> Cc: Priyanka Jain <priyanka.jain@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>
> Subject: [PATCH 1/5] armv8: lsch3: Use SVR based timer base address detection
> 
> Timer base address has been changed from LS2080A SoC to
> new SoCs like LS2088A, LS1088A.
> 
> Use SVR based timer base address detection to avoid compile time #ifdef.
> 
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |   14 +++++++++++++-
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    3 ++-
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index b7a2e0c..ce04e48 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -424,8 +424,10 @@ int arch_early_init_r(void)
> 
>  int timer_init(void)
>  {
> -	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
> +	u32 __iomem *cntcr;
>  #ifdef CONFIG_FSL_LSCH3
> +	struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +	u32 svr, ver;
>  	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
>  #endif
>  #ifdef CONFIG_LS2080A
> @@ -439,6 +441,16 @@ int timer_init(void)
>  #endif
> 
>  #ifdef CONFIG_FSL_LSCH3
> +	svr = gur_in32(&gur->svr);
> +	ver = SVR_SOC_VER(svr);
> +	if ((ver == SVR_LS2080A) || (ver == SVR_LS2040A) ||
> +	    (ver == SVR_LS2085A) || (ver == SVR_LS2045A))
> +		cntcr = (u32 *)LS2080A_LS2085A_TIMER_ADDR;
> +	else
> +#endif
> +		cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
> +
> +#ifdef CONFIG_FSL_LSCH3
>  	/* Enable timebase for all clusters.
>  	 * It is safe to do so even some clusters are not enabled.
>  	 */
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 7acba27..e6cdfcb 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -23,7 +23,8 @@
>  #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR +
> 0x01240000)
>  #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR +
> 0x011C0500)
>  #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR +
> 0x011C0600)
> -#define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
> +#define LS2080A_LS2085A_TIMER_ADDR		0x023d0000

Is this ok to define new constant without CONFIG_?
Only problem, it is not consistent with existing defines. 

-prabhakar

  reply	other threads:[~2016-10-20  3:28 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-19  9:36 [U-Boot] [PATCH 0/5] Update LS2080A SoC code to support LS2088A SoC Priyanka Jain
2016-10-19  9:36 ` [U-Boot] [PATCH 1/5] armv8: lsch3: Use SVR based timer base address detection Priyanka Jain
2016-10-20  3:28   ` Prabhakar Kushwaha [this message]
2016-10-20  5:15     ` york sun
2016-10-24  6:29       ` Priyanka Jain
2016-10-24 15:24         ` york sun
2016-10-19  9:36 ` [U-Boot] [PATCH 2/5] armv8: fsl-layerscape: Update TZASC registers type Priyanka Jain
2016-10-19  9:36 ` [U-Boot] [PATCH 3/5] armv8: fsl-layerscape : Check SVR for initializing TZASC Priyanka Jain
2016-10-19  9:36 ` [U-Boot] [PATCH 4/5] armv8: fsl-layerscape: Add NXP LS2088A SoC support Priyanka Jain
2016-10-20  3:33   ` Prabhakar Kushwaha
2016-10-24  6:25     ` Priyanka Jain
2016-10-19  9:36 ` [U-Boot] [PATCH 5/5] armv8/fsl-lsch3: Update code to release secondary cores Priyanka Jain

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