* [PATCH v2] PCI: rockchip: remove the pointer to L1 substate cap
@ 2016-10-20 7:53 Shawn Lin
2016-11-11 22:27 ` Bjorn Helgaas
0 siblings, 1 reply; 3+ messages in thread
From: Shawn Lin @ 2016-10-20 7:53 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, linux-rockchip, Rajat Jain, Wenrui Li, Brian Norris,
Shawn Lin
Per the errata of TRM, the RC can't support L1 substate, so we
need to remove the L1 substate cap as well as operation for
PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Brian Norris <briannorris@chromium.org>
---
Changes in v2:
- Add Brian's tag and remove operation for PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.
drivers/pci/host/pcie-rockchip.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e0b22da..a23c7f1 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -142,6 +142,8 @@
#define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
#define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
+#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
+#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
#define PCIE_CORE_AXI_CONF_BASE 0xc00000
#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
@@ -481,15 +483,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
return err;
}
- /*
- * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
- * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
- * reliable and enabling ASPM doesn't work. This is a controller
- * bug we need to work around.
- */
- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-
/* Fix the transmitted FTS count desired to exit from L0s. */
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
@@ -558,6 +551,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
rockchip_pcie_write(rockchip,
PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
PCIE_RC_CONFIG_RID_CCR);
+
+ /* Clear THP cap's next cap pointer to remove L1 substate cap */
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
+ status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
+
rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
rockchip_pcie_write(rockchip,
--
2.3.7
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] PCI: rockchip: remove the pointer to L1 substate cap
@ 2016-11-11 22:27 ` Bjorn Helgaas
0 siblings, 0 replies; 3+ messages in thread
From: Bjorn Helgaas @ 2016-11-11 22:27 UTC (permalink / raw)
To: Shawn Lin
Cc: Bjorn Helgaas, linux-pci, linux-rockchip, Rajat Jain, Wenrui Li,
Brian Norris
On Thu, Oct 20, 2016 at 03:53:20PM +0800, Shawn Lin wrote:
> Per the errata of TRM, the RC can't support L1 substate, so we
> need to remove the L1 substate cap as well as operation for
> PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> Tested-by: Brian Norris <briannorris@chromium.org>
Applied to pci/host-rockchip for v4.10, thanks!
> ---
>
> Changes in v2:
> - Add Brian's tag and remove operation for PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.
>
> drivers/pci/host/pcie-rockchip.c | 17 ++++++++---------
> 1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index e0b22da..a23c7f1 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -142,6 +142,8 @@
> #define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
> #define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
> #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
> +#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
> +#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
>
> #define PCIE_CORE_AXI_CONF_BASE 0xc00000
> #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
> @@ -481,15 +483,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> return err;
> }
>
> - /*
> - * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
> - * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
> - * reliable and enabling ASPM doesn't work. This is a controller
> - * bug we need to work around.
> - */
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> -
> /* Fix the transmitted FTS count desired to exit from L0s. */
> status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
> status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
> @@ -558,6 +551,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> rockchip_pcie_write(rockchip,
> PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
> PCIE_RC_CONFIG_RID_CCR);
> +
> + /* Clear THP cap's next cap pointer to remove L1 substate cap */
> + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
> + status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
> + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
> +
> rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
>
> rockchip_pcie_write(rockchip,
> --
> 2.3.7
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] PCI: rockchip: remove the pointer to L1 substate cap
@ 2016-11-11 22:27 ` Bjorn Helgaas
0 siblings, 0 replies; 3+ messages in thread
From: Bjorn Helgaas @ 2016-11-11 22:27 UTC (permalink / raw)
To: Shawn Lin
Cc: Wenrui Li, linux-pci-u79uwXL29TY76Z2rM5mHXA, Brian Norris,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Bjorn Helgaas,
Rajat Jain
On Thu, Oct 20, 2016 at 03:53:20PM +0800, Shawn Lin wrote:
> Per the errata of TRM, the RC can't support L1 substate, so we
> need to remove the L1 substate cap as well as operation for
> PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.
>
> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> Tested-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Applied to pci/host-rockchip for v4.10, thanks!
> ---
>
> Changes in v2:
> - Add Brian's tag and remove operation for PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.
>
> drivers/pci/host/pcie-rockchip.c | 17 ++++++++---------
> 1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index e0b22da..a23c7f1 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -142,6 +142,8 @@
> #define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
> #define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
> #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
> +#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
> +#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
>
> #define PCIE_CORE_AXI_CONF_BASE 0xc00000
> #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
> @@ -481,15 +483,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> return err;
> }
>
> - /*
> - * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
> - * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
> - * reliable and enabling ASPM doesn't work. This is a controller
> - * bug we need to work around.
> - */
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> -
> /* Fix the transmitted FTS count desired to exit from L0s. */
> status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
> status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
> @@ -558,6 +551,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> rockchip_pcie_write(rockchip,
> PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
> PCIE_RC_CONFIG_RID_CCR);
> +
> + /* Clear THP cap's next cap pointer to remove L1 substate cap */
> + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
> + status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
> + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
> +
> rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
>
> rockchip_pcie_write(rockchip,
> --
> 2.3.7
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2016-11-11 22:28 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2016-10-20 7:53 [PATCH v2] PCI: rockchip: remove the pointer to L1 substate cap Shawn Lin
2016-11-11 22:27 ` Bjorn Helgaas
2016-11-11 22:27 ` Bjorn Helgaas
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