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* [PATCH] iommu: arm-smmu-v2: Enable 16 bit ASID
@ 2016-10-22  5:02 ` Geetha sowjanya
  0 siblings, 0 replies; 4+ messages in thread
From: Geetha sowjanya @ 2016-10-22  5:02 UTC (permalink / raw)
  To: robin.murphy, will.deacon, mark.rutland
  Cc: Prasun.Kapoor, Geetha sowjanya, Tirumalesh.Chalamarla, iommu,
	Geetha sowjanya, linux-arm-kernel

 Support up to 16 bit ASID. This patch enables
 16 bit ASID when supported.

Signed-off-by: Geetha sowjanya <gakula@cavium.com>
Acked-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
---
 drivers/iommu/arm-smmu.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index c841eb7..9740846 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -258,6 +258,9 @@ enum arm_smmu_s2cr_privcfg {
 #define TTBCR2_SEP_SHIFT		15
 #define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)
 
+#define TTBCR2_AS_SHIFT			4
+#define TTBCR2_AS_ENABLE		(1 << TTBCR2_AS_SHIFT)
+
 #define TTBRn_ASID_SHIFT		48
 
 #define FSR_MULTI			(1 << 31)
@@ -773,6 +776,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 			reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
 			reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
 			reg2 |= TTBCR2_SEP_UPSTREAM;
+		/* Enable 16 bit ASID if 16 bit VMID is supported */
+			if (smmu->features & ARM_SMMU_FEAT_VMID16)
+				reg |= TTBCR2_AS_ENABLE;
 		}
 		if (smmu->version > ARM_SMMU_V1)
 			writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
-- 
1.7.1

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] iommu: arm-smmu-v2: Enable 16 bit ASID
@ 2016-10-22  5:02 ` Geetha sowjanya
  0 siblings, 0 replies; 4+ messages in thread
From: Geetha sowjanya @ 2016-10-22  5:02 UTC (permalink / raw)
  To: linux-arm-kernel

 Support up to 16 bit ASID. This patch enables
 16 bit ASID when supported.

Signed-off-by: Geetha sowjanya <gakula@cavium.com>
Acked-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
---
 drivers/iommu/arm-smmu.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index c841eb7..9740846 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -258,6 +258,9 @@ enum arm_smmu_s2cr_privcfg {
 #define TTBCR2_SEP_SHIFT		15
 #define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)
 
+#define TTBCR2_AS_SHIFT			4
+#define TTBCR2_AS_ENABLE		(1 << TTBCR2_AS_SHIFT)
+
 #define TTBRn_ASID_SHIFT		48
 
 #define FSR_MULTI			(1 << 31)
@@ -773,6 +776,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 			reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
 			reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
 			reg2 |= TTBCR2_SEP_UPSTREAM;
+		/* Enable 16 bit ASID if 16 bit VMID is supported */
+			if (smmu->features & ARM_SMMU_FEAT_VMID16)
+				reg |= TTBCR2_AS_ENABLE;
 		}
 		if (smmu->version > ARM_SMMU_V1)
 			writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
-- 
1.7.1

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] iommu: arm-smmu-v2: Enable 16 bit ASID
  2016-10-22  5:02 ` Geetha sowjanya
@ 2016-10-24 11:01     ` Robin Murphy
  -1 siblings, 0 replies; 4+ messages in thread
From: Robin Murphy @ 2016-10-24 11:01 UTC (permalink / raw)
  To: Geetha sowjanya, will.deacon-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8
  Cc: Prasun.Kapoor-YGCgFSpz5w/QT0dZR+AlfA,
	iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
	Tirumalesh.Chalamarla-YGCgFSpz5w/QT0dZR+AlfA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	Geetha sowjanya

Hi Geetha,

On 22/10/16 06:02, Geetha sowjanya wrote:
>  Support up to 16 bit ASID. This patch enables
>  16 bit ASID when supported.

Why? "Because we can" is not a compelling rationale. I assume this is
actually related to the globally-unique ASID workaround for the TLB
sharing erratum, but if so that should be called out explicitly -
describe the problem being fixed.

> Signed-off-by: Geetha sowjanya <gakula-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> Acked-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> ---
>  drivers/iommu/arm-smmu.c |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index c841eb7..9740846 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -258,6 +258,9 @@ enum arm_smmu_s2cr_privcfg {
>  #define TTBCR2_SEP_SHIFT		15
>  #define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)
>  
> +#define TTBCR2_AS_SHIFT			4
> +#define TTBCR2_AS_ENABLE		(1 << TTBCR2_AS_SHIFT)
> +

The style here for single-bit fields is simply:

#define TTBCR2_AS			(1 << 4)

>  #define TTBRn_ASID_SHIFT		48
>  
>  #define FSR_MULTI			(1 << 31)
> @@ -773,6 +776,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
>  			reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
>  			reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
>  			reg2 |= TTBCR2_SEP_UPSTREAM;
> +		/* Enable 16 bit ASID if 16 bit VMID is supported */
> +			if (smmu->features & ARM_SMMU_FEAT_VMID16)

This should be a check for AArch64 context format - VMID16 has nothing
to do with it. 16-bit ASID support for stage 1 AArch64 contexts is
already implied by SMMUv2 (TCR2.AS is not optional).

Robin.

> +				reg |= TTBCR2_AS_ENABLE;
>  		}
>  		if (smmu->version > ARM_SMMU_V1)
>  			writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH] iommu: arm-smmu-v2: Enable 16 bit ASID
@ 2016-10-24 11:01     ` Robin Murphy
  0 siblings, 0 replies; 4+ messages in thread
From: Robin Murphy @ 2016-10-24 11:01 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Geetha,

On 22/10/16 06:02, Geetha sowjanya wrote:
>  Support up to 16 bit ASID. This patch enables
>  16 bit ASID when supported.

Why? "Because we can" is not a compelling rationale. I assume this is
actually related to the globally-unique ASID workaround for the TLB
sharing erratum, but if so that should be called out explicitly -
describe the problem being fixed.

> Signed-off-by: Geetha sowjanya <gakula@cavium.com>
> Acked-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
> ---
>  drivers/iommu/arm-smmu.c |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index c841eb7..9740846 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -258,6 +258,9 @@ enum arm_smmu_s2cr_privcfg {
>  #define TTBCR2_SEP_SHIFT		15
>  #define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)
>  
> +#define TTBCR2_AS_SHIFT			4
> +#define TTBCR2_AS_ENABLE		(1 << TTBCR2_AS_SHIFT)
> +

The style here for single-bit fields is simply:

#define TTBCR2_AS			(1 << 4)

>  #define TTBRn_ASID_SHIFT		48
>  
>  #define FSR_MULTI			(1 << 31)
> @@ -773,6 +776,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
>  			reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
>  			reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
>  			reg2 |= TTBCR2_SEP_UPSTREAM;
> +		/* Enable 16 bit ASID if 16 bit VMID is supported */
> +			if (smmu->features & ARM_SMMU_FEAT_VMID16)

This should be a check for AArch64 context format - VMID16 has nothing
to do with it. 16-bit ASID support for stage 1 AArch64 contexts is
already implied by SMMUv2 (TCR2.AS is not optional).

Robin.

> +				reg |= TTBCR2_AS_ENABLE;
>  		}
>  		if (smmu->version > ARM_SMMU_V1)
>  			writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-10-24 11:01 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-22  5:02 [PATCH] iommu: arm-smmu-v2: Enable 16 bit ASID Geetha sowjanya
2016-10-22  5:02 ` Geetha sowjanya
     [not found] ` <1477112524-13023-1-git-send-email-gakula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2016-10-24 11:01   ` Robin Murphy
2016-10-24 11:01     ` Robin Murphy

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