* [Qemu-devel] [PATCH v1 0/3] POWER9 TCG enablements - part7
@ 2016-10-25 6:19 Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 1/3] target-ppc: add xscmp[eq, gt, ge, ne]dp instructions Nikunj A Dadhania
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-10-25 6:19 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, sandipandas1990, ego
This series contains 8 new instructions for POWER9 ISA3.0
VSX Scalar compare
Vector Rotate Left Dword
Vector Rotate Left Word
Changelog:
v0:
* Use extract32 and extract64 helper
* Use rol32 and rol64 helper
Patches:
01:
xscmpeqdp: VSX Scalar Compare Equal Double-Precision
xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision
xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision
xscmpnedp: VSX Scalar Compare Not Equal Double-Precision
02:
vrldmi: Vector Rotate Left Dword then Mask Insert
vrlwmi: Vector Rotate Left Word then Mask Insert
03:
vrldnm: Vector Rotate Left Doubleword then AND with Mask
vrlwnm: Vector Rotate Left Word then AND with Mask
Bharata B Rao (1):
target-ppc: add vrldnm and vrlwnm instructions
Gautham R. Shenoy (1):
target-ppc: add vrldnmi and vrlwmi instructions
Sandipan Das (1):
target-ppc: add xscmp[eq,gt,ge,ne]dp instructions
disas/ppc.c | 4 ++
target-ppc/fpu_helper.c | 52 +++++++++++++++++++++++++
target-ppc/helper.h | 8 ++++
target-ppc/int_helper.c | 77 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 12 ++++++
target-ppc/translate/vmx-ops.inc.c | 8 ++--
target-ppc/translate/vsx-impl.inc.c | 4 ++
target-ppc/translate/vsx-ops.inc.c | 4 ++
8 files changed, 165 insertions(+), 4 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v1 1/3] target-ppc: add xscmp[eq, gt, ge, ne]dp instructions
2016-10-25 6:19 [Qemu-devel] [PATCH v1 0/3] POWER9 TCG enablements - part7 Nikunj A Dadhania
@ 2016-10-25 6:19 ` Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 2/3] target-ppc: add vrldnmi and vrlwmi instructions Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 3/3] target-ppc: add vrldnm and vrlwnm instructions Nikunj A Dadhania
2 siblings, 0 replies; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-10-25 6:19 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, sandipandas1990, ego
From: Sandipan Das <sandipandas1990@gmail.com>
xscmpeqdp: VSX Scalar Compare Equal Double-Precision
xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision
xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision
xscmpnedp: VSX Scalar Compare Not Equal Double-Precision
Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/fpu_helper.c | 52 +++++++++++++++++++++++++++++++++++++
target-ppc/helper.h | 4 +++
target-ppc/translate/vsx-impl.inc.c | 4 +++
target-ppc/translate/vsx-ops.inc.c | 4 +++
4 files changed, 64 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index b0760f0..4906372 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2362,6 +2362,58 @@ VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0)
VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0)
VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0)
+/* VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
+ * op - instruction mnemonic
+ * cmp - comparison operation
+ * exp - expected result of comparison
+ * svxvc - set VXVC bit
+ */
+#define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xB(opcode), &xb, env); \
+ getVSR(xT(opcode), &xt, env); \
+ \
+ if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
+ float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ if (fpscr_ve == 0 && svxvc) { \
+ vxvc_flag = true; \
+ } \
+ } else if (svxvc) { \
+ vxvc_flag = float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) || \
+ float64_is_quiet_nan(xb.VsrD(0), &env->fp_status); \
+ } \
+ if (vxsnan_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (vxvc_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
+ } \
+ vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
+ \
+ if (!vex_flag) { \
+ if (float64_##cmp(xb.VsrD(0), xa.VsrD(0), &env->fp_status) == exp) { \
+ xt.VsrD(0) = -1; \
+ xt.VsrD(1) = 0; \
+ } else { \
+ xt.VsrD(0) = 0; \
+ xt.VsrD(1) = 0; \
+ } \
+ } \
+ putVSR(xT(opcode), &xt, env); \
+ helper_float_check_status(env); \
+}
+
+VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
+VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
+VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
+VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
+
#define VSX_SCALAR_CMP(op, ordered) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5fcc546..0337292 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -389,6 +389,10 @@ DEF_HELPER_2(xsnmaddadp, void, env, i32)
DEF_HELPER_2(xsnmaddmdp, void, env, i32)
DEF_HELPER_2(xsnmsubadp, void, env, i32)
DEF_HELPER_2(xsnmsubmdp, void, env, i32)
+DEF_HELPER_2(xscmpeqdp, void, env, i32)
+DEF_HELPER_2(xscmpgtdp, void, env, i32)
+DEF_HELPER_2(xscmpgedp, void, env, i32)
+DEF_HELPER_2(xscmpnedp, void, env, i32)
DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 1508bd1..bf167d0 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -620,6 +620,10 @@ GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index af0d27e..202c557 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -114,6 +114,10 @@ GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
+GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
+GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
+GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
+GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300),
GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v1 2/3] target-ppc: add vrldnmi and vrlwmi instructions
2016-10-25 6:19 [Qemu-devel] [PATCH v1 0/3] POWER9 TCG enablements - part7 Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 1/3] target-ppc: add xscmp[eq, gt, ge, ne]dp instructions Nikunj A Dadhania
@ 2016-10-25 6:19 ` Nikunj A Dadhania
2016-10-25 17:02 ` Richard Henderson
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 3/3] target-ppc: add vrldnm and vrlwnm instructions Nikunj A Dadhania
2 siblings, 1 reply; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-10-25 6:19 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, sandipandas1990, ego
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
vrldmi: Vector Rotate Left Dword then Mask Insert
vrlwmi: Vector Rotate Left Word then Mask Insert
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
( use extract[32,64] and rol[32,64] )
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
disas/ppc.c | 2 ++
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 59 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 6 ++++
target-ppc/translate/vmx-ops.inc.c | 4 +--
5 files changed, 71 insertions(+), 2 deletions(-)
diff --git a/disas/ppc.c b/disas/ppc.c
index 052cebe..32f0d8d 100644
--- a/disas/ppc.c
+++ b/disas/ppc.c
@@ -2286,6 +2286,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
+{ "vrldmi", VX(4, 197), VX_MASK, PPCVEC, { VD, VA, VB } },
+{ "vrlwmi", VX(4, 133), VX_MASK, PPCVEC, { VD, VA, VB} },
{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0337292..9fb8f0d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -325,6 +325,8 @@ DEF_HELPER_4(vmaxfp, void, env, avr, avr, avr)
DEF_HELPER_4(vminfp, void, env, avr, avr, avr)
DEF_HELPER_3(vrefp, void, env, avr, avr)
DEF_HELPER_3(vrsqrtefp, void, env, avr, avr)
+DEF_HELPER_3(vrlwmi, void, avr, avr, avr)
+DEF_HELPER_3(vrldmi, void, avr, avr, avr)
DEF_HELPER_5(vmaddfp, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vnmsubfp, void, env, avr, avr, avr, avr)
DEF_HELPER_3(vexptefp, void, env, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index dca4798..697f8fb 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1717,6 +1717,65 @@ void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
}
}
+#define MASK(size, max_val) \
+static inline uint##size##_t mask_u##size(uint##size##_t start, \
+ uint##size##_t end) \
+{ \
+ uint##size##_t ret, max_bit = size - 1; \
+ \
+ if (likely(start == 0)) { \
+ ret = max_val << (max_bit - end); \
+ } else if (likely(end == max_bit)) { \
+ ret = max_val >> start; \
+ } else { \
+ ret = (((uint##size##_t)(-1ULL)) >> (start)) ^ \
+ (((uint##size##_t)(-1ULL) >> (end)) >> 1); \
+ if (unlikely(start > end)) { \
+ return ~ret; \
+ } \
+ } \
+ \
+ return ret; \
+}
+
+MASK(32, UINT32_MAX);
+MASK(64, UINT64_MAX);
+
+#define VRLMI(name, size, element, \
+ begin_last, end_last, shift_last, \
+ num_bits) \
+void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+{ \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ uint##size##_t src1 = a->element[i]; \
+ uint##size##_t src2 = b->element[i]; \
+ uint##size##_t src3 = r->element[i]; \
+ uint##size##_t begin, end, shift, mask, rot_val; \
+ \
+ begin = extract##size(src2, size - begin_last - 1, num_bits); \
+ end = extract##size(src2, size - end_last - 1, num_bits); \
+ shift = extract##size(src2, size - shift_last - 1, num_bits); \
+ rot_val = rol##size(src1, shift); \
+ mask = mask_u##size(begin, end); \
+ r->element[i] = (rot_val & mask) | (src3 & ~mask); \
+ } \
+}
+
+VRLMI(vrldmi, 64, u64,
+ 47, /* begin_last */
+ 55, /* end_last */
+ 63, /* shift_last */
+ 6 /* num_bits */
+ );
+
+VRLMI(vrlwmi, 32, u32,
+ 15, /* begin_last */
+ 23, /* end_last */
+ 31, /* shift_last */
+ 6 /* num_bits */
+ );
+
void helper_vsel(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
{
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index fc612d9..fdfbd6a 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -488,7 +488,13 @@ GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
GEN_VXFORM(vrlb, 2, 0);
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
+GEN_VXFORM(vrlwmi, 2, 2);
+GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
+ vrlwmi, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vrld, 2, 3);
+GEN_VXFORM(vrldmi, 2, 3);
+GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
+ vrldmi, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vsl, 2, 7);
GEN_VXFORM(vsr, 2, 11);
GEN_VXFORM_ENV(vpkuhum, 7, 0);
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index cc7ed7e..76b3593 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -143,8 +143,8 @@ GEN_VXFORM_207(vsubcuq, 0, 21),
GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM(vrlb, 2, 0),
GEN_VXFORM(vrlh, 2, 1),
-GEN_VXFORM(vrlw, 2, 2),
-GEN_VXFORM_207(vrld, 2, 3),
+GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM(vsl, 2, 7),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v1 3/3] target-ppc: add vrldnm and vrlwnm instructions
2016-10-25 6:19 [Qemu-devel] [PATCH v1 0/3] POWER9 TCG enablements - part7 Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 1/3] target-ppc: add xscmp[eq, gt, ge, ne]dp instructions Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 2/3] target-ppc: add vrldnmi and vrlwmi instructions Nikunj A Dadhania
@ 2016-10-25 6:19 ` Nikunj A Dadhania
2 siblings, 0 replies; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-10-25 6:19 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, sandipandas1990, ego
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
vrldnm: Vector Rotate Left Doubleword then AND with Mask
vrlwnm: Vector Rotate Left Word then AND with Mask
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
disas/ppc.c | 2 ++
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 30 ++++++++++++++++++++++++------
target-ppc/translate/vmx-impl.inc.c | 6 ++++++
target-ppc/translate/vmx-ops.inc.c | 4 ++--
5 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/disas/ppc.c b/disas/ppc.c
index 32f0d8d..bd05623 100644
--- a/disas/ppc.c
+++ b/disas/ppc.c
@@ -2287,7 +2287,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
{ "vrldmi", VX(4, 197), VX_MASK, PPCVEC, { VD, VA, VB } },
+{ "vrldnm", VX(4, 453), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vrlwmi", VX(4, 133), VX_MASK, PPCVEC, { VD, VA, VB} },
+{ "vrlwnm", VX(4, 389), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9fb8f0d..d6ee26e 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -327,6 +327,8 @@ DEF_HELPER_3(vrefp, void, env, avr, avr)
DEF_HELPER_3(vrsqrtefp, void, env, avr, avr)
DEF_HELPER_3(vrlwmi, void, avr, avr, avr)
DEF_HELPER_3(vrldmi, void, avr, avr, avr)
+DEF_HELPER_3(vrldnm, void, avr, avr, avr)
+DEF_HELPER_3(vrlwnm, void, avr, avr, avr)
DEF_HELPER_5(vmaddfp, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vnmsubfp, void, env, avr, avr, avr, avr)
DEF_HELPER_3(vexptefp, void, env, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 697f8fb..5396df7 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1743,7 +1743,7 @@ MASK(64, UINT64_MAX);
#define VRLMI(name, size, element, \
begin_last, end_last, shift_last, \
- num_bits) \
+ num_bits, insert) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
@@ -1758,7 +1758,11 @@ void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
shift = extract##size(src2, size - shift_last - 1, num_bits); \
rot_val = rol##size(src1, shift); \
mask = mask_u##size(begin, end); \
- r->element[i] = (rot_val & mask) | (src3 & ~mask); \
+ if (insert) { \
+ r->element[i] = (rot_val & mask) | (src3 & ~mask); \
+ } else { \
+ r->element[i] = (rot_val & mask); \
+ } \
} \
}
@@ -1766,15 +1770,29 @@ VRLMI(vrldmi, 64, u64,
47, /* begin_last */
55, /* end_last */
63, /* shift_last */
- 6 /* num_bits */
- );
+ 6, /* num_bits */
+ 1); /* mask and insert */
VRLMI(vrlwmi, 32, u32,
15, /* begin_last */
23, /* end_last */
31, /* shift_last */
- 6 /* num_bits */
- );
+ 6, /* num_bits */
+ 1); /* mask and insert */
+
+VRLMI(vrldnm, 64, u64,
+ 47, /* begin_last */
+ 55, /* end_last */
+ 63, /* shift_last */
+ 6, /* num_bits */
+ 0); /* mask and insert */
+
+VRLMI(vrlwnm, 32, u32,
+ 15, /* begin_last */
+ 23, /* end_last */
+ 31, /* shift_last */
+ 6, /* num_bits */
+ 0); /* mask and insert */
void helper_vsel(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index fdfbd6a..500c43f 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -442,6 +442,9 @@ GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vslb, 2, 4);
GEN_VXFORM(vslh, 2, 5);
GEN_VXFORM(vslw, 2, 6);
+GEN_VXFORM(vrlwnm, 2, 6);
+GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
+ vrlwnm, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vsld, 2, 23);
GEN_VXFORM(vsrb, 2, 8);
GEN_VXFORM(vsrh, 2, 9);
@@ -496,6 +499,9 @@ GEN_VXFORM(vrldmi, 2, 3);
GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
vrldmi, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vsl, 2, 7);
+GEN_VXFORM(vrldnm, 2, 7);
+GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
+ vrldnm, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vsr, 2, 11);
GEN_VXFORM_ENV(vpkuhum, 7, 0);
GEN_VXFORM_ENV(vpkuwum, 7, 1);
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index 76b3593..a5ad4d4 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -107,7 +107,7 @@ GEN_VXFORM(vmulesh, 4, 13),
GEN_VXFORM_207(vmulesw, 4, 14),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
-GEN_VXFORM(vslw, 2, 6),
+GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_207(vsld, 2, 23),
GEN_VXFORM(vsrb, 2, 8),
GEN_VXFORM(vsrh, 2, 9),
@@ -145,7 +145,7 @@ GEN_VXFORM(vrlb, 2, 0),
GEN_VXFORM(vrlh, 2, 1),
GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM(vsl, 2, 7),
+GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
GEN_VXFORM(vpkuwum, 7, 1),
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v1 2/3] target-ppc: add vrldnmi and vrlwmi instructions
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 2/3] target-ppc: add vrldnmi and vrlwmi instructions Nikunj A Dadhania
@ 2016-10-25 17:02 ` Richard Henderson
2016-10-26 4:43 ` Nikunj A Dadhania
0 siblings, 1 reply; 6+ messages in thread
From: Richard Henderson @ 2016-10-25 17:02 UTC (permalink / raw)
To: Nikunj A Dadhania, qemu-ppc, david
Cc: qemu-devel, bharata, sandipandas1990, ego
On 10/24/2016 11:19 PM, Nikunj A Dadhania wrote:
> + begin = extract##size(src2, size - begin_last - 1, num_bits); \
> + end = extract##size(src2, size - end_last - 1, num_bits); \
> + shift = extract##size(src2, size - shift_last - 1, num_bits); \
What I mean is
shift = extract##size(src2, 0, 6);
end = extract##size(src2, 8, 6);
begin = extract##size(src2, 16, 6);
The values are at the *same* position for both instructions. There's no need
to parameterize with silly bigendian numberings.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v1 2/3] target-ppc: add vrldnmi and vrlwmi instructions
2016-10-25 17:02 ` Richard Henderson
@ 2016-10-26 4:43 ` Nikunj A Dadhania
0 siblings, 0 replies; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-10-26 4:43 UTC (permalink / raw)
To: Richard Henderson, qemu-ppc, david
Cc: qemu-devel, bharata, sandipandas1990, ego
Richard Henderson <rth@twiddle.net> writes:
> On 10/24/2016 11:19 PM, Nikunj A Dadhania wrote:
>> + begin = extract##size(src2, size - begin_last - 1, num_bits); \
>> + end = extract##size(src2, size - end_last - 1, num_bits); \
>> + shift = extract##size(src2, size - shift_last - 1, num_bits); \
>
> What I mean is
>
> shift = extract##size(src2, 0, 6);
> end = extract##size(src2, 8, 6);
> begin = extract##size(src2, 16, 6);
>
> The values are at the *same* position for both instructions. There's no need
> to parameterize with silly bigendian numberings.
Ah.. ok. You are right.
Regards
Nikunj
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-10-26 4:43 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-25 6:19 [Qemu-devel] [PATCH v1 0/3] POWER9 TCG enablements - part7 Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 1/3] target-ppc: add xscmp[eq, gt, ge, ne]dp instructions Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 2/3] target-ppc: add vrldnmi and vrlwmi instructions Nikunj A Dadhania
2016-10-25 17:02 ` Richard Henderson
2016-10-26 4:43 ` Nikunj A Dadhania
2016-10-25 6:19 ` [Qemu-devel] [PATCH v1 3/3] target-ppc: add vrldnm and vrlwnm instructions Nikunj A Dadhania
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