* [U-Boot] [PATCH] Add workaround for USB PHY errata
@ 2016-10-25 7:05 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008 Suresh Gupta
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY
Suresh Gupta (8):
armv8: Add workaround for USB erratum A-009008
armv8: Add workaround for USB erratum A-009798
armv8: Add workaround for USB erratum A-008997
armv8: Add workaround for USB erratum A-009007
armv7: Add workaround for USB erratum A-009008
armv7: Add workaround for USB erratum A-009798
armv7: Add workaround for USB erratum A-008997
armv7: Add workaround for USB erratum A-009007
arch/arm/cpu/armv7/ls102xa/Kconfig | 16 +++
arch/arm/cpu/armv7/ls102xa/soc.c | 50 +++++++++
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 118 +++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 +++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 19 ++++
7 files changed, 259 insertions(+)
--
1.9.3
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
2016-11-07 18:59 ` york sun
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009798 Suresh Gupta
` (6 subsequent siblings)
7 siblings, 1 reply; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 38 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..ec3e50d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -12,6 +12,7 @@ config ARCH_LS1043A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_ERRATUM_A009008
config ARCH_LS1046A
bool
@@ -21,6 +22,7 @@ config ARCH_LS1046A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
+ select SYS_FSL_ERRATUM_A009008
config ARCH_LS2080A
bool
@@ -30,6 +32,7 @@ config ARCH_LS2080A
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
+ select SYS_FSL_ERRATUM_A009008
config FSL_LSCH2
bool
@@ -53,6 +56,9 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
+config SYS_FSL_ERRATUM_A009008
+ bool "Workaround for USB PHY erratum A009008"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d68eeba..88cced1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -26,6 +26,29 @@
DECLARE_GLOBAL_DATA_PTR;
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -191,6 +214,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+ erratum_a009008();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -367,6 +391,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+ erratum_a009008();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..b8c9926 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -335,6 +335,12 @@ struct ccsr_gur {
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM1CR_USB3 0x088
+#define USB_TXVREFTUNE 0x9
+
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..3683b39 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -134,6 +134,7 @@
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
+#define USB_TXVREFTUNE 0x9
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009798
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008 Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-008997 Suresh Gupta
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 29 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ec3e50d..c62958e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -13,6 +13,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
config ARCH_LS1046A
bool
@@ -23,6 +24,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
config ARCH_LS2080A
bool
@@ -33,6 +35,7 @@ config ARCH_LS2080A
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
config FSL_LSCH2
bool
@@ -59,6 +62,9 @@ config SYS_FSL_ERRATUM_A010539
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 88cced1..6b18252 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -49,6 +49,25 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+ val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -215,6 +234,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+ erratum_a009798();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -392,6 +412,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+ erratum_a009798();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b8c9926..b72d47a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -340,6 +340,7 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR_USB2 0x07C
#define SCFG_USB3PRM1CR_USB3 0x088
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3683b39..a4bc036 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -135,6 +135,7 @@
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-008997
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009798 Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009007 Suresh Gupta
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 29 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 +++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
4 files changed, 41 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c62958e..a2f3237 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -14,6 +14,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
config ARCH_LS1046A
bool
@@ -25,6 +26,7 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
config ARCH_LS2080A
bool
@@ -36,6 +38,7 @@ config ARCH_LS2080A
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
config FSL_LSCH2
bool
@@ -65,6 +68,9 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997
+ bool "Workaround for USB PHY erratum A008997"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6b18252..1d0354d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -68,6 +68,33 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -235,6 +262,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -413,6 +441,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b72d47a..a7e36cd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -337,10 +337,14 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM2CR_USB1 0x074
#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM2CR_USB2 0x080
#define SCFG_USB3PRM1CR_USB3 0x088
+#define SCFG_USB3PRM2CR_USB3 0x08c
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index a4bc036..cdc08ed 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -133,9 +133,11 @@
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
+#define SCFG_USB3PRM2CR 0x004
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009007
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
` (2 preceding siblings ...)
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-008997 Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009008 Suresh Gupta
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 9 +++++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 ++++
4 files changed, 66 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a2f3237..9965228 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -15,6 +15,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
config ARCH_LS1046A
bool
@@ -27,6 +28,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
config ARCH_LS2080A
bool
@@ -39,6 +41,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
config FSL_LSCH2
bool
@@ -71,6 +74,9 @@ config SYS_FSL_ERRATUM_A009798
config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
+config SYS_FSL_ERRATUM_A009007
+ bool "Workaround for USB PHY erratum A009007"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1d0354d..1f08b89 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -95,6 +95,47 @@ static void erratum_a008997(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+ u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1;
+ writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ usb_phy = (u32 __iomem *)USB_PHY2;
+ writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ usb_phy = (u32 __iomem *)USB_PHY3;
+ writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE;
+ writew(USB_PHY_RX_EQ_VAL_1,
+ (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2,
+ (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3,
+ (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4,
+ (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_1,
+ (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2,
+ (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3,
+ (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4,
+ (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -263,6 +304,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -442,6 +484,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index a7e36cd..9a9eeae 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -345,6 +345,15 @@ struct ccsr_gur {
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY1 0x084F0000
+#define USB_PHY2 0x08500000
+#define USB_PHY3 0x08510000
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+/* TODO : make it generic */
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index cdc08ed..f4fdee1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -138,6 +138,14 @@
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
#define USB_PCSTXSWINGFULL 0x47
+#define DCSR_BASE 0x700000000ULL
+#define DCSR_USB_PHY1 0x4600000
+#define DCSR_USB_PHY2 0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x1006
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x0080
+#define USB_PHY_RX_EQ_VAL_3 0x0380
+#define USB_PHY_RX_EQ_VAL_4 0x0b80
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009008
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
` (3 preceding siblings ...)
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009007 Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009798 Suresh Gupta
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++
3 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 28bf778..9f0188a 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A009008
menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -31,6 +32,9 @@ config NUM_DDR_CONTROLLERS
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008
+ bool "Workaround for USB PHY erratum A009008"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..c54daee 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
return major;
}
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+ val &= ~(0xF << 6);
+ out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
void s_init(void)
{
}
@@ -146,6 +156,8 @@ int arch_soc_init(void)
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
+ /* Erratum */
+ erratum_a009008();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR 0x070
+#define USB_TXVREFTUNE 0x9
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u32 dpslpcr;
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009798
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
` (4 preceding siblings ...)
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009008 Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-008997 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009007 Suresh Gupta
7 siblings, 0 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
3 files changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9f0188a..f816ed1 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -35,6 +36,9 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index c54daee..2e64708 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+ out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
void s_init(void)
{
}
@@ -158,6 +167,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
+ erratum_a009798();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR 0x070
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-008997
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
` (5 preceding siblings ...)
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009798 Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009007 Suresh Gupta
7 siblings, 0 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 16 ++++++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 9 +++++++++
3 files changed, 29 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f816ed1..d8a8257 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -39,6 +40,9 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997
+ bool "Workaround for USB PHY erratum A008997"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 2e64708..19eb361 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+ u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+ writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+ (u8 *)(usb_phy) + USB_PHY_TX_OVRD_DRV_LO);
+ writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+ (u8 *)(usb_phy) + USB_PHY_MPLL_OVRD_IN_HI);
+ writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+ (u8 *)(usb_phy) + USB_PHY_LEVEL_OVRD_IN);
+ writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+ (u8 *)(usb_phy) + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
void s_init(void)
{
}
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..c0e4372 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,15 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR 0x070
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PHY_BASE 0x08510000
+#define USB_PHY_TX_OVRD_DRV_LO 0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI 0x0024
+#define USB_PHY_LEVEL_OVRD_IN 0x002a
+#define USB_PHY_TX_OVRD_IN_HI 0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL 0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL 0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL 0x0003
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009007
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
` (6 preceding siblings ...)
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-008997 Suresh Gupta
@ 2016-10-25 7:05 ` Suresh Gupta
7 siblings, 0 replies; 10+ messages in thread
From: Suresh Gupta @ 2016-10-25 7:05 UTC (permalink / raw)
To: u-boot
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index d8a8257..9313c11 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -43,6 +44,9 @@ config SYS_FSL_ERRATUM_A009798
config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
+config SYS_FSL_ERRATUM_A009007
+ bool "Workaround for USB PHY erratum A009007"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 19eb361..4754907 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+ u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+ writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
void s_init(void)
{
}
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
#define USB_PHY_MPLL_OVRD_IN_HI 0x0024
#define USB_PHY_LEVEL_OVRD_IN 0x002a
#define USB_PHY_TX_OVRD_IN_HI 0x2002
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
#define USB_PHY_MPLL_OVRD_IN_HI_VAL 0x0080
#define USB_PHY_LEVEL_OVRD_IN_VAL 0xA9A5
#define USB_PHY_TX_OVRD_IN_HI_VAL 0x0003
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8004
+#define USB_PHY_RX_EQ_VAL_4 0x800C
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
1.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008 Suresh Gupta
@ 2016-11-07 18:59 ` york sun
0 siblings, 0 replies; 10+ messages in thread
From: york sun @ 2016-11-07 18:59 UTC (permalink / raw)
To: u-boot
On 10/25/2016 12:03 AM, Suresh Gupta wrote:
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXVREFTUNE value to 1001 is observed, change
> set the same vale.
>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++
> .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
> 4 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 94ec8d5..ec3e50d 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -12,6 +12,7 @@ config ARCH_LS1043A
> select SYS_FSL_DDR_VER_50
> select SYS_FSL_ERRATUM_A010315
> select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
>
> config ARCH_LS1046A
> bool
> @@ -21,6 +22,7 @@ config ARCH_LS1046A
> select SYS_FSL_DDR_VER_50
> select SYS_FSL_ERRATUM_A010539
> select SYS_FSL_SRDS_2
> + select SYS_FSL_ERRATUM_A009008
>
> config ARCH_LS2080A
> bool
> @@ -30,6 +32,7 @@ config ARCH_LS2080A
> select SYS_FSL_DDR_VER_50
> select SYS_FSL_HAS_DP_DDR
> select SYS_FSL_SRDS_2
> + select SYS_FSL_ERRATUM_A009008
>
> config FSL_LSCH2
> bool
> @@ -53,6 +56,9 @@ config SYS_FSL_ERRATUM_A010315
> config SYS_FSL_ERRATUM_A010539
> bool "Workaround for PIN MUX erratum A010539"
>
> +config SYS_FSL_ERRATUM_A009008
> + bool "Workaround for USB PHY erratum A009008"
> +
> config MAX_CPUS
> int "Maximum number of CPUs permitted for Layerscape"
> default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index d68eeba..88cced1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -26,6 +26,29 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +static void erratum_a009008(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
> +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
I think it is better use CONFIG_ARCH_LS1046A which is defined by
Kconfig. The old macros are defined in header file. We will convert them
to use Kconfig eventually. Agree?
York
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-11-07 18:59 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-25 7:05 [U-Boot] [PATCH] Add workaround for USB PHY errata Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008 Suresh Gupta
2016-11-07 18:59 ` york sun
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009798 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-008997 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009007 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009008 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009798 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-008997 Suresh Gupta
2016-10-25 7:05 ` [U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009007 Suresh Gupta
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