From: Keerthy <j-keerthy@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
Date: Sat, 29 Oct 2016 15:19:10 +0530 [thread overview]
Message-ID: <1477734550-17989-2-git-send-email-j-keerthy@ti.com> (raw)
In-Reply-To: <1477734550-17989-1-git-send-email-j-keerthy@ti.com>
While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.
Fix this to mark the regions as XN by default.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
Changes in v2:
* Changed printing option value from decimal to hex.
arch/arm/include/asm/system.h | 2 +-
arch/arm/lib/cache-cp15.c | 5 +++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b928bd8..2f430ad 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -329,7 +329,7 @@ static inline void set_dacr(unsigned int val)
/* options available for data cache on each page */
enum dcache_option {
- DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+ DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9f9fc9..e9bbcf5 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
+#ifdef CONFIG_ARMV7_LPAE
+ debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
+ option);
+#else
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
+#endif
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
--
1.9.1
next prev parent reply other threads:[~2016-10-29 9:49 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-29 9:49 [U-Boot] [PATCH v2 1/2] arm: print the cache config option in hex instead of decimal Keerthy
2016-10-29 9:49 ` Keerthy [this message]
2016-10-29 17:41 ` [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode Tom Rini
2016-10-29 17:44 ` Marek Vasut
2016-10-29 17:47 ` Tom Rini
2016-10-29 17:49 ` Marek Vasut
2016-10-30 1:59 ` Keerthy
2016-10-30 12:00 ` Marek Vasut
2016-11-07 4:07 ` Keerthy
2016-11-13 20:56 ` [U-Boot] [U-Boot, v2, " Tom Rini
2016-10-29 17:41 ` [U-Boot] [PATCH v2 1/2] arm: print the cache config option in hex instead of decimal Tom Rini
2016-11-13 20:56 ` [U-Boot] [U-Boot, v2, " Tom Rini
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