* [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework
@ 2016-11-01 10:04 macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition macro.wave.z at gmail.com
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: macro.wave.z at gmail.com @ 2016-11-01 10:04 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
v1-v2 changes:
- The new config options are introduced in Kconfig when used for first time
- Introduce new config options in armv8/Kconfig instead of LS1043 platform
- Move previous patch 5/6 to current 2/6 place
v1 notes:
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are
implemented a default dummy one, it is up to each platform to implement their
own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI.
Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up.
The last 6/6 adds a most simple implementation on NXP LS1043 platform, to
verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and
merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6):
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
ARMv8: Enable SMC instruction
ARMv8: Add secure sections for PSCI text and data
ARMv8: Add basic PSCI framework
ARMv8: Setup PSCI memory and dt
ARMv8: LS1043A: Enable LS1043A default PSCI support
arch/arm/config.mk | 3 +-
arch/arm/cpu/armv8/Kconfig | 44 ++++
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/cpu-dt.c | 12 +-
arch/arm/cpu/armv8/cpu.c | 22 ++
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +-
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +-
arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++
arch/arm/cpu/armv8/psci.S | 286 +++++++++++++++++++++++
arch/arm/cpu/armv8/sec_firmware.c | 2 +-
arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +-
arch/arm/cpu/armv8/u-boot.lds | 57 +++++
arch/arm/include/asm/armv8/sec_firmware.h | 2 +-
arch/arm/include/asm/macro.h | 2 +-
arch/arm/include/asm/psci.h | 15 ++
arch/arm/include/asm/secure.h | 2 +-
arch/arm/include/asm/system.h | 11 +
arch/arm/lib/bootm-fdt.c | 3 +-
arch/arm/lib/bootm.c | 3 +
arch/arm/lib/psci-dt.c | 5 +-
board/freescale/ls1043ardb/Kconfig | 9 +
configs/ls1043ardb_defconfig | 1 +
include/configs/ls1043ardb.h | 2 +-
24 files changed, 498 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
create mode 100644 arch/arm/cpu/armv8/psci.S
--
2.1.4
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
2016-11-01 10:04 [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework macro.wave.z at gmail.com
@ 2016-11-01 10:04 ` macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-01 10:04 ` [U-Boot] [PATCH v2 2/6] ARMv8: Enable SMC instruction macro.wave.z at gmail.com
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: macro.wave.z at gmail.com @ 2016-11-01 10:04 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/cpu/armv8/cpu-dt.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 ++-
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 ++-
arch/arm/cpu/armv8/sec_firmware.c | 2 +-
arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +-
arch/arm/include/asm/armv8/sec_firmware.h | 2 +-
arch/arm/lib/bootm-fdt.c | 2 +-
arch/arm/lib/psci-dt.c | 2 +-
include/configs/ls1043ardb.h | 2 +-
9 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..659ec27 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -13,7 +13,7 @@
int psci_update_dt(void *fdt)
{
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI)
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
* If the PSCI in SEC Firmware didn't work, avoid to update the
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b7a2e0c..e5dd360 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -402,7 +402,8 @@ int arch_early_init_r(void)
#endif
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
/* Check the psci version to determine if the psci is supported */
psci_ver = sec_firmware_support_psci_version();
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..d95546a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -41,7 +41,8 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int node;
u32 psci_ver;
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 2ddd67e..0b973f0 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -209,7 +209,7 @@ __weak bool sec_firmware_is_valid(const void *sec_firmware_img)
return true;
}
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
/*
* The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
* v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 0c6a462..d4a26b4 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry)
ret
ENDPROC(_sec_firmware_entry)
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
ENTRY(_sec_firmware_support_psci_version)
mov x0, 0x84000000
mov x1, 0x0
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
index eb68185..a4e144b 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -14,7 +14,7 @@
int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
unsigned int sec_firmware_support_psci_version(void);
unsigned int _sec_firmware_support_psci_version(void);
#endif
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index a517550..10a56e8 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -53,7 +53,7 @@ int arch_fixup_fdt(void *blob)
return ret;
#endif
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index baf6d70..41e139e 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,7 @@
int fdt_psci(void *fdt)
{
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 1d0a1ac..d2f8fc0 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -12,7 +12,7 @@
#if defined(CONFIG_FSL_LS_PPA)
#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#define SEC_FIRMWARE_ERET_ADDR_REVERT
-#define CONFIG_ARMV8_PSCI
+#define CONFIG_FSL_PPA_ARMV8_PSCI
#define CONFIG_SYS_LS_PPA_FW_IN_XIP
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
--
2.1.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 2/6] ARMv8: Enable SMC instruction
2016-11-01 10:04 [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition macro.wave.z at gmail.com
@ 2016-11-01 10:04 ` macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-01 10:04 ` [U-Boot] [PATCH v2 3/6] ARMv8: Add secure sections for PSCI text and data macro.wave.z at gmail.com
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: macro.wave.z at gmail.com @ 2016-11-01 10:04 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
PSCI implementation needs the SMC instruction to be enabled.
Following the legacy codes pattern, no bit macro definition and bit operation
are used, only the immediate data used in line is changed.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/include/asm/macro.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..35ea002 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -137,7 +137,7 @@ lr .req x30
.macro armv8_switch_to_el2_m, xreg1
/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
- mov \xreg1, #0x5b1
+ mov \xreg1, #0x531
msr scr_el3, \xreg1
msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
mov \xreg1, #0x33ff
--
2.1.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 3/6] ARMv8: Add secure sections for PSCI text and data
2016-11-01 10:04 [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 2/6] ARMv8: Enable SMC instruction macro.wave.z at gmail.com
@ 2016-11-01 10:04 ` macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-01 10:04 ` [U-Boot] [PATCH v2 4/6] ARMv8: Add basic PSCI framework macro.wave.z at gmail.com
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: macro.wave.z at gmail.com @ 2016-11-01 10:04 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/config.mk | 3 ++-
arch/arm/cpu/armv8/Kconfig | 31 +++++++++++++++++++++++
arch/arm/cpu/armv8/u-boot.lds | 57 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 542b897..112e334 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -118,7 +118,8 @@ endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+ -j .u_boot_list -j .rela.dyn
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index cd2d9bb..f2a43b8 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -39,4 +39,35 @@ config PSCI_RESET
Select Y here to make use of PSCI calls for system reset
+config ARMV8_PSCI
+ bool "Enable PSCI support" if EXPERT
+ default n
+ help
+ PSCI is Power State Coordination Interface defined by ARM.
+ The PSCI in U-boot provides a general framework and each platform
+ can implement their own specific PSCI functions.
+ Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+ int "Maximum supported CPUs for PSCI"
+ depends on ARMV8_PSCI
+ default 4
+ help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of CPUs in
+ the actual hardware implementation.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+ hex "Secure address for PSCI image"
+ depends on ARMV8_PSCI
+ help
+ Address for placing the PSCI text, data and stack sections.
+ If not defined, the PSCI sections are placed together with the u-boot
+ but platform can choose to place PSCI code image separately in other
+ places such as some secure RAM built-in SOC etc.
+
+endif
+
endif
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad5..22195b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <config.h>
+#include <asm/psci.h>
+
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x00000000;
. = ALIGN(8);
@@ -23,6 +29,57 @@ SECTIONS
*(.text*)
}
+#ifdef CONFIG_ARMV8_PSCI
+ .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+ ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+ {
+ KEEP(*(.__secure_start))
+ }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+ .secure_text CONFIG_ARMV8_SECURE_BASE :
+ AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+ {
+ *(._secure.text)
+ }
+
+ .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+ {
+ *(._secure.data)
+ }
+
+ .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+ CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+ AT(ADDR(.secure_stack))
+#else
+ AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+ {
+ KEEP(*(.__secure_stack_start))
+
+ . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+ . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+ KEEP(*(.__secure_stack_end))
+ }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+ . = LOADADDR(.secure_stack);
+#endif
+
+ .__secure_end : AT(ADDR(.__secure_end)) {
+ KEEP(*(.__secure_end))
+ LONG(0x1d1071c); /* Must output something to reset LMA */
+ }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
--
2.1.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 4/6] ARMv8: Add basic PSCI framework
2016-11-01 10:04 [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework macro.wave.z at gmail.com
` (2 preceding siblings ...)
2016-11-01 10:04 ` [U-Boot] [PATCH v2 3/6] ARMv8: Add secure sections for PSCI text and data macro.wave.z at gmail.com
@ 2016-11-01 10:04 ` macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support macro.wave.z at gmail.com
5 siblings, 0 replies; 16+ messages in thread
From: macro.wave.z at gmail.com @ 2016-11-01 10:04 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/cpu/armv8/Kconfig | 10 ++
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/psci.S | 286 ++++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/psci.h | 15 +++
4 files changed, 312 insertions(+)
create mode 100644 arch/arm/cpu/armv8/psci.S
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index f2a43b8..173950d 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -57,6 +57,16 @@ config ARMV8_PSCI_NR_CPUS
It is no problem to set a larger value than the number of CPUs in
the actual hardware implementation.
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+ int "Number of CPUs per cluster"
+ depends on ARMV8_PSCI
+ default 0
+ help
+ The number of CPUs per cluster, suppose each cluster has same number
+ of CPU cores, platforms with asymmetric clusters don't apply here.
+ A value 0 or no definition of it works for single cluster system.
+ System with multi-cluster should difine their own exact value.
+
if SYS_HAS_ARMV8_SECURE_BASE
config ARMV8_SECURE_BASE
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..28ba786 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
new file mode 100644
index 0000000..43d5d6b
--- /dev/null
+++ b/arch/arm/cpu/armv8/psci.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+ ENTRY(__fn); \
+ mov w0, #ARM_PSCI_RET_NI; \
+ ret; \
+ ENDPROC(__fn); \
+ .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+ .word __id; \
+ .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+
+.align 3
+_psci_64_table:
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
+PSCI_TABLE(0, 0)
+
+.macro psci_enter
+ /* PSCI call is Fast Call(atomic), so mask DAIF */
+ mrs x15, DAIF
+ stp x15, xzr, [sp, #-16]!
+ ldr x15, =0x3C0
+ msr DAIF, x15
+ /* SMC convention, x18 ~ x30 should be saved by callee */
+ stp x29, x30, [sp, #-16]!
+ stp x27, x28, [sp, #-16]!
+ stp x25, x26, [sp, #-16]!
+ stp x23, x24, [sp, #-16]!
+ stp x21, x22, [sp, #-16]!
+ stp x19, x20, [sp, #-16]!
+ mrs x15, elr_el3
+ stp x18, x15, [sp, #-16]!
+.endm
+
+.macro psci_return
+ /* restore registers */
+ ldp x18, x15, [sp], #16
+ msr elr_el3, x15
+ ldp x19, x20, [sp], #16
+ ldp x21, x22, [sp], #16
+ ldp x23, x24, [sp], #16
+ ldp x25, x26, [sp], #16
+ ldp x27, x28, [sp], #16
+ ldp x29, x30, [sp], #16
+ /* restore DAIF */
+ ldp x15, xzr, [sp], #16
+ msr DAIF, x15
+ eret
+.endm
+
+/* Caller must put PSCI function-ID table base in x9 */
+handle_psci:
+ psci_enter
+1: ldr x10, [x9] /* Load PSCI function table */
+ ubfx x11, x10, #32, #32
+ ubfx x10, x10, #0, #32
+ cbz x10, 3f /* If reach the end, bail out */
+ cmp x10, x0
+ b.eq 2f /* PSCI function found */
+ add x9, x9, #8 /* If not match, try next entry */
+ b 1b
+
+2: blr x11 /* Call PSCI function */
+ psci_return
+
+3: mov x0, #ARM_PSCI_RET_NI
+ psci_return
+
+unknown_smc_id:
+ ldr x0, =0xFFFFFFFF
+ eret
+
+handle_smc32:
+ /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
+ ldr w9, =0x8400001F
+ cmp w0, w9
+ b.gt unknown_smc_id
+ ldr w9, =0x84000000
+ cmp w0, w9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_32_table
+ b handle_psci
+
+handle_smc64:
+ /* check SMC32 or SMC64 calls */
+ ubfx x9, x0, #30, #1
+ cbz x9, handle_smc32
+
+ /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
+ ldr x9, =0xC400001F
+ cmp x0, x9
+ b.gt unknown_smc_id
+ ldr x9, =0xC4000000
+ cmp x0, x9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_64_table
+ b handle_psci
+
+/*
+ * Get CPU ID from MPIDR, suppose every cluster has same number of CPU cores,
+ * Platform with asymmetric clusters should implement their own interface.
+ * In case this function being called by other platform's C code, the ARM
+ * Architecture Procedure Call Standard is considered, e.g. register X0 is
+ * used for the return value, while in this PSCI environment, X0 usually holds
+ * the SMC function identifier, so X0 should be saved by caller function.
+ */
+ENTRY(psci_get_cpu_id)
+#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mrs x9, MPIDR_EL1
+ ubfx x9, x9, #8, #8
+ ldr x10, =CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mul x9, x10, x9
+#else
+ mov x9, xzr
+#endif
+ mrs x10, MPIDR_EL1
+ ubfx x10, x10, #0, #8
+ add x0, x10, x9
+ ret
+ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
+
+/* CPU ID input in x0, stack top output in x0*/
+LENTRY(psci_get_cpu_stack_top)
+ adr x9, __secure_stack_end
+ lsl x0, x0, #ARM_PSCI_STACK_SHIFT
+ sub x0, x9, x0
+ ret
+ENDPROC(psci_get_cpu_stack_top)
+
+unhandled_exception:
+ b unhandled_exception /* simply dead loop */
+
+handle_sync:
+ mov x15, x30
+ mov x14, x0
+
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ mov x9, #1
+ msr spsel, x9
+ mov sp, x0
+
+ mov x0, x14
+ mov x30, x15
+
+ mrs x9, esr_el3
+ ubfx x9, x9, #26, #6
+ cmp x9, #0x13
+ b.eq handle_smc32
+ cmp x9, #0x17
+ b.eq handle_smc64
+
+ b unhandled_exception
+
+ .align 11
+ .globl el3_exception_vectors
+el3_exception_vectors:
+ b unhandled_exception /* Sync, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* Sync, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SPx */
+ .align 7
+ b handle_sync /* Sync, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* Sync, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch32 */
+
+ENTRY(psci_setup_vectors)
+ adr x0, el3_exception_vectors
+ msr vbar_el3, x0
+ ret
+ENDPROC(psci_setup_vectors)
+
+ENTRY(psci_arch_init)
+ ret
+ENDPROC(psci_arch_init)
+.weak psci_arch_init
+
+.popsection
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 9f1f779..ac8b00d 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -45,6 +45,9 @@
#define ARM_PSCI_0_2_FN_BASE 0x84000000
#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+#define ARM_PSCI_0_2_FN64_BASE 0xC4000000
+#define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n))
+
#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
@@ -56,6 +59,12 @@
#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+#define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1)
+#define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3)
+#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4)
+#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
+#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
+
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
@@ -66,6 +75,12 @@
#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12)
+#define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13)
+#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14)
+#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16)
+#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17)
+
/* 1KB stack per core */
#define ARM_PSCI_STACK_SHIFT 10
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
--
2.1.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt
2016-11-01 10:04 [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework macro.wave.z at gmail.com
` (3 preceding siblings ...)
2016-11-01 10:04 ` [U-Boot] [PATCH v2 4/6] ARMv8: Add basic PSCI framework macro.wave.z at gmail.com
@ 2016-11-01 10:04 ` macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-01 10:04 ` [U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support macro.wave.z at gmail.com
5 siblings, 1 reply; 16+ messages in thread
From: macro.wave.z at gmail.com @ 2016-11-01 10:04 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/cpu/armv8/cpu-dt.c | 10 ++++++++++
arch/arm/cpu/armv8/cpu.c | 22 ++++++++++++++++++++++
arch/arm/include/asm/secure.h | 2 +-
arch/arm/include/asm/system.h | 11 +++++++++++
arch/arm/lib/bootm-fdt.c | 3 ++-
arch/arm/lib/bootm.c | 3 +++
arch/arm/lib/psci-dt.c | 5 +++--
7 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 659ec27..753e21f 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/psci.h>
+#include <asm/system.h>
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
@@ -27,5 +28,14 @@ int psci_update_dt(void *fdt)
fdt_psci(fdt);
#endif
#endif
+
+#ifdef CONFIG_ARMV8_PSCI
+ fdt_psci(fdt);
+#ifndef CONFIG_ARMV8_SECURE_BASE
+ /* secure code lives in RAM, keep it alive */
+ fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+ __secure_end - __secure_start);
+#endif
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..5dcb5e2 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
#include <asm/system.h>
+#include <asm/secure.h>
#include <linux/compiler.h>
int cleanup_before_linux(void)
@@ -41,3 +42,24 @@ int cleanup_before_linux(void)
return 0;
}
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ size_t sz = __secure_end - __secure_start;
+
+ memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+ flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+ CONFIG_ARMV8_SECURE_BASE + sz + 1);
+ invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+ relocate_secure_section();
+ secure_ram_addr(psci_setup_vectors)();
+ secure_ram_addr(psci_arch_init)();
+}
+#endif
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 5a403bc..d23044a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,7 +6,7 @@
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
/*
* Warning, horror ahead.
*
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b928bd8..9064e6b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -118,6 +118,17 @@ void smc_call(struct pt_regs *args);
void __noreturn psci_system_reset(void);
void __noreturn psci_system_off(void);
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 10a56e8..b23bce4 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -53,7 +53,8 @@ int arch_fixup_fdt(void *blob)
return ret;
#endif
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI) || \
+ defined(CONFIG_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 53c3141..9fe1a5f 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -291,6 +291,9 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
announce_and_cleanup(fake);
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+ armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
kernel_entry(images->ft_addr, NULL, NULL, NULL);
}
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index 41e139e..cc5e33d 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,8 @@
int fdt_psci(void *fdt)
{
-#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) || \
+ defined(CONFIG_ARMV8_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
@@ -65,7 +66,7 @@ int fdt_psci(void *fdt)
init_psci_node:
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
#endif
switch (psci_ver) {
--
2.1.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support
2016-11-01 10:04 [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework macro.wave.z at gmail.com
` (4 preceding siblings ...)
2016-11-01 10:04 ` [U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt macro.wave.z at gmail.com
@ 2016-11-01 10:04 ` macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
5 siblings, 1 reply; 16+ messages in thread
From: macro.wave.z at gmail.com @ 2016-11-01 10:04 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/cpu/armv8/Kconfig | 3 +++
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++++++++++++++++++++
board/freescale/ls1043ardb/Kconfig | 9 +++++++++
configs/ls1043ardb_defconfig | 1 +
5 files changed, 34 insertions(+)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 173950d..985bfca 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -51,6 +51,7 @@ config ARMV8_PSCI
config ARMV8_PSCI_NR_CPUS
int "Maximum supported CPUs for PSCI"
depends on ARMV8_PSCI
+ default 4 if TARGET_LS1043ARDB
default 4
help
The maximum number of CPUs supported in the PSCI firmware.
@@ -60,6 +61,7 @@ config ARMV8_PSCI_NR_CPUS
config ARMV8_PSCI_CPUS_PER_CLUSTER
int "Number of CPUs per cluster"
depends on ARMV8_PSCI
+ default 4 if TARGET_LS1043ARDB
default 0
help
The number of CPUs per cluster, suppose each cluster has same number
@@ -72,6 +74,7 @@ if SYS_HAS_ARMV8_SECURE_BASE
config ARMV8_SECURE_BASE
hex "Secure address for PSCI image"
depends on ARMV8_PSCI
+ default 0x10010000 if TARGET_LS1043ARDB
help
Address for placing the PSCI text, data and stack sections.
If not defined, the PSCI sections are placed together with the u-boot
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 51c1cee..423b4b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
endif
ifneq ($(CONFIG_ARCH_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
new file mode 100644
index 0000000..86045ac
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+ ldr w0, =0x00010000 /* PSCI v1.0 */
+ ret
+
+ .popsection
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index 51818ec..0c596f9 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,4 +13,13 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1043ardb"
+config SYS_HAS_ARMV8_SECURE_BASE
+ bool "Enable secure RAM for PSCI image"
+ depends on ARMV8_PSCI
+ default y
+ help
+ PSCI image can be re-located to secure RAM.
+ If enabled, please also define the value for ARMV8_SECURE_BASE,
+ for LS1043ARDB, it is address in OCRAM.
+
endif
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 7d627af..4bfd0aa 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -27,3 +27,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_ARMV8_PSCI=y
--
2.1.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
2016-11-01 10:04 ` [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition macro.wave.z at gmail.com
@ 2016-11-02 14:27 ` Tom Rini
2016-11-03 9:56 ` Hongbo Zhang
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2016-11-02 14:27 UTC (permalink / raw)
To: u-boot
On Tue, Nov 01, 2016 at 06:04:27PM +0800, macro.wave.z at gmail.com wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
> implementation in PPA firmware, but this macro naming too generic, so this
> patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
> And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
> which will be added in following patchs.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
[snip]
> diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
> index 1d0a1ac..d2f8fc0 100644
> --- a/include/configs/ls1043ardb.h
> +++ b/include/configs/ls1043ardb.h
> @@ -12,7 +12,7 @@
> #if defined(CONFIG_FSL_LS_PPA)
> #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
> #define SEC_FIRMWARE_ERET_ADDR_REVERT
> -#define CONFIG_ARMV8_PSCI
> +#define CONFIG_FSL_PPA_ARMV8_PSCI
>
> #define CONFIG_SYS_LS_PPA_FW_IN_XIP
> #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
This will trip-up the whitelist check, please move the new symbol to
Kconfig and select it from LS1043ARDB + FSL_LS_PPA. Thanks!
--
Tom
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* [U-Boot] [PATCH v2 2/6] ARMv8: Enable SMC instruction
2016-11-01 10:04 ` [U-Boot] [PATCH v2 2/6] ARMv8: Enable SMC instruction macro.wave.z at gmail.com
@ 2016-11-02 14:27 ` Tom Rini
0 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2016-11-02 14:27 UTC (permalink / raw)
To: u-boot
On Tue, Nov 01, 2016 at 06:04:28PM +0800, macro.wave.z at gmail.com wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> PSCI implementation needs the SMC instruction to be enabled.
> Following the legacy codes pattern, no bit macro definition and bit operation
> are used, only the immediate data used in line is changed.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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* [U-Boot] [PATCH v2 3/6] ARMv8: Add secure sections for PSCI text and data
2016-11-01 10:04 ` [U-Boot] [PATCH v2 3/6] ARMv8: Add secure sections for PSCI text and data macro.wave.z at gmail.com
@ 2016-11-02 14:27 ` Tom Rini
0 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2016-11-02 14:27 UTC (permalink / raw)
To: u-boot
On Tue, Nov 01, 2016 at 06:04:29PM +0800, macro.wave.z at gmail.com wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
> hold PSCI text and data, and it is based on the legacy implementation of ARMv7.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt
2016-11-01 10:04 ` [U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt macro.wave.z at gmail.com
@ 2016-11-02 14:27 ` Tom Rini
2016-11-03 10:20 ` Hongbo Zhang
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2016-11-02 14:27 UTC (permalink / raw)
To: u-boot
On Tue, Nov 01, 2016 at 06:04:31PM +0800, macro.wave.z at gmail.com wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
> place, this patch does all the setup steps.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
[snip]
> diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
> index 659ec27..753e21f 100644
> --- a/arch/arm/cpu/armv8/cpu-dt.c
> +++ b/arch/arm/cpu/armv8/cpu-dt.c
> @@ -6,6 +6,7 @@
>
> #include <common.h>
> #include <asm/psci.h>
> +#include <asm/system.h>
> #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
> #include <asm/armv8/sec_firmware.h>
> #endif
> @@ -27,5 +28,14 @@ int psci_update_dt(void *fdt)
> fdt_psci(fdt);
> #endif
> #endif
> +
> +#ifdef CONFIG_ARMV8_PSCI
> + fdt_psci(fdt);
> +#ifndef CONFIG_ARMV8_SECURE_BASE
> + /* secure code lives in RAM, keep it alive */
> + fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
> + __secure_end - __secure_start);
> +#endif
> +#endif
> return 0;
Looking just above this context, I think we need to re-work the #if
tests now when adding this in.
--
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support
2016-11-01 10:04 ` [U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support macro.wave.z at gmail.com
@ 2016-11-02 14:27 ` Tom Rini
2016-11-03 10:12 ` Hongbo Zhang
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2016-11-02 14:27 UTC (permalink / raw)
To: u-boot
On Tue, Nov 01, 2016 at 06:04:32PM +0800, macro.wave.z at gmail.com wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> A most basic PSCI implementation with only one psci_version is added for
> LS1043A, this can verify the generic PSCI framework, and more platform specific
> implementation will be added later.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> ---
> arch/arm/cpu/armv8/Kconfig | 3 +++
> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
> arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++++++++++++++++++++
> board/freescale/ls1043ardb/Kconfig | 9 +++++++++
> configs/ls1043ardb_defconfig | 1 +
> 5 files changed, 34 insertions(+)
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
>
> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> index 173950d..985bfca 100644
> --- a/arch/arm/cpu/armv8/Kconfig
> +++ b/arch/arm/cpu/armv8/Kconfig
> @@ -51,6 +51,7 @@ config ARMV8_PSCI
> config ARMV8_PSCI_NR_CPUS
> int "Maximum supported CPUs for PSCI"
> depends on ARMV8_PSCI
> + default 4 if TARGET_LS1043ARDB
> default 4
Since 4 is the default we don't need to add in a line here.
> @@ -60,6 +61,7 @@ config ARMV8_PSCI_NR_CPUS
> config ARMV8_PSCI_CPUS_PER_CLUSTER
> int "Number of CPUs per cluster"
> depends on ARMV8_PSCI
> + default 4 if TARGET_LS1043ARDB
> default 0
> help
> The number of CPUs per cluster, suppose each cluster has same number
> @@ -72,6 +74,7 @@ if SYS_HAS_ARMV8_SECURE_BASE
> config ARMV8_SECURE_BASE
> hex "Secure address for PSCI image"
> depends on ARMV8_PSCI
> + default 0x10010000 if TARGET_LS1043ARDB
> help
> Address for placing the PSCI text, data and stack sections.
> If not defined, the PSCI sections are placed together with the u-boot
I think we should put those of these into the defconfig and once we add
more targets we can see if there's good reason, and non-TARGET_xxx we
can key off of to provide default values.
Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
2016-11-02 14:27 ` Tom Rini
@ 2016-11-03 9:56 ` Hongbo Zhang
2016-11-04 8:25 ` Hongbo Zhang
0 siblings, 1 reply; 16+ messages in thread
From: Hongbo Zhang @ 2016-11-03 9:56 UTC (permalink / raw)
To: u-boot
On Wed, Nov 2, 2016 at 10:27 PM, Tom Rini <trini@konsulko.com> wrote:
> On Tue, Nov 01, 2016 at 06:04:27PM +0800, macro.wave.z at gmail.com wrote:
>
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
>> implementation in PPA firmware, but this macro naming too generic, so this
>> patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
>> And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
>> which will be added in following patchs.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> [snip]
>> diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
>> index 1d0a1ac..d2f8fc0 100644
>> --- a/include/configs/ls1043ardb.h
>> +++ b/include/configs/ls1043ardb.h
>> @@ -12,7 +12,7 @@
>> #if defined(CONFIG_FSL_LS_PPA)
>> #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
>> #define SEC_FIRMWARE_ERET_ADDR_REVERT
>> -#define CONFIG_ARMV8_PSCI
>> +#define CONFIG_FSL_PPA_ARMV8_PSCI
>>
>> #define CONFIG_SYS_LS_PPA_FW_IN_XIP
>> #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
>
> This will trip-up the whitelist check, please move the new symbol to
> Kconfig and select it from LS1043ARDB + FSL_LS_PPA. Thanks!
>
Payed much attention to the config options I introduced in the common
framework, but neglected this legacy one.
Yes will update this.
> --
> Tom
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support
2016-11-02 14:27 ` Tom Rini
@ 2016-11-03 10:12 ` Hongbo Zhang
0 siblings, 0 replies; 16+ messages in thread
From: Hongbo Zhang @ 2016-11-03 10:12 UTC (permalink / raw)
To: u-boot
On Wed, Nov 2, 2016 at 10:27 PM, Tom Rini <trini@konsulko.com> wrote:
> On Tue, Nov 01, 2016 at 06:04:32PM +0800, macro.wave.z at gmail.com wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> A most basic PSCI implementation with only one psci_version is added for
>> LS1043A, this can verify the generic PSCI framework, and more platform specific
>> implementation will be added later.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> ---
>> arch/arm/cpu/armv8/Kconfig | 3 +++
>> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
>> arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++++++++++++++++++++
>> board/freescale/ls1043ardb/Kconfig | 9 +++++++++
>> configs/ls1043ardb_defconfig | 1 +
>> 5 files changed, 34 insertions(+)
>> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
>>
>> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
>> index 173950d..985bfca 100644
>> --- a/arch/arm/cpu/armv8/Kconfig
>> +++ b/arch/arm/cpu/armv8/Kconfig
>> @@ -51,6 +51,7 @@ config ARMV8_PSCI
>> config ARMV8_PSCI_NR_CPUS
>> int "Maximum supported CPUs for PSCI"
>> depends on ARMV8_PSCI
>> + default 4 if TARGET_LS1043ARDB
>> default 4
>
> Since 4 is the default we don't need to add in a line here.
>
>> @@ -60,6 +61,7 @@ config ARMV8_PSCI_NR_CPUS
>> config ARMV8_PSCI_CPUS_PER_CLUSTER
>> int "Number of CPUs per cluster"
>> depends on ARMV8_PSCI
>> + default 4 if TARGET_LS1043ARDB
>> default 0
>> help
>> The number of CPUs per cluster, suppose each cluster has same number
>> @@ -72,6 +74,7 @@ if SYS_HAS_ARMV8_SECURE_BASE
>> config ARMV8_SECURE_BASE
>> hex "Secure address for PSCI image"
>> depends on ARMV8_PSCI
>> + default 0x10010000 if TARGET_LS1043ARDB
>> help
>> Address for placing the PSCI text, data and stack sections.
>> If not defined, the PSCI sections are placed together with the u-boot
>
> I think we should put those of these into the defconfig and once we add
> more targets we can see if there's good reason, and non-TARGET_xxx we
> can key off of to provide default values.
>
I knew when more targets added there will be mess here, I always tried
to follow your suggestion to move these three configs here, and forgot
to use platform defconfig.
Yes I'll move these three configs to our platform defconfig.
> Thanks!
>
> --
> Tom
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt
2016-11-02 14:27 ` Tom Rini
@ 2016-11-03 10:20 ` Hongbo Zhang
0 siblings, 0 replies; 16+ messages in thread
From: Hongbo Zhang @ 2016-11-03 10:20 UTC (permalink / raw)
To: u-boot
On Wed, Nov 2, 2016 at 10:27 PM, Tom Rini <trini@konsulko.com> wrote:
> On Tue, Nov 01, 2016 at 06:04:31PM +0800, macro.wave.z at gmail.com wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
>> place, this patch does all the setup steps.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> [snip]
>> diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
>> index 659ec27..753e21f 100644
>> --- a/arch/arm/cpu/armv8/cpu-dt.c
>> +++ b/arch/arm/cpu/armv8/cpu-dt.c
>> @@ -6,6 +6,7 @@
>>
>> #include <common.h>
>> #include <asm/psci.h>
>> +#include <asm/system.h>
>> #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
>> #include <asm/armv8/sec_firmware.h>
>> #endif
>> @@ -27,5 +28,14 @@ int psci_update_dt(void *fdt)
>> fdt_psci(fdt);
>> #endif
>> #endif
>> +
>> +#ifdef CONFIG_ARMV8_PSCI
>> + fdt_psci(fdt);
>> +#ifndef CONFIG_ARMV8_SECURE_BASE
>> + /* secure code lives in RAM, keep it alive */
>> + fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
>> + __secure_end - __secure_start);
>> +#endif
>> +#endif
>> return 0;
>
> Looking just above this context, I think we need to re-work the #if
> tests now when adding this in.
>
Yes, when the CONFIG_FSL_PPA_ARMV8_PSCI moved to Kconfig, there should
be less #if #else in the function psci_update_dt(), so I can add my
codes neatly.
> --
> Tom
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
2016-11-03 9:56 ` Hongbo Zhang
@ 2016-11-04 8:25 ` Hongbo Zhang
0 siblings, 0 replies; 16+ messages in thread
From: Hongbo Zhang @ 2016-11-04 8:25 UTC (permalink / raw)
To: u-boot
Talked to the author Zhiqiang Hou who introduced the previous
CONFIG_ARMV8_PSCI, although this config was introduced due to FSL PPA,
codes covered by it in the armv8/cpu-dt.c, bootm-dt.c, psci-dt.c also
work for the coming generic ARMv8 PSCI framework, what's more,
Zhiqiang is sending patches to clean up PPA related configs to
Kconfig, so I don't need to send this 1/6 patch any more, I'll send
the other updated 5 patches in v3.
On Thu, Nov 3, 2016 at 5:56 PM, Hongbo Zhang <macro.wave.z@gmail.com> wrote:
> On Wed, Nov 2, 2016 at 10:27 PM, Tom Rini <trini@konsulko.com> wrote:
>> On Tue, Nov 01, 2016 at 06:04:27PM +0800, macro.wave.z at gmail.com wrote:
>>
>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>
>>> NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
>>> implementation in PPA firmware, but this macro naming too generic, so this
>>> patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
>>> And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
>>> which will be added in following patchs.
>>>
>>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> [snip]
>>> diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
>>> index 1d0a1ac..d2f8fc0 100644
>>> --- a/include/configs/ls1043ardb.h
>>> +++ b/include/configs/ls1043ardb.h
>>> @@ -12,7 +12,7 @@
>>> #if defined(CONFIG_FSL_LS_PPA)
>>> #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
>>> #define SEC_FIRMWARE_ERET_ADDR_REVERT
>>> -#define CONFIG_ARMV8_PSCI
>>> +#define CONFIG_FSL_PPA_ARMV8_PSCI
>>>
>>> #define CONFIG_SYS_LS_PPA_FW_IN_XIP
>>> #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
>>
>> This will trip-up the whitelist check, please move the new symbol to
>> Kconfig and select it from LS1043ARDB + FSL_LS_PPA. Thanks!
>>
>
> Payed much attention to the config options I introduced in the common
> framework, but neglected this legacy one.
> Yes will update this.
>
>> --
>> Tom
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-11-04 8:25 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-01 10:04 [U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-03 9:56 ` Hongbo Zhang
2016-11-04 8:25 ` Hongbo Zhang
2016-11-01 10:04 ` [U-Boot] [PATCH v2 2/6] ARMv8: Enable SMC instruction macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-01 10:04 ` [U-Boot] [PATCH v2 3/6] ARMv8: Add secure sections for PSCI text and data macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-01 10:04 ` [U-Boot] [PATCH v2 4/6] ARMv8: Add basic PSCI framework macro.wave.z at gmail.com
2016-11-01 10:04 ` [U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-03 10:20 ` Hongbo Zhang
2016-11-01 10:04 ` [U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support macro.wave.z at gmail.com
2016-11-02 14:27 ` Tom Rini
2016-11-03 10:12 ` Hongbo Zhang
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