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* [PATCH 0/5] dev_priv cleanup continuation
@ 2016-11-04 14:42 Tvrtko Ursulin
  2016-11-04 14:42 ` [PATCH 1/5] drm/i915: Assorted dev_priv cleanups Tvrtko Ursulin
                   ` (7 more replies)
  0 siblings, 8 replies; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-04 14:42 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

A few small patches towards the goal of getting rid of the
__I915__ polymorphism.

Series starts with three patches to convert some more IS/HAS macros to accepting
dev_priv only, and continues with a patch to make all users of INTEL_INFO pass
in dev_priv, apart from the ones which can be replaced with INTEL_GEN.

This leaves the disruptive conversion to the latter as the only remaining bit
before the __I915__ can be completely eliminated.

To start with that, last patch converts i915_drv.c, going with the idea to do
this gradually over time on a file by file basis.

When all this is done at some point in the future, we can also tackle the
opportunities to change some local function signatures to take dev_priv and so
make further cleanups where appropriate.

Tvrtko Ursulin (5):
  drm/i915: Assorted dev_priv cleanups
  drm/i915: More assorted dev_priv cleanups
  drm/i915: Further assorted dev_priv cleanups
  drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen
    use
  drm/i915: Convert i915_drv.c to INTEL_GEN

 drivers/gpu/drm/i915/i915_drv.c            | 18 ++++----
 drivers/gpu/drm/i915/i915_drv.h            | 70 +++++++++++++++---------------
 drivers/gpu/drm/i915/i915_gem.c            | 13 +++---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  6 +--
 drivers/gpu/drm/i915/i915_gem_gtt.c        |  2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c     |  3 +-
 drivers/gpu/drm/i915/i915_gem_userptr.c    |  3 +-
 drivers/gpu/drm/i915/i915_gpu_error.c      |  4 +-
 drivers/gpu/drm/i915/i915_irq.c            |  8 ++--
 drivers/gpu/drm/i915/intel_color.c         | 31 ++++++-------
 drivers/gpu/drm/i915/intel_crt.c           |  8 ++--
 drivers/gpu/drm/i915/intel_display.c       | 32 +++++++-------
 drivers/gpu/drm/i915/intel_dp.c            |  8 ++--
 drivers/gpu/drm/i915/intel_fbdev.c         | 10 ++---
 drivers/gpu/drm/i915/intel_guc_loader.c    | 10 ++---
 drivers/gpu/drm/i915/intel_hotplug.c       |  2 +-
 drivers/gpu/drm/i915/intel_pm.c            |  7 +--
 drivers/gpu/drm/i915/intel_psr.c           |  2 +-
 18 files changed, 118 insertions(+), 119 deletions(-)

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PATCH 1/5] drm/i915: Assorted dev_priv cleanups
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
@ 2016-11-04 14:42 ` Tvrtko Ursulin
  2016-11-09 10:37   ` David Weinehall
  2016-11-04 14:42 ` [PATCH 2/5] drm/i915: More assorted " Tvrtko Ursulin
                   ` (6 subsequent siblings)
  7 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-04 14:42 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

A small selection of macros which can only accept dev_priv from
now on and a resulting trickle of fixups.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            | 31 ++++++++++++++++--------------
 drivers/gpu/drm/i915/i915_gem.c            | 13 +++++++------
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  4 ++--
 drivers/gpu/drm/i915/i915_gem_stolen.c     |  3 ++-
 drivers/gpu/drm/i915/i915_gem_userptr.c    |  3 ++-
 drivers/gpu/drm/i915/i915_gpu_error.c      |  2 +-
 drivers/gpu/drm/i915/intel_dp.c            |  6 +++---
 7 files changed, 34 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4735b4177100..45a30f730216 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2851,28 +2851,31 @@ struct drm_i915_cmd_table {
 #define ALL_ENGINES	(~0)
 
 #define HAS_ENGINE(dev_priv, id) \
-	(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
+	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
 
 #define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
 #define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
 #define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
 #define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)
 
-#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
-#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
-#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
+#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
+#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
+#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
 #define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
 				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
-#define HWS_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->hws_needs_physical)
 
-#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
-#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)
-#define USES_PPGTT(dev)		(i915.enable_ppgtt)
-#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
+#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
 
-#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
+#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
+#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
+		((dev_priv)->info.has_logical_ring_contexts)
+#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
+#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
+#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)
+
+#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
+#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
+		((dev_priv)->info.overlay_needs_physical)
 
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_845G(dev_priv))
@@ -2889,8 +2892,8 @@ struct drm_i915_cmd_table {
  * legacy irq no. is shared with another device. The kernel then disables that
  * interrupt source and so prevents the other device from working properly.
  */
-#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
-#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
+#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
+#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1f995ced524e..e9808c8ef55b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -48,7 +48,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
 static bool cpu_cache_is_coherent(struct drm_device *dev,
 				  enum i915_cache_level level)
 {
-	return HAS_LLC(dev) || level != I915_CACHE_NONE;
+	return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
 }
 
 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
@@ -1757,7 +1757,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
 		goto err_rpm;
 
 	/* Access to snoopable pages through the GTT is incoherent. */
-	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
+	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
 		ret = -EFAULT;
 		goto err_unlock;
 	}
@@ -3414,7 +3414,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 		if (ret)
 			return ret;
 
-		if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) {
+		if (!HAS_LLC(to_i915(obj->base.dev)) &&
+		    cache_level != I915_CACHE_NONE) {
 			/* Access to snoopable pages through the GTT is
 			 * incoherent and on some machines causes a hard
 			 * lockup. Relinquish the CPU mmaping to force
@@ -4199,7 +4200,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size)
 	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
 
-	if (HAS_LLC(dev)) {
+	if (HAS_LLC(dev_priv)) {
 		/* On some devices, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 * compared to uncached.  Graphics requests other than
@@ -4444,7 +4445,7 @@ int i915_gem_suspend(struct drm_device *dev)
 	 * machines is a good idea, we don't - just in case it leaves the
 	 * machine in an unusable condition.
 	 */
-	if (HAS_HW_CONTEXTS(dev)) {
+	if (HAS_HW_CONTEXTS(dev_priv)) {
 		int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 		WARN_ON(reset && reset != -ENODEV);
 	}
@@ -4535,7 +4536,7 @@ i915_gem_init_hw(struct drm_device *dev)
 	/* Double layer security blanket, see i915_gem_init() */
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-	if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
+	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
 	if (IS_HASWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 322c580a739f..9c7d9c88d879 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -287,7 +287,7 @@ static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 	if (DBG_USE_CPU_RELOC)
 		return DBG_USE_CPU_RELOC > 0;
 
-	return (HAS_LLC(obj->base.dev) ||
+	return (HAS_LLC(to_i915(obj->base.dev)) ||
 		obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 		obj->cache_level != I915_CACHE_NONE);
 }
@@ -833,7 +833,7 @@ need_reloc_mappable(struct i915_vma *vma)
 		return false;
 
 	/* See also use_cpu_reloc() */
-	if (HAS_LLC(vma->obj->base.dev))
+	if (HAS_LLC(to_i915(vma->obj->base.dev)))
 		return false;
 
 	if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index b1d367dba347..54085df1f227 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -596,7 +596,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev,
 
 	obj->stolen = stolen;
 	obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
-	obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
+	obj->cache_level = HAS_LLC(to_i915(dev)) ?
+			   I915_CACHE_LLC : I915_CACHE_NONE;
 
 	if (i915_gem_object_pin_pages(obj))
 		goto cleanup;
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 64261639f547..107ddf51065e 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -753,12 +753,13 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = {
 int
 i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
 {
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_i915_gem_userptr *args = data;
 	struct drm_i915_gem_object *obj;
 	int ret;
 	u32 handle;
 
-	if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) {
+	if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) {
 		/* We cannot support coherent userptr objects on hw without
 		 * LLC and broken snooping.
 		 */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 204093f3eaa5..d430b9441e6b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1489,7 +1489,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 	}
 
 	/* 4: Everything else */
-	if (HAS_HW_CONTEXTS(dev))
+	if (HAS_HW_CONTEXTS(dev_priv))
 		error->ccid = I915_READ(CCID);
 
 	if (INTEL_INFO(dev)->gen >= 8) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9df331b3305b..d4e9cf3ad26e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -942,14 +942,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		uint8_t *recv, int recv_size)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv =
+			to_i915(intel_dig_port->base.base.dev);
 	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 	uint32_t aux_clock_divider;
 	int i, ret, recv_bytes;
 	uint32_t status;
 	int try, clock = 0;
-	bool has_aux_irq = HAS_AUX_IRQ(dev);
+	bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
 	bool vdd;
 
 	pps_lock(intel_dp);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 2/5] drm/i915: More assorted dev_priv cleanups
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
  2016-11-04 14:42 ` [PATCH 1/5] drm/i915: Assorted dev_priv cleanups Tvrtko Ursulin
@ 2016-11-04 14:42 ` Tvrtko Ursulin
  2016-11-04 15:32   ` Ville Syrjälä
  2016-11-04 14:42 ` [PATCH 3/5] drm/i915: Further " Tvrtko Ursulin
                   ` (5 subsequent siblings)
  7 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-04 14:42 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

A small selection of macros which can only accept dev_priv from
now on and a resulting trickle of fixups.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       | 27 ++++++++++++---------------
 drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
 drivers/gpu/drm/i915/i915_irq.c       |  6 +++---
 drivers/gpu/drm/i915/intel_crt.c      |  8 ++++----
 drivers/gpu/drm/i915/intel_display.c  |  4 ++--
 drivers/gpu/drm/i915/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/intel_hotplug.c  |  2 +-
 drivers/gpu/drm/i915/intel_psr.c      |  2 +-
 8 files changed, 25 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 45a30f730216..6060e41d25e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2901,28 +2901,25 @@ struct drm_i915_cmd_table {
 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
 					 !(IS_I915G(dev_priv) || \
 					 IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
-#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
-
-#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
-#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
-#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
+#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
+#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
 
+#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
+#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
+#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
-
-#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
-
+#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
 #define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
-#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
-#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
-
-#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
+#define HAS_PSR(dev_priv)	((dev_priv)->info.has_psr)
+#define HAS_RC6(dev_priv)	((dev_priv)->info.has_rc6)
+#define HAS_RC6p(dev_priv)	((dev_priv)->info.has_rc6p)
+#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
 
 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
 
+#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
+
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
  * command submission once loaded. But these are logically independent
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index d430b9441e6b..35b13f178b61 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -573,7 +573,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 		   pdev->subsystem_device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 
-	if (HAS_CSR(dev)) {
+	if (HAS_CSR(dev_priv)) {
 		struct intel_csr *csr = &dev_priv->csr;
 
 		err_printf(m, "DMC loaded: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6d7505b5c5e7..285ee1e4352a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3678,7 +3678,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe;
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 	}
@@ -3712,7 +3712,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
 		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		I915_USER_INTERRUPT;
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
 		POSTING_READ(PORT_HOTPLUG_EN);
 
@@ -3880,7 +3880,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe;
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 	}
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 30eb95b54dcf..fed61958ffd4 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -693,7 +693,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
 	power_domain = intel_display_port_power_domain(intel_encoder);
 	intel_display_power_get(dev_priv, power_domain);
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		/* We can not rely on the HPD pin always being correctly wired
 		 * up, for example many KVM do not pass it through, and so
 		 * only trust an assertion that the monitor is connected.
@@ -715,7 +715,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
 	 * broken monitor (without edid) to work behind a broken kvm (that fails
 	 * to have the right resistors for HP detection) needs to fix this up.
 	 * For now just bail out. */
-	if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
+	if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
 		status = connector_status_disconnected;
 		goto out;
 	}
@@ -915,7 +915,7 @@ void intel_crt_init(struct drm_device *dev)
 		crt->base.disable = intel_disable_crt;
 	}
 	crt->base.enable = intel_enable_crt;
-	if (I915_HAS_HOTPLUG(dev) &&
+	if (I915_HAS_HOTPLUG(dev_priv) &&
 	    !dmi_check_system(intel_spurious_crt_detect))
 		crt->base.hpd_pin = HPD_CRT;
 	if (HAS_DDI(dev_priv)) {
@@ -932,7 +932,7 @@ void intel_crt_init(struct drm_device *dev)
 
 	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 
-	if (!I915_HAS_HOTPLUG(dev))
+	if (!I915_HAS_HOTPLUG(dev_priv))
 		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 
 	/*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 97589102442c..bf8099ed0b20 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8438,7 +8438,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 		}
 	}
 
-	if (HAS_PIPE_CXSR(dev)) {
+	if (HAS_PIPE_CXSR(dev_priv)) {
 		if (intel_crtc->lowfreq_avail) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
 			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
@@ -15620,7 +15620,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 	} else if (IS_GEN2(dev_priv))
 		intel_dvo_init(dev);
 
-	if (SUPPORTS_TV(dev))
+	if (SUPPORTS_TV(dev_priv))
 		intel_tv_init(dev);
 
 	intel_psr_init(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d4e9cf3ad26e..4c9981ccfc23 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5742,7 +5742,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	}
 
 	/* init MST on ports that can support it */
-	if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
+	if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
 	    (port == PORT_B || port == PORT_C || port == PORT_D))
 		intel_dp_mst_encoder_init(intel_dig_port,
 					  intel_connector->base.base.id);
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 334d47b5811a..3d546c019de0 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -501,7 +501,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
 		if (intel_connector->mst_port)
 			continue;
 
-		if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
+		if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) &&
 		    intel_connector->encoder->hpd_pin > HPD_NONE) {
 			connector->polled = enabled ?
 				DRM_CONNECTOR_POLL_CONNECT |
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 271a3e29ff23..41e6e920d9d7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -427,7 +427,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 
-	if (!HAS_PSR(dev)) {
+	if (!HAS_PSR(dev_priv)) {
 		DRM_DEBUG_KMS("PSR not supported on this platform\n");
 		return;
 	}
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 3/5] drm/i915: Further assorted dev_priv cleanups
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
  2016-11-04 14:42 ` [PATCH 1/5] drm/i915: Assorted dev_priv cleanups Tvrtko Ursulin
  2016-11-04 14:42 ` [PATCH 2/5] drm/i915: More assorted " Tvrtko Ursulin
@ 2016-11-04 14:42 ` Tvrtko Ursulin
  2016-11-09 10:38   ` David Weinehall
  2016-11-04 14:42 ` [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use Tvrtko Ursulin
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-04 14:42 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

A small selection of macros which can only accept dev_priv from
now on and a resulting trickle of fixups.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            | 12 ++++++------
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  2 +-
 drivers/gpu/drm/i915/i915_irq.c            |  2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c    | 10 +++++-----
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6060e41d25e5..f392b0fb9b86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2700,7 +2700,7 @@ struct drm_i915_cmd_table {
 #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
 
 #define REVID_FOREVER		0xff
-#define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
+#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
 
 #define GEN_FOREVER (0)
 /*
@@ -2925,13 +2925,13 @@ struct drm_i915_cmd_table {
  * command submission once loaded. But these are logically independent
  * properties, so we have separate macros to test them.
  */
-#define HAS_GUC(dev)		(INTEL_INFO(dev)->has_guc)
-#define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
-#define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
+#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
+#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
+#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
 
-#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
+#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
 
-#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
+#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9c7d9c88d879..f98921174161 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1616,7 +1616,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 	}
 
 	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
-		if (!HAS_RESOURCE_STREAMER(dev)) {
+		if (!HAS_RESOURCE_STREAMER(dev_priv)) {
 			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
 			return -EINVAL;
 		}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 285ee1e4352a..cb8a75f6ca16 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4145,7 +4145,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
 	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 
-	if (HAS_GUC_SCHED(dev))
+	if (HAS_GUC_SCHED(dev_priv))
 		dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
 
 	/* Let's track the enabled rps events */
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 1aa85236b788..34d6ad2cf7c1 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -566,7 +566,7 @@ int intel_guc_setup(struct drm_device *dev)
 		ret = 0;
 	}
 
-	if (err == 0 && !HAS_GUC_UCODE(dev))
+	if (err == 0 && !HAS_GUC_UCODE(dev_priv))
 		;	/* Don't mention the GuC! */
 	else if (err == 0)
 		DRM_INFO("GuC firmware load skipped\n");
@@ -725,18 +725,18 @@ void intel_guc_init(struct drm_device *dev)
 	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	const char *fw_path;
 
-	if (!HAS_GUC(dev)) {
+	if (!HAS_GUC(dev_priv)) {
 		i915.enable_guc_loading = 0;
 		i915.enable_guc_submission = 0;
 	} else {
 		/* A negative value means "use platform default" */
 		if (i915.enable_guc_loading < 0)
-			i915.enable_guc_loading = HAS_GUC_UCODE(dev);
+			i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
 		if (i915.enable_guc_submission < 0)
-			i915.enable_guc_submission = HAS_GUC_SCHED(dev);
+			i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
 	}
 
-	if (!HAS_GUC_UCODE(dev)) {
+	if (!HAS_GUC_UCODE(dev_priv)) {
 		fw_path = NULL;
 	} else if (IS_SKYLAKE(dev_priv)) {
 		fw_path = I915_SKL_GUC_UCODE;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
                   ` (2 preceding siblings ...)
  2016-11-04 14:42 ` [PATCH 3/5] drm/i915: Further " Tvrtko Ursulin
@ 2016-11-04 14:42 ` Tvrtko Ursulin
  2016-11-09 10:38   ` David Weinehall
  2016-11-04 14:42 ` [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN Tvrtko Ursulin
                   ` (3 subsequent siblings)
  7 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-04 14:42 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

After this patch only conversion of INTEL_INFO(p)->gen to
INTEL_GEN(dev_priv) remains before the __I915__ macro can
be removed.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      |  4 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  2 +-
 drivers/gpu/drm/i915/intel_color.c   | 31 ++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
 drivers/gpu/drm/i915/intel_fbdev.c   | 10 +++++-----
 drivers/gpu/drm/i915/intel_pm.c      |  7 ++++---
 6 files changed, 39 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 79cea49183b3..35940192e569 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
 	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 	 * (which really amounts to a PCH but no South Display).
 	 */
-	if (INTEL_INFO(dev)->num_pipes == 0) {
+	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 		dev_priv->pch_type = PCH_NOP;
 		return;
 	}
@@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
 	intel_modeset_gem_init(dev);
 
-	if (INTEL_INFO(dev)->num_pipes == 0)
+	if (INTEL_INFO(dev_priv)->num_pipes == 0)
 		return 0;
 
 	ret = intel_fbdev_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cad6de65947d..b98f11735c5b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -714,7 +714,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
  */
 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 {
-	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
+	ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
 }
 
 /* Removes entries from a single page table, releasing it if it's empty.
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 445108855275..3784940a4e7a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
 static void broadwell_load_luts(struct drm_crtc_state *state)
 {
 	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	if (crtc_state_is_legacy(state)) {
 		haswell_load_luts(state);
@@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
 static void cherryview_load_luts(struct drm_crtc_state *state)
 {
 	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 	struct drm_color_lut *lut;
 	uint32_t i, lut_size;
@@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
 
 	if (state->degamma_lut) {
 		lut = (struct drm_color_lut *) state->degamma_lut->data;
-		lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.14 format. */
 			word0 =
@@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
 
 	if (state->gamma_lut) {
 		lut = (struct drm_color_lut *) state->gamma_lut->data;
-		lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
+		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.10 format. */
 			word0 =
@@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
 int intel_color_check(struct drm_crtc *crtc,
 		      struct drm_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	size_t gamma_length, degamma_length;
 
-	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
+	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
 		sizeof(struct drm_color_lut);
-	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
+	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
 		sizeof(struct drm_color_lut);
 
 	/*
@@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
 
 void intel_color_init(struct drm_crtc *crtc)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 
 	drm_mode_crtc_set_gamma_size(crtc, 256);
 
@@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
 	}
 
 	/* Enable color management support when we have degamma & gamma LUTs. */
-	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
-	    INTEL_INFO(dev)->color.gamma_lut_size != 0)
+	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
+	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
 		drm_crtc_enable_color_mgmt(crtc,
-					INTEL_INFO(dev)->color.degamma_lut_size,
-					true,
-					INTEL_INFO(dev)->color.gamma_lut_size);
+					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
+					   true,
+					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bf8099ed0b20..aad264583378 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7057,7 +7057,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
 		}
 	}
 
-	if (INTEL_INFO(dev)->num_pipes == 2)
+	if (INTEL_INFO(dev_priv)->num_pipes == 2)
 		return 0;
 
 	/* Ivybridge 3 pipe is really complicated */
@@ -14706,8 +14706,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 {
 	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(new_state->state);
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct drm_framebuffer *fb = new_state->fb;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
@@ -14764,7 +14763,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 	}
 
 	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
-	    INTEL_INFO(dev)->cursor_needs_physical) {
+	    INTEL_INFO(dev_priv)->cursor_needs_physical) {
 		int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
 		ret = i915_gem_object_attach_phys(obj, align);
 		if (ret) {
@@ -14797,7 +14796,7 @@ void
 intel_cleanup_plane_fb(struct drm_plane *plane,
 		       struct drm_plane_state *old_state)
 {
-	struct drm_device *dev = plane->dev;
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct intel_plane_state *old_intel_state;
 	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
 	struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
@@ -14808,7 +14807,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 		return;
 
 	if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
-	    !INTEL_INFO(dev)->cursor_needs_physical))
+	    !INTEL_INFO(dev_priv)->cursor_needs_physical))
 		intel_unpin_fb_obj(old_state->fb, old_state->rotation);
 }
 
@@ -15133,13 +15132,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
 {
 	struct drm_crtc *crtc = crtc_state->base.crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_device *dev = plane->dev;
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
 	uint32_t addr;
 
 	if (!obj)
 		addr = 0;
-	else if (!INTEL_INFO(dev)->cursor_needs_physical)
+	else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
 		addr = i915_gem_object_ggtt_offset(obj, NULL);
 	else
 		addr = obj->phys_handle->busaddr;
@@ -16421,7 +16420,7 @@ int intel_modeset_init(struct drm_device *dev)
 
 	intel_init_pm(dev_priv);
 
-	if (INTEL_INFO(dev)->num_pipes == 0)
+	if (INTEL_INFO(dev_priv)->num_pipes == 0)
 		return 0;
 
 	/*
@@ -16467,8 +16466,8 @@ int intel_modeset_init(struct drm_device *dev)
 	dev->mode_config.fb_base = ggtt->mappable_base;
 
 	DRM_DEBUG_KMS("%d display pipe%s available.\n",
-		      INTEL_INFO(dev)->num_pipes,
-		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
+		      INTEL_INFO(dev_priv)->num_pipes,
+		      INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
 
 	for_each_pipe(dev_priv, pipe) {
 		int ret;
@@ -16556,11 +16555,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
 static bool
 intel_check_plane_mapping(struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val;
 
-	if (INTEL_INFO(dev)->num_pipes == 1)
+	if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		return true;
 
 	val = I915_READ(DSPCNTR(!crtc->plane));
@@ -17313,7 +17311,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
 	if (!error)
 		return;
 
-	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
+	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		err_printf(m, "PWR_WELL_CTL2: %08x\n",
 			   error->power_well_driver);
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index b7098f98bb67..e3cf655bec3b 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
 				    struct drm_fb_offset *offsets,
 				    bool *enabled, int width, int height)
 {
-	struct drm_device *dev = fb_helper->dev;
+	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
 	unsigned long conn_configured, mask;
 	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
 	int i, j;
@@ -512,7 +512,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
 	 * fbdev helper library.
 	 */
 	if (num_connectors_enabled != num_connectors_detected &&
-	    num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
+	    num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
 		DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
 		DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
 			      num_connectors_detected);
@@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
 
 int intel_fbdev_init(struct drm_device *dev)
 {
-	struct intel_fbdev *ifbdev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_fbdev *ifbdev;
 	int ret;
 
-	if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
+	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
 		return -ENODEV;
 
 	ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
@@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
 		ifbdev->preferred_bpp = 32;
 
 	ret = drm_fb_helper_init(dev, &ifbdev->helper,
-				 INTEL_INFO(dev)->num_pipes, 4);
+				 INTEL_INFO(dev_priv)->num_pipes, 4);
 	if (ret) {
 		kfree(ifbdev);
 		return ret;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c989b9c..4512069e4555 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
 
 	for (level = 0; level < wm_state->num_levels; level++) {
 		struct drm_device *dev = crtc->base.dev;
-		const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
+		const int sr_fifo_size =
+			INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
 		struct intel_plane *plane;
 
 		wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
@@ -1093,7 +1094,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
 	struct drm_device *dev = crtc->base.dev;
 	struct vlv_wm_state *wm_state = &crtc->wm_state;
 	struct intel_plane *plane;
-	int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
+	int sr_fifo_size = INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
 	int level;
 
 	memset(wm_state, 0, sizeof(*wm_state));
@@ -1920,7 +1921,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
 
 	/* HSW allows LP1+ watermarks even with multiple pipes */
 	if (level == 0 || config->num_pipes_active > 1) {
-		fifo_size /= INTEL_INFO(dev)->num_pipes;
+		fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
 
 		/*
 		 * For some reason the non self refresh
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
                   ` (3 preceding siblings ...)
  2016-11-04 14:42 ` [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use Tvrtko Ursulin
@ 2016-11-04 14:42 ` Tvrtko Ursulin
  2016-11-09 10:39   ` David Weinehall
  2016-11-04 15:23 ` ✗ Fi.CI.BAT: failure for dev_priv cleanup continuation Patchwork
                   ` (2 subsequent siblings)
  7 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-04 14:42 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 35940192e569..096c368bda0b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -374,12 +374,12 @@ static int
 intel_alloc_mchbar_resource(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp_lo, temp_hi = 0;
 	u64 mchbar_addr;
 	int ret;
 
-	if (INTEL_INFO(dev)->gen >= 4)
+	if (INTEL_GEN(dev_priv) >= 4)
 		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -406,7 +406,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
 		return ret;
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4)
+	if (INTEL_GEN(dev_priv) >= 4)
 		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 				       upper_32_bits(dev_priv->mch_res.start));
 
@@ -420,7 +420,7 @@ static void
 intel_setup_mchbar(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp;
 	bool enabled;
 
@@ -460,7 +460,7 @@ static void
 intel_teardown_mchbar(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 
 	if (dev_priv->mchbar_need_disable) {
 		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
@@ -879,7 +879,7 @@ static int i915_mmio_setup(struct drm_device *dev)
 	 * the register BAR remains the same size for all the earlier
 	 * generations up to Ironlake.
 	 */
-	if (INTEL_INFO(dev)->gen < 5)
+	if (INTEL_GEN(dev_priv) < 5)
 		mmio_size = 512 * 1024;
 	else
 		mmio_size = 2 * 1024 * 1024;
@@ -1512,7 +1512,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 	 * Fujitsu FSC S7110
 	 * Acer Aspire 1830T
 	 */
-	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
+	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
 		pci_set_power_state(pdev, PCI_D3hot);
 
 	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* ✗ Fi.CI.BAT: failure for dev_priv cleanup continuation
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
                   ` (4 preceding siblings ...)
  2016-11-04 14:42 ` [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN Tvrtko Ursulin
@ 2016-11-04 15:23 ` Patchwork
  2016-11-07 10:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev2) Patchwork
  2016-11-09 12:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3) Patchwork
  7 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2016-11-04 15:23 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx

== Series Details ==

Series: dev_priv cleanup continuation
URL   : https://patchwork.freedesktop.org/series/14844/
State : failure

== Summary ==

Series 14844v1 dev_priv cleanup continuation
https://patchwork.freedesktop.org/api/1.0/series/14844/revisions/1/mbox/

Test kms_busy:
        Subgroup basic-flip-default-c:
                pass       -> INCOMPLETE (fi-skl-6260u)

fi-bdw-5557u     total:241  pass:226  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:241  pass:201  dwarn:0   dfail:0   fail:0   skip:40 
fi-byt-j1900     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:241  pass:209  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:241  pass:221  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:241  pass:221  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:241  pass:188  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:165  pass:159  dwarn:0   dfail:0   fail:0   skip:5  
fi-skl-6700hq    total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:241  pass:219  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:241  pass:227  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:241  pass:209  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:241  pass:208  dwarn:0   dfail:0   fail:0   skip:33 

f302fec3503812bb71a8f71511a0bd4f720d5091 drm-intel-nightly: 2016y-11m-04d-11h-56m-52s UTC integration manifest
01f89f2 drm/i915: Convert i915_drv.c to INTEL_GEN
f1ccc0b drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
ef23459 drm/i915: Further assorted dev_priv cleanups
28a34c7 drm/i915: More assorted dev_priv cleanups
8c5b825 drm/i915: Assorted dev_priv cleanups

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2906/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 2/5] drm/i915: More assorted dev_priv cleanups
  2016-11-04 14:42 ` [PATCH 2/5] drm/i915: More assorted " Tvrtko Ursulin
@ 2016-11-04 15:32   ` Ville Syrjälä
  2016-11-04 16:03     ` Tvrtko Ursulin
  0 siblings, 1 reply; 23+ messages in thread
From: Ville Syrjälä @ 2016-11-04 15:32 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Fri, Nov 04, 2016 at 02:42:45PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> A small selection of macros which can only accept dev_priv from
> now on and a resulting trickle of fixups.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       | 27 ++++++++++++---------------
>  drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c       |  6 +++---
>  drivers/gpu/drm/i915/intel_crt.c      |  8 ++++----
>  drivers/gpu/drm/i915/intel_display.c  |  4 ++--
>  drivers/gpu/drm/i915/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/intel_hotplug.c  |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c      |  2 +-
>  8 files changed, 25 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 45a30f730216..6060e41d25e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2901,28 +2901,25 @@ struct drm_i915_cmd_table {
>  #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
>  					 !(IS_I915G(dev_priv) || \
>  					 IS_I915GM(dev_priv)))
> -#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
> -#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
> -
> -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> -#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> -#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
> +#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
> +#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
>  
> +#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
> +#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
> +#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
>  #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
> -
> -#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
> -
> +#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
>  #define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
> -#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
> -#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
> -
> -#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
> +#define HAS_PSR(dev_priv)	((dev_priv)->info.has_psr)
> +#define HAS_RC6(dev_priv)	((dev_priv)->info.has_rc6)
> +#define HAS_RC6p(dev_priv)	((dev_priv)->info.has_rc6p)
> +#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
>  
>  #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
>  #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
>  
> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)

What's confusing me is this reordering of these macros. Was there a
particular reason for doing that?

Outside that it all looks pretty reasonable. Could got a bit further
with passing around dev_priv in some cases, but I guess we can leave
that to future work.


One random idea that did pop into my head was this:

static inline const struct ... *
intel_info(struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}
#define HAS_WHATEVER(dev_priv) (intel_info(dev_priv)->whatever)

for some extra type safety. Any thoughts?

> +
>  /*
>   * For now, anything with a GuC requires uCode loading, and then supports
>   * command submission once loaded. But these are logically independent
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d430b9441e6b..35b13f178b61 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -573,7 +573,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  		   pdev->subsystem_device);
>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>  
> -	if (HAS_CSR(dev)) {
> +	if (HAS_CSR(dev_priv)) {
>  		struct intel_csr *csr = &dev_priv->csr;
>  
>  		err_printf(m, "DMC loaded: %s\n",
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d7505b5c5e7..285ee1e4352a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3678,7 +3678,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int pipe;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  	}
> @@ -3712,7 +3712,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
>  		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
>  		I915_USER_INTERRUPT;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		POSTING_READ(PORT_HOTPLUG_EN);
>  
> @@ -3880,7 +3880,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int pipe;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 30eb95b54dcf..fed61958ffd4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -693,7 +693,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
>  	power_domain = intel_display_port_power_domain(intel_encoder);
>  	intel_display_power_get(dev_priv, power_domain);
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		/* We can not rely on the HPD pin always being correctly wired
>  		 * up, for example many KVM do not pass it through, and so
>  		 * only trust an assertion that the monitor is connected.
> @@ -715,7 +715,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
>  	 * broken monitor (without edid) to work behind a broken kvm (that fails
>  	 * to have the right resistors for HP detection) needs to fix this up.
>  	 * For now just bail out. */
> -	if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
> +	if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
>  		status = connector_status_disconnected;
>  		goto out;
>  	}
> @@ -915,7 +915,7 @@ void intel_crt_init(struct drm_device *dev)
>  		crt->base.disable = intel_disable_crt;
>  	}
>  	crt->base.enable = intel_enable_crt;
> -	if (I915_HAS_HOTPLUG(dev) &&
> +	if (I915_HAS_HOTPLUG(dev_priv) &&
>  	    !dmi_check_system(intel_spurious_crt_detect))
>  		crt->base.hpd_pin = HPD_CRT;
>  	if (HAS_DDI(dev_priv)) {
> @@ -932,7 +932,7 @@ void intel_crt_init(struct drm_device *dev)
>  
>  	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
>  
> -	if (!I915_HAS_HOTPLUG(dev))
> +	if (!I915_HAS_HOTPLUG(dev_priv))
>  		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 97589102442c..bf8099ed0b20 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8438,7 +8438,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  		}
>  	}
>  
> -	if (HAS_PIPE_CXSR(dev)) {
> +	if (HAS_PIPE_CXSR(dev_priv)) {
>  		if (intel_crtc->lowfreq_avail) {
>  			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
>  			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
> @@ -15620,7 +15620,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  	} else if (IS_GEN2(dev_priv))
>  		intel_dvo_init(dev);
>  
> -	if (SUPPORTS_TV(dev))
> +	if (SUPPORTS_TV(dev_priv))
>  		intel_tv_init(dev);
>  
>  	intel_psr_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d4e9cf3ad26e..4c9981ccfc23 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5742,7 +5742,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	}
>  
>  	/* init MST on ports that can support it */
> -	if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
> +	if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
>  	    (port == PORT_B || port == PORT_C || port == PORT_D))
>  		intel_dp_mst_encoder_init(intel_dig_port,
>  					  intel_connector->base.base.id);
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index 334d47b5811a..3d546c019de0 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -501,7 +501,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
>  		if (intel_connector->mst_port)
>  			continue;
>  
> -		if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
> +		if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) &&
>  		    intel_connector->encoder->hpd_pin > HPD_NONE) {
>  			connector->polled = enabled ?
>  				DRM_CONNECTOR_POLL_CONNECT |
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 271a3e29ff23..41e6e920d9d7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -427,7 +427,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>  
> -	if (!HAS_PSR(dev)) {
> +	if (!HAS_PSR(dev_priv)) {
>  		DRM_DEBUG_KMS("PSR not supported on this platform\n");
>  		return;
>  	}
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 2/5] drm/i915: More assorted dev_priv cleanups
  2016-11-04 15:32   ` Ville Syrjälä
@ 2016-11-04 16:03     ` Tvrtko Ursulin
  2016-11-04 16:29       ` Ville Syrjälä
  0 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-04 16:03 UTC (permalink / raw)
  To: Ville Syrjälä, Tvrtko Ursulin; +Cc: Intel-gfx


On 04/11/2016 15:32, Ville Syrjälä wrote:
> On Fri, Nov 04, 2016 at 02:42:45PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> A small selection of macros which can only accept dev_priv from
>> now on and a resulting trickle of fixups.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h       | 27 ++++++++++++---------------
>>  drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
>>  drivers/gpu/drm/i915/i915_irq.c       |  6 +++---
>>  drivers/gpu/drm/i915/intel_crt.c      |  8 ++++----
>>  drivers/gpu/drm/i915/intel_display.c  |  4 ++--
>>  drivers/gpu/drm/i915/intel_dp.c       |  2 +-
>>  drivers/gpu/drm/i915/intel_hotplug.c  |  2 +-
>>  drivers/gpu/drm/i915/intel_psr.c      |  2 +-
>>  8 files changed, 25 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 45a30f730216..6060e41d25e5 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2901,28 +2901,25 @@ struct drm_i915_cmd_table {
>>  #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
>>  					 !(IS_I915G(dev_priv) || \
>>  					 IS_I915GM(dev_priv)))
>> -#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
>> -#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
>> -
>> -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
>> -#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
>> -#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>> +#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
>> +#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
>>
>> +#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
>> +#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
>> +#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
>>  #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>> -
>> -#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
>> -
>> +#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
>>  #define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)
>> -#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
>> -#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
>> -#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
>> -#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
>> -
>> -#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
>> +#define HAS_PSR(dev_priv)	((dev_priv)->info.has_psr)
>> +#define HAS_RC6(dev_priv)	((dev_priv)->info.has_rc6)
>> +#define HAS_RC6p(dev_priv)	((dev_priv)->info.has_rc6p)
>> +#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
>>
>>  #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
>>  #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
>>
>> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
>
> What's confusing me is this reordering of these macros. Was there a
> particular reason for doing that?

Just because of its long name, so I pulled it out and separated so the 
alignment is nicer in the blocks above it.

> Outside that it all looks pretty reasonable. Could got a bit further
> with passing around dev_priv in some cases, but I guess we can leave
> that to future work.

Yes, I mention that in the cover letter.

> One random idea that did pop into my head was this:
>
> static inline const struct ... *
> intel_info(struct drm_i915_private *dev_priv)
> {
> 	return &dev_priv->info;
> }
> #define HAS_WHATEVER(dev_priv) (intel_info(dev_priv)->whatever)
>
> for some extra type safety. Any thoughts?

Sounds like a good idea to me. And it would be really easy to do, 
localized to i915_drv.h, and then when the last INTEL_INFO(dev) gets 
converted we can make it use the inline as well.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 2/5] drm/i915: More assorted dev_priv cleanups
  2016-11-04 16:03     ` Tvrtko Ursulin
@ 2016-11-04 16:29       ` Ville Syrjälä
  2016-11-07  9:29         ` [PATCH v2 " Tvrtko Ursulin
  0 siblings, 1 reply; 23+ messages in thread
From: Ville Syrjälä @ 2016-11-04 16:29 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Fri, Nov 04, 2016 at 04:03:55PM +0000, Tvrtko Ursulin wrote:
> 
> On 04/11/2016 15:32, Ville Syrjälä wrote:
> > On Fri, Nov 04, 2016 at 02:42:45PM +0000, Tvrtko Ursulin wrote:
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> A small selection of macros which can only accept dev_priv from
> >> now on and a resulting trickle of fixups.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h       | 27 ++++++++++++---------------
> >>  drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
> >>  drivers/gpu/drm/i915/i915_irq.c       |  6 +++---
> >>  drivers/gpu/drm/i915/intel_crt.c      |  8 ++++----
> >>  drivers/gpu/drm/i915/intel_display.c  |  4 ++--
> >>  drivers/gpu/drm/i915/intel_dp.c       |  2 +-
> >>  drivers/gpu/drm/i915/intel_hotplug.c  |  2 +-
> >>  drivers/gpu/drm/i915/intel_psr.c      |  2 +-
> >>  8 files changed, 25 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 45a30f730216..6060e41d25e5 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -2901,28 +2901,25 @@ struct drm_i915_cmd_table {
> >>  #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
> >>  					 !(IS_I915G(dev_priv) || \
> >>  					 IS_I915GM(dev_priv)))
> >> -#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
> >> -#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
> >> -
> >> -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> >> -#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> >> -#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
> >> +#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
> >> +#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
> >>
> >> +#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
> >> +#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
> >> +#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
> >>  #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
> >> -
> >> -#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
> >> -
> >> +#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
> >>  #define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)
> >> -#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> >> -#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
> >> -#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
> >> -#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
> >> -
> >> -#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
> >> +#define HAS_PSR(dev_priv)	((dev_priv)->info.has_psr)
> >> +#define HAS_RC6(dev_priv)	((dev_priv)->info.has_rc6)
> >> +#define HAS_RC6p(dev_priv)	((dev_priv)->info.has_rc6p)
> >> +#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
> >>
> >>  #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
> >>  #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
> >>
> >> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
> >
> > What's confusing me is this reordering of these macros. Was there a
> > particular reason for doing that?
> 
> Just because of its long name, so I pulled it out and separated so the 
> alignment is nicer in the blocks above it.

The original grouping looked more based on functionality, so made a bit
more sense to me.

> 
> > Outside that it all looks pretty reasonable. Could got a bit further
> > with passing around dev_priv in some cases, but I guess we can leave
> > that to future work.
> 
> Yes, I mention that in the cover letter.
> 
> > One random idea that did pop into my head was this:
> >
> > static inline const struct ... *
> > intel_info(struct drm_i915_private *dev_priv)
> > {
> > 	return &dev_priv->info;
> > }
> > #define HAS_WHATEVER(dev_priv) (intel_info(dev_priv)->whatever)
> >
> > for some extra type safety. Any thoughts?
> 
> Sounds like a good idea to me. And it would be really easy to do, 
> localized to i915_drv.h, and then when the last INTEL_INFO(dev) gets 
> converted we can make it use the inline as well.
> 
> Regards,
> 
> Tvrtko

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PATCH v2 2/5] drm/i915: More assorted dev_priv cleanups
  2016-11-04 16:29       ` Ville Syrjälä
@ 2016-11-07  9:29         ` Tvrtko Ursulin
  2016-11-09 10:38           ` David Weinehall
  0 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-07  9:29 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

A small selection of macros which can only accept dev_priv from
now on and a resulting trickle of fixups.

v2: Keep original order. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       | 24 ++++++++++++------------
 drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
 drivers/gpu/drm/i915/i915_irq.c       |  6 +++---
 drivers/gpu/drm/i915/intel_crt.c      |  8 ++++----
 drivers/gpu/drm/i915/intel_display.c  |  4 ++--
 drivers/gpu/drm/i915/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/intel_hotplug.c  |  2 +-
 drivers/gpu/drm/i915/intel_psr.c      |  2 +-
 8 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 45a30f730216..c56d6cf73219 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2901,24 +2901,24 @@ struct drm_i915_cmd_table {
 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
 					 !(IS_I915G(dev_priv) || \
 					 IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
-#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
+#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
+#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
 
-#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
-#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
-#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
+#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
+#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
+#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
 
 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 
-#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
+#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
 
-#define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
-#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
-#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
+#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
+#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
+#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
+#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
 
-#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
+#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
 
 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index d430b9441e6b..35b13f178b61 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -573,7 +573,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 		   pdev->subsystem_device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 
-	if (HAS_CSR(dev)) {
+	if (HAS_CSR(dev_priv)) {
 		struct intel_csr *csr = &dev_priv->csr;
 
 		err_printf(m, "DMC loaded: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6d7505b5c5e7..285ee1e4352a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3678,7 +3678,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe;
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 	}
@@ -3712,7 +3712,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
 		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		I915_USER_INTERRUPT;
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
 		POSTING_READ(PORT_HOTPLUG_EN);
 
@@ -3880,7 +3880,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe;
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 	}
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 30eb95b54dcf..fed61958ffd4 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -693,7 +693,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
 	power_domain = intel_display_port_power_domain(intel_encoder);
 	intel_display_power_get(dev_priv, power_domain);
 
-	if (I915_HAS_HOTPLUG(dev)) {
+	if (I915_HAS_HOTPLUG(dev_priv)) {
 		/* We can not rely on the HPD pin always being correctly wired
 		 * up, for example many KVM do not pass it through, and so
 		 * only trust an assertion that the monitor is connected.
@@ -715,7 +715,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
 	 * broken monitor (without edid) to work behind a broken kvm (that fails
 	 * to have the right resistors for HP detection) needs to fix this up.
 	 * For now just bail out. */
-	if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
+	if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
 		status = connector_status_disconnected;
 		goto out;
 	}
@@ -915,7 +915,7 @@ void intel_crt_init(struct drm_device *dev)
 		crt->base.disable = intel_disable_crt;
 	}
 	crt->base.enable = intel_enable_crt;
-	if (I915_HAS_HOTPLUG(dev) &&
+	if (I915_HAS_HOTPLUG(dev_priv) &&
 	    !dmi_check_system(intel_spurious_crt_detect))
 		crt->base.hpd_pin = HPD_CRT;
 	if (HAS_DDI(dev_priv)) {
@@ -932,7 +932,7 @@ void intel_crt_init(struct drm_device *dev)
 
 	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 
-	if (!I915_HAS_HOTPLUG(dev))
+	if (!I915_HAS_HOTPLUG(dev_priv))
 		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 
 	/*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 92ab01f33208..3a3b97ae6b10 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8438,7 +8438,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 		}
 	}
 
-	if (HAS_PIPE_CXSR(dev)) {
+	if (HAS_PIPE_CXSR(dev_priv)) {
 		if (intel_crtc->lowfreq_avail) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
 			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
@@ -15643,7 +15643,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 	} else if (IS_GEN2(dev_priv))
 		intel_dvo_init(dev);
 
-	if (SUPPORTS_TV(dev))
+	if (SUPPORTS_TV(dev_priv))
 		intel_tv_init(dev);
 
 	intel_psr_init(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d4e9cf3ad26e..4c9981ccfc23 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5742,7 +5742,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	}
 
 	/* init MST on ports that can support it */
-	if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
+	if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
 	    (port == PORT_B || port == PORT_C || port == PORT_D))
 		intel_dp_mst_encoder_init(intel_dig_port,
 					  intel_connector->base.base.id);
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 334d47b5811a..3d546c019de0 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -501,7 +501,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
 		if (intel_connector->mst_port)
 			continue;
 
-		if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
+		if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) &&
 		    intel_connector->encoder->hpd_pin > HPD_NONE) {
 			connector->polled = enabled ?
 				DRM_CONNECTOR_POLL_CONNECT |
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 271a3e29ff23..41e6e920d9d7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -427,7 +427,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 
-	if (!HAS_PSR(dev)) {
+	if (!HAS_PSR(dev_priv)) {
 		DRM_DEBUG_KMS("PSR not supported on this platform\n");
 		return;
 	}
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev2)
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
                   ` (5 preceding siblings ...)
  2016-11-04 15:23 ` ✗ Fi.CI.BAT: failure for dev_priv cleanup continuation Patchwork
@ 2016-11-07 10:45 ` Patchwork
  2016-11-09 12:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3) Patchwork
  7 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2016-11-07 10:45 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx

== Series Details ==

Series: dev_priv cleanup continuation (rev2)
URL   : https://patchwork.freedesktop.org/series/14844/
State : success

== Summary ==

Series 14844v2 dev_priv cleanup continuation
https://patchwork.freedesktop.org/api/1.0/series/14844/revisions/2/mbox/


fi-bdw-5557u     total:241  pass:226  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:241  pass:201  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:241  pass:209  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:241  pass:221  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:241  pass:221  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:241  pass:188  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:241  pass:227  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:241  pass:219  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:241  pass:227  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:241  pass:209  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:241  pass:208  dwarn:0   dfail:0   fail:0   skip:33 

5385d13fdacbf8fbb345ecdc533ee407fd86e2f2 drm-intel-nightly: 2016y-11m-07d-09h-18m-42s UTC integration manifest
5b85b4c drm/i915: Convert i915_drv.c to INTEL_GEN
c14a127 drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
d4d7260 drm/i915: Further assorted dev_priv cleanups
b1e3250 drm/i915: More assorted dev_priv cleanups
3d041e7 drm/i915: Assorted dev_priv cleanups

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2917/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 1/5] drm/i915: Assorted dev_priv cleanups
  2016-11-04 14:42 ` [PATCH 1/5] drm/i915: Assorted dev_priv cleanups Tvrtko Ursulin
@ 2016-11-09 10:37   ` David Weinehall
  0 siblings, 0 replies; 23+ messages in thread
From: David Weinehall @ 2016-11-09 10:37 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Fri, Nov 04, 2016 at 02:42:44PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> A small selection of macros which can only accept dev_priv from
> now on and a resulting trickle of fixups.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h            | 31 ++++++++++++++++--------------
>  drivers/gpu/drm/i915/i915_gem.c            | 13 +++++++------
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  4 ++--
>  drivers/gpu/drm/i915/i915_gem_stolen.c     |  3 ++-
>  drivers/gpu/drm/i915/i915_gem_userptr.c    |  3 ++-
>  drivers/gpu/drm/i915/i915_gpu_error.c      |  2 +-
>  drivers/gpu/drm/i915/intel_dp.c            |  6 +++---
>  7 files changed, 34 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4735b4177100..45a30f730216 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2851,28 +2851,31 @@ struct drm_i915_cmd_table {
>  #define ALL_ENGINES	(~0)
>  
>  #define HAS_ENGINE(dev_priv, id) \
> -	(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
> +	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
>  
>  #define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
>  #define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
>  #define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
>  #define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)
>  
> -#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
> -#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
> -#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
> +#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
> +#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
> +#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
>  #define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
>  				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
> -#define HWS_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->hws_needs_physical)
>  
> -#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
> -#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)
> -#define USES_PPGTT(dev)		(i915.enable_ppgtt)
> -#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
> +#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
>  
> -#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
> -#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
> +#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
> +#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
> +		((dev_priv)->info.has_logical_ring_contexts)
> +#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
> +#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
> +#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)
> +
> +#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
> +#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
> +		((dev_priv)->info.overlay_needs_physical)
>  
>  /* Early gen2 have a totally busted CS tlb and require pinned batches. */
>  #define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_845G(dev_priv))
> @@ -2889,8 +2892,8 @@ struct drm_i915_cmd_table {
>   * legacy irq no. is shared with another device. The kernel then disables that
>   * interrupt source and so prevents the other device from working properly.
>   */
> -#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
> -#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
> +#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
> +#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
>  
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1f995ced524e..e9808c8ef55b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -48,7 +48,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
>  static bool cpu_cache_is_coherent(struct drm_device *dev,
>  				  enum i915_cache_level level)
>  {
> -	return HAS_LLC(dev) || level != I915_CACHE_NONE;
> +	return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
>  }
>  
>  static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
> @@ -1757,7 +1757,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
>  		goto err_rpm;
>  
>  	/* Access to snoopable pages through the GTT is incoherent. */
> -	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
> +	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
>  		ret = -EFAULT;
>  		goto err_unlock;
>  	}
> @@ -3414,7 +3414,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
>  		if (ret)
>  			return ret;
>  
> -		if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) {
> +		if (!HAS_LLC(to_i915(obj->base.dev)) &&
> +		    cache_level != I915_CACHE_NONE) {
>  			/* Access to snoopable pages through the GTT is
>  			 * incoherent and on some machines causes a hard
>  			 * lockup. Relinquish the CPU mmaping to force
> @@ -4199,7 +4200,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size)
>  	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
>  	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
>  
> -	if (HAS_LLC(dev)) {
> +	if (HAS_LLC(dev_priv)) {
>  		/* On some devices, we can have the GPU use the LLC (the CPU
>  		 * cache) for about a 10% performance improvement
>  		 * compared to uncached.  Graphics requests other than
> @@ -4444,7 +4445,7 @@ int i915_gem_suspend(struct drm_device *dev)
>  	 * machines is a good idea, we don't - just in case it leaves the
>  	 * machine in an unusable condition.
>  	 */
> -	if (HAS_HW_CONTEXTS(dev)) {
> +	if (HAS_HW_CONTEXTS(dev_priv)) {
>  		int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
>  		WARN_ON(reset && reset != -ENODEV);
>  	}
> @@ -4535,7 +4536,7 @@ i915_gem_init_hw(struct drm_device *dev)
>  	/* Double layer security blanket, see i915_gem_init() */
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
> -	if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
> +	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
>  		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>  
>  	if (IS_HASWELL(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 322c580a739f..9c7d9c88d879 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -287,7 +287,7 @@ static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
>  	if (DBG_USE_CPU_RELOC)
>  		return DBG_USE_CPU_RELOC > 0;
>  
> -	return (HAS_LLC(obj->base.dev) ||
> +	return (HAS_LLC(to_i915(obj->base.dev)) ||
>  		obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
>  		obj->cache_level != I915_CACHE_NONE);
>  }
> @@ -833,7 +833,7 @@ need_reloc_mappable(struct i915_vma *vma)
>  		return false;
>  
>  	/* See also use_cpu_reloc() */
> -	if (HAS_LLC(vma->obj->base.dev))
> +	if (HAS_LLC(to_i915(vma->obj->base.dev)))
>  		return false;
>  
>  	if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index b1d367dba347..54085df1f227 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -596,7 +596,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev,
>  
>  	obj->stolen = stolen;
>  	obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
> -	obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
> +	obj->cache_level = HAS_LLC(to_i915(dev)) ?
> +			   I915_CACHE_LLC : I915_CACHE_NONE;
>  
>  	if (i915_gem_object_pin_pages(obj))
>  		goto cleanup;
> diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
> index 64261639f547..107ddf51065e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
> @@ -753,12 +753,13 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = {
>  int
>  i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct drm_i915_gem_userptr *args = data;
>  	struct drm_i915_gem_object *obj;
>  	int ret;
>  	u32 handle;
>  
> -	if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) {
> +	if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) {
>  		/* We cannot support coherent userptr objects on hw without
>  		 * LLC and broken snooping.
>  		 */
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 204093f3eaa5..d430b9441e6b 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1489,7 +1489,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>  	}
>  
>  	/* 4: Everything else */
> -	if (HAS_HW_CONTEXTS(dev))
> +	if (HAS_HW_CONTEXTS(dev_priv))
>  		error->ccid = I915_READ(CCID);
>  
>  	if (INTEL_INFO(dev)->gen >= 8) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9df331b3305b..d4e9cf3ad26e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -942,14 +942,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  		uint8_t *recv, int recv_size)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_device *dev = intel_dig_port->base.base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv =
> +			to_i915(intel_dig_port->base.base.dev);
>  	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
>  	uint32_t aux_clock_divider;
>  	int i, ret, recv_bytes;
>  	uint32_t status;
>  	int try, clock = 0;
> -	bool has_aux_irq = HAS_AUX_IRQ(dev);
> +	bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
>  	bool vdd;
>  
>  	pps_lock(intel_dp);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/5] drm/i915: More assorted dev_priv cleanups
  2016-11-07  9:29         ` [PATCH v2 " Tvrtko Ursulin
@ 2016-11-09 10:38           ` David Weinehall
  0 siblings, 0 replies; 23+ messages in thread
From: David Weinehall @ 2016-11-09 10:38 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Mon, Nov 07, 2016 at 09:29:20AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> A small selection of macros which can only accept dev_priv from
> now on and a resulting trickle of fixups.
> 
> v2: Keep original order. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       | 24 ++++++++++++------------
>  drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c       |  6 +++---
>  drivers/gpu/drm/i915/intel_crt.c      |  8 ++++----
>  drivers/gpu/drm/i915/intel_display.c  |  4 ++--
>  drivers/gpu/drm/i915/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/intel_hotplug.c  |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c      |  2 +-
>  8 files changed, 25 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 45a30f730216..c56d6cf73219 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2901,24 +2901,24 @@ struct drm_i915_cmd_table {
>  #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
>  					 !(IS_I915G(dev_priv) || \
>  					 IS_I915GM(dev_priv)))
> -#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
> -#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
> +#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
> +#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
>  
> -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> -#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> -#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
> +#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
> +#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
> +#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
>  
>  #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>  
> -#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
> +#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
>  
> -#define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
> -#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
> -#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
> +#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
> +#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
> +#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
> +#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
>  
> -#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
> +#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
>  
>  #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
>  #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d430b9441e6b..35b13f178b61 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -573,7 +573,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  		   pdev->subsystem_device);
>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>  
> -	if (HAS_CSR(dev)) {
> +	if (HAS_CSR(dev_priv)) {
>  		struct intel_csr *csr = &dev_priv->csr;
>  
>  		err_printf(m, "DMC loaded: %s\n",
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d7505b5c5e7..285ee1e4352a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3678,7 +3678,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int pipe;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  	}
> @@ -3712,7 +3712,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
>  		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
>  		I915_USER_INTERRUPT;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		POSTING_READ(PORT_HOTPLUG_EN);
>  
> @@ -3880,7 +3880,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int pipe;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 30eb95b54dcf..fed61958ffd4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -693,7 +693,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
>  	power_domain = intel_display_port_power_domain(intel_encoder);
>  	intel_display_power_get(dev_priv, power_domain);
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		/* We can not rely on the HPD pin always being correctly wired
>  		 * up, for example many KVM do not pass it through, and so
>  		 * only trust an assertion that the monitor is connected.
> @@ -715,7 +715,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
>  	 * broken monitor (without edid) to work behind a broken kvm (that fails
>  	 * to have the right resistors for HP detection) needs to fix this up.
>  	 * For now just bail out. */
> -	if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
> +	if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
>  		status = connector_status_disconnected;
>  		goto out;
>  	}
> @@ -915,7 +915,7 @@ void intel_crt_init(struct drm_device *dev)
>  		crt->base.disable = intel_disable_crt;
>  	}
>  	crt->base.enable = intel_enable_crt;
> -	if (I915_HAS_HOTPLUG(dev) &&
> +	if (I915_HAS_HOTPLUG(dev_priv) &&
>  	    !dmi_check_system(intel_spurious_crt_detect))
>  		crt->base.hpd_pin = HPD_CRT;
>  	if (HAS_DDI(dev_priv)) {
> @@ -932,7 +932,7 @@ void intel_crt_init(struct drm_device *dev)
>  
>  	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
>  
> -	if (!I915_HAS_HOTPLUG(dev))
> +	if (!I915_HAS_HOTPLUG(dev_priv))
>  		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 92ab01f33208..3a3b97ae6b10 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8438,7 +8438,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  		}
>  	}
>  
> -	if (HAS_PIPE_CXSR(dev)) {
> +	if (HAS_PIPE_CXSR(dev_priv)) {
>  		if (intel_crtc->lowfreq_avail) {
>  			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
>  			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
> @@ -15643,7 +15643,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  	} else if (IS_GEN2(dev_priv))
>  		intel_dvo_init(dev);
>  
> -	if (SUPPORTS_TV(dev))
> +	if (SUPPORTS_TV(dev_priv))
>  		intel_tv_init(dev);
>  
>  	intel_psr_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d4e9cf3ad26e..4c9981ccfc23 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5742,7 +5742,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	}
>  
>  	/* init MST on ports that can support it */
> -	if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
> +	if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
>  	    (port == PORT_B || port == PORT_C || port == PORT_D))
>  		intel_dp_mst_encoder_init(intel_dig_port,
>  					  intel_connector->base.base.id);
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index 334d47b5811a..3d546c019de0 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -501,7 +501,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
>  		if (intel_connector->mst_port)
>  			continue;
>  
> -		if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
> +		if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) &&
>  		    intel_connector->encoder->hpd_pin > HPD_NONE) {
>  			connector->polled = enabled ?
>  				DRM_CONNECTOR_POLL_CONNECT |
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 271a3e29ff23..41e6e920d9d7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -427,7 +427,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>  
> -	if (!HAS_PSR(dev)) {
> +	if (!HAS_PSR(dev_priv)) {
>  		DRM_DEBUG_KMS("PSR not supported on this platform\n");
>  		return;
>  	}
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: Further assorted dev_priv cleanups
  2016-11-04 14:42 ` [PATCH 3/5] drm/i915: Further " Tvrtko Ursulin
@ 2016-11-09 10:38   ` David Weinehall
  0 siblings, 0 replies; 23+ messages in thread
From: David Weinehall @ 2016-11-09 10:38 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Fri, Nov 04, 2016 at 02:42:46PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> A small selection of macros which can only accept dev_priv from
> now on and a resulting trickle of fixups.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h            | 12 ++++++------
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c            |  2 +-
>  drivers/gpu/drm/i915/intel_guc_loader.c    | 10 +++++-----
>  4 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6060e41d25e5..f392b0fb9b86 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2700,7 +2700,7 @@ struct drm_i915_cmd_table {
>  #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
>  
>  #define REVID_FOREVER		0xff
> -#define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
> +#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
>  
>  #define GEN_FOREVER (0)
>  /*
> @@ -2925,13 +2925,13 @@ struct drm_i915_cmd_table {
>   * command submission once loaded. But these are logically independent
>   * properties, so we have separate macros to test them.
>   */
> -#define HAS_GUC(dev)		(INTEL_INFO(dev)->has_guc)
> -#define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
> -#define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
> +#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
> +#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
> +#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
>  
> -#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
> +#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
>  
> -#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
> +#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 9c7d9c88d879..f98921174161 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1616,7 +1616,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>  	}
>  
>  	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
> -		if (!HAS_RESOURCE_STREAMER(dev)) {
> +		if (!HAS_RESOURCE_STREAMER(dev_priv)) {
>  			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
>  			return -EINVAL;
>  		}
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 285ee1e4352a..cb8a75f6ca16 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4145,7 +4145,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
>  	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
>  
> -	if (HAS_GUC_SCHED(dev))
> +	if (HAS_GUC_SCHED(dev_priv))
>  		dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
>  
>  	/* Let's track the enabled rps events */
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 1aa85236b788..34d6ad2cf7c1 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -566,7 +566,7 @@ int intel_guc_setup(struct drm_device *dev)
>  		ret = 0;
>  	}
>  
> -	if (err == 0 && !HAS_GUC_UCODE(dev))
> +	if (err == 0 && !HAS_GUC_UCODE(dev_priv))
>  		;	/* Don't mention the GuC! */
>  	else if (err == 0)
>  		DRM_INFO("GuC firmware load skipped\n");
> @@ -725,18 +725,18 @@ void intel_guc_init(struct drm_device *dev)
>  	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>  	const char *fw_path;
>  
> -	if (!HAS_GUC(dev)) {
> +	if (!HAS_GUC(dev_priv)) {
>  		i915.enable_guc_loading = 0;
>  		i915.enable_guc_submission = 0;
>  	} else {
>  		/* A negative value means "use platform default" */
>  		if (i915.enable_guc_loading < 0)
> -			i915.enable_guc_loading = HAS_GUC_UCODE(dev);
> +			i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
>  		if (i915.enable_guc_submission < 0)
> -			i915.enable_guc_submission = HAS_GUC_SCHED(dev);
> +			i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
>  	}
>  
> -	if (!HAS_GUC_UCODE(dev)) {
> +	if (!HAS_GUC_UCODE(dev_priv)) {
>  		fw_path = NULL;
>  	} else if (IS_SKYLAKE(dev_priv)) {
>  		fw_path = I915_SKL_GUC_UCODE;
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
  2016-11-04 14:42 ` [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use Tvrtko Ursulin
@ 2016-11-09 10:38   ` David Weinehall
  2016-11-09 11:30     ` [PATCH v2 " Tvrtko Ursulin
  0 siblings, 1 reply; 23+ messages in thread
From: David Weinehall @ 2016-11-09 10:38 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Fri, Nov 04, 2016 at 02:42:47PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> After this patch only conversion of INTEL_INFO(p)->gen to
> INTEL_GEN(dev_priv) remains before the __I915__ macro can
> be removed.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c      |  4 ++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c  |  2 +-
>  drivers/gpu/drm/i915/intel_color.c   | 31 ++++++++++++++-----------------
>  drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
>  drivers/gpu/drm/i915/intel_fbdev.c   | 10 +++++-----
>  drivers/gpu/drm/i915/intel_pm.c      |  7 ++++---
>  6 files changed, 39 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 79cea49183b3..35940192e569 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
>  	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
>  	 * (which really amounts to a PCH but no South Display).
>  	 */
> -	if (INTEL_INFO(dev)->num_pipes == 0) {
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
>  		dev_priv->pch_type = PCH_NOP;
>  		return;
>  	}
> @@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  
>  	intel_modeset_gem_init(dev);
>  
> -	if (INTEL_INFO(dev)->num_pipes == 0)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0)
>  		return 0;
>  
>  	ret = intel_fbdev_init(dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cad6de65947d..b98f11735c5b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -714,7 +714,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
>   */
>  static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
>  {
> -	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
> +	ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
>  }
>  
>  /* Removes entries from a single page table, releasing it if it's empty.
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 445108855275..3784940a4e7a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
>  static void broadwell_load_luts(struct drm_crtc_state *state)
>  {
>  	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
>  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> -	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> +	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  
>  	if (crtc_state_is_legacy(state)) {
>  		haswell_load_luts(state);
> @@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
>  static void cherryview_load_luts(struct drm_crtc_state *state)
>  {
>  	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>  	struct drm_color_lut *lut;
>  	uint32_t i, lut_size;
> @@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  
>  	if (state->degamma_lut) {
>  		lut = (struct drm_color_lut *) state->degamma_lut->data;
> -		lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> +		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.14 format. */
>  			word0 =
> @@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  
>  	if (state->gamma_lut) {
>  		lut = (struct drm_color_lut *) state->gamma_lut->data;
> -		lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
> +		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.10 format. */
>  			word0 =
> @@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
>  int intel_color_check(struct drm_crtc *crtc,
>  		      struct drm_crtc_state *crtc_state)
>  {
> -	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	size_t gamma_length, degamma_length;
>  
> -	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
> +	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
>  		sizeof(struct drm_color_lut);
> -	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
> +	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
>  		sizeof(struct drm_color_lut);
>  
>  	/*
> @@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
>  
>  void intel_color_init(struct drm_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  
>  	drm_mode_crtc_set_gamma_size(crtc, 256);
>  
> @@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
>  	}
>  
>  	/* Enable color management support when we have degamma & gamma LUTs. */
> -	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
> -	    INTEL_INFO(dev)->color.gamma_lut_size != 0)
> +	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
> +	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
>  		drm_crtc_enable_color_mgmt(crtc,
> -					INTEL_INFO(dev)->color.degamma_lut_size,
> -					true,
> -					INTEL_INFO(dev)->color.gamma_lut_size);
> +					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
> +					   true,
> +					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bf8099ed0b20..aad264583378 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7057,7 +7057,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
>  		}
>  	}
>  
> -	if (INTEL_INFO(dev)->num_pipes == 2)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 2)
>  		return 0;
>  
>  	/* Ivybridge 3 pipe is really complicated */
> @@ -14706,8 +14706,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>  {
>  	struct intel_atomic_state *intel_state =
>  		to_intel_atomic_state(new_state->state);
> -	struct drm_device *dev = plane->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct drm_framebuffer *fb = new_state->fb;
>  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> @@ -14764,7 +14763,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>  	}
>  
>  	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> -	    INTEL_INFO(dev)->cursor_needs_physical) {
> +	    INTEL_INFO(dev_priv)->cursor_needs_physical) {
>  		int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
>  		ret = i915_gem_object_attach_phys(obj, align);
>  		if (ret) {
> @@ -14797,7 +14796,7 @@ void
>  intel_cleanup_plane_fb(struct drm_plane *plane,
>  		       struct drm_plane_state *old_state)
>  {
> -	struct drm_device *dev = plane->dev;
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct intel_plane_state *old_intel_state;
>  	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
>  	struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
> @@ -14808,7 +14807,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
>  		return;
>  
>  	if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
> -	    !INTEL_INFO(dev)->cursor_needs_physical))
> +	    !INTEL_INFO(dev_priv)->cursor_needs_physical))
>  		intel_unpin_fb_obj(old_state->fb, old_state->rotation);
>  }
>  
> @@ -15133,13 +15132,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
>  {
>  	struct drm_crtc *crtc = crtc_state->base.crtc;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct drm_device *dev = plane->dev;
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
>  	uint32_t addr;
>  
>  	if (!obj)
>  		addr = 0;
> -	else if (!INTEL_INFO(dev)->cursor_needs_physical)
> +	else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
>  		addr = i915_gem_object_ggtt_offset(obj, NULL);
>  	else
>  		addr = obj->phys_handle->busaddr;
> @@ -16421,7 +16420,7 @@ int intel_modeset_init(struct drm_device *dev)
>  
>  	intel_init_pm(dev_priv);
>  
> -	if (INTEL_INFO(dev)->num_pipes == 0)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0)
>  		return 0;
>  
>  	/*
> @@ -16467,8 +16466,8 @@ int intel_modeset_init(struct drm_device *dev)
>  	dev->mode_config.fb_base = ggtt->mappable_base;
>  
>  	DRM_DEBUG_KMS("%d display pipe%s available.\n",
> -		      INTEL_INFO(dev)->num_pipes,
> -		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
> +		      INTEL_INFO(dev_priv)->num_pipes,
> +		      INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
>  
>  	for_each_pipe(dev_priv, pipe) {
>  		int ret;
> @@ -16556,11 +16555,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
>  static bool
>  intel_check_plane_mapping(struct intel_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 val;
>  
> -	if (INTEL_INFO(dev)->num_pipes == 1)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 1)
>  		return true;
>  
>  	val = I915_READ(DSPCNTR(!crtc->plane));
> @@ -17313,7 +17311,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
>  	if (!error)
>  		return;
>  
> -	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
> +	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		err_printf(m, "PWR_WELL_CTL2: %08x\n",
>  			   error->power_well_driver);
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index b7098f98bb67..e3cf655bec3b 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
>  				    struct drm_fb_offset *offsets,
>  				    bool *enabled, int width, int height)
>  {
> -	struct drm_device *dev = fb_helper->dev;
> +	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
>  	unsigned long conn_configured, mask;
>  	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
>  	int i, j;
> @@ -512,7 +512,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
>  	 * fbdev helper library.
>  	 */
>  	if (num_connectors_enabled != num_connectors_detected &&
> -	    num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
> +	    num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
>  		DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
>  		DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
>  			      num_connectors_detected);
> @@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
>  
>  int intel_fbdev_init(struct drm_device *dev)
>  {
> -	struct intel_fbdev *ifbdev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_fbdev *ifbdev;
>  	int ret;
>  
> -	if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
> +	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
>  		return -ENODEV;
>  
>  	ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
> @@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
>  		ifbdev->preferred_bpp = 32;
>  
>  	ret = drm_fb_helper_init(dev, &ifbdev->helper,
> -				 INTEL_INFO(dev)->num_pipes, 4);
> +				 INTEL_INFO(dev_priv)->num_pipes, 4);
>  	if (ret) {
>  		kfree(ifbdev);
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 88e28c989b9c..4512069e4555 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
>  
>  	for (level = 0; level < wm_state->num_levels; level++) {
>  		struct drm_device *dev = crtc->base.dev;
> -		const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> +		const int sr_fifo_size =
> +			INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
>  		struct intel_plane *plane;
>  
>  		wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
> @@ -1093,7 +1094,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
>  	struct drm_device *dev = crtc->base.dev;
>  	struct vlv_wm_state *wm_state = &crtc->wm_state;
>  	struct intel_plane *plane;
> -	int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> +	int sr_fifo_size = INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
>  	int level;
>  
>  	memset(wm_state, 0, sizeof(*wm_state));

This function now contains 3 cases of to_i915(dev) and only one case
that actually uses dev directly. How about rewriting it as converting to
dev_priv only once and instead getting dev from dev_priv->drm?

> @@ -1920,7 +1921,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>  
>  	/* HSW allows LP1+ watermarks even with multiple pipes */
>  	if (level == 0 || config->num_pipes_active > 1) {
> -		fifo_size /= INTEL_INFO(dev)->num_pipes;
> +		fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
>  
>  		/*
>  		 * For some reason the non self refresh


Regards, David
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN
  2016-11-04 14:42 ` [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN Tvrtko Ursulin
@ 2016-11-09 10:39   ` David Weinehall
  0 siblings, 0 replies; 23+ messages in thread
From: David Weinehall @ 2016-11-09 10:39 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Fri, Nov 04, 2016 at 02:42:48PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 35940192e569..096c368bda0b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -374,12 +374,12 @@ static int
>  intel_alloc_mchbar_resource(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> +	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>  	u32 temp_lo, temp_hi = 0;
>  	u64 mchbar_addr;
>  	int ret;
>  
> -	if (INTEL_INFO(dev)->gen >= 4)
> +	if (INTEL_GEN(dev_priv) >= 4)
>  		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
>  	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
>  	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
> @@ -406,7 +406,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
>  		return ret;
>  	}
>  
> -	if (INTEL_INFO(dev)->gen >= 4)
> +	if (INTEL_GEN(dev_priv) >= 4)
>  		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
>  				       upper_32_bits(dev_priv->mch_res.start));
>  
> @@ -420,7 +420,7 @@ static void
>  intel_setup_mchbar(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> +	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>  	u32 temp;
>  	bool enabled;
>  
> @@ -460,7 +460,7 @@ static void
>  intel_teardown_mchbar(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> +	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>  
>  	if (dev_priv->mchbar_need_disable) {
>  		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> @@ -879,7 +879,7 @@ static int i915_mmio_setup(struct drm_device *dev)
>  	 * the register BAR remains the same size for all the earlier
>  	 * generations up to Ironlake.
>  	 */
> -	if (INTEL_INFO(dev)->gen < 5)
> +	if (INTEL_GEN(dev_priv) < 5)
>  		mmio_size = 512 * 1024;
>  	else
>  		mmio_size = 2 * 1024 * 1024;
> @@ -1512,7 +1512,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
>  	 * Fujitsu FSC S7110
>  	 * Acer Aspire 1830T
>  	 */
> -	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
> +	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
>  		pci_set_power_state(pdev, PCI_D3hot);
>  
>  	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PATCH v2 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
  2016-11-09 10:38   ` David Weinehall
@ 2016-11-09 11:30     ` Tvrtko Ursulin
  2016-11-09 11:42       ` David Weinehall
  0 siblings, 1 reply; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-09 11:30 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

After this patch only conversion of INTEL_INFO(p)->gen to
INTEL_GEN(dev_priv) remains before the __I915__ macro can
be removed.

v2: Tidy vlv_compute_wm. (David Weinehall)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      |  4 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  2 +-
 drivers/gpu/drm/i915/intel_color.c   | 31 ++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
 drivers/gpu/drm/i915/intel_fbdev.c   | 10 +++++-----
 drivers/gpu/drm/i915/intel_pm.c      | 12 +++++++-----
 6 files changed, 42 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0213a3090ab3..20b1e19d982b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
 	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 	 * (which really amounts to a PCH but no South Display).
 	 */
-	if (INTEL_INFO(dev)->num_pipes == 0) {
+	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 		dev_priv->pch_type = PCH_NOP;
 		return;
 	}
@@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
 	intel_modeset_gem_init(dev);
 
-	if (INTEL_INFO(dev)->num_pipes == 0)
+	if (INTEL_INFO(dev_priv)->num_pipes == 0)
 		return 0;
 
 	ret = intel_fbdev_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a5fafa3d4fc8..2eb22ba06bc0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -714,7 +714,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
  */
 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 {
-	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
+	ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
 }
 
 /* Removes entries from a single page table, releasing it if it's empty.
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 445108855275..3784940a4e7a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
 static void broadwell_load_luts(struct drm_crtc_state *state)
 {
 	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	if (crtc_state_is_legacy(state)) {
 		haswell_load_luts(state);
@@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
 static void cherryview_load_luts(struct drm_crtc_state *state)
 {
 	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 	struct drm_color_lut *lut;
 	uint32_t i, lut_size;
@@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
 
 	if (state->degamma_lut) {
 		lut = (struct drm_color_lut *) state->degamma_lut->data;
-		lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.14 format. */
 			word0 =
@@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
 
 	if (state->gamma_lut) {
 		lut = (struct drm_color_lut *) state->gamma_lut->data;
-		lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
+		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.10 format. */
 			word0 =
@@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
 int intel_color_check(struct drm_crtc *crtc,
 		      struct drm_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	size_t gamma_length, degamma_length;
 
-	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
+	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
 		sizeof(struct drm_color_lut);
-	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
+	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
 		sizeof(struct drm_color_lut);
 
 	/*
@@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
 
 void intel_color_init(struct drm_crtc *crtc)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 
 	drm_mode_crtc_set_gamma_size(crtc, 256);
 
@@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
 	}
 
 	/* Enable color management support when we have degamma & gamma LUTs. */
-	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
-	    INTEL_INFO(dev)->color.gamma_lut_size != 0)
+	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
+	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
 		drm_crtc_enable_color_mgmt(crtc,
-					INTEL_INFO(dev)->color.degamma_lut_size,
-					true,
-					INTEL_INFO(dev)->color.gamma_lut_size);
+					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
+					   true,
+					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2a1abf293a35..e0ad0975755e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7053,7 +7053,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
 		}
 	}
 
-	if (INTEL_INFO(dev)->num_pipes == 2)
+	if (INTEL_INFO(dev_priv)->num_pipes == 2)
 		return 0;
 
 	/* Ivybridge 3 pipe is really complicated */
@@ -14725,8 +14725,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 {
 	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(new_state->state);
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct drm_framebuffer *fb = new_state->fb;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
@@ -14783,7 +14782,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 	}
 
 	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
-	    INTEL_INFO(dev)->cursor_needs_physical) {
+	    INTEL_INFO(dev_priv)->cursor_needs_physical) {
 		int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
 		ret = i915_gem_object_attach_phys(obj, align);
 		if (ret) {
@@ -14816,7 +14815,7 @@ void
 intel_cleanup_plane_fb(struct drm_plane *plane,
 		       struct drm_plane_state *old_state)
 {
-	struct drm_device *dev = plane->dev;
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct intel_plane_state *old_intel_state;
 	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
 	struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
@@ -14827,7 +14826,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 		return;
 
 	if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
-	    !INTEL_INFO(dev)->cursor_needs_physical))
+	    !INTEL_INFO(dev_priv)->cursor_needs_physical))
 		intel_unpin_fb_obj(old_state->fb, old_state->rotation);
 }
 
@@ -15152,13 +15151,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
 {
 	struct drm_crtc *crtc = crtc_state->base.crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_device *dev = plane->dev;
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
 	uint32_t addr;
 
 	if (!obj)
 		addr = 0;
-	else if (!INTEL_INFO(dev)->cursor_needs_physical)
+	else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
 		addr = i915_gem_object_ggtt_offset(obj, NULL);
 	else
 		addr = obj->phys_handle->busaddr;
@@ -16440,7 +16439,7 @@ int intel_modeset_init(struct drm_device *dev)
 
 	intel_init_pm(dev_priv);
 
-	if (INTEL_INFO(dev)->num_pipes == 0)
+	if (INTEL_INFO(dev_priv)->num_pipes == 0)
 		return 0;
 
 	/*
@@ -16486,8 +16485,8 @@ int intel_modeset_init(struct drm_device *dev)
 	dev->mode_config.fb_base = ggtt->mappable_base;
 
 	DRM_DEBUG_KMS("%d display pipe%s available.\n",
-		      INTEL_INFO(dev)->num_pipes,
-		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
+		      INTEL_INFO(dev_priv)->num_pipes,
+		      INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
 
 	for_each_pipe(dev_priv, pipe) {
 		int ret;
@@ -16575,11 +16574,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
 static bool
 intel_check_plane_mapping(struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val;
 
-	if (INTEL_INFO(dev)->num_pipes == 1)
+	if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		return true;
 
 	val = I915_READ(DSPCNTR(!crtc->plane));
@@ -17332,7 +17330,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
 	if (!error)
 		return;
 
-	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
+	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		err_printf(m, "PWR_WELL_CTL2: %08x\n",
 			   error->power_well_driver);
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index b7098f98bb67..e3cf655bec3b 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
 				    struct drm_fb_offset *offsets,
 				    bool *enabled, int width, int height)
 {
-	struct drm_device *dev = fb_helper->dev;
+	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
 	unsigned long conn_configured, mask;
 	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
 	int i, j;
@@ -512,7 +512,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
 	 * fbdev helper library.
 	 */
 	if (num_connectors_enabled != num_connectors_detected &&
-	    num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
+	    num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
 		DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
 		DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
 			      num_connectors_detected);
@@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
 
 int intel_fbdev_init(struct drm_device *dev)
 {
-	struct intel_fbdev *ifbdev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_fbdev *ifbdev;
 	int ret;
 
-	if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
+	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
 		return -ENODEV;
 
 	ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
@@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
 		ifbdev->preferred_bpp = 32;
 
 	ret = drm_fb_helper_init(dev, &ifbdev->helper,
-				 INTEL_INFO(dev)->num_pipes, 4);
+				 INTEL_INFO(dev_priv)->num_pipes, 4);
 	if (ret) {
 		kfree(ifbdev);
 		return ret;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c989b9c..368f801aee0f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
 
 	for (level = 0; level < wm_state->num_levels; level++) {
 		struct drm_device *dev = crtc->base.dev;
-		const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
+		const int sr_fifo_size =
+			INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
 		struct intel_plane *plane;
 
 		wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
@@ -1091,15 +1092,16 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
 static void vlv_compute_wm(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct vlv_wm_state *wm_state = &crtc->wm_state;
 	struct intel_plane *plane;
-	int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
+	int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
 	int level;
 
 	memset(wm_state, 0, sizeof(*wm_state));
 
 	wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
-	wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
+	wm_state->num_levels = dev_priv->wm.max_level + 1;
 
 	wm_state->num_active_planes = 0;
 
@@ -1179,7 +1181,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
 	}
 
 	/* clear any (partially) filled invalid levels */
-	for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
+	for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
 		memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
 		memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
 	}
@@ -1920,7 +1922,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
 
 	/* HSW allows LP1+ watermarks even with multiple pipes */
 	if (level == 0 || config->num_pipes_active > 1) {
-		fifo_size /= INTEL_INFO(dev)->num_pipes;
+		fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
 
 		/*
 		 * For some reason the non self refresh
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* Re: [PATCH v2 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
  2016-11-09 11:30     ` [PATCH v2 " Tvrtko Ursulin
@ 2016-11-09 11:42       ` David Weinehall
  0 siblings, 0 replies; 23+ messages in thread
From: David Weinehall @ 2016-11-09 11:42 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: Intel-gfx

On Wed, Nov 09, 2016 at 11:30:45AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> After this patch only conversion of INTEL_INFO(p)->gen to
> INTEL_GEN(dev_priv) remains before the __I915__ macro can
> be removed.
> 
> v2: Tidy vlv_compute_wm. (David Weinehall)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c      |  4 ++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c  |  2 +-
>  drivers/gpu/drm/i915/intel_color.c   | 31 ++++++++++++++-----------------
>  drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
>  drivers/gpu/drm/i915/intel_fbdev.c   | 10 +++++-----
>  drivers/gpu/drm/i915/intel_pm.c      | 12 +++++++-----
>  6 files changed, 42 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0213a3090ab3..20b1e19d982b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
>  	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
>  	 * (which really amounts to a PCH but no South Display).
>  	 */
> -	if (INTEL_INFO(dev)->num_pipes == 0) {
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
>  		dev_priv->pch_type = PCH_NOP;
>  		return;
>  	}
> @@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  
>  	intel_modeset_gem_init(dev);
>  
> -	if (INTEL_INFO(dev)->num_pipes == 0)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0)
>  		return 0;
>  
>  	ret = intel_fbdev_init(dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a5fafa3d4fc8..2eb22ba06bc0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -714,7 +714,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
>   */
>  static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
>  {
> -	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
> +	ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
>  }
>  
>  /* Removes entries from a single page table, releasing it if it's empty.
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 445108855275..3784940a4e7a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
>  static void broadwell_load_luts(struct drm_crtc_state *state)
>  {
>  	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
>  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> -	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> +	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  
>  	if (crtc_state_is_legacy(state)) {
>  		haswell_load_luts(state);
> @@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
>  static void cherryview_load_luts(struct drm_crtc_state *state)
>  {
>  	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>  	struct drm_color_lut *lut;
>  	uint32_t i, lut_size;
> @@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  
>  	if (state->degamma_lut) {
>  		lut = (struct drm_color_lut *) state->degamma_lut->data;
> -		lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> +		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.14 format. */
>  			word0 =
> @@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  
>  	if (state->gamma_lut) {
>  		lut = (struct drm_color_lut *) state->gamma_lut->data;
> -		lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
> +		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.10 format. */
>  			word0 =
> @@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
>  int intel_color_check(struct drm_crtc *crtc,
>  		      struct drm_crtc_state *crtc_state)
>  {
> -	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	size_t gamma_length, degamma_length;
>  
> -	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
> +	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
>  		sizeof(struct drm_color_lut);
> -	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
> +	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
>  		sizeof(struct drm_color_lut);
>  
>  	/*
> @@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
>  
>  void intel_color_init(struct drm_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  
>  	drm_mode_crtc_set_gamma_size(crtc, 256);
>  
> @@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
>  	}
>  
>  	/* Enable color management support when we have degamma & gamma LUTs. */
> -	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
> -	    INTEL_INFO(dev)->color.gamma_lut_size != 0)
> +	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
> +	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
>  		drm_crtc_enable_color_mgmt(crtc,
> -					INTEL_INFO(dev)->color.degamma_lut_size,
> -					true,
> -					INTEL_INFO(dev)->color.gamma_lut_size);
> +					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
> +					   true,
> +					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2a1abf293a35..e0ad0975755e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7053,7 +7053,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
>  		}
>  	}
>  
> -	if (INTEL_INFO(dev)->num_pipes == 2)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 2)
>  		return 0;
>  
>  	/* Ivybridge 3 pipe is really complicated */
> @@ -14725,8 +14725,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>  {
>  	struct intel_atomic_state *intel_state =
>  		to_intel_atomic_state(new_state->state);
> -	struct drm_device *dev = plane->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct drm_framebuffer *fb = new_state->fb;
>  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> @@ -14783,7 +14782,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>  	}
>  
>  	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> -	    INTEL_INFO(dev)->cursor_needs_physical) {
> +	    INTEL_INFO(dev_priv)->cursor_needs_physical) {
>  		int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
>  		ret = i915_gem_object_attach_phys(obj, align);
>  		if (ret) {
> @@ -14816,7 +14815,7 @@ void
>  intel_cleanup_plane_fb(struct drm_plane *plane,
>  		       struct drm_plane_state *old_state)
>  {
> -	struct drm_device *dev = plane->dev;
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct intel_plane_state *old_intel_state;
>  	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
>  	struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
> @@ -14827,7 +14826,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
>  		return;
>  
>  	if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
> -	    !INTEL_INFO(dev)->cursor_needs_physical))
> +	    !INTEL_INFO(dev_priv)->cursor_needs_physical))
>  		intel_unpin_fb_obj(old_state->fb, old_state->rotation);
>  }
>  
> @@ -15152,13 +15151,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
>  {
>  	struct drm_crtc *crtc = crtc_state->base.crtc;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct drm_device *dev = plane->dev;
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
>  	uint32_t addr;
>  
>  	if (!obj)
>  		addr = 0;
> -	else if (!INTEL_INFO(dev)->cursor_needs_physical)
> +	else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
>  		addr = i915_gem_object_ggtt_offset(obj, NULL);
>  	else
>  		addr = obj->phys_handle->busaddr;
> @@ -16440,7 +16439,7 @@ int intel_modeset_init(struct drm_device *dev)
>  
>  	intel_init_pm(dev_priv);
>  
> -	if (INTEL_INFO(dev)->num_pipes == 0)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0)
>  		return 0;
>  
>  	/*
> @@ -16486,8 +16485,8 @@ int intel_modeset_init(struct drm_device *dev)
>  	dev->mode_config.fb_base = ggtt->mappable_base;
>  
>  	DRM_DEBUG_KMS("%d display pipe%s available.\n",
> -		      INTEL_INFO(dev)->num_pipes,
> -		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
> +		      INTEL_INFO(dev_priv)->num_pipes,
> +		      INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
>  
>  	for_each_pipe(dev_priv, pipe) {
>  		int ret;
> @@ -16575,11 +16574,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
>  static bool
>  intel_check_plane_mapping(struct intel_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 val;
>  
> -	if (INTEL_INFO(dev)->num_pipes == 1)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 1)
>  		return true;
>  
>  	val = I915_READ(DSPCNTR(!crtc->plane));
> @@ -17332,7 +17330,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
>  	if (!error)
>  		return;
>  
> -	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
> +	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		err_printf(m, "PWR_WELL_CTL2: %08x\n",
>  			   error->power_well_driver);
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index b7098f98bb67..e3cf655bec3b 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
>  				    struct drm_fb_offset *offsets,
>  				    bool *enabled, int width, int height)
>  {
> -	struct drm_device *dev = fb_helper->dev;
> +	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
>  	unsigned long conn_configured, mask;
>  	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
>  	int i, j;
> @@ -512,7 +512,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
>  	 * fbdev helper library.
>  	 */
>  	if (num_connectors_enabled != num_connectors_detected &&
> -	    num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
> +	    num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
>  		DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
>  		DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
>  			      num_connectors_detected);
> @@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
>  
>  int intel_fbdev_init(struct drm_device *dev)
>  {
> -	struct intel_fbdev *ifbdev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_fbdev *ifbdev;
>  	int ret;
>  
> -	if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
> +	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
>  		return -ENODEV;
>  
>  	ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
> @@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
>  		ifbdev->preferred_bpp = 32;
>  
>  	ret = drm_fb_helper_init(dev, &ifbdev->helper,
> -				 INTEL_INFO(dev)->num_pipes, 4);
> +				 INTEL_INFO(dev_priv)->num_pipes, 4);
>  	if (ret) {
>  		kfree(ifbdev);
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 88e28c989b9c..368f801aee0f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
>  
>  	for (level = 0; level < wm_state->num_levels; level++) {
>  		struct drm_device *dev = crtc->base.dev;
> -		const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> +		const int sr_fifo_size =
> +			INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
>  		struct intel_plane *plane;
>  
>  		wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
> @@ -1091,15 +1092,16 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
>  static void vlv_compute_wm(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct vlv_wm_state *wm_state = &crtc->wm_state;
>  	struct intel_plane *plane;
> -	int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> +	int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
>  	int level;
>  
>  	memset(wm_state, 0, sizeof(*wm_state));
>  
>  	wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
> -	wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
> +	wm_state->num_levels = dev_priv->wm.max_level + 1;
>  
>  	wm_state->num_active_planes = 0;
>  
> @@ -1179,7 +1181,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
>  	}
>  
>  	/* clear any (partially) filled invalid levels */
> -	for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
> +	for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
>  		memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
>  		memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
>  	}
> @@ -1920,7 +1922,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>  
>  	/* HSW allows LP1+ watermarks even with multiple pipes */
>  	if (level == 0 || config->num_pipes_active > 1) {
> -		fifo_size /= INTEL_INFO(dev)->num_pipes;
> +		fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
>  
>  		/*
>  		 * For some reason the non self refresh
> -- 
> 2.7.4
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3)
  2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
                   ` (6 preceding siblings ...)
  2016-11-07 10:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev2) Patchwork
@ 2016-11-09 12:45 ` Patchwork
  2016-11-10  9:42   ` Tvrtko Ursulin
  7 siblings, 1 reply; 23+ messages in thread
From: Patchwork @ 2016-11-09 12:45 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx

== Series Details ==

Series: dev_priv cleanup continuation (rev3)
URL   : https://patchwork.freedesktop.org/series/14844/
State : success

== Summary ==

Series 14844v3 dev_priv cleanup continuation
https://patchwork.freedesktop.org/api/1.0/series/14844/revisions/3/mbox/


fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

972b631c86ecf25d43d16b3617672f481a5cbd08 drm-intel-nightly: 2016y-11m-09d-10h-46m-28s UTC integration manifest
afa7665 drm/i915: Convert i915_drv.c to INTEL_GEN
4ee340c drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
b15872b drm/i915: Further assorted dev_priv cleanups
2b8c634 drm/i915: More assorted dev_priv cleanups
0e86e55 drm/i915: Assorted dev_priv cleanups

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2942/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3)
  2016-11-09 12:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3) Patchwork
@ 2016-11-10  9:42   ` Tvrtko Ursulin
  2016-11-10 12:00     ` Joonas Lahtinen
  2016-11-11 15:01     ` Tvrtko Ursulin
  0 siblings, 2 replies; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-10  9:42 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Daniel Vetter, Jani Nikula


Hi,

On 09/11/2016 12:45, Patchwork wrote:
> == Series Details ==
>
> Series: dev_priv cleanup continuation (rev3)
> URL   : https://patchwork.freedesktop.org/series/14844/
> State : success
>
> == Summary ==
>
> Series 14844v3 dev_priv cleanup continuation
> https://patchwork.freedesktop.org/api/1.0/series/14844/revisions/3/mbox/
>
>
> fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15
> fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40
> fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28
> fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32
> fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20
> fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20
> fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53
> fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22
> fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22
> fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22
> fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14
> fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21
> fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21
> fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32
> fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33
>
> 972b631c86ecf25d43d16b3617672f481a5cbd08 drm-intel-nightly: 2016y-11m-09d-10h-46m-28s UTC integration manifest
> afa7665 drm/i915: Convert i915_drv.c to INTEL_GEN
> 4ee340c drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
> b15872b drm/i915: Further assorted dev_priv cleanups
> 2b8c634 drm/i915: More assorted dev_priv cleanups
> 0e86e55 drm/i915: Assorted dev_priv cleanups

Ready for merging and just looking for some maintainer acks.

This is not a very disruptive series so should be fine.

After this the only remaining bit of work is to convert everyone to 
INTEL_GEN which I planned to do per file with no strict schedule. One 
file this week, another next and so on.

When that is done the __I915__ magic can be removed.

Afterwards we can follow up with looking at which local functions can be 
converted to take dev_priv instead of dev, where applicable.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3)
  2016-11-10  9:42   ` Tvrtko Ursulin
@ 2016-11-10 12:00     ` Joonas Lahtinen
  2016-11-11 15:01     ` Tvrtko Ursulin
  1 sibling, 0 replies; 23+ messages in thread
From: Joonas Lahtinen @ 2016-11-10 12:00 UTC (permalink / raw)
  To: Tvrtko Ursulin, intel-gfx, Tvrtko Ursulin, Daniel Vetter, Jani Nikula

On to, 2016-11-10 at 09:42 +0000, Tvrtko Ursulin wrote:
> Ready for merging and just looking for some maintainer acks.

+1 on this.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3)
  2016-11-10  9:42   ` Tvrtko Ursulin
  2016-11-10 12:00     ` Joonas Lahtinen
@ 2016-11-11 15:01     ` Tvrtko Ursulin
  1 sibling, 0 replies; 23+ messages in thread
From: Tvrtko Ursulin @ 2016-11-11 15:01 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin


On 10/11/2016 09:42, Tvrtko Ursulin wrote:
> On 09/11/2016 12:45, Patchwork wrote:
>> == Series Details ==
>>
>> Series: dev_priv cleanup continuation (rev3)
>> URL   : https://patchwork.freedesktop.org/series/14844/
>> State : success
>>
>> == Summary ==
>>
>> Series 14844v3 dev_priv cleanup continuation
>> https://patchwork.freedesktop.org/api/1.0/series/14844/revisions/3/mbox/
>>
>>
>> fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0
>> skip:15
>> fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0
>> skip:40
>> fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0
>> skip:28
>> fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0
>> skip:32
>> fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0
>> skip:20
>> fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0
>> skip:20
>> fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0
>> skip:53
>> fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0
>> skip:22
>> fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0
>> skip:22
>> fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0
>> skip:22
>> fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0
>> skip:14
>> fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0
>> skip:21
>> fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0
>> skip:21
>> fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0
>> skip:32
>> fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0
>> skip:33
>>
>> 972b631c86ecf25d43d16b3617672f481a5cbd08 drm-intel-nightly:
>> 2016y-11m-09d-10h-46m-28s UTC integration manifest
>> afa7665 drm/i915: Convert i915_drv.c to INTEL_GEN
>> 4ee340c drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from
>> the gen use
>> b15872b drm/i915: Further assorted dev_priv cleanups
>> 2b8c634 drm/i915: More assorted dev_priv cleanups
>> 0e86e55 drm/i915: Assorted dev_priv cleanups
>
> Ready for merging and just looking for some maintainer acks.
>
> This is not a very disruptive series so should be fine.
>
> After this the only remaining bit of work is to convert everyone to
> INTEL_GEN which I planned to do per file with no strict schedule. One
> file this week, another next and so on.
>
> When that is done the __I915__ magic can be removed.
>
> Afterwards we can follow up with looking at which local functions can be
> converted to take dev_priv instead of dev, where applicable.

Merged to dinq now since Daniel acked it on #intel-gfx.

Many thanks David for reviewing these boring patches, again!

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
end of thread, other threads:[~2016-11-11 15:02 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
2016-11-04 14:42 ` [PATCH 1/5] drm/i915: Assorted dev_priv cleanups Tvrtko Ursulin
2016-11-09 10:37   ` David Weinehall
2016-11-04 14:42 ` [PATCH 2/5] drm/i915: More assorted " Tvrtko Ursulin
2016-11-04 15:32   ` Ville Syrjälä
2016-11-04 16:03     ` Tvrtko Ursulin
2016-11-04 16:29       ` Ville Syrjälä
2016-11-07  9:29         ` [PATCH v2 " Tvrtko Ursulin
2016-11-09 10:38           ` David Weinehall
2016-11-04 14:42 ` [PATCH 3/5] drm/i915: Further " Tvrtko Ursulin
2016-11-09 10:38   ` David Weinehall
2016-11-04 14:42 ` [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use Tvrtko Ursulin
2016-11-09 10:38   ` David Weinehall
2016-11-09 11:30     ` [PATCH v2 " Tvrtko Ursulin
2016-11-09 11:42       ` David Weinehall
2016-11-04 14:42 ` [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN Tvrtko Ursulin
2016-11-09 10:39   ` David Weinehall
2016-11-04 15:23 ` ✗ Fi.CI.BAT: failure for dev_priv cleanup continuation Patchwork
2016-11-07 10:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev2) Patchwork
2016-11-09 12:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3) Patchwork
2016-11-10  9:42   ` Tvrtko Ursulin
2016-11-10 12:00     ` Joonas Lahtinen
2016-11-11 15:01     ` Tvrtko Ursulin

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