[PATCH 0/9] drm/i915: Add a per-pipe plane identifier enum

[PATCH 0/9] drm/i915: Add a per-pipe plane identifier enum

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This series aims to clean up the mess we have with intel_plane->plane
by adding a new intel_plane->id thing. Afterwards the two are clearly
separated so that intel_plane->id is the per-pipe plane identifier,
and intel_plane->plane is the legacy primary plane identifier
(ie. same as intel_plane->pipe everwhere except potentially gen2/3).

Ville Syrjälä (9):
  drm/i915: Remove some duplicated plane swapping logic
  drm/i915: Add per-pipe plane identifier
  drm/i915: Add crtc->plane_ids_mask
  drm/i915: Use enum plane_id in SKL wm code
  drm/i915: Use enum plane_id in SKL plane code
  drm/i915: Use enum plane_id in VLV/CHV sprite code
  drm/i915: Use enum plane_id in VLV/CHV wm code
  drm/i915: Rename the local 'plane' variable to 'plane_id' in primary
    plane code
  drm/i915: Don't populate plane->plane for cursors and sprites

 drivers/gpu/drm/i915/i915_drv.h      |  30 ++++-
 drivers/gpu/drm/i915/i915_reg.h      |  58 +++++----
 drivers/gpu/drm/i915/intel_display.c | 118 +++++++++---------
 drivers/gpu/drm/i915/intel_drv.h     |   6 +-
 drivers/gpu/drm/i915/intel_pm.c      | 229 +++++++++++++++--------------------
 drivers/gpu/drm/i915/intel_sprite.c  | 126 +++++++++----------
 6 files changed, 282 insertions(+), 285 deletions(-)

-- 
2.7.4

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[PATCH 1/9] drm/i915: Remove some duplicated plane swapping logic

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On pre-gen4 we connect plane A to pipe B and vice versa to get an FBC
capable plane feeding the LVDS port by default. We have the logic for
the plane swapping duplicated in many places. Let's remove a bit of the
duplication by having the crtc look up the thing from the primary plane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0bb24b4e8815..10869360cfdc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15000,11 +15000,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		state->scaler_id = -1;
 	}
 	primary->pipe = pipe;
-	primary->plane = pipe;
+	/*
+	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
+	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
+	 */
+	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
+		primary->plane = (enum plane) !pipe;
+	else
+		primary->plane = (enum plane) pipe;
 	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
 	primary->check_plane = intel_check_primary_plane;
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
-		primary->plane = !pipe;
 
 	if (INTEL_GEN(dev_priv) >= 9) {
 		intel_primary_formats = skl_primary_formats;
@@ -15310,16 +15315,8 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 	if (ret)
 		goto fail;
 
-	/*
-	 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
-	 * is hooked to pipe B. Hence we want plane A feeding pipe B.
-	 */
 	intel_crtc->pipe = pipe;
-	intel_crtc->plane = (enum plane) pipe;
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) {
-		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
-		intel_crtc->plane = !pipe;
-	}
+	intel_crtc->plane = primary->plane;
 
 	intel_crtc->cursor_base = ~0;
 	intel_crtc->cursor_cntl = ~0;
-- 
2.7.4

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Re: [PATCH 1/9] drm/i915: Remove some duplicated plane swapping logic

[Chris Wilson]

On Tue, Nov 08, 2016 at 04:47:11PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On pre-gen4 we connect plane A to pipe B and vice versa to get an FBC
> capable plane feeding the LVDS port by default. We have the logic for
> the plane swapping duplicated in many places. Let's remove a bit of the
> duplication by having the crtc look up the thing from the primary plane.

And intel_crtc->plane is just a left over to be removed when we go full
atomic.
 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
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Re: [PATCH 1/9] drm/i915: Remove some duplicated plane swapping logic

[Ville Syrjälä]

On Tue, Nov 08, 2016 at 03:23:14PM +0000, Chris Wilson wrote:
> On Tue, Nov 08, 2016 at 04:47:11PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On pre-gen4 we connect plane A to pipe B and vice versa to get an FBC
> > capable plane feeding the LVDS port by default. We have the logic for
> > the plane swapping duplicated in many places. Let's remove a bit of the
> > duplication by having the crtc look up the thing from the primary plane.
> 
> And intel_crtc->plane is just a left over to be removed when we go full
> atomic.

Yeah, that should die. Just need to sort out the few remaning users
somehow, assuming they won't just disappear magically.

>  
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/9] drm/i915: Remove some duplicated plane swapping logic

[Ville Syrjälä]

On Tue, Nov 08, 2016 at 03:23:14PM +0000, Chris Wilson wrote:
> On Tue, Nov 08, 2016 at 04:47:11PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On pre-gen4 we connect plane A to pipe B and vice versa to get an FBC
> > capable plane feeding the LVDS port by default. We have the logic for
> > the plane swapping duplicated in many places. Let's remove a bit of the
> > duplication by having the crtc look up the thing from the primary plane.
> 
> And intel_crtc->plane is just a left over to be removed when we go full
> atomic.
>  
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Pushed this one to dinq. Thanks for the review.

-- 
Ville Syrjälä
Intel OTC
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[PATCH 2/9] drm/i915: Add per-pipe plane identifier

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

As I told people in [1] we really should not be confusing enum plane
as a per-pipe plane identifier. Looks like that happened nonetheless, so
let's fix it up by splitting the two into two enums.

We'll also want something we just directly pass to various register
offset macros and whatnot on SKL+. So let's make this new thing work for that.
Currently we pass intel_plane->plane for the "sprites" and just a
hardcoded zero for the "primary" planes. We want to get rid of that
hardocoding so that we can share the same code for all planes (apart
from the legacy cursor of course).

[1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/076082.html

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  1 +
 4 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30777dee3f9c..2451b88b1e82 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
 }
 
 /*
- * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
- * number of planes per CRTC.  Not all platforms really have this many planes,
- * which means some arrays of size I915_MAX_PLANES may have unused entries
- * between the topmost sprite plane and the cursor plane.
+ * Global legacy plane identifier. Valid only for primary/sprite
+ * planes on pre-g4x, and only for primary planes on g4x+.
  */
 enum plane {
-	PLANE_A = 0,
+	PLANE_A,
 	PLANE_B,
 	PLANE_C,
-	PLANE_CURSOR,
-	I915_MAX_PLANES,
 };
 #define plane_name(p) ((p) + 'A')
 
 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 
+/*
+ * Per-pipe plane identifier.
+ * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
+ * number of planes per CRTC.  Not all platforms really have this many planes,
+ * which means some arrays of size I915_MAX_PLANES may have unused entries
+ * between the topmost sprite plane and the cursor plane.
+ *
+ * This is expected to be passed to various register macros
+ * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
+ */
+enum plane_id {
+	PLANE_PRIMARY,
+	PLANE_SPRITE0,
+	PLANE_SPRITE1,
+	PLANE_CURSOR,
+	I915_MAX_PLANES,
+};
+
 enum port {
 	PORT_NONE = -1,
 	PORT_A = 0,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 10869360cfdc..b318119330e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		primary->plane = (enum plane) !pipe;
 	else
 		primary->plane = (enum plane) pipe;
+	primary->id = PLANE_PRIMARY;
 	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
 	primary->check_plane = intel_check_primary_plane;
 
@@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	cursor->max_downscale = 1;
 	cursor->pipe = pipe;
 	cursor->plane = pipe;
+	cursor->id = PLANE_CURSOR;
 	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
 	cursor->check_plane = intel_check_cursor_plane;
 	cursor->update_plane = intel_update_cursor_plane;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 398195bf6dd1..58fc8e1d2aa8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
 
 struct intel_plane {
 	struct drm_plane base;
-	int plane;
+	u8 plane;
+	enum plane_id id;
 	enum pipe pipe;
 	bool can_scale;
 	int max_downscale;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 5e4eb7cafef0..4b44863a07c2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 	intel_plane->pipe = pipe;
 	intel_plane->plane = plane;
+	intel_plane->id = PLANE_SPRITE0 + plane;
 	intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
 	intel_plane->check_plane = intel_check_sprite_plane;
 
-- 
2.7.4

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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Chris Wilson]

On Tue, Nov 08, 2016 at 04:47:12PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> As I told people in [1] we really should not be confusing enum plane
> as a per-pipe plane identifier. Looks like that happened nonetheless, so
> let's fix it up by splitting the two into two enums.
> 
> We'll also want something we just directly pass to various register
> offset macros and whatnot on SKL+. So let's make this new thing work for that.
> Currently we pass intel_plane->plane for the "sprites" and just a
> hardcoded zero for the "primary" planes. We want to get rid of that
> hardocoding so that we can share the same code for all planes (apart
> from the legacy cursor of course).
> 
> [1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/076082.html
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-------
>  drivers/gpu/drm/i915/intel_display.c |  2 ++
>  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
>  4 files changed, 26 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 30777dee3f9c..2451b88b1e82 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
>  }
>  
>  /*
> - * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> - * number of planes per CRTC.  Not all platforms really have this many planes,
> - * which means some arrays of size I915_MAX_PLANES may have unused entries
> - * between the topmost sprite plane and the cursor plane.
> + * Global legacy plane identifier. Valid only for primary/sprite
> + * planes on pre-g4x, and only for primary planes on g4x+.
>   */
>  enum plane {
> -	PLANE_A = 0,
> +	PLANE_A,
>  	PLANE_B,
>  	PLANE_C,
> -	PLANE_CURSOR,
> -	I915_MAX_PLANES,
>  };
>  #define plane_name(p) ((p) + 'A')

And make then non-interchangeable with PLANE_A = 'A', PLANE_B = 'B' etc?

>  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')

But that makes that macro even worse. It was an idea.

>  struct intel_plane {
>  	struct drm_plane base;
> -	int plane;
> +	u8 plane;

enum plane plane ?

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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Ville Syrjälä]

On Tue, Nov 08, 2016 at 03:26:31PM +0000, Chris Wilson wrote:
> On Tue, Nov 08, 2016 at 04:47:12PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > As I told people in [1] we really should not be confusing enum plane
> > as a per-pipe plane identifier. Looks like that happened nonetheless, so
> > let's fix it up by splitting the two into two enums.
> > 
> > We'll also want something we just directly pass to various register
> > offset macros and whatnot on SKL+. So let's make this new thing work for that.
> > Currently we pass intel_plane->plane for the "sprites" and just a
> > hardcoded zero for the "primary" planes. We want to get rid of that
> > hardocoding so that we can share the same code for all planes (apart
> > from the legacy cursor of course).
> > 
> > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/076082.html
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-------
> >  drivers/gpu/drm/i915/intel_display.c |  2 ++
> >  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
> >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >  4 files changed, 26 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 30777dee3f9c..2451b88b1e82 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
> >  }
> >  
> >  /*
> > - * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> > - * number of planes per CRTC.  Not all platforms really have this many planes,
> > - * which means some arrays of size I915_MAX_PLANES may have unused entries
> > - * between the topmost sprite plane and the cursor plane.
> > + * Global legacy plane identifier. Valid only for primary/sprite
> > + * planes on pre-g4x, and only for primary planes on g4x+.
> >   */
> >  enum plane {
> > -	PLANE_A = 0,
> > +	PLANE_A,
> >  	PLANE_B,
> >  	PLANE_C,
> > -	PLANE_CURSOR,
> > -	I915_MAX_PLANES,
> >  };
> >  #define plane_name(p) ((p) + 'A')
> 
> And make then non-interchangeable with PLANE_A = 'A', PLANE_B = 'B' etc?
> 
> >  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
> 
> But that makes that macro even worse. It was an idea.

Yeah, would be nice to make it harder to mix things up somehow. But I
must admit I didn't spend much time thinking what would be the best way
to achieve that.

> 
> >  struct intel_plane {
> >  	struct drm_plane base;
> > -	int plane;
> > +	u8 plane;
> 
> enum plane plane ?

A bit later ;)

-- 
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Matt Roper]

On Tue, Nov 08, 2016 at 04:47:12PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> As I told people in [1] we really should not be confusing enum plane
> as a per-pipe plane identifier. Looks like that happened nonetheless, so
> let's fix it up by splitting the two into two enums.
> 
> We'll also want something we just directly pass to various register
> offset macros and whatnot on SKL+. So let's make this new thing work for that.
> Currently we pass intel_plane->plane for the "sprites" and just a
> hardcoded zero for the "primary" planes. We want to get rid of that
> hardocoding so that we can share the same code for all planes (apart
> from the legacy cursor of course).
> 
> [1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/076082.html
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

So the goal here is to make intel_plane->plane represent which of the
system's primary planes (A, B, or C) the plane structure refers to?
From a quick Cocci test, it looks like there's only a single use of the
value for that purpose in our driver (in primary_get_hw_state).  I think
all of the other calls to DSPCNTR are actually using crtc->plane as
their index, which should have the same value.  Would it make more sense
to just drop intel_plane->plane entirely and switch the last user over
to crtc->plane so that we're not carrying around a structure field that
is either bogus or empty on the majority of the platform's planes?

While we're at it, we could rename 'enum plane' to something like 'enum
primary_plane' to make it extra clear what its purpose is and avoid
future confusion.  And maybe a similar rename to crtc->plane as well.
We use the standalone term 'plane' in a generic manner in too many
places in our driver and it means something slightly different
everywhere...


Matt

> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-------
>  drivers/gpu/drm/i915/intel_display.c |  2 ++
>  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
>  4 files changed, 26 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 30777dee3f9c..2451b88b1e82 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
>  }
>  
>  /*
> - * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> - * number of planes per CRTC.  Not all platforms really have this many planes,
> - * which means some arrays of size I915_MAX_PLANES may have unused entries
> - * between the topmost sprite plane and the cursor plane.
> + * Global legacy plane identifier. Valid only for primary/sprite
> + * planes on pre-g4x, and only for primary planes on g4x+.
>   */
>  enum plane {
> -	PLANE_A = 0,
> +	PLANE_A,
>  	PLANE_B,
>  	PLANE_C,
> -	PLANE_CURSOR,
> -	I915_MAX_PLANES,
>  };
>  #define plane_name(p) ((p) + 'A')
>  
>  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
>  
> +/*
> + * Per-pipe plane identifier.
> + * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> + * number of planes per CRTC.  Not all platforms really have this many planes,
> + * which means some arrays of size I915_MAX_PLANES may have unused entries
> + * between the topmost sprite plane and the cursor plane.
> + *
> + * This is expected to be passed to various register macros
> + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> + */
> +enum plane_id {
> +	PLANE_PRIMARY,
> +	PLANE_SPRITE0,
> +	PLANE_SPRITE1,
> +	PLANE_CURSOR,
> +	I915_MAX_PLANES,
> +};
> +
>  enum port {
>  	PORT_NONE = -1,
>  	PORT_A = 0,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 10869360cfdc..b318119330e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		primary->plane = (enum plane) !pipe;
>  	else
>  		primary->plane = (enum plane) pipe;
> +	primary->id = PLANE_PRIMARY;
>  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
>  	primary->check_plane = intel_check_primary_plane;
>  
> @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	cursor->max_downscale = 1;
>  	cursor->pipe = pipe;
>  	cursor->plane = pipe;
> +	cursor->id = PLANE_CURSOR;
>  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
>  	cursor->check_plane = intel_check_cursor_plane;
>  	cursor->update_plane = intel_update_cursor_plane;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 398195bf6dd1..58fc8e1d2aa8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
>  
>  struct intel_plane {
>  	struct drm_plane base;
> -	int plane;
> +	u8 plane;
> +	enum plane_id id;
>  	enum pipe pipe;
>  	bool can_scale;
>  	int max_downscale;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 5e4eb7cafef0..4b44863a07c2 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  
>  	intel_plane->pipe = pipe;
>  	intel_plane->plane = plane;
> +	intel_plane->id = PLANE_SPRITE0 + plane;
>  	intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
>  	intel_plane->check_plane = intel_check_sprite_plane;
>  
> -- 
> 2.7.4
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Ville Syrjälä]

On Tue, Nov 08, 2016 at 04:53:20PM -0800, Matt Roper wrote:
> On Tue, Nov 08, 2016 at 04:47:12PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > As I told people in [1] we really should not be confusing enum plane
> > as a per-pipe plane identifier. Looks like that happened nonetheless, so
> > let's fix it up by splitting the two into two enums.
> > 
> > We'll also want something we just directly pass to various register
> > offset macros and whatnot on SKL+. So let's make this new thing work for that.
> > Currently we pass intel_plane->plane for the "sprites" and just a
> > hardcoded zero for the "primary" planes. We want to get rid of that
> > hardocoding so that we can share the same code for all planes (apart
> > from the legacy cursor of course).
> > 
> > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/076082.html
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> So the goal here is to make intel_plane->plane represent which of the
> system's primary planes (A, B, or C) the plane structure refers to?

It's the index we pass to DSPCNTR & co. On SKL+ we theoretically don't
need it since we index most of plane registers via the plane->id, but
there are still a few exceptions left perhaps, which is why I didn't
outlaw it fully on SKL+ at this point.

> >From a quick Cocci test, it looks like there's only a single use of the
> value for that purpose in our driver (in primary_get_hw_state).  I think
> all of the other calls to DSPCNTR are actually using crtc->plane as
> their index, which should have the same value.  Would it make more sense
> to just drop intel_plane->plane entirely and switch the last user over
> to crtc->plane so that we're not carrying around a structure field that
> is either bogus or empty on the majority of the platform's planes?

crtc->plane needs to die. We want the planes to be independent of crtcs
on pre-g4x.

> 
> While we're at it, we could rename 'enum plane' to something like 'enum
> primary_plane' to make it extra clear what its purpose is and avoid
> future confusion.  And maybe a similar rename to crtc->plane as well.
> We use the standalone term 'plane' in a generic manner in too many
> places in our driver and it means something slightly different
> everywhere...

I think I want to resurrect plane->plane for cursor at some point since
on gen2/3 cursors can move between pipes as well. Alternative we could
add some other enum for those.

Anyways, I was thinking of calling this thing legacy_plane_id or
something like that, but couldn't really convince myself that any
particular name was good, so I left it as is for now.

> 
> 
> Matt
> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-------
> >  drivers/gpu/drm/i915/intel_display.c |  2 ++
> >  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
> >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >  4 files changed, 26 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 30777dee3f9c..2451b88b1e82 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
> >  }
> >  
> >  /*
> > - * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> > - * number of planes per CRTC.  Not all platforms really have this many planes,
> > - * which means some arrays of size I915_MAX_PLANES may have unused entries
> > - * between the topmost sprite plane and the cursor plane.
> > + * Global legacy plane identifier. Valid only for primary/sprite
> > + * planes on pre-g4x, and only for primary planes on g4x+.
> >   */
> >  enum plane {
> > -	PLANE_A = 0,
> > +	PLANE_A,
> >  	PLANE_B,
> >  	PLANE_C,
> > -	PLANE_CURSOR,
> > -	I915_MAX_PLANES,
> >  };
> >  #define plane_name(p) ((p) + 'A')
> >  
> >  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
> >  
> > +/*
> > + * Per-pipe plane identifier.
> > + * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> > + * number of planes per CRTC.  Not all platforms really have this many planes,
> > + * which means some arrays of size I915_MAX_PLANES may have unused entries
> > + * between the topmost sprite plane and the cursor plane.
> > + *
> > + * This is expected to be passed to various register macros
> > + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> > + */
> > +enum plane_id {
> > +	PLANE_PRIMARY,
> > +	PLANE_SPRITE0,
> > +	PLANE_SPRITE1,
> > +	PLANE_CURSOR,
> > +	I915_MAX_PLANES,
> > +};
> > +
> >  enum port {
> >  	PORT_NONE = -1,
> >  	PORT_A = 0,
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 10869360cfdc..b318119330e8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  		primary->plane = (enum plane) !pipe;
> >  	else
> >  		primary->plane = (enum plane) pipe;
> > +	primary->id = PLANE_PRIMARY;
> >  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
> >  	primary->check_plane = intel_check_primary_plane;
> >  
> > @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  	cursor->max_downscale = 1;
> >  	cursor->pipe = pipe;
> >  	cursor->plane = pipe;
> > +	cursor->id = PLANE_CURSOR;
> >  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
> >  	cursor->check_plane = intel_check_cursor_plane;
> >  	cursor->update_plane = intel_update_cursor_plane;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 398195bf6dd1..58fc8e1d2aa8 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
> >  
> >  struct intel_plane {
> >  	struct drm_plane base;
> > -	int plane;
> > +	u8 plane;
> > +	enum plane_id id;
> >  	enum pipe pipe;
> >  	bool can_scale;
> >  	int max_downscale;
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 5e4eb7cafef0..4b44863a07c2 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  	intel_plane->pipe = pipe;
> >  	intel_plane->plane = plane;
> > +	intel_plane->id = PLANE_SPRITE0 + plane;
> >  	intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
> >  	intel_plane->check_plane = intel_check_sprite_plane;
> >  
> > -- 
> > 2.7.4
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Paulo Zanoni]

Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> As I told people in [1] we really should not be confusing enum plane
> as a per-pipe plane identifier. Looks like that happened nonetheless,
> so
> let's fix it up by splitting the two into two enums.
> 
> We'll also want something we just directly pass to various register
> offset macros and whatnot on SKL+. So let's make this new thing work
> for that.
> Currently we pass intel_plane->plane for the "sprites" and just a
> hardcoded zero for the "primary" planes. We want to get rid of that
> hardocoding so that we can share the same code for all planes (apart
> from the legacy cursor of course).
> 
> [1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/0
> 76082.html
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-----
> --
>  drivers/gpu/drm/i915/intel_display.c |  2 ++
>  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
>  4 files changed, 26 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 30777dee3f9c..2451b88b1e82 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum
> transcoder transcoder)
>  }
>  
>  /*
> - * I915_MAX_PLANES in the enum below is the maximum (across all
> platforms)
> - * number of planes per CRTC.  Not all platforms really have this
> many planes,
> - * which means some arrays of size I915_MAX_PLANES may have unused
> entries
> - * between the topmost sprite plane and the cursor plane.
> + * Global legacy plane identifier. Valid only for primary/sprite
> + * planes on pre-g4x, and only for primary planes on g4x+.
>   */
>  enum plane {
> -	PLANE_A = 0,
> +	PLANE_A,
>  	PLANE_B,
>  	PLANE_C,
> -	PLANE_CURSOR,
> -	I915_MAX_PLANES,
>  };
>  #define plane_name(p) ((p) + 'A')
>  
>  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)-
> >num_sprites[(p)] + (s) + 'A')
>  
> +/*
> + * Per-pipe plane identifier.
> + * I915_MAX_PLANES in the enum below is the maximum (across all
> platforms)
> + * number of planes per CRTC.  Not all platforms really have this
> many planes,
> + * which means some arrays of size I915_MAX_PLANES may have unused
> entries
> + * between the topmost sprite plane and the cursor plane.
> + *
> + * This is expected to be passed to various register macros
> + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> + */
> +enum plane_id {
> +	PLANE_PRIMARY,
> +	PLANE_SPRITE0,
> +	PLANE_SPRITE1,
> +	PLANE_CURSOR,
> +	I915_MAX_PLANES,
> +};

We now have two different enums defining PLANE_SOMETHING, and we even
moved some stuff from one to the other. I think this adds more
confusion to the code, so we would probably be saner with:

enum plane_id {
	PLANE_ID_PRIMARY,
	PLANE_ID_SPRITE0,
	PLANE_ID_SPRITE1,
	PLANE_ID_CURSOR,
	PLANE_ID_{MAX,NUM,TOTAL,SOMETHINGELSE},
};

Otherwise, the patch does what it says, so:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

But please get Matt's ack before merging the series since he's been
touching this area of the code for his work on changing how we treat
the plane cursor.

Also, please consider the renames :).

> +
>  enum port {
>  	PORT_NONE = -1,
>  	PORT_A = 0,
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 10869360cfdc..b318119330e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>  		primary->plane = (enum plane) !pipe;
>  	else
>  		primary->plane = (enum plane) pipe;
> +	primary->id = PLANE_PRIMARY;
>  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
>  	primary->check_plane = intel_check_primary_plane;
>  
> @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>  	cursor->max_downscale = 1;
>  	cursor->pipe = pipe;
>  	cursor->plane = pipe;
> +	cursor->id = PLANE_CURSOR;
>  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
>  	cursor->check_plane = intel_check_cursor_plane;
>  	cursor->update_plane = intel_update_cursor_plane;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 398195bf6dd1..58fc8e1d2aa8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
>  
>  struct intel_plane {
>  	struct drm_plane base;
> -	int plane;
> +	u8 plane;
> +	enum plane_id id;
>  	enum pipe pipe;
>  	bool can_scale;
>  	int max_downscale;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 5e4eb7cafef0..4b44863a07c2 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
>  
>  	intel_plane->pipe = pipe;
>  	intel_plane->plane = plane;
> +	intel_plane->id = PLANE_SPRITE0 + plane;
>  	intel_plane->frontbuffer_bit =
> INTEL_FRONTBUFFER_SPRITE(pipe, plane);
>  	intel_plane->check_plane = intel_check_sprite_plane;
>  
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Ville Syrjälä]

On Thu, Nov 17, 2016 at 05:09:38PM -0200, Paulo Zanoni wrote:
> Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> escreveu:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > As I told people in [1] we really should not be confusing enum plane
> > as a per-pipe plane identifier. Looks like that happened nonetheless,
> > so
> > let's fix it up by splitting the two into two enums.
> > 
> > We'll also want something we just directly pass to various register
> > offset macros and whatnot on SKL+. So let's make this new thing work
> > for that.
> > Currently we pass intel_plane->plane for the "sprites" and just a
> > hardcoded zero for the "primary" planes. We want to get rid of that
> > hardocoding so that we can share the same code for all planes (apart
> > from the legacy cursor of course).
> > 
> > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/0
> > 76082.html
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-----
> > --
> >  drivers/gpu/drm/i915/intel_display.c |  2 ++
> >  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
> >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >  4 files changed, 26 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 30777dee3f9c..2451b88b1e82 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum
> > transcoder transcoder)
> >  }
> >  
> >  /*
> > - * I915_MAX_PLANES in the enum below is the maximum (across all
> > platforms)
> > - * number of planes per CRTC.  Not all platforms really have this
> > many planes,
> > - * which means some arrays of size I915_MAX_PLANES may have unused
> > entries
> > - * between the topmost sprite plane and the cursor plane.
> > + * Global legacy plane identifier. Valid only for primary/sprite
> > + * planes on pre-g4x, and only for primary planes on g4x+.
> >   */
> >  enum plane {
> > -	PLANE_A = 0,
> > +	PLANE_A,
> >  	PLANE_B,
> >  	PLANE_C,
> > -	PLANE_CURSOR,
> > -	I915_MAX_PLANES,
> >  };
> >  #define plane_name(p) ((p) + 'A')
> >  
> >  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)-
> > >num_sprites[(p)] + (s) + 'A')
> >  
> > +/*
> > + * Per-pipe plane identifier.
> > + * I915_MAX_PLANES in the enum below is the maximum (across all
> > platforms)
> > + * number of planes per CRTC.  Not all platforms really have this
> > many planes,
> > + * which means some arrays of size I915_MAX_PLANES may have unused
> > entries
> > + * between the topmost sprite plane and the cursor plane.
> > + *
> > + * This is expected to be passed to various register macros
> > + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> > + */
> > +enum plane_id {
> > +	PLANE_PRIMARY,
> > +	PLANE_SPRITE0,
> > +	PLANE_SPRITE1,
> > +	PLANE_CURSOR,
> > +	I915_MAX_PLANES,
> > +};
> 
> We now have two different enums defining PLANE_SOMETHING, and we even
> moved some stuff from one to the other. I think this adds more
> confusion to the code, so we would probably be saner with:
> 
> enum plane_id {
> 	PLANE_ID_PRIMARY,
> 	PLANE_ID_SPRITE0,
> 	PLANE_ID_SPRITE1,
> 	PLANE_ID_CURSOR,
> 	PLANE_ID_{MAX,NUM,TOTAL,SOMETHINGELSE},
> };

I did have _ID_ in there originally, but then decided it was just wasted
space. Weren't you complaining about me exceeding 80cols already too
much? ;)

I915_MAX_PLANES I wanted to leave be since it was already in use, and it
does match our weird naming convention for these things. So if we change
it we should change all other similar things.

> 
> Otherwise, the patch does what it says, so:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> But please get Matt's ack before merging the series since he's been
> touching this area of the code for his work on changing how we treat
> the plane cursor.

Nod.

> 
> Also, please consider the renames :).

Which ones? The _ID_ thing, or just renaming the entire enum plane to
something else? For the latter my best idea was legacy_plane_id, but
not sure anyone else likes it. I guess we could also make it
primary_plane_id, but like I said that might complicate my long term
plan of restoring its use for cursor planes.

> 
> > +
> >  enum port {
> >  	PORT_NONE = -1,
> >  	PORT_A = 0,
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 10869360cfdc..b318119330e8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> >  		primary->plane = (enum plane) !pipe;
> >  	else
> >  		primary->plane = (enum plane) pipe;
> > +	primary->id = PLANE_PRIMARY;
> >  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
> >  	primary->check_plane = intel_check_primary_plane;
> >  
> > @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> >  	cursor->max_downscale = 1;
> >  	cursor->pipe = pipe;
> >  	cursor->plane = pipe;
> > +	cursor->id = PLANE_CURSOR;
> >  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
> >  	cursor->check_plane = intel_check_cursor_plane;
> >  	cursor->update_plane = intel_update_cursor_plane;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 398195bf6dd1..58fc8e1d2aa8 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
> >  
> >  struct intel_plane {
> >  	struct drm_plane base;
> > -	int plane;
> > +	u8 plane;
> > +	enum plane_id id;
> >  	enum pipe pipe;
> >  	bool can_scale;
> >  	int max_downscale;
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 5e4eb7cafef0..4b44863a07c2 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> >  
> >  	intel_plane->pipe = pipe;
> >  	intel_plane->plane = plane;
> > +	intel_plane->id = PLANE_SPRITE0 + plane;
> >  	intel_plane->frontbuffer_bit =
> > INTEL_FRONTBUFFER_SPRITE(pipe, plane);
> >  	intel_plane->check_plane = intel_check_sprite_plane;
> >  

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Paulo Zanoni]

Em Qui, 2016-11-17 às 21:43 +0200, Ville Syrjälä escreveu:
> On Thu, Nov 17, 2016 at 05:09:38PM -0200, Paulo Zanoni wrote:
> > 
> > Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> > escreveu:
> > > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > As I told people in [1] we really should not be confusing enum
> > > plane
> > > as a per-pipe plane identifier. Looks like that happened
> > > nonetheless,
> > > so
> > > let's fix it up by splitting the two into two enums.
> > > 
> > > We'll also want something we just directly pass to various
> > > register
> > > offset macros and whatnot on SKL+. So let's make this new thing
> > > work
> > > for that.
> > > Currently we pass intel_plane->plane for the "sprites" and just a
> > > hardcoded zero for the "primary" planes. We want to get rid of
> > > that
> > > hardocoding so that we can share the same code for all planes
> > > (apart
> > > from the legacy cursor of course).
> > > 
> > > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-Septemb
> > > er/0
> > > 76082.html
> > > 
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Daniel Vetter <daniel@ffwll.ch>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-
> > > ----
> > > --
> > >  drivers/gpu/drm/i915/intel_display.c |  2 ++
> > >  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
> > >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> > >  4 files changed, 26 insertions(+), 8 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 30777dee3f9c..2451b88b1e82 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum
> > > transcoder transcoder)
> > >  }
> > >  
> > >  /*
> > > - * I915_MAX_PLANES in the enum below is the maximum (across all
> > > platforms)
> > > - * number of planes per CRTC.  Not all platforms really have
> > > this
> > > many planes,
> > > - * which means some arrays of size I915_MAX_PLANES may have
> > > unused
> > > entries
> > > - * between the topmost sprite plane and the cursor plane.
> > > + * Global legacy plane identifier. Valid only for primary/sprite
> > > + * planes on pre-g4x, and only for primary planes on g4x+.
> > >   */
> > >  enum plane {
> > > -	PLANE_A = 0,
> > > +	PLANE_A,
> > >  	PLANE_B,
> > >  	PLANE_C,
> > > -	PLANE_CURSOR,
> > > -	I915_MAX_PLANES,
> > >  };
> > >  #define plane_name(p) ((p) + 'A')
> > >  
> > >  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)-
> > > > 
> > > > num_sprites[(p)] + (s) + 'A')
> > >  
> > > +/*
> > > + * Per-pipe plane identifier.
> > > + * I915_MAX_PLANES in the enum below is the maximum (across all
> > > platforms)
> > > + * number of planes per CRTC.  Not all platforms really have
> > > this
> > > many planes,
> > > + * which means some arrays of size I915_MAX_PLANES may have
> > > unused
> > > entries
> > > + * between the topmost sprite plane and the cursor plane.
> > > + *
> > > + * This is expected to be passed to various register macros
> > > + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> > > + */
> > > +enum plane_id {
> > > +	PLANE_PRIMARY,
> > > +	PLANE_SPRITE0,
> > > +	PLANE_SPRITE1,
> > > +	PLANE_CURSOR,
> > > +	I915_MAX_PLANES,
> > > +};
> > 
> > We now have two different enums defining PLANE_SOMETHING, and we
> > even
> > moved some stuff from one to the other. I think this adds more
> > confusion to the code, so we would probably be saner with:
> > 
> > enum plane_id {
> > 	PLANE_ID_PRIMARY,
> > 	PLANE_ID_SPRITE0,
> > 	PLANE_ID_SPRITE1,
> > 	PLANE_ID_CURSOR,
> > 	PLANE_ID_{MAX,NUM,TOTAL,SOMETHINGELSE},
> > };
> 
> I did have _ID_ in there originally, but then decided it was just
> wasted
> space. Weren't you complaining about me exceeding 80cols already too
> much? ;)

I like to have big_descriptive_variable_names but still stay under 80
columns. It's a design pattern called Masochism.

> 
> I915_MAX_PLANES I wanted to leave be since it was already in use, and
> it
> does match our weird naming convention for these things. So if we
> change
> it we should change all other similar things.

Makes sense.

> 
> > 
> > 
> > Otherwise, the patch does what it says, so:
> > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > 
> > But please get Matt's ack before merging the series since he's been
> > touching this area of the code for his work on changing how we
> > treat
> > the plane cursor.
> 
> Nod.
> 
> > 
> > 
> > Also, please consider the renames :).
> 
> Which ones? The _ID_ thing, or just renaming the entire enum plane to
> something else? For the latter my best idea was legacy_plane_id, but
> not sure anyone else likes it. I guess we could also make it
> primary_plane_id, but like I said that might complicate my long term
> plan of restoring its use for cursor planes.

The big problem addressed by this series is: we have two different
things we call "plane". One refers to the fact that in older hardware
Plane A isn't necessarily attached to Pipe A, so we need the variable
to know how things are connected in the hardware, which hardware plane
we're talking about. The other is for the new platforms, and it refers
to the Z order of the planes on a pipe.

I think this series does a nice job of using "plane_id" to refer to
everything related to the Z order (except for the fact that its enum
doesn't say "id"), but we still use "plane" to refer to the first case.
Having the "plane" vs "plane_id" is already an improvement, but IMHO
there's room to make it even better.

So there are two problems.

Problem 1 is making sure we use "id" every time we're talking about the
Z order. IMHO the only missing thing here would be adding "id" to the
enums.

Problem 2 is finding a more appropriated name to what's still being
called just "plane". How about just renaming it to hw_plane? Or really
just plane_name? plane_selected?

I'm always in favor of having the dumbest possible code, so I wouldn't
complain if you just renamed everything to plane_letter and
plane_number :). I know it sounds super silly, but I bet people would
quickly understand it.

Anyway, you already have the R-B tag for the patch since I believe
we're already better with the code you wrote. Feel free to adopt the
suggestions you think make more sense. Maybe do some of the renames as
later patches if you want.


> 
> > 
> > 
> > > 
> > > +
> > >  enum port {
> > >  	PORT_NONE = -1,
> > >  	PORT_A = 0,
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 10869360cfdc..b318119330e8 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct
> > > drm_i915_private *dev_priv, enum pipe pipe)
> > >  		primary->plane = (enum plane) !pipe;
> > >  	else
> > >  		primary->plane = (enum plane) pipe;
> > > +	primary->id = PLANE_PRIMARY;
> > >  	primary->frontbuffer_bit =
> > > INTEL_FRONTBUFFER_PRIMARY(pipe);
> > >  	primary->check_plane = intel_check_primary_plane;
> > >  
> > > @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct
> > > drm_i915_private *dev_priv, enum pipe pipe)
> > >  	cursor->max_downscale = 1;
> > >  	cursor->pipe = pipe;
> > >  	cursor->plane = pipe;
> > > +	cursor->id = PLANE_CURSOR;
> > >  	cursor->frontbuffer_bit =
> > > INTEL_FRONTBUFFER_CURSOR(pipe);
> > >  	cursor->check_plane = intel_check_cursor_plane;
> > >  	cursor->update_plane = intel_update_cursor_plane;
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 398195bf6dd1..58fc8e1d2aa8 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
> > >  
> > >  struct intel_plane {
> > >  	struct drm_plane base;
> > > -	int plane;
> > > +	u8 plane;
> > > +	enum plane_id id;
> > >  	enum pipe pipe;
> > >  	bool can_scale;
> > >  	int max_downscale;
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > > b/drivers/gpu/drm/i915/intel_sprite.c
> > > index 5e4eb7cafef0..4b44863a07c2 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct
> > > drm_i915_private *dev_priv,
> > >  
> > >  	intel_plane->pipe = pipe;
> > >  	intel_plane->plane = plane;
> > > +	intel_plane->id = PLANE_SPRITE0 + plane;
> > >  	intel_plane->frontbuffer_bit =
> > > INTEL_FRONTBUFFER_SPRITE(pipe, plane);
> > >  	intel_plane->check_plane = intel_check_sprite_plane;
> > >  
> 
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Ville Syrjälä]

On Fri, Nov 18, 2016 at 12:17:06PM -0200, Paulo Zanoni wrote:
> Em Qui, 2016-11-17 às 21:43 +0200, Ville Syrjälä escreveu:
> > On Thu, Nov 17, 2016 at 05:09:38PM -0200, Paulo Zanoni wrote:
> > > 
> > > Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> > > escreveu:
> > > > 
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > As I told people in [1] we really should not be confusing enum
> > > > plane
> > > > as a per-pipe plane identifier. Looks like that happened
> > > > nonetheless,
> > > > so
> > > > let's fix it up by splitting the two into two enums.
> > > > 
> > > > We'll also want something we just directly pass to various
> > > > register
> > > > offset macros and whatnot on SKL+. So let's make this new thing
> > > > work
> > > > for that.
> > > > Currently we pass intel_plane->plane for the "sprites" and just a
> > > > hardcoded zero for the "primary" planes. We want to get rid of
> > > > that
> > > > hardocoding so that we can share the same code for all planes
> > > > (apart
> > > > from the legacy cursor of course).
> > > > 
> > > > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-Septemb
> > > > er/0
> > > > 76082.html
> > > > 
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Daniel Vetter <daniel@ffwll.ch>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-
> > > > ----
> > > > --
> > > >  drivers/gpu/drm/i915/intel_display.c |  2 ++
> > > >  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
> > > >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> > > >  4 files changed, 26 insertions(+), 8 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 30777dee3f9c..2451b88b1e82 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum
> > > > transcoder transcoder)
> > > >  }
> > > >  
> > > >  /*
> > > > - * I915_MAX_PLANES in the enum below is the maximum (across all
> > > > platforms)
> > > > - * number of planes per CRTC.  Not all platforms really have
> > > > this
> > > > many planes,
> > > > - * which means some arrays of size I915_MAX_PLANES may have
> > > > unused
> > > > entries
> > > > - * between the topmost sprite plane and the cursor plane.
> > > > + * Global legacy plane identifier. Valid only for primary/sprite
> > > > + * planes on pre-g4x, and only for primary planes on g4x+.
> > > >   */
> > > >  enum plane {
> > > > -	PLANE_A = 0,
> > > > +	PLANE_A,
> > > >  	PLANE_B,
> > > >  	PLANE_C,
> > > > -	PLANE_CURSOR,
> > > > -	I915_MAX_PLANES,
> > > >  };
> > > >  #define plane_name(p) ((p) + 'A')
> > > >  
> > > >  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)-
> > > > > 
> > > > > num_sprites[(p)] + (s) + 'A')
> > > >  
> > > > +/*
> > > > + * Per-pipe plane identifier.
> > > > + * I915_MAX_PLANES in the enum below is the maximum (across all
> > > > platforms)
> > > > + * number of planes per CRTC.  Not all platforms really have
> > > > this
> > > > many planes,
> > > > + * which means some arrays of size I915_MAX_PLANES may have
> > > > unused
> > > > entries
> > > > + * between the topmost sprite plane and the cursor plane.
> > > > + *
> > > > + * This is expected to be passed to various register macros
> > > > + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> > > > + */
> > > > +enum plane_id {
> > > > +	PLANE_PRIMARY,
> > > > +	PLANE_SPRITE0,
> > > > +	PLANE_SPRITE1,
> > > > +	PLANE_CURSOR,
> > > > +	I915_MAX_PLANES,
> > > > +};
> > > 
> > > We now have two different enums defining PLANE_SOMETHING, and we
> > > even
> > > moved some stuff from one to the other. I think this adds more
> > > confusion to the code, so we would probably be saner with:
> > > 
> > > enum plane_id {
> > > 	PLANE_ID_PRIMARY,
> > > 	PLANE_ID_SPRITE0,
> > > 	PLANE_ID_SPRITE1,
> > > 	PLANE_ID_CURSOR,
> > > 	PLANE_ID_{MAX,NUM,TOTAL,SOMETHINGELSE},
> > > };
> > 
> > I did have _ID_ in there originally, but then decided it was just
> > wasted
> > space. Weren't you complaining about me exceeding 80cols already too
> > much? ;)
> 
> I like to have big_descriptive_variable_names but still stay under 80
> columns. It's a design pattern called Masochism.
> 
> > 
> > I915_MAX_PLANES I wanted to leave be since it was already in use, and
> > it
> > does match our weird naming convention for these things. So if we
> > change
> > it we should change all other similar things.
> 
> Makes sense.
> 
> > 
> > > 
> > > 
> > > Otherwise, the patch does what it says, so:
> > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > 
> > > But please get Matt's ack before merging the series since he's been
> > > touching this area of the code for his work on changing how we
> > > treat
> > > the plane cursor.
> > 
> > Nod.
> > 
> > > 
> > > 
> > > Also, please consider the renames :).
> > 
> > Which ones? The _ID_ thing, or just renaming the entire enum plane to
> > something else? For the latter my best idea was legacy_plane_id, but
> > not sure anyone else likes it. I guess we could also make it
> > primary_plane_id, but like I said that might complicate my long term
> > plan of restoring its use for cursor planes.
> 
> The big problem addressed by this series is: we have two different
> things we call "plane". One refers to the fact that in older hardware
> Plane A isn't necessarily attached to Pipe A, so we need the variable
> to know how things are connected in the hardware, which hardware plane
> we're talking about. The other is for the new platforms, and it refers
> to the Z order of the planes on a pipe.

Not Z order on VLV/CHV as that stuff is actually configurable. But
it's some kind of per pipe plane identifier.

> 
> I think this series does a nice job of using "plane_id" to refer to
> everything related to the Z order (except for the fact that its enum
> doesn't say "id"),

It does. Or yoy mean the actual values? Those don't indeed spell it out.

> but we still use "plane" to refer to the first case.
> Having the "plane" vs "plane_id" is already an improvement, but IMHO
> there's room to make it even better.
> 
> So there are two problems.
> 
> Problem 1 is making sure we use "id" every time we're talking about the
> Z order. IMHO the only missing thing here would be adding "id" to the
> enums.
> 
> Problem 2 is finding a more appropriated name to what's still being
> called just "plane". How about just renaming it to hw_plane? Or really
> just plane_name? plane_selected?

I don't really like any of those. legacy_plane_id is still what I think
I like best.

I mean, we could even go as far as eliminating the enum plane usage
entirely on g4x+, but that would mean duplicating the primary plane code
which would be silly. We have already too much duplication the plane
programming code. For skl+ we shouldn't need it at all since we already
have the plane registers indexed the other way.

The good thing is that the enum plane usage is entirely encapsulated in
the pre-skl primary plane code. So IMO getting the naming just right is
not very important. Limited use, so chances of doing something wrong
are also limited. Although that will change a little eventually as I'll
probably want to start using it a bit more extensively in the pre-g4x
watermark code (when I get around to rewriting it all).

> 
> I'm always in favor of having the dumbest possible code, so I wouldn't
> complain if you just renamed everything to plane_letter and
> plane_number :). I know it sounds super silly, but I bet people would
> quickly understand it.
> 
> Anyway, you already have the R-B tag for the patch since I believe
> we're already better with the code you wrote. Feel free to adopt the
> suggestions you think make more sense. Maybe do some of the renames as
> later patches if you want.
> 
> 
> > 
> > > 
> > > 
> > > > 
> > > > +
> > > >  enum port {
> > > >  	PORT_NONE = -1,
> > > >  	PORT_A = 0,
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index 10869360cfdc..b318119330e8 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct
> > > > drm_i915_private *dev_priv, enum pipe pipe)
> > > >  		primary->plane = (enum plane) !pipe;
> > > >  	else
> > > >  		primary->plane = (enum plane) pipe;
> > > > +	primary->id = PLANE_PRIMARY;
> > > >  	primary->frontbuffer_bit =
> > > > INTEL_FRONTBUFFER_PRIMARY(pipe);
> > > >  	primary->check_plane = intel_check_primary_plane;
> > > >  
> > > > @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct
> > > > drm_i915_private *dev_priv, enum pipe pipe)
> > > >  	cursor->max_downscale = 1;
> > > >  	cursor->pipe = pipe;
> > > >  	cursor->plane = pipe;
> > > > +	cursor->id = PLANE_CURSOR;
> > > >  	cursor->frontbuffer_bit =
> > > > INTEL_FRONTBUFFER_CURSOR(pipe);
> > > >  	cursor->check_plane = intel_check_cursor_plane;
> > > >  	cursor->update_plane = intel_update_cursor_plane;
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index 398195bf6dd1..58fc8e1d2aa8 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
> > > >  
> > > >  struct intel_plane {
> > > >  	struct drm_plane base;
> > > > -	int plane;
> > > > +	u8 plane;
> > > > +	enum plane_id id;
> > > >  	enum pipe pipe;
> > > >  	bool can_scale;
> > > >  	int max_downscale;
> > > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > > > b/drivers/gpu/drm/i915/intel_sprite.c
> > > > index 5e4eb7cafef0..4b44863a07c2 100644
> > > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > > @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct
> > > > drm_i915_private *dev_priv,
> > > >  
> > > >  	intel_plane->pipe = pipe;
> > > >  	intel_plane->plane = plane;
> > > > +	intel_plane->id = PLANE_SPRITE0 + plane;
> > > >  	intel_plane->frontbuffer_bit =
> > > > INTEL_FRONTBUFFER_SPRITE(pipe, plane);
> > > >  	intel_plane->check_plane = intel_check_sprite_plane;
> > > >  
> > 

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Paulo Zanoni]

Em Sex, 2016-11-18 às 16:32 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 18, 2016 at 12:17:06PM -0200, Paulo Zanoni wrote:
> > 
> > Em Qui, 2016-11-17 às 21:43 +0200, Ville Syrjälä escreveu:
> > > 
> > > On Thu, Nov 17, 2016 at 05:09:38PM -0200, Paulo Zanoni wrote:
> > > > 
> > > > 
> > > > Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.co
> > > > m
> > > > escreveu:
> > > > > 
> > > > > 
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > 
> > > > > As I told people in [1] we really should not be confusing
> > > > > enum
> > > > > plane
> > > > > as a per-pipe plane identifier. Looks like that happened
> > > > > nonetheless,
> > > > > so
> > > > > let's fix it up by splitting the two into two enums.
> > > > > 
> > > > > We'll also want something we just directly pass to various
> > > > > register
> > > > > offset macros and whatnot on SKL+. So let's make this new
> > > > > thing
> > > > > work
> > > > > for that.
> > > > > Currently we pass intel_plane->plane for the "sprites" and
> > > > > just a
> > > > > hardcoded zero for the "primary" planes. We want to get rid
> > > > > of
> > > > > that
> > > > > hardocoding so that we can share the same code for all planes
> > > > > (apart
> > > > > from the legacy cursor of course).
> > > > > 
> > > > > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-Sep
> > > > > temb
> > > > > er/0
> > > > > 76082.html
> > > > > 
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Cc: Daniel Vetter <daniel@ffwll.ch>
> > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/i915_drv.h      | 28
> > > > > +++++++++++++++++++++-
> > > > > ----
> > > > > --
> > > > >  drivers/gpu/drm/i915/intel_display.c |  2 ++
> > > > >  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
> > > > >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> > > > >  4 files changed, 26 insertions(+), 8 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > > index 30777dee3f9c..2451b88b1e82 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > @@ -171,22 +171,36 @@ static inline bool
> > > > > transcoder_is_dsi(enum
> > > > > transcoder transcoder)
> > > > >  }
> > > > >  
> > > > >  /*
> > > > > - * I915_MAX_PLANES in the enum below is the maximum (across
> > > > > all
> > > > > platforms)
> > > > > - * number of planes per CRTC.  Not all platforms really have
> > > > > this
> > > > > many planes,
> > > > > - * which means some arrays of size I915_MAX_PLANES may have
> > > > > unused
> > > > > entries
> > > > > - * between the topmost sprite plane and the cursor plane.
> > > > > + * Global legacy plane identifier. Valid only for
> > > > > primary/sprite
> > > > > + * planes on pre-g4x, and only for primary planes on g4x+.
> > > > >   */
> > > > >  enum plane {
> > > > > -	PLANE_A = 0,
> > > > > +	PLANE_A,
> > > > >  	PLANE_B,
> > > > >  	PLANE_C,
> > > > > -	PLANE_CURSOR,
> > > > > -	I915_MAX_PLANES,
> > > > >  };
> > > > >  #define plane_name(p) ((p) + 'A')
> > > > >  
> > > > >  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)-
> > > > > > 
> > > > > > 
> > > > > > num_sprites[(p)] + (s) + 'A')
> > > > >  
> > > > > +/*
> > > > > + * Per-pipe plane identifier.
> > > > > + * I915_MAX_PLANES in the enum below is the maximum (across
> > > > > all
> > > > > platforms)
> > > > > + * number of planes per CRTC.  Not all platforms really have
> > > > > this
> > > > > many planes,
> > > > > + * which means some arrays of size I915_MAX_PLANES may have
> > > > > unused
> > > > > entries
> > > > > + * between the topmost sprite plane and the cursor plane.
> > > > > + *
> > > > > + * This is expected to be passed to various register macros
> > > > > + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with
> > > > > care.
> > > > > + */
> > > > > +enum plane_id {
> > > > > +	PLANE_PRIMARY,
> > > > > +	PLANE_SPRITE0,
> > > > > +	PLANE_SPRITE1,
> > > > > +	PLANE_CURSOR,
> > > > > +	I915_MAX_PLANES,
> > > > > +};
> > > > 
> > > > We now have two different enums defining PLANE_SOMETHING, and
> > > > we
> > > > even
> > > > moved some stuff from one to the other. I think this adds more
> > > > confusion to the code, so we would probably be saner with:
> > > > 
> > > > enum plane_id {
> > > > 	PLANE_ID_PRIMARY,
> > > > 	PLANE_ID_SPRITE0,
> > > > 	PLANE_ID_SPRITE1,
> > > > 	PLANE_ID_CURSOR,
> > > > 	PLANE_ID_{MAX,NUM,TOTAL,SOMETHINGELSE},
> > > > };
> > > 
> > > I did have _ID_ in there originally, but then decided it was just
> > > wasted
> > > space. Weren't you complaining about me exceeding 80cols already
> > > too
> > > much? ;)
> > 
> > I like to have big_descriptive_variable_names but still stay under
> > 80
> > columns. It's a design pattern called Masochism.
> > 
> > > 
> > > 
> > > I915_MAX_PLANES I wanted to leave be since it was already in use,
> > > and
> > > it
> > > does match our weird naming convention for these things. So if we
> > > change
> > > it we should change all other similar things.
> > 
> > Makes sense.
> > 
> > > 
> > > 
> > > > 
> > > > 
> > > > 
> > > > Otherwise, the patch does what it says, so:
> > > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > 
> > > > But please get Matt's ack before merging the series since he's
> > > > been
> > > > touching this area of the code for his work on changing how we
> > > > treat
> > > > the plane cursor.
> > > 
> > > Nod.
> > > 
> > > > 
> > > > 
> > > > 
> > > > Also, please consider the renames :).
> > > 
> > > Which ones? The _ID_ thing, or just renaming the entire enum
> > > plane to
> > > something else? For the latter my best idea was legacy_plane_id,
> > > but
> > > not sure anyone else likes it. I guess we could also make it
> > > primary_plane_id, but like I said that might complicate my long
> > > term
> > > plan of restoring its use for cursor planes.
> > 
> > The big problem addressed by this series is: we have two different
> > things we call "plane". One refers to the fact that in older
> > hardware
> > Plane A isn't necessarily attached to Pipe A, so we need the
> > variable
> > to know how things are connected in the hardware, which hardware
> > plane
> > we're talking about. The other is for the new platforms, and it
> > refers
> > to the Z order of the planes on a pipe.
> 
> Not Z order on VLV/CHV as that stuff is actually configurable. But
> it's some kind of per pipe plane identifier.
> 
> > 
> > 
> > I think this series does a nice job of using "plane_id" to refer to
> > everything related to the Z order (except for the fact that its
> > enum
> > doesn't say "id"),
> 
> It does. Or yoy mean the actual values? Those don't indeed spell it
> out.

I was talking about my suggestion of PLANE_ID_PRIMARY, etc.

> 
> > 
> > but we still use "plane" to refer to the first case.
> > Having the "plane" vs "plane_id" is already an improvement, but
> > IMHO
> > there's room to make it even better.
> > 
> > So there are two problems.
> > 
> > Problem 1 is making sure we use "id" every time we're talking about
> > the
> > Z order. IMHO the only missing thing here would be adding "id" to
> > the
> > enums.
> > 
> > Problem 2 is finding a more appropriated name to what's still being
> > called just "plane". How about just renaming it to hw_plane? Or
> > really
> > just plane_name? plane_selected?
> 
> I don't really like any of those. legacy_plane_id is still what I
> think
> I like best.

Well, at least I tried :).

I agree it's hard to come up with a good name for this thing. I can
definitely live with legacy_plane_id.

> 
> I mean, we could even go as far as eliminating the enum plane usage
> entirely on g4x+, but that would mean duplicating the primary plane
> code
> which would be silly. We have already too much duplication the plane
> programming code. For skl+ we shouldn't need it at all since we
> already
> have the plane registers indexed the other way.
> 
> The good thing is that the enum plane usage is entirely encapsulated
> in
> the pre-skl primary plane code. So IMO getting the naming just right
> is
> not very important. Limited use, so chances of doing something wrong
> are also limited. Although that will change a little eventually as
> I'll
> probably want to start using it a bit more extensively in the pre-g4x
> watermark code (when I get around to rewriting it all).

Well, I already gave the r-b for the current version of the patch, so
it's up to you. My goal here was to try to add some suggestions to make
the code even better to read, but they are not required. I won't block
your series based on the renames. Also, you can even do this as an
additional patch at the end of the series if you want. Feel free to
submit v2 with what you think is the best approach.

> 
> > 
> > 
> > I'm always in favor of having the dumbest possible code, so I
> > wouldn't
> > complain if you just renamed everything to plane_letter and
> > plane_number :). I know it sounds super silly, but I bet people
> > would
> > quickly understand it.
> > 
> > Anyway, you already have the R-B tag for the patch since I believe
> > we're already better with the code you wrote. Feel free to adopt
> > the
> > suggestions you think make more sense. Maybe do some of the renames
> > as
> > later patches if you want.
> > 
> > 
> > > 
> > > 
> > > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > +
> > > > >  enum port {
> > > > >  	PORT_NONE = -1,
> > > > >  	PORT_A = 0,
> > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > > index 10869360cfdc..b318119330e8 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > > @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct
> > > > > drm_i915_private *dev_priv, enum pipe pipe)
> > > > >  		primary->plane = (enum plane) !pipe;
> > > > >  	else
> > > > >  		primary->plane = (enum plane) pipe;
> > > > > +	primary->id = PLANE_PRIMARY;
> > > > >  	primary->frontbuffer_bit =
> > > > > INTEL_FRONTBUFFER_PRIMARY(pipe);
> > > > >  	primary->check_plane = intel_check_primary_plane;
> > > > >  
> > > > > @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct
> > > > > drm_i915_private *dev_priv, enum pipe pipe)
> > > > >  	cursor->max_downscale = 1;
> > > > >  	cursor->pipe = pipe;
> > > > >  	cursor->plane = pipe;
> > > > > +	cursor->id = PLANE_CURSOR;
> > > > >  	cursor->frontbuffer_bit =
> > > > > INTEL_FRONTBUFFER_CURSOR(pipe);
> > > > >  	cursor->check_plane = intel_check_cursor_plane;
> > > > >  	cursor->update_plane = intel_update_cursor_plane;
> > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > > index 398195bf6dd1..58fc8e1d2aa8 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > > @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
> > > > >  
> > > > >  struct intel_plane {
> > > > >  	struct drm_plane base;
> > > > > -	int plane;
> > > > > +	u8 plane;
> > > > > +	enum plane_id id;
> > > > >  	enum pipe pipe;
> > > > >  	bool can_scale;
> > > > >  	int max_downscale;
> > > > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > > > > b/drivers/gpu/drm/i915/intel_sprite.c
> > > > > index 5e4eb7cafef0..4b44863a07c2 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > > > @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct
> > > > > drm_i915_private *dev_priv,
> > > > >  
> > > > >  	intel_plane->pipe = pipe;
> > > > >  	intel_plane->plane = plane;
> > > > > +	intel_plane->id = PLANE_SPRITE0 + plane;
> > > > >  	intel_plane->frontbuffer_bit =
> > > > > INTEL_FRONTBUFFER_SPRITE(pipe, plane);
> > > > >  	intel_plane->check_plane = intel_check_sprite_plane;
> > > > >  
> > > 
> 
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Re: [PATCH 2/9] drm/i915: Add per-pipe plane identifier

[Matt Roper]

On Thu, Nov 17, 2016 at 05:09:38PM -0200, Paulo Zanoni wrote:
> Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> escreveu:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > As I told people in [1] we really should not be confusing enum plane
> > as a per-pipe plane identifier. Looks like that happened nonetheless,
> > so
> > let's fix it up by splitting the two into two enums.
> > 
> > We'll also want something we just directly pass to various register
> > offset macros and whatnot on SKL+. So let's make this new thing work
> > for that.
> > Currently we pass intel_plane->plane for the "sprites" and just a
> > hardcoded zero for the "primary" planes. We want to get rid of that
> > hardocoding so that we can share the same code for all planes (apart
> > from the legacy cursor of course).
> > 
> > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-September/0
> > 76082.html
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      | 28 +++++++++++++++++++++-----
> > --
> >  drivers/gpu/drm/i915/intel_display.c |  2 ++
> >  drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
> >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >  4 files changed, 26 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 30777dee3f9c..2451b88b1e82 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -171,22 +171,36 @@ static inline bool transcoder_is_dsi(enum
> > transcoder transcoder)
> >  }
> >  
> >  /*
> > - * I915_MAX_PLANES in the enum below is the maximum (across all
> > platforms)
> > - * number of planes per CRTC.  Not all platforms really have this
> > many planes,
> > - * which means some arrays of size I915_MAX_PLANES may have unused
> > entries
> > - * between the topmost sprite plane and the cursor plane.
> > + * Global legacy plane identifier. Valid only for primary/sprite
> > + * planes on pre-g4x, and only for primary planes on g4x+.
> >   */
> >  enum plane {
> > -	PLANE_A = 0,
> > +	PLANE_A,
> >  	PLANE_B,
> >  	PLANE_C,
> > -	PLANE_CURSOR,
> > -	I915_MAX_PLANES,
> >  };
> >  #define plane_name(p) ((p) + 'A')
> >  
> >  #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)-
> > >num_sprites[(p)] + (s) + 'A')
> >  
> > +/*
> > + * Per-pipe plane identifier.
> > + * I915_MAX_PLANES in the enum below is the maximum (across all
> > platforms)
> > + * number of planes per CRTC.  Not all platforms really have this
> > many planes,
> > + * which means some arrays of size I915_MAX_PLANES may have unused
> > entries
> > + * between the topmost sprite plane and the cursor plane.
> > + *
> > + * This is expected to be passed to various register macros
> > + * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> > + */
> > +enum plane_id {
> > +	PLANE_PRIMARY,
> > +	PLANE_SPRITE0,
> > +	PLANE_SPRITE1,
> > +	PLANE_CURSOR,
> > +	I915_MAX_PLANES,
> > +};
> 
> We now have two different enums defining PLANE_SOMETHING, and we even
> moved some stuff from one to the other. I think this adds more
> confusion to the code, so we would probably be saner with:
> 
> enum plane_id {
> 	PLANE_ID_PRIMARY,
> 	PLANE_ID_SPRITE0,
> 	PLANE_ID_SPRITE1,
> 	PLANE_ID_CURSOR,
> 	PLANE_ID_{MAX,NUM,TOTAL,SOMETHINGELSE},
> };
> 
> Otherwise, the patch does what it says, so:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> But please get Matt's ack before merging the series since he's been
> touching this area of the code for his work on changing how we treat
> the plane cursor.

Don't worry about conflicting with my series for now.  My patches are
probably on hold for a while until we deal with the stuff being
discussed on the other mailing list.  I'll take care of updating and
rebasing my patches when that's straightened out.


Matt

> 
> Also, please consider the renames :).
> 
> > +
> >  enum port {
> >  	PORT_NONE = -1,
> >  	PORT_A = 0,
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 10869360cfdc..b318119330e8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15008,6 +15008,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> >  		primary->plane = (enum plane) !pipe;
> >  	else
> >  		primary->plane = (enum plane) pipe;
> > +	primary->id = PLANE_PRIMARY;
> >  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
> >  	primary->check_plane = intel_check_primary_plane;
> >  
> > @@ -15203,6 +15204,7 @@ intel_cursor_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> >  	cursor->max_downscale = 1;
> >  	cursor->pipe = pipe;
> >  	cursor->plane = pipe;
> > +	cursor->id = PLANE_CURSOR;
> >  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
> >  	cursor->check_plane = intel_check_cursor_plane;
> >  	cursor->update_plane = intel_update_cursor_plane;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 398195bf6dd1..58fc8e1d2aa8 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -767,7 +767,8 @@ struct intel_plane_wm_parameters {
> >  
> >  struct intel_plane {
> >  	struct drm_plane base;
> > -	int plane;
> > +	u8 plane;
> > +	enum plane_id id;
> >  	enum pipe pipe;
> >  	bool can_scale;
> >  	int max_downscale;
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 5e4eb7cafef0..4b44863a07c2 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1126,6 +1126,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> >  
> >  	intel_plane->pipe = pipe;
> >  	intel_plane->plane = plane;
> > +	intel_plane->id = PLANE_SPRITE0 + plane;
> >  	intel_plane->frontbuffer_bit =
> > INTEL_FRONTBUFFER_SPRITE(pipe, plane);
> >  	intel_plane->check_plane = intel_check_sprite_plane;
> >  
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[PATCH 3/9] drm/i915: Add crtc->plane_ids_mask

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a mask of which planes are available for each pipe. This doesn't
quite work for old platforms with dynamic plane<->pipe assignment, but
as we don't support that sort of stuff (yet) we can get away with it.

The main use I have for this is the for_each_plane_id_on_crtc() macro
for iterating over all possible planes on the crtc. I suppose we could
not add the mask, and instead iterate by comparing intel_plane->pipe
but then we'd need a local intel_plane variable which is just
unnecessary clutter in some cases. But I'm not hung up on this, so if
people prefer the other option I could be convinced to use it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      | 4 ++++
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 drivers/gpu/drm/i915/intel_drv.h     | 3 ++-
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2451b88b1e82..2325efacbd5c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -201,6 +201,10 @@ enum plane_id {
 	I915_MAX_PLANES,
 };
 
+#define for_each_plane_id_on_crtc(__crtc, __p) \
+	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
+		for_each_if ((__crtc)->plane_ids_mask & (1 << (__p)))
+
 enum port {
 	PORT_NONE = -1,
 	PORT_A = 0,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b318119330e8..e3ed5d1fcf0d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15293,6 +15293,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 		ret = PTR_ERR(primary);
 		goto fail;
 	}
+	intel_crtc->plane_ids_mask |= BIT(primary->id);
 
 	for_each_sprite(dev_priv, pipe, sprite) {
 		struct intel_plane *plane;
@@ -15302,6 +15303,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 			ret = PTR_ERR(plane);
 			goto fail;
 		}
+		intel_crtc->plane_ids_mask |= BIT(plane->id);
 	}
 
 	cursor = intel_cursor_plane_create(dev_priv, pipe);
@@ -15309,6 +15311,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 		ret = PTR_ERR(cursor);
 		goto fail;
 	}
+	intel_crtc->plane_ids_mask |= BIT(cursor->id);
 
 	ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
 					&primary->base, &cursor->base,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 58fc8e1d2aa8..a3c696d8bf93 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -689,8 +689,9 @@ struct intel_crtc {
 	 * some outputs connected to this crtc.
 	 */
 	bool active;
-	unsigned long enabled_power_domains;
 	bool lowfreq_avail;
+	u8 plane_ids_mask;
+	unsigned long enabled_power_domains;
 	struct intel_overlay *overlay;
 	struct intel_flip_work *flip_work;
 
-- 
2.7.4

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Re: [PATCH 3/9] drm/i915: Add crtc->plane_ids_mask

[Paulo Zanoni]

Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a mask of which planes are available for each pipe. This doesn't
> quite work for old platforms with dynamic plane<->pipe assignment,
> but
> as we don't support that sort of stuff (yet) we can get away with it.
> 
> The main use I have for this is the for_each_plane_id_on_crtc() macro
> for iterating over all possible planes on the crtc. I suppose we
> could
> not add the mask, and instead iterate by comparing intel_plane->pipe
> but then we'd need a local intel_plane variable which is just
> unnecessary clutter in some cases. But I'm not hung up on this, so if
> people prefer the other option I could be convinced to use it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 4 ++++
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/intel_drv.h     | 3 ++-
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 2451b88b1e82..2325efacbd5c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -201,6 +201,10 @@ enum plane_id {
>  	I915_MAX_PLANES,
>  };
>  
> +#define for_each_plane_id_on_crtc(__crtc, __p) \
> +	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES;
> (__p)++) \
> +		for_each_if ((__crtc)->plane_ids_mask & (1 <<
> (__p)))
> +

Let's be consistent: either use BIT() everywhere or use (1 << bit)
everywhere :).

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>.


>  enum port {
>  	PORT_NONE = -1,
>  	PORT_A = 0,
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b318119330e8..e3ed5d1fcf0d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15293,6 +15293,7 @@ static int intel_crtc_init(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>  		ret = PTR_ERR(primary);
>  		goto fail;
>  	}
> +	intel_crtc->plane_ids_mask |= BIT(primary->id);
>  
>  	for_each_sprite(dev_priv, pipe, sprite) {
>  		struct intel_plane *plane;
> @@ -15302,6 +15303,7 @@ static int intel_crtc_init(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>  			ret = PTR_ERR(plane);
>  			goto fail;
>  		}
> +		intel_crtc->plane_ids_mask |= BIT(plane->id);
>  	}
>  
>  	cursor = intel_cursor_plane_create(dev_priv, pipe);
> @@ -15309,6 +15311,7 @@ static int intel_crtc_init(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>  		ret = PTR_ERR(cursor);
>  		goto fail;
>  	}
> +	intel_crtc->plane_ids_mask |= BIT(cursor->id);
>  
>  	ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc-
> >base,
>  					&primary->base, &cursor-
> >base,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 58fc8e1d2aa8..a3c696d8bf93 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -689,8 +689,9 @@ struct intel_crtc {
>  	 * some outputs connected to this crtc.
>  	 */
>  	bool active;
> -	unsigned long enabled_power_domains;
>  	bool lowfreq_avail;
> +	u8 plane_ids_mask;
> +	unsigned long enabled_power_domains;
>  	struct intel_overlay *overlay;
>  	struct intel_flip_work *flip_work;
>  
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[PATCH 4/9] drm/i915: Use enum plane_id in SKL wm code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Nuke skl_wm_plane_id() and just use the new intel_plane->id.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Lyude <cpaul@redhat.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 156 +++++++++++++++++-----------------------
 1 file changed, 64 insertions(+), 92 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c989b9c..fd8cbc224b07 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2863,28 +2863,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*
- * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
- * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
- * other universal planes are in indices 1..n.  Note that this may leave unused
- * indices between the top "sprite" plane and the cursor.
- */
-static int
-skl_wm_plane_id(const struct intel_plane *plane)
-{
-	switch (plane->base.type) {
-	case DRM_PLANE_TYPE_PRIMARY:
-		return 0;
-	case DRM_PLANE_TYPE_CURSOR:
-		return PLANE_CURSOR;
-	case DRM_PLANE_TYPE_OVERLAY:
-		return plane->plane + 1;
-	default:
-		MISSING_CASE(plane->base.type);
-		return plane->plane;
-	}
-}
-
-/*
  * FIXME: We still don't have the proper code detect if we need to apply the WA,
  * so assume we'll always need it in order to avoid underruns.
  */
@@ -3022,7 +3000,6 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 	struct intel_crtc *crtc;
 	struct intel_plane *plane;
 	struct intel_crtc_state *cstate;
-	struct skl_plane_wm *wm;
 	enum pipe pipe;
 	int level, latency;
 
@@ -3049,7 +3026,8 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 		return false;
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
-		wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
+		struct skl_plane_wm *wm =
+			&cstate->wm.skl.optimal.planes[plane->id];
 
 		/* Skip this plane if it's not enabled */
 		if (!wm->wm[0].plane_en)
@@ -3148,28 +3126,28 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */)
 {
-	enum pipe pipe;
-	int plane;
+	struct intel_crtc *crtc;
 	u32 val;
 
 	memset(ddb, 0, sizeof(*ddb));
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		enum intel_display_power_domain power_domain;
+		enum plane_id plane_id;
+		enum pipe pipe = crtc->pipe;
 
 		power_domain = POWER_DOMAIN_PIPE(pipe);
 		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 			continue;
 
-		for_each_universal_plane(dev_priv, pipe, plane) {
-			val = I915_READ(PLANE_BUF_CFG(pipe, plane));
-			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
-						   val);
-		}
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			if (plane_id != PLANE_CURSOR)
+				val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+			else
+				val = I915_READ(CUR_BUF_CFG(pipe));
 
-		val = I915_READ(CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
-					   val);
+			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+		}
 
 		intel_display_power_put(dev_priv, power_domain);
 	}
@@ -3270,30 +3248,30 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
 	struct drm_crtc_state *cstate = &intel_cstate->base;
 	struct drm_atomic_state *state = cstate->state;
 	struct drm_plane *plane;
-	const struct intel_plane *intel_plane;
 	const struct drm_plane_state *pstate;
-	unsigned int rate, total_data_rate = 0;
-	int id;
+	unsigned int total_data_rate = 0;
 
 	if (WARN_ON(!state))
 		return 0;
 
 	/* Calculate and cache data rate for each plane */
 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
-		id = skl_wm_plane_id(to_intel_plane(plane));
-		intel_plane = to_intel_plane(plane);
+		enum plane_id plane_id = to_intel_plane(plane)->id;
+		unsigned int rate;
+
+		/* FIXME cursor shouldn't be here no? */
 
 		/* packed/uv */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 0);
-		plane_data_rate[id] = rate;
+		plane_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 
 		/* y-plane */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 1);
-		plane_y_data_rate[id] = rate;
+		plane_y_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 	}
@@ -3372,17 +3350,16 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
 	struct drm_plane *plane;
 
 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
-		struct intel_plane *intel_plane = to_intel_plane(plane);
-		int id = skl_wm_plane_id(intel_plane);
+		enum plane_id plane_id = to_intel_plane(plane)->id;
 
-		if (id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR)
 			continue;
 
 		if (!pstate->visible)
 			continue;
 
-		minimum[id] = skl_ddb_min_alloc(pstate, 0);
-		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
+		minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
+		y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -3402,8 +3379,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	uint16_t minimum[I915_MAX_PLANES] = {};
 	uint16_t y_minimum[I915_MAX_PLANES] = {};
 	unsigned int total_data_rate;
+	enum plane_id plane_id;
 	int num_active;
-	int id, i;
 	unsigned plane_data_rate[I915_MAX_PLANES] = {};
 	unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
 
@@ -3438,9 +3415,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	 * proportional to the data rate.
 	 */
 
-	for (i = 0; i < I915_MAX_PLANES; i++) {
-		alloc_size -= minimum[i];
-		alloc_size -= y_minimum[i];
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		alloc_size -= minimum[plane_id];
+		alloc_size -= y_minimum[plane_id];
 	}
 
 	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
@@ -3459,28 +3436,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		return 0;
 
 	start = alloc->start;
-	for (id = 0; id < I915_MAX_PLANES; id++) {
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
 		unsigned int data_rate, y_data_rate;
 		uint16_t plane_blocks, y_plane_blocks = 0;
 
-		if (id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR)
 			continue;
 
-		data_rate = plane_data_rate[id];
+		data_rate = plane_data_rate[plane_id];
 
 		/*
 		 * allocation for (packed formats) or (uv-plane part of planar format):
 		 * promote the expression to 64 bits to avoid overflowing, the
 		 * result is < available as data_rate / total_data_rate < 1
 		 */
-		plane_blocks = minimum[id];
+		plane_blocks = minimum[plane_id];
 		plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
 					total_data_rate);
 
 		/* Leave disabled planes at (0,0) */
 		if (data_rate) {
-			ddb->plane[pipe][id].start = start;
-			ddb->plane[pipe][id].end = start + plane_blocks;
+			ddb->plane[pipe][plane_id].start = start;
+			ddb->plane[pipe][plane_id].end = start + plane_blocks;
 		}
 
 		start += plane_blocks;
@@ -3488,15 +3465,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		/*
 		 * allocation for y_plane part of planar format:
 		 */
-		y_data_rate = plane_y_data_rate[id];
+		y_data_rate = plane_y_data_rate[plane_id];
 
-		y_plane_blocks = y_minimum[id];
+		y_plane_blocks = y_minimum[plane_id];
 		y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
 					total_data_rate);
 
 		if (y_data_rate) {
-			ddb->y_plane[pipe][id].start = start;
-			ddb->y_plane[pipe][id].end = start + y_plane_blocks;
+			ddb->y_plane[pipe][plane_id].start = start;
+			ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
 		}
 
 		start += y_plane_blocks;
@@ -3688,11 +3665,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 			return 0;
 		} else {
 			DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
-			DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
-				      to_intel_crtc(cstate->base.crtc)->pipe,
-				      skl_wm_plane_id(to_intel_plane(pstate->plane)),
-				      res_blocks, ddb_allocation, res_lines);
-
+			DRM_DEBUG_KMS("%s: blocks required = %u/%u, lines required = %u/31\n",
+				      pstate->plane->name, res_blocks, ddb_allocation, res_lines);
 			return -EINVAL;
 		}
 	}
@@ -3719,7 +3693,6 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 	uint16_t ddb_blocks;
 	enum pipe pipe = intel_crtc->pipe;
 	int ret;
-	int i = skl_wm_plane_id(intel_plane);
 
 	if (state)
 		intel_pstate =
@@ -3742,7 +3715,7 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 
 	WARN_ON(!intel_pstate->base.fb);
 
-	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
+	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
 
 	ret = skl_compute_plane_wm(dev_priv,
 				   cstate,
@@ -3805,7 +3778,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 	for_each_intel_plane_mask(&dev_priv->drm,
 				  intel_plane,
 				  cstate->base.plane_mask) {
-		wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
+		wm = &pipe_wm->planes[intel_plane->id];
 
 		for (level = 0; level <= max_level; level++) {
 			ret = skl_compute_wm_level(dev_priv, ddb, cstate,
@@ -3981,17 +3954,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 	struct drm_plane_state *plane_state;
 	struct drm_plane *plane;
 	enum pipe pipe = intel_crtc->pipe;
-	int id;
 
 	WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
 
 	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
-		id = skl_wm_plane_id(to_intel_plane(plane));
+		enum plane_id plane_id = to_intel_plane(plane)->id;
 
-		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
-					&new_ddb->plane[pipe][id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
-					&new_ddb->y_plane[pipe][id]))
+		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
+					&new_ddb->plane[pipe][plane_id]) &&
+		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
+					&new_ddb->y_plane[pipe][plane_id]))
 			continue;
 
 		plane_state = drm_atomic_get_plane_state(state, plane);
@@ -4103,7 +4075,6 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 	const struct intel_plane *intel_plane;
 	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
 	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
-	int id;
 	int i;
 
 	for_each_crtc_in_state(state, crtc, cstate, i) {
@@ -4111,11 +4082,11 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 		enum pipe pipe = intel_crtc->pipe;
 
 		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+			enum plane_id plane_id = intel_plane->id;
 			const struct skl_ddb_entry *old, *new;
 
-			id = skl_wm_plane_id(intel_plane);
-			old = &old_ddb->plane[pipe][id];
-			new = &new_ddb->plane[pipe][id];
+			old = &old_ddb->plane[pipe][plane_id];
+			new = &new_ddb->plane[pipe][plane_id];
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
@@ -4219,14 +4190,16 @@ static void skl_update_wm(struct intel_crtc *intel_crtc)
 	 * their watermarks updated once we update their planes.
 	 */
 	if (intel_crtc->base.state->active_changed) {
-		int plane;
-
-		for_each_universal_plane(dev_priv, pipe, plane)
-			skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
-					   &results->ddb, plane);
+		enum plane_id plane_id;
 
-		skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
-				    &results->ddb);
+		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+			if (plane_id != PLANE_CURSOR)
+				skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane_id],
+						   &results->ddb, plane_id);
+			else
+				skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[plane_id],
+						    &results->ddb);
+		}
 	}
 
 	skl_copy_wm_for_pipe(hw_vals, results, pipe);
@@ -4327,7 +4300,6 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_plane *intel_plane;
-	struct skl_plane_wm *wm;
 	enum pipe pipe = intel_crtc->pipe;
 	int level, id, max_level;
 	uint32_t val;
@@ -4335,20 +4307,20 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 	max_level = ilk_wm_max_level(dev_priv);
 
 	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-		id = skl_wm_plane_id(intel_plane);
-		wm = &out->planes[id];
+		enum plane_id plane_id = intel_plane->id;
+		struct skl_plane_wm *wm = &out->planes[plane_id];
 
 		for (level = 0; level <= max_level; level++) {
 			if (id != PLANE_CURSOR)
-				val = I915_READ(PLANE_WM(pipe, id, level));
+				val = I915_READ(PLANE_WM(pipe, plane_id, level));
 			else
 				val = I915_READ(CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
 		}
 
-		if (id != PLANE_CURSOR)
-			val = I915_READ(PLANE_WM_TRANS(pipe, id));
+		if (plane_id != PLANE_CURSOR)
+			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
 		else
 			val = I915_READ(CUR_WM_TRANS(pipe));
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 4/9] drm/i915: Use enum plane_id in SKL wm code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Nuke skl_wm_plane_id() and just use the new intel_plane->id.

v2: Convert skl_write_plane_wm() as well

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Lyude <cpaul@redhat.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h |   2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 170 ++++++++++++++++-----------------------
 2 files changed, 72 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a3c696d8bf93..6a4cd6edafa5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1751,7 +1751,7 @@ void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 			const struct skl_plane_wm *wm,
 			const struct skl_ddb_allocation *ddb,
-			int plane);
+			enum plane_id plane_id);
 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 bool ilk_disable_lp_wm(struct drm_device *dev);
 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c989b9c..93595ce64cb7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2863,28 +2863,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*
- * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
- * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
- * other universal planes are in indices 1..n.  Note that this may leave unused
- * indices between the top "sprite" plane and the cursor.
- */
-static int
-skl_wm_plane_id(const struct intel_plane *plane)
-{
-	switch (plane->base.type) {
-	case DRM_PLANE_TYPE_PRIMARY:
-		return 0;
-	case DRM_PLANE_TYPE_CURSOR:
-		return PLANE_CURSOR;
-	case DRM_PLANE_TYPE_OVERLAY:
-		return plane->plane + 1;
-	default:
-		MISSING_CASE(plane->base.type);
-		return plane->plane;
-	}
-}
-
-/*
  * FIXME: We still don't have the proper code detect if we need to apply the WA,
  * so assume we'll always need it in order to avoid underruns.
  */
@@ -3022,7 +3000,6 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 	struct intel_crtc *crtc;
 	struct intel_plane *plane;
 	struct intel_crtc_state *cstate;
-	struct skl_plane_wm *wm;
 	enum pipe pipe;
 	int level, latency;
 
@@ -3049,7 +3026,8 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 		return false;
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
-		wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
+		struct skl_plane_wm *wm =
+			&cstate->wm.skl.optimal.planes[plane->id];
 
 		/* Skip this plane if it's not enabled */
 		if (!wm->wm[0].plane_en)
@@ -3148,28 +3126,28 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */)
 {
-	enum pipe pipe;
-	int plane;
+	struct intel_crtc *crtc;
 	u32 val;
 
 	memset(ddb, 0, sizeof(*ddb));
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		enum intel_display_power_domain power_domain;
+		enum plane_id plane_id;
+		enum pipe pipe = crtc->pipe;
 
 		power_domain = POWER_DOMAIN_PIPE(pipe);
 		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 			continue;
 
-		for_each_universal_plane(dev_priv, pipe, plane) {
-			val = I915_READ(PLANE_BUF_CFG(pipe, plane));
-			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
-						   val);
-		}
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			if (plane_id != PLANE_CURSOR)
+				val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+			else
+				val = I915_READ(CUR_BUF_CFG(pipe));
 
-		val = I915_READ(CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
-					   val);
+			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+		}
 
 		intel_display_power_put(dev_priv, power_domain);
 	}
@@ -3270,30 +3248,30 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
 	struct drm_crtc_state *cstate = &intel_cstate->base;
 	struct drm_atomic_state *state = cstate->state;
 	struct drm_plane *plane;
-	const struct intel_plane *intel_plane;
 	const struct drm_plane_state *pstate;
-	unsigned int rate, total_data_rate = 0;
-	int id;
+	unsigned int total_data_rate = 0;
 
 	if (WARN_ON(!state))
 		return 0;
 
 	/* Calculate and cache data rate for each plane */
 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
-		id = skl_wm_plane_id(to_intel_plane(plane));
-		intel_plane = to_intel_plane(plane);
+		enum plane_id plane_id = to_intel_plane(plane)->id;
+		unsigned int rate;
+
+		/* FIXME cursor shouldn't be here no? */
 
 		/* packed/uv */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 0);
-		plane_data_rate[id] = rate;
+		plane_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 
 		/* y-plane */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 1);
-		plane_y_data_rate[id] = rate;
+		plane_y_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 	}
@@ -3372,17 +3350,16 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
 	struct drm_plane *plane;
 
 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
-		struct intel_plane *intel_plane = to_intel_plane(plane);
-		int id = skl_wm_plane_id(intel_plane);
+		enum plane_id plane_id = to_intel_plane(plane)->id;
 
-		if (id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR)
 			continue;
 
 		if (!pstate->visible)
 			continue;
 
-		minimum[id] = skl_ddb_min_alloc(pstate, 0);
-		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
+		minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
+		y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -3402,8 +3379,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	uint16_t minimum[I915_MAX_PLANES] = {};
 	uint16_t y_minimum[I915_MAX_PLANES] = {};
 	unsigned int total_data_rate;
+	enum plane_id plane_id;
 	int num_active;
-	int id, i;
 	unsigned plane_data_rate[I915_MAX_PLANES] = {};
 	unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
 
@@ -3438,9 +3415,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	 * proportional to the data rate.
 	 */
 
-	for (i = 0; i < I915_MAX_PLANES; i++) {
-		alloc_size -= minimum[i];
-		alloc_size -= y_minimum[i];
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		alloc_size -= minimum[plane_id];
+		alloc_size -= y_minimum[plane_id];
 	}
 
 	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
@@ -3459,28 +3436,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		return 0;
 
 	start = alloc->start;
-	for (id = 0; id < I915_MAX_PLANES; id++) {
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
 		unsigned int data_rate, y_data_rate;
 		uint16_t plane_blocks, y_plane_blocks = 0;
 
-		if (id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR)
 			continue;
 
-		data_rate = plane_data_rate[id];
+		data_rate = plane_data_rate[plane_id];
 
 		/*
 		 * allocation for (packed formats) or (uv-plane part of planar format):
 		 * promote the expression to 64 bits to avoid overflowing, the
 		 * result is < available as data_rate / total_data_rate < 1
 		 */
-		plane_blocks = minimum[id];
+		plane_blocks = minimum[plane_id];
 		plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
 					total_data_rate);
 
 		/* Leave disabled planes at (0,0) */
 		if (data_rate) {
-			ddb->plane[pipe][id].start = start;
-			ddb->plane[pipe][id].end = start + plane_blocks;
+			ddb->plane[pipe][plane_id].start = start;
+			ddb->plane[pipe][plane_id].end = start + plane_blocks;
 		}
 
 		start += plane_blocks;
@@ -3488,15 +3465,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		/*
 		 * allocation for y_plane part of planar format:
 		 */
-		y_data_rate = plane_y_data_rate[id];
+		y_data_rate = plane_y_data_rate[plane_id];
 
-		y_plane_blocks = y_minimum[id];
+		y_plane_blocks = y_minimum[plane_id];
 		y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
 					total_data_rate);
 
 		if (y_data_rate) {
-			ddb->y_plane[pipe][id].start = start;
-			ddb->y_plane[pipe][id].end = start + y_plane_blocks;
+			ddb->y_plane[pipe][plane_id].start = start;
+			ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
 		}
 
 		start += y_plane_blocks;
@@ -3688,11 +3665,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 			return 0;
 		} else {
 			DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
-			DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
-				      to_intel_crtc(cstate->base.crtc)->pipe,
-				      skl_wm_plane_id(to_intel_plane(pstate->plane)),
-				      res_blocks, ddb_allocation, res_lines);
-
+			DRM_DEBUG_KMS("%s: blocks required = %u/%u, lines required = %u/31\n",
+				      pstate->plane->name, res_blocks, ddb_allocation, res_lines);
 			return -EINVAL;
 		}
 	}
@@ -3719,7 +3693,6 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 	uint16_t ddb_blocks;
 	enum pipe pipe = intel_crtc->pipe;
 	int ret;
-	int i = skl_wm_plane_id(intel_plane);
 
 	if (state)
 		intel_pstate =
@@ -3742,7 +3715,7 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 
 	WARN_ON(!intel_pstate->base.fb);
 
-	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
+	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
 
 	ret = skl_compute_plane_wm(dev_priv,
 				   cstate,
@@ -3805,7 +3778,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 	for_each_intel_plane_mask(&dev_priv->drm,
 				  intel_plane,
 				  cstate->base.plane_mask) {
-		wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
+		wm = &pipe_wm->planes[intel_plane->id];
 
 		for (level = 0; level <= max_level; level++) {
 			ret = skl_compute_wm_level(dev_priv, ddb, cstate,
@@ -3849,7 +3822,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 			const struct skl_plane_wm *wm,
 			const struct skl_ddb_allocation *ddb,
-			int plane)
+			enum plane_id plane_id)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
 	struct drm_device *dev = crtc->dev;
@@ -3858,16 +3831,16 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 	enum pipe pipe = intel_crtc->pipe;
 
 	for (level = 0; level <= max_level; level++) {
-		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
+		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
 				   &wm->wm[level]);
 	}
-	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
+	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
 
-	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
-			    &ddb->plane[pipe][plane]);
-	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
-			    &ddb->y_plane[pipe][plane]);
+	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+			    &ddb->plane[pipe][plane_id]);
+	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
+			    &ddb->y_plane[pipe][plane_id]);
 }
 
 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -3981,17 +3954,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 	struct drm_plane_state *plane_state;
 	struct drm_plane *plane;
 	enum pipe pipe = intel_crtc->pipe;
-	int id;
 
 	WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
 
 	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
-		id = skl_wm_plane_id(to_intel_plane(plane));
+		enum plane_id plane_id = to_intel_plane(plane)->id;
 
-		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
-					&new_ddb->plane[pipe][id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
-					&new_ddb->y_plane[pipe][id]))
+		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
+					&new_ddb->plane[pipe][plane_id]) &&
+		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
+					&new_ddb->y_plane[pipe][plane_id]))
 			continue;
 
 		plane_state = drm_atomic_get_plane_state(state, plane);
@@ -4103,7 +4075,6 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 	const struct intel_plane *intel_plane;
 	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
 	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
-	int id;
 	int i;
 
 	for_each_crtc_in_state(state, crtc, cstate, i) {
@@ -4111,11 +4082,11 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 		enum pipe pipe = intel_crtc->pipe;
 
 		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+			enum plane_id plane_id = intel_plane->id;
 			const struct skl_ddb_entry *old, *new;
 
-			id = skl_wm_plane_id(intel_plane);
-			old = &old_ddb->plane[pipe][id];
-			new = &new_ddb->plane[pipe][id];
+			old = &old_ddb->plane[pipe][plane_id];
+			new = &new_ddb->plane[pipe][plane_id];
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
@@ -4219,14 +4190,16 @@ static void skl_update_wm(struct intel_crtc *intel_crtc)
 	 * their watermarks updated once we update their planes.
 	 */
 	if (intel_crtc->base.state->active_changed) {
-		int plane;
-
-		for_each_universal_plane(dev_priv, pipe, plane)
-			skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
-					   &results->ddb, plane);
+		enum plane_id plane_id;
 
-		skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
-				    &results->ddb);
+		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+			if (plane_id != PLANE_CURSOR)
+				skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane_id],
+						   &results->ddb, plane_id);
+			else
+				skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[plane_id],
+						    &results->ddb);
+		}
 	}
 
 	skl_copy_wm_for_pipe(hw_vals, results, pipe);
@@ -4327,7 +4300,6 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_plane *intel_plane;
-	struct skl_plane_wm *wm;
 	enum pipe pipe = intel_crtc->pipe;
 	int level, id, max_level;
 	uint32_t val;
@@ -4335,20 +4307,20 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 	max_level = ilk_wm_max_level(dev_priv);
 
 	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-		id = skl_wm_plane_id(intel_plane);
-		wm = &out->planes[id];
+		enum plane_id plane_id = intel_plane->id;
+		struct skl_plane_wm *wm = &out->planes[plane_id];
 
 		for (level = 0; level <= max_level; level++) {
 			if (id != PLANE_CURSOR)
-				val = I915_READ(PLANE_WM(pipe, id, level));
+				val = I915_READ(PLANE_WM(pipe, plane_id, level));
 			else
 				val = I915_READ(CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
 		}
 
-		if (id != PLANE_CURSOR)
-			val = I915_READ(PLANE_WM_TRANS(pipe, id));
+		if (plane_id != PLANE_CURSOR)
+			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
 		else
 			val = I915_READ(CUR_WM_TRANS(pipe));
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 4/9] drm/i915: Use enum plane_id in SKL wm code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Nuke skl_wm_plane_id() and just use the new intel_plane->id.

v2: Convert skl_write_plane_wm() as well
v3: Convert skl_pipe_wm_get_hw_state() correctly

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Lyude <cpaul@redhat.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h |   2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 180 ++++++++++++++++-----------------------
 2 files changed, 76 insertions(+), 106 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a3c696d8bf93..6a4cd6edafa5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1751,7 +1751,7 @@ void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 			const struct skl_plane_wm *wm,
 			const struct skl_ddb_allocation *ddb,
-			int plane);
+			enum plane_id plane_id);
 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 bool ilk_disable_lp_wm(struct drm_device *dev);
 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c989b9c..bae7eea6de16 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2863,28 +2863,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*
- * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
- * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
- * other universal planes are in indices 1..n.  Note that this may leave unused
- * indices between the top "sprite" plane and the cursor.
- */
-static int
-skl_wm_plane_id(const struct intel_plane *plane)
-{
-	switch (plane->base.type) {
-	case DRM_PLANE_TYPE_PRIMARY:
-		return 0;
-	case DRM_PLANE_TYPE_CURSOR:
-		return PLANE_CURSOR;
-	case DRM_PLANE_TYPE_OVERLAY:
-		return plane->plane + 1;
-	default:
-		MISSING_CASE(plane->base.type);
-		return plane->plane;
-	}
-}
-
-/*
  * FIXME: We still don't have the proper code detect if we need to apply the WA,
  * so assume we'll always need it in order to avoid underruns.
  */
@@ -3022,7 +3000,6 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 	struct intel_crtc *crtc;
 	struct intel_plane *plane;
 	struct intel_crtc_state *cstate;
-	struct skl_plane_wm *wm;
 	enum pipe pipe;
 	int level, latency;
 
@@ -3049,7 +3026,8 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 		return false;
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
-		wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
+		struct skl_plane_wm *wm =
+			&cstate->wm.skl.optimal.planes[plane->id];
 
 		/* Skip this plane if it's not enabled */
 		if (!wm->wm[0].plane_en)
@@ -3148,28 +3126,28 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */)
 {
-	enum pipe pipe;
-	int plane;
+	struct intel_crtc *crtc;
 	u32 val;
 
 	memset(ddb, 0, sizeof(*ddb));
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		enum intel_display_power_domain power_domain;
+		enum plane_id plane_id;
+		enum pipe pipe = crtc->pipe;
 
 		power_domain = POWER_DOMAIN_PIPE(pipe);
 		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 			continue;
 
-		for_each_universal_plane(dev_priv, pipe, plane) {
-			val = I915_READ(PLANE_BUF_CFG(pipe, plane));
-			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
-						   val);
-		}
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			if (plane_id != PLANE_CURSOR)
+				val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+			else
+				val = I915_READ(CUR_BUF_CFG(pipe));
 
-		val = I915_READ(CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
-					   val);
+			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+		}
 
 		intel_display_power_put(dev_priv, power_domain);
 	}
@@ -3270,30 +3248,30 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
 	struct drm_crtc_state *cstate = &intel_cstate->base;
 	struct drm_atomic_state *state = cstate->state;
 	struct drm_plane *plane;
-	const struct intel_plane *intel_plane;
 	const struct drm_plane_state *pstate;
-	unsigned int rate, total_data_rate = 0;
-	int id;
+	unsigned int total_data_rate = 0;
 
 	if (WARN_ON(!state))
 		return 0;
 
 	/* Calculate and cache data rate for each plane */
 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
-		id = skl_wm_plane_id(to_intel_plane(plane));
-		intel_plane = to_intel_plane(plane);
+		enum plane_id plane_id = to_intel_plane(plane)->id;
+		unsigned int rate;
+
+		/* FIXME cursor shouldn't be here no? */
 
 		/* packed/uv */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 0);
-		plane_data_rate[id] = rate;
+		plane_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 
 		/* y-plane */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 1);
-		plane_y_data_rate[id] = rate;
+		plane_y_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 	}
@@ -3372,17 +3350,16 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
 	struct drm_plane *plane;
 
 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
-		struct intel_plane *intel_plane = to_intel_plane(plane);
-		int id = skl_wm_plane_id(intel_plane);
+		enum plane_id plane_id = to_intel_plane(plane)->id;
 
-		if (id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR)
 			continue;
 
 		if (!pstate->visible)
 			continue;
 
-		minimum[id] = skl_ddb_min_alloc(pstate, 0);
-		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
+		minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
+		y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -3402,8 +3379,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	uint16_t minimum[I915_MAX_PLANES] = {};
 	uint16_t y_minimum[I915_MAX_PLANES] = {};
 	unsigned int total_data_rate;
+	enum plane_id plane_id;
 	int num_active;
-	int id, i;
 	unsigned plane_data_rate[I915_MAX_PLANES] = {};
 	unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
 
@@ -3438,9 +3415,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	 * proportional to the data rate.
 	 */
 
-	for (i = 0; i < I915_MAX_PLANES; i++) {
-		alloc_size -= minimum[i];
-		alloc_size -= y_minimum[i];
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		alloc_size -= minimum[plane_id];
+		alloc_size -= y_minimum[plane_id];
 	}
 
 	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
@@ -3459,28 +3436,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		return 0;
 
 	start = alloc->start;
-	for (id = 0; id < I915_MAX_PLANES; id++) {
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
 		unsigned int data_rate, y_data_rate;
 		uint16_t plane_blocks, y_plane_blocks = 0;
 
-		if (id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR)
 			continue;
 
-		data_rate = plane_data_rate[id];
+		data_rate = plane_data_rate[plane_id];
 
 		/*
 		 * allocation for (packed formats) or (uv-plane part of planar format):
 		 * promote the expression to 64 bits to avoid overflowing, the
 		 * result is < available as data_rate / total_data_rate < 1
 		 */
-		plane_blocks = minimum[id];
+		plane_blocks = minimum[plane_id];
 		plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
 					total_data_rate);
 
 		/* Leave disabled planes at (0,0) */
 		if (data_rate) {
-			ddb->plane[pipe][id].start = start;
-			ddb->plane[pipe][id].end = start + plane_blocks;
+			ddb->plane[pipe][plane_id].start = start;
+			ddb->plane[pipe][plane_id].end = start + plane_blocks;
 		}
 
 		start += plane_blocks;
@@ -3488,15 +3465,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		/*
 		 * allocation for y_plane part of planar format:
 		 */
-		y_data_rate = plane_y_data_rate[id];
+		y_data_rate = plane_y_data_rate[plane_id];
 
-		y_plane_blocks = y_minimum[id];
+		y_plane_blocks = y_minimum[plane_id];
 		y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
 					total_data_rate);
 
 		if (y_data_rate) {
-			ddb->y_plane[pipe][id].start = start;
-			ddb->y_plane[pipe][id].end = start + y_plane_blocks;
+			ddb->y_plane[pipe][plane_id].start = start;
+			ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
 		}
 
 		start += y_plane_blocks;
@@ -3688,11 +3665,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 			return 0;
 		} else {
 			DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
-			DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
-				      to_intel_crtc(cstate->base.crtc)->pipe,
-				      skl_wm_plane_id(to_intel_plane(pstate->plane)),
-				      res_blocks, ddb_allocation, res_lines);
-
+			DRM_DEBUG_KMS("%s: blocks required = %u/%u, lines required = %u/31\n",
+				      pstate->plane->name, res_blocks, ddb_allocation, res_lines);
 			return -EINVAL;
 		}
 	}
@@ -3719,7 +3693,6 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 	uint16_t ddb_blocks;
 	enum pipe pipe = intel_crtc->pipe;
 	int ret;
-	int i = skl_wm_plane_id(intel_plane);
 
 	if (state)
 		intel_pstate =
@@ -3742,7 +3715,7 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 
 	WARN_ON(!intel_pstate->base.fb);
 
-	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
+	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
 
 	ret = skl_compute_plane_wm(dev_priv,
 				   cstate,
@@ -3805,7 +3778,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 	for_each_intel_plane_mask(&dev_priv->drm,
 				  intel_plane,
 				  cstate->base.plane_mask) {
-		wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
+		wm = &pipe_wm->planes[intel_plane->id];
 
 		for (level = 0; level <= max_level; level++) {
 			ret = skl_compute_wm_level(dev_priv, ddb, cstate,
@@ -3849,7 +3822,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 			const struct skl_plane_wm *wm,
 			const struct skl_ddb_allocation *ddb,
-			int plane)
+			enum plane_id plane_id)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
 	struct drm_device *dev = crtc->dev;
@@ -3858,16 +3831,16 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 	enum pipe pipe = intel_crtc->pipe;
 
 	for (level = 0; level <= max_level; level++) {
-		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
+		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
 				   &wm->wm[level]);
 	}
-	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
+	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
 
-	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
-			    &ddb->plane[pipe][plane]);
-	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
-			    &ddb->y_plane[pipe][plane]);
+	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+			    &ddb->plane[pipe][plane_id]);
+	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
+			    &ddb->y_plane[pipe][plane_id]);
 }
 
 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -3981,17 +3954,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 	struct drm_plane_state *plane_state;
 	struct drm_plane *plane;
 	enum pipe pipe = intel_crtc->pipe;
-	int id;
 
 	WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
 
 	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
-		id = skl_wm_plane_id(to_intel_plane(plane));
+		enum plane_id plane_id = to_intel_plane(plane)->id;
 
-		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
-					&new_ddb->plane[pipe][id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
-					&new_ddb->y_plane[pipe][id]))
+		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
+					&new_ddb->plane[pipe][plane_id]) &&
+		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
+					&new_ddb->y_plane[pipe][plane_id]))
 			continue;
 
 		plane_state = drm_atomic_get_plane_state(state, plane);
@@ -4103,7 +4075,6 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 	const struct intel_plane *intel_plane;
 	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
 	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
-	int id;
 	int i;
 
 	for_each_crtc_in_state(state, crtc, cstate, i) {
@@ -4111,11 +4082,11 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 		enum pipe pipe = intel_crtc->pipe;
 
 		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+			enum plane_id plane_id = intel_plane->id;
 			const struct skl_ddb_entry *old, *new;
 
-			id = skl_wm_plane_id(intel_plane);
-			old = &old_ddb->plane[pipe][id];
-			new = &new_ddb->plane[pipe][id];
+			old = &old_ddb->plane[pipe][plane_id];
+			new = &new_ddb->plane[pipe][plane_id];
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
@@ -4219,14 +4190,16 @@ static void skl_update_wm(struct intel_crtc *intel_crtc)
 	 * their watermarks updated once we update their planes.
 	 */
 	if (intel_crtc->base.state->active_changed) {
-		int plane;
-
-		for_each_universal_plane(dev_priv, pipe, plane)
-			skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
-					   &results->ddb, plane);
+		enum plane_id plane_id;
 
-		skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
-				    &results->ddb);
+		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+			if (plane_id != PLANE_CURSOR)
+				skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane_id],
+						   &results->ddb, plane_id);
+			else
+				skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[plane_id],
+						    &results->ddb);
+		}
 	}
 
 	skl_copy_wm_for_pipe(hw_vals, results, pipe);
@@ -4323,32 +4296,29 @@ static inline void skl_wm_level_from_reg_val(uint32_t val,
 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 			      struct skl_pipe_wm *out)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_plane *intel_plane;
-	struct skl_plane_wm *wm;
 	enum pipe pipe = intel_crtc->pipe;
-	int level, id, max_level;
+	int level, max_level;
+	enum plane_id plane_id;
 	uint32_t val;
 
 	max_level = ilk_wm_max_level(dev_priv);
 
-	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-		id = skl_wm_plane_id(intel_plane);
-		wm = &out->planes[id];
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		struct skl_plane_wm *wm = &out->planes[plane_id];
 
 		for (level = 0; level <= max_level; level++) {
-			if (id != PLANE_CURSOR)
-				val = I915_READ(PLANE_WM(pipe, id, level));
+			if (plane_id != PLANE_CURSOR)
+				val = I915_READ(PLANE_WM(pipe, plane_id, level));
 			else
 				val = I915_READ(CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
 		}
 
-		if (id != PLANE_CURSOR)
-			val = I915_READ(PLANE_WM_TRANS(pipe, id));
+		if (plane_id != PLANE_CURSOR)
+			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
 		else
 			val = I915_READ(CUR_WM_TRANS(pipe));
 
-- 
2.7.4

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Re: [PATCH v3 4/9] drm/i915: Use enum plane_id in SKL wm code

[Paulo Zanoni]

Em Qua, 2016-11-09 às 17:03 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Nuke skl_wm_plane_id() and just use the new intel_plane->id.
> 
> v2: Convert skl_write_plane_wm() as well
> v3: Convert skl_pipe_wm_get_hw_state() correctly

In general, I really like the fact that we unified plane/id/i into just
plane_id.

In general, I dislike the fact that many new lines go past 80 columns
now :).

A few comments follow:

> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Lyude <cpaul@redhat.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_drv.h |   2 +-
>  drivers/gpu/drm/i915/intel_pm.c  | 180 ++++++++++++++++-------------
> ----------
>  2 files changed, 76 insertions(+), 106 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index a3c696d8bf93..6a4cd6edafa5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1751,7 +1751,7 @@ void skl_write_cursor_wm(struct intel_crtc
> *intel_crtc,
>  void skl_write_plane_wm(struct intel_crtc *intel_crtc,
>  			const struct skl_plane_wm *wm,
>  			const struct skl_ddb_allocation *ddb,
> -			int plane);
> +			enum plane_id plane_id);
>  uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
> *pipe_config);
>  bool ilk_disable_lp_wm(struct drm_device *dev);
>  int sanitize_rc6_option(struct drm_i915_private *dev_priv, int
> enable_rc6);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 88e28c989b9c..bae7eea6de16 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2863,28 +2863,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
>  #define SKL_SAGV_BLOCK_TIME	30 /* µs */
>  
>  /*
> - * Return the index of a plane in the SKL DDB and wm result
> arrays.  Primary
> - * plane is always in slot 0, cursor is always in slot
> I915_MAX_PLANES-1, and
> - * other universal planes are in indices 1..n.  Note that this may
> leave unused
> - * indices between the top "sprite" plane and the cursor.
> - */
> -static int
> -skl_wm_plane_id(const struct intel_plane *plane)
> -{
> -	switch (plane->base.type) {
> -	case DRM_PLANE_TYPE_PRIMARY:
> -		return 0;
> -	case DRM_PLANE_TYPE_CURSOR:
> -		return PLANE_CURSOR;
> -	case DRM_PLANE_TYPE_OVERLAY:
> -		return plane->plane + 1;
> -	default:
> -		MISSING_CASE(plane->base.type);
> -		return plane->plane;
> -	}
> -}
> -
> -/*
>   * FIXME: We still don't have the proper code detect if we need to
> apply the WA,
>   * so assume we'll always need it in order to avoid underruns.
>   */
> @@ -3022,7 +3000,6 @@ bool intel_can_enable_sagv(struct
> drm_atomic_state *state)
>  	struct intel_crtc *crtc;
>  	struct intel_plane *plane;
>  	struct intel_crtc_state *cstate;
> -	struct skl_plane_wm *wm;
>  	enum pipe pipe;
>  	int level, latency;
>  
> @@ -3049,7 +3026,8 @@ bool intel_can_enable_sagv(struct
> drm_atomic_state *state)
>  		return false;
>  
>  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> -		wm = &cstate-
> >wm.skl.optimal.planes[skl_wm_plane_id(plane)];
> +		struct skl_plane_wm *wm =
> +			&cstate->wm.skl.optimal.planes[plane->id];
>  
>  		/* Skip this plane if it's not enabled */
>  		if (!wm->wm[0].plane_en)
> @@ -3148,28 +3126,28 @@ static void skl_ddb_entry_init_from_hw(struct
> skl_ddb_entry *entry, u32 reg)
>  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>  			  struct skl_ddb_allocation *ddb /* out */)
>  {
> -	enum pipe pipe;
> -	int plane;
> +	struct intel_crtc *crtc;
>  	u32 val;
>  
>  	memset(ddb, 0, sizeof(*ddb));
>  
> -	for_each_pipe(dev_priv, pipe) {
> +	for_each_intel_crtc(&dev_priv->drm, crtc) {
>  		enum intel_display_power_domain power_domain;
> +		enum plane_id plane_id;
> +		enum pipe pipe = crtc->pipe;
>  
>  		power_domain = POWER_DOMAIN_PIPE(pipe);
>  		if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
>  			continue;
>  
> -		for_each_universal_plane(dev_priv, pipe, plane) {
> -			val = I915_READ(PLANE_BUF_CFG(pipe, plane));
> -			skl_ddb_entry_init_from_hw(&ddb-
> >plane[pipe][plane],
> -						   val);
> -		}
> +		for_each_plane_id_on_crtc(crtc, plane_id) {
> +			if (plane_id != PLANE_CURSOR)
> +				val = I915_READ(PLANE_BUF_CFG(pipe,
> plane_id));
> +			else
> +				val = I915_READ(CUR_BUF_CFG(pipe));
>  
> -		val = I915_READ(CUR_BUF_CFG(pipe));
> -		skl_ddb_entry_init_from_hw(&ddb-
> >plane[pipe][PLANE_CURSOR],
> -					   val);
> +			skl_ddb_entry_init_from_hw(&ddb-
> >plane[pipe][plane_id], val);
> +		}
>  
>  		intel_display_power_put(dev_priv, power_domain);
>  	}
> @@ -3270,30 +3248,30 @@ skl_get_total_relative_data_rate(struct
> intel_crtc_state *intel_cstate,
>  	struct drm_crtc_state *cstate = &intel_cstate->base;
>  	struct drm_atomic_state *state = cstate->state;
>  	struct drm_plane *plane;
> -	const struct intel_plane *intel_plane;
>  	const struct drm_plane_state *pstate;
> -	unsigned int rate, total_data_rate = 0;
> -	int id;
> +	unsigned int total_data_rate = 0;
>  
>  	if (WARN_ON(!state))
>  		return 0;
>  
>  	/* Calculate and cache data rate for each plane */
>  	drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
> cstate) {
> -		id = skl_wm_plane_id(to_intel_plane(plane));
> -		intel_plane = to_intel_plane(plane);
> +		enum plane_id plane_id = to_intel_plane(plane)->id;
> +		unsigned int rate;
> +
> +		/* FIXME cursor shouldn't be here no? */

No, because skl_plane_relative_data_rate() returns 0 for the cursor.
Not that I like the current design, but I think the FIXME can make
things even more confusing. I see 3 options: (i) just remove the FIXME;
(ii) add a comment explaining why we don't check for the cursor; (iii)
just add a check for the cursor here, maybe removing it from
skl_plane_relative_data_rate().


>  
>  		/* packed/uv */
>  		rate = skl_plane_relative_data_rate(intel_cstate,
>  						    pstate, 0);
> -		plane_data_rate[id] = rate;
> +		plane_data_rate[plane_id] = rate;
>  
>  		total_data_rate += rate;
>  
>  		/* y-plane */
>  		rate = skl_plane_relative_data_rate(intel_cstate,
>  						    pstate, 1);
> -		plane_y_data_rate[id] = rate;
> +		plane_y_data_rate[plane_id] = rate;
>  
>  		total_data_rate += rate;
>  	}
> @@ -3372,17 +3350,16 @@ skl_ddb_calc_min(const struct
> intel_crtc_state *cstate, int num_active,
>  	struct drm_plane *plane;
>  
>  	drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
> &cstate->base) {
> -		struct intel_plane *intel_plane =
> to_intel_plane(plane);
> -		int id = skl_wm_plane_id(intel_plane);
> +		enum plane_id plane_id = to_intel_plane(plane)->id;
>  
> -		if (id == PLANE_CURSOR)
> +		if (plane_id == PLANE_CURSOR)
>  			continue;
>  
>  		if (!pstate->visible)
>  			continue;
>  
> -		minimum[id] = skl_ddb_min_alloc(pstate, 0);
> -		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
> +		minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
> +		y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
>  	}
>  
>  	minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
> @@ -3402,8 +3379,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
>  	uint16_t minimum[I915_MAX_PLANES] = {};
>  	uint16_t y_minimum[I915_MAX_PLANES] = {};
>  	unsigned int total_data_rate;
> +	enum plane_id plane_id;
>  	int num_active;
> -	int id, i;
>  	unsigned plane_data_rate[I915_MAX_PLANES] = {};
>  	unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
>  
> @@ -3438,9 +3415,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
>  	 * proportional to the data rate.
>  	 */
>  
> -	for (i = 0; i < I915_MAX_PLANES; i++) {
> -		alloc_size -= minimum[i];
> -		alloc_size -= y_minimum[i];
> +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		alloc_size -= minimum[plane_id];
> +		alloc_size -= y_minimum[plane_id];
>  	}
>  
>  	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end -
> minimum[PLANE_CURSOR];
> @@ -3459,28 +3436,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
>  		return 0;
>  
>  	start = alloc->start;
> -	for (id = 0; id < I915_MAX_PLANES; id++) {
> +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
>  		unsigned int data_rate, y_data_rate;
>  		uint16_t plane_blocks, y_plane_blocks = 0;
>  
> -		if (id == PLANE_CURSOR)
> +		if (plane_id == PLANE_CURSOR)
>  			continue;
>  
> -		data_rate = plane_data_rate[id];
> +		data_rate = plane_data_rate[plane_id];
>  
>  		/*
>  		 * allocation for (packed formats) or (uv-plane part
> of planar format):
>  		 * promote the expression to 64 bits to avoid
> overflowing, the
>  		 * result is < available as data_rate /
> total_data_rate < 1
>  		 */
> -		plane_blocks = minimum[id];
> +		plane_blocks = minimum[plane_id];
>  		plane_blocks += div_u64((uint64_t)alloc_size *
> data_rate,
>  					total_data_rate);
>  
>  		/* Leave disabled planes at (0,0) */
>  		if (data_rate) {
> -			ddb->plane[pipe][id].start = start;
> -			ddb->plane[pipe][id].end = start +
> plane_blocks;
> +			ddb->plane[pipe][plane_id].start = start;
> +			ddb->plane[pipe][plane_id].end = start +
> plane_blocks;
>  		}
>  
>  		start += plane_blocks;
> @@ -3488,15 +3465,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
>  		/*
>  		 * allocation for y_plane part of planar format:
>  		 */
> -		y_data_rate = plane_y_data_rate[id];
> +		y_data_rate = plane_y_data_rate[plane_id];
>  
> -		y_plane_blocks = y_minimum[id];
> +		y_plane_blocks = y_minimum[plane_id];
>  		y_plane_blocks += div_u64((uint64_t)alloc_size *
> y_data_rate,
>  					total_data_rate);
>  
>  		if (y_data_rate) {
> -			ddb->y_plane[pipe][id].start = start;
> -			ddb->y_plane[pipe][id].end = start +
> y_plane_blocks;
> +			ddb->y_plane[pipe][plane_id].start = start;
> +			ddb->y_plane[pipe][plane_id].end = start +
> y_plane_blocks;
>  		}
>  
>  		start += y_plane_blocks;
> @@ -3688,11 +3665,8 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
>  			return 0;
>  		} else {
>  			DRM_DEBUG_KMS("Requested display
> configuration exceeds system watermark limitations\n");
> -			DRM_DEBUG_KMS("Plane %d.%d: blocks required
> = %u/%u, lines required = %u/31\n",
> -				      to_intel_crtc(cstate-
> >base.crtc)->pipe,
> -				      skl_wm_plane_id(to_intel_plane
> (pstate->plane)),
> -				      res_blocks, ddb_allocation,
> res_lines);
> -
> +			DRM_DEBUG_KMS("%s: blocks required = %u/%u,
> lines required = %u/31\n",
> +				      pstate->plane->name,
> res_blocks, ddb_allocation, res_lines);

Feels like this belongs to a separate patch...

Can't we keep the "Plane" word here? Or maybe, why not do like the
other debug prints we have and do [PLANE:%d:%s]?

Everything else looks correct. With the comments addressed:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>  			return -EINVAL;
>  		}
>  	}
> @@ -3719,7 +3693,6 @@ skl_compute_wm_level(const struct
> drm_i915_private *dev_priv,
>  	uint16_t ddb_blocks;
>  	enum pipe pipe = intel_crtc->pipe;
>  	int ret;
> -	int i = skl_wm_plane_id(intel_plane);
>  
>  	if (state)
>  		intel_pstate =
> @@ -3742,7 +3715,7 @@ skl_compute_wm_level(const struct
> drm_i915_private *dev_priv,
>  
>  	WARN_ON(!intel_pstate->base.fb);
>  
> -	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
> +	ddb_blocks = skl_ddb_entry_size(&ddb-
> >plane[pipe][intel_plane->id]);
>  
>  	ret = skl_compute_plane_wm(dev_priv,
>  				   cstate,
> @@ -3805,7 +3778,7 @@ static int skl_build_pipe_wm(struct
> intel_crtc_state *cstate,
>  	for_each_intel_plane_mask(&dev_priv->drm,
>  				  intel_plane,
>  				  cstate->base.plane_mask) {
> -		wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
> +		wm = &pipe_wm->planes[intel_plane->id];
>  
>  		for (level = 0; level <= max_level; level++) {
>  			ret = skl_compute_wm_level(dev_priv, ddb,
> cstate,
> @@ -3849,7 +3822,7 @@ static void skl_write_wm_level(struct
> drm_i915_private *dev_priv,
>  void skl_write_plane_wm(struct intel_crtc *intel_crtc,
>  			const struct skl_plane_wm *wm,
>  			const struct skl_ddb_allocation *ddb,
> -			int plane)
> +			enum plane_id plane_id)
>  {
>  	struct drm_crtc *crtc = &intel_crtc->base;
>  	struct drm_device *dev = crtc->dev;
> @@ -3858,16 +3831,16 @@ void skl_write_plane_wm(struct intel_crtc
> *intel_crtc,
>  	enum pipe pipe = intel_crtc->pipe;
>  
>  	for (level = 0; level <= max_level; level++) {
> -		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane,
> level),
> +		skl_write_wm_level(dev_priv, PLANE_WM(pipe,
> plane_id, level),
>  				   &wm->wm[level]);
>  	}
> -	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
> +	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
>  			   &wm->trans_wm);
>  
> -	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
> -			    &ddb->plane[pipe][plane]);
> -	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe,
> plane),
> -			    &ddb->y_plane[pipe][plane]);
> +	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> +			    &ddb->plane[pipe][plane_id]);
> +	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe,
> plane_id),
> +			    &ddb->y_plane[pipe][plane_id]);
>  }
>  
>  void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> @@ -3981,17 +3954,16 @@ skl_ddb_add_affected_planes(struct
> intel_crtc_state *cstate)
>  	struct drm_plane_state *plane_state;
>  	struct drm_plane *plane;
>  	enum pipe pipe = intel_crtc->pipe;
> -	int id;
>  
>  	WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
>  
>  	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) 
> {
> -		id = skl_wm_plane_id(to_intel_plane(plane));
> +		enum plane_id plane_id = to_intel_plane(plane)->id;
>  
> -		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
> -					&new_ddb->plane[pipe][id])
> &&
> -		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
> -					&new_ddb-
> >y_plane[pipe][id]))
> +		if (skl_ddb_entry_equal(&cur_ddb-
> >plane[pipe][plane_id],
> +					&new_ddb-
> >plane[pipe][plane_id]) &&
> +		    skl_ddb_entry_equal(&cur_ddb-
> >y_plane[pipe][plane_id],
> +					&new_ddb-
> >y_plane[pipe][plane_id]))
>  			continue;
>  
>  		plane_state = drm_atomic_get_plane_state(state,
> plane);
> @@ -4103,7 +4075,6 @@ skl_print_wm_changes(const struct
> drm_atomic_state *state)
>  	const struct intel_plane *intel_plane;
>  	const struct skl_ddb_allocation *old_ddb = &dev_priv-
> >wm.skl_hw.ddb;
>  	const struct skl_ddb_allocation *new_ddb = &intel_state-
> >wm_results.ddb;
> -	int id;
>  	int i;
>  
>  	for_each_crtc_in_state(state, crtc, cstate, i) {
> @@ -4111,11 +4082,11 @@ skl_print_wm_changes(const struct
> drm_atomic_state *state)
>  		enum pipe pipe = intel_crtc->pipe;
>  
>  		for_each_intel_plane_on_crtc(dev, intel_crtc,
> intel_plane) {
> +			enum plane_id plane_id = intel_plane->id;
>  			const struct skl_ddb_entry *old, *new;
>  
> -			id = skl_wm_plane_id(intel_plane);
> -			old = &old_ddb->plane[pipe][id];
> -			new = &new_ddb->plane[pipe][id];
> +			old = &old_ddb->plane[pipe][plane_id];
> +			new = &new_ddb->plane[pipe][plane_id];
>  
>  			if (skl_ddb_entry_equal(old, new))
>  				continue;
> @@ -4219,14 +4190,16 @@ static void skl_update_wm(struct intel_crtc
> *intel_crtc)
>  	 * their watermarks updated once we update their planes.
>  	 */
>  	if (intel_crtc->base.state->active_changed) {
> -		int plane;
> -
> -		for_each_universal_plane(dev_priv, pipe, plane)
> -			skl_write_plane_wm(intel_crtc, &pipe_wm-
> >planes[plane],
> -					   &results->ddb, plane);
> +		enum plane_id plane_id;
>  
> -		skl_write_cursor_wm(intel_crtc, &pipe_wm-
> >planes[PLANE_CURSOR],
> -				    &results->ddb);
> +		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +			if (plane_id != PLANE_CURSOR)
> +				skl_write_plane_wm(intel_crtc,
> &pipe_wm->planes[plane_id],
> +						   &results->ddb,
> plane_id);
> +			else
> +				skl_write_cursor_wm(intel_crtc,
> &pipe_wm->planes[plane_id],
> +						    &results->ddb);
> +		}
>  	}
>  
>  	skl_copy_wm_for_pipe(hw_vals, results, pipe);
> @@ -4323,32 +4296,29 @@ static inline void
> skl_wm_level_from_reg_val(uint32_t val,
>  void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
>  			      struct skl_pipe_wm *out)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct intel_plane *intel_plane;
> -	struct skl_plane_wm *wm;
>  	enum pipe pipe = intel_crtc->pipe;
> -	int level, id, max_level;
> +	int level, max_level;
> +	enum plane_id plane_id;
>  	uint32_t val;
>  
>  	max_level = ilk_wm_max_level(dev_priv);
>  
> -	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> -		id = skl_wm_plane_id(intel_plane);
> -		wm = &out->planes[id];
> +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		struct skl_plane_wm *wm = &out->planes[plane_id];
>  
>  		for (level = 0; level <= max_level; level++) {
> -			if (id != PLANE_CURSOR)
> -				val = I915_READ(PLANE_WM(pipe, id,
> level));
> +			if (plane_id != PLANE_CURSOR)
> +				val = I915_READ(PLANE_WM(pipe,
> plane_id, level));
>  			else
>  				val = I915_READ(CUR_WM(pipe,
> level));
>  
>  			skl_wm_level_from_reg_val(val, &wm-
> >wm[level]);
>  		}
>  
> -		if (id != PLANE_CURSOR)
> -			val = I915_READ(PLANE_WM_TRANS(pipe, id));
> +		if (plane_id != PLANE_CURSOR)
> +			val = I915_READ(PLANE_WM_TRANS(pipe,
> plane_id));
>  		else
>  			val = I915_READ(CUR_WM_TRANS(pipe));
>  
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Re: [PATCH v3 4/9] drm/i915: Use enum plane_id in SKL wm code

[Ville Syrjälä]

On Thu, Nov 17, 2016 at 05:12:13PM -0200, Paulo Zanoni wrote:
> Em Qua, 2016-11-09 às 17:03 +0200, ville.syrjala@linux.intel.com
> escreveu:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Nuke skl_wm_plane_id() and just use the new intel_plane->id.
> > 
> > v2: Convert skl_write_plane_wm() as well
> > v3: Convert skl_pipe_wm_get_hw_state() correctly
> 
> In general, I really like the fact that we unified plane/id/i into just
> plane_id.
> 
> In general, I dislike the fact that many new lines go past 80 columns
> now :).
> 
> A few comments follow:
> 
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Lyude <cpaul@redhat.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_drv.h |   2 +-
> >  drivers/gpu/drm/i915/intel_pm.c  | 180 ++++++++++++++++-------------
> > ----------
> >  2 files changed, 76 insertions(+), 106 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index a3c696d8bf93..6a4cd6edafa5 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1751,7 +1751,7 @@ void skl_write_cursor_wm(struct intel_crtc
> > *intel_crtc,
> >  void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> >  			const struct skl_plane_wm *wm,
> >  			const struct skl_ddb_allocation *ddb,
> > -			int plane);
> > +			enum plane_id plane_id);
> >  uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
> > *pipe_config);
> >  bool ilk_disable_lp_wm(struct drm_device *dev);
> >  int sanitize_rc6_option(struct drm_i915_private *dev_priv, int
> > enable_rc6);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 88e28c989b9c..bae7eea6de16 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2863,28 +2863,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
> >  #define SKL_SAGV_BLOCK_TIME	30 /* µs */
> >  
> >  /*
> > - * Return the index of a plane in the SKL DDB and wm result
> > arrays.  Primary
> > - * plane is always in slot 0, cursor is always in slot
> > I915_MAX_PLANES-1, and
> > - * other universal planes are in indices 1..n.  Note that this may
> > leave unused
> > - * indices between the top "sprite" plane and the cursor.
> > - */
> > -static int
> > -skl_wm_plane_id(const struct intel_plane *plane)
> > -{
> > -	switch (plane->base.type) {
> > -	case DRM_PLANE_TYPE_PRIMARY:
> > -		return 0;
> > -	case DRM_PLANE_TYPE_CURSOR:
> > -		return PLANE_CURSOR;
> > -	case DRM_PLANE_TYPE_OVERLAY:
> > -		return plane->plane + 1;
> > -	default:
> > -		MISSING_CASE(plane->base.type);
> > -		return plane->plane;
> > -	}
> > -}
> > -
> > -/*
> >   * FIXME: We still don't have the proper code detect if we need to
> > apply the WA,
> >   * so assume we'll always need it in order to avoid underruns.
> >   */
> > @@ -3022,7 +3000,6 @@ bool intel_can_enable_sagv(struct
> > drm_atomic_state *state)
> >  	struct intel_crtc *crtc;
> >  	struct intel_plane *plane;
> >  	struct intel_crtc_state *cstate;
> > -	struct skl_plane_wm *wm;
> >  	enum pipe pipe;
> >  	int level, latency;
> >  
> > @@ -3049,7 +3026,8 @@ bool intel_can_enable_sagv(struct
> > drm_atomic_state *state)
> >  		return false;
> >  
> >  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > -		wm = &cstate-
> > >wm.skl.optimal.planes[skl_wm_plane_id(plane)];
> > +		struct skl_plane_wm *wm =
> > +			&cstate->wm.skl.optimal.planes[plane->id];
> >  
> >  		/* Skip this plane if it's not enabled */
> >  		if (!wm->wm[0].plane_en)
> > @@ -3148,28 +3126,28 @@ static void skl_ddb_entry_init_from_hw(struct
> > skl_ddb_entry *entry, u32 reg)
> >  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> >  			  struct skl_ddb_allocation *ddb /* out */)
> >  {
> > -	enum pipe pipe;
> > -	int plane;
> > +	struct intel_crtc *crtc;
> >  	u32 val;
> >  
> >  	memset(ddb, 0, sizeof(*ddb));
> >  
> > -	for_each_pipe(dev_priv, pipe) {
> > +	for_each_intel_crtc(&dev_priv->drm, crtc) {
> >  		enum intel_display_power_domain power_domain;
> > +		enum plane_id plane_id;
> > +		enum pipe pipe = crtc->pipe;
> >  
> >  		power_domain = POWER_DOMAIN_PIPE(pipe);
> >  		if (!intel_display_power_get_if_enabled(dev_priv,
> > power_domain))
> >  			continue;
> >  
> > -		for_each_universal_plane(dev_priv, pipe, plane) {
> > -			val = I915_READ(PLANE_BUF_CFG(pipe, plane));
> > -			skl_ddb_entry_init_from_hw(&ddb-
> > >plane[pipe][plane],
> > -						   val);
> > -		}
> > +		for_each_plane_id_on_crtc(crtc, plane_id) {
> > +			if (plane_id != PLANE_CURSOR)
> > +				val = I915_READ(PLANE_BUF_CFG(pipe,
> > plane_id));
> > +			else
> > +				val = I915_READ(CUR_BUF_CFG(pipe));
> >  
> > -		val = I915_READ(CUR_BUF_CFG(pipe));
> > -		skl_ddb_entry_init_from_hw(&ddb-
> > >plane[pipe][PLANE_CURSOR],
> > -					   val);
> > +			skl_ddb_entry_init_from_hw(&ddb-
> > >plane[pipe][plane_id], val);
> > +		}
> >  
> >  		intel_display_power_put(dev_priv, power_domain);
> >  	}
> > @@ -3270,30 +3248,30 @@ skl_get_total_relative_data_rate(struct
> > intel_crtc_state *intel_cstate,
> >  	struct drm_crtc_state *cstate = &intel_cstate->base;
> >  	struct drm_atomic_state *state = cstate->state;
> >  	struct drm_plane *plane;
> > -	const struct intel_plane *intel_plane;
> >  	const struct drm_plane_state *pstate;
> > -	unsigned int rate, total_data_rate = 0;
> > -	int id;
> > +	unsigned int total_data_rate = 0;
> >  
> >  	if (WARN_ON(!state))
> >  		return 0;
> >  
> >  	/* Calculate and cache data rate for each plane */
> >  	drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
> > cstate) {
> > -		id = skl_wm_plane_id(to_intel_plane(plane));
> > -		intel_plane = to_intel_plane(plane);
> > +		enum plane_id plane_id = to_intel_plane(plane)->id;
> > +		unsigned int rate;
> > +
> > +		/* FIXME cursor shouldn't be here no? */
> 
> No, because skl_plane_relative_data_rate() returns 0 for the cursor.
> Not that I like the current design, but I think the FIXME can make
> things even more confusing. I see 3 options: (i) just remove the FIXME;
> (ii) add a comment explaining why we don't check for the cursor; (iii)
> just add a check for the cursor here, maybe removing it from
> skl_plane_relative_data_rate().

Should probably made explicit here as IIRC it's explicit in the place
where this gets compared to the per-plane rate.

> 
> 
> >  
> >  		/* packed/uv */
> >  		rate = skl_plane_relative_data_rate(intel_cstate,
> >  						    pstate, 0);
> > -		plane_data_rate[id] = rate;
> > +		plane_data_rate[plane_id] = rate;
> >  
> >  		total_data_rate += rate;
> >  
> >  		/* y-plane */
> >  		rate = skl_plane_relative_data_rate(intel_cstate,
> >  						    pstate, 1);
> > -		plane_y_data_rate[id] = rate;
> > +		plane_y_data_rate[plane_id] = rate;
> >  
> >  		total_data_rate += rate;
> >  	}
> > @@ -3372,17 +3350,16 @@ skl_ddb_calc_min(const struct
> > intel_crtc_state *cstate, int num_active,
> >  	struct drm_plane *plane;
> >  
> >  	drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
> > &cstate->base) {
> > -		struct intel_plane *intel_plane =
> > to_intel_plane(plane);
> > -		int id = skl_wm_plane_id(intel_plane);
> > +		enum plane_id plane_id = to_intel_plane(plane)->id;
> >  
> > -		if (id == PLANE_CURSOR)
> > +		if (plane_id == PLANE_CURSOR)
> >  			continue;
> >  
> >  		if (!pstate->visible)
> >  			continue;
> >  
> > -		minimum[id] = skl_ddb_min_alloc(pstate, 0);
> > -		y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
> > +		minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
> > +		y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
> >  	}
> >  
> >  	minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
> > @@ -3402,8 +3379,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> >  	uint16_t minimum[I915_MAX_PLANES] = {};
> >  	uint16_t y_minimum[I915_MAX_PLANES] = {};
> >  	unsigned int total_data_rate;
> > +	enum plane_id plane_id;
> >  	int num_active;
> > -	int id, i;
> >  	unsigned plane_data_rate[I915_MAX_PLANES] = {};
> >  	unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
> >  
> > @@ -3438,9 +3415,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> >  	 * proportional to the data rate.
> >  	 */
> >  
> > -	for (i = 0; i < I915_MAX_PLANES; i++) {
> > -		alloc_size -= minimum[i];
> > -		alloc_size -= y_minimum[i];
> > +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > +		alloc_size -= minimum[plane_id];
> > +		alloc_size -= y_minimum[plane_id];
> >  	}
> >  
> >  	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end -
> > minimum[PLANE_CURSOR];
> > @@ -3459,28 +3436,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> >  		return 0;
> >  
> >  	start = alloc->start;
> > -	for (id = 0; id < I915_MAX_PLANES; id++) {
> > +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> >  		unsigned int data_rate, y_data_rate;
> >  		uint16_t plane_blocks, y_plane_blocks = 0;
> >  
> > -		if (id == PLANE_CURSOR)
> > +		if (plane_id == PLANE_CURSOR)
> >  			continue;
> >  
> > -		data_rate = plane_data_rate[id];
> > +		data_rate = plane_data_rate[plane_id];
> >  
> >  		/*
> >  		 * allocation for (packed formats) or (uv-plane part
> > of planar format):
> >  		 * promote the expression to 64 bits to avoid
> > overflowing, the
> >  		 * result is < available as data_rate /
> > total_data_rate < 1
> >  		 */
> > -		plane_blocks = minimum[id];
> > +		plane_blocks = minimum[plane_id];
> >  		plane_blocks += div_u64((uint64_t)alloc_size *
> > data_rate,
> >  					total_data_rate);
> >  
> >  		/* Leave disabled planes at (0,0) */
> >  		if (data_rate) {
> > -			ddb->plane[pipe][id].start = start;
> > -			ddb->plane[pipe][id].end = start +
> > plane_blocks;
> > +			ddb->plane[pipe][plane_id].start = start;
> > +			ddb->plane[pipe][plane_id].end = start +
> > plane_blocks;
> >  		}
> >  
> >  		start += plane_blocks;
> > @@ -3488,15 +3465,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> >  		/*
> >  		 * allocation for y_plane part of planar format:
> >  		 */
> > -		y_data_rate = plane_y_data_rate[id];
> > +		y_data_rate = plane_y_data_rate[plane_id];
> >  
> > -		y_plane_blocks = y_minimum[id];
> > +		y_plane_blocks = y_minimum[plane_id];
> >  		y_plane_blocks += div_u64((uint64_t)alloc_size *
> > y_data_rate,
> >  					total_data_rate);
> >  
> >  		if (y_data_rate) {
> > -			ddb->y_plane[pipe][id].start = start;
> > -			ddb->y_plane[pipe][id].end = start +
> > y_plane_blocks;
> > +			ddb->y_plane[pipe][plane_id].start = start;
> > +			ddb->y_plane[pipe][plane_id].end = start +
> > y_plane_blocks;
> >  		}
> >  
> >  		start += y_plane_blocks;
> > @@ -3688,11 +3665,8 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> >  			return 0;
> >  		} else {
> >  			DRM_DEBUG_KMS("Requested display
> > configuration exceeds system watermark limitations\n");
> > -			DRM_DEBUG_KMS("Plane %d.%d: blocks required
> > = %u/%u, lines required = %u/31\n",
> > -				      to_intel_crtc(cstate-
> > >base.crtc)->pipe,
> > -				      skl_wm_plane_id(to_intel_plane
> > (pstate->plane)),
> > -				      res_blocks, ddb_allocation,
> > res_lines);
> > -
> > +			DRM_DEBUG_KMS("%s: blocks required = %u/%u,
> > lines required = %u/31\n",
> > +				      pstate->plane->name,
> > res_blocks, ddb_allocation, res_lines);
> 
> Feels like this belongs to a separate patch...

I supposed I could split it out into a prep patch. Can't do it as
a fixup patch since I'd rather nuke skl_wm_plane_id() in one go.

> 
> Can't we keep the "Plane" word here? Or maybe, why not do like the
> other debug prints we have and do [PLANE:%d:%s]?

The plane name already has "plane" in it. So nak on the idea of keeping
"Plane" here, but I'm fine with converting to the standard [PLANE:...]
notation.

> 
> Everything else looks correct. With the comments addressed:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> >  			return -EINVAL;
> >  		}
> >  	}
> > @@ -3719,7 +3693,6 @@ skl_compute_wm_level(const struct
> > drm_i915_private *dev_priv,
> >  	uint16_t ddb_blocks;
> >  	enum pipe pipe = intel_crtc->pipe;
> >  	int ret;
> > -	int i = skl_wm_plane_id(intel_plane);
> >  
> >  	if (state)
> >  		intel_pstate =
> > @@ -3742,7 +3715,7 @@ skl_compute_wm_level(const struct
> > drm_i915_private *dev_priv,
> >  
> >  	WARN_ON(!intel_pstate->base.fb);
> >  
> > -	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
> > +	ddb_blocks = skl_ddb_entry_size(&ddb-
> > >plane[pipe][intel_plane->id]);
> >  
> >  	ret = skl_compute_plane_wm(dev_priv,
> >  				   cstate,
> > @@ -3805,7 +3778,7 @@ static int skl_build_pipe_wm(struct
> > intel_crtc_state *cstate,
> >  	for_each_intel_plane_mask(&dev_priv->drm,
> >  				  intel_plane,
> >  				  cstate->base.plane_mask) {
> > -		wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
> > +		wm = &pipe_wm->planes[intel_plane->id];
> >  
> >  		for (level = 0; level <= max_level; level++) {
> >  			ret = skl_compute_wm_level(dev_priv, ddb,
> > cstate,
> > @@ -3849,7 +3822,7 @@ static void skl_write_wm_level(struct
> > drm_i915_private *dev_priv,
> >  void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> >  			const struct skl_plane_wm *wm,
> >  			const struct skl_ddb_allocation *ddb,
> > -			int plane)
> > +			enum plane_id plane_id)
> >  {
> >  	struct drm_crtc *crtc = &intel_crtc->base;
> >  	struct drm_device *dev = crtc->dev;
> > @@ -3858,16 +3831,16 @@ void skl_write_plane_wm(struct intel_crtc
> > *intel_crtc,
> >  	enum pipe pipe = intel_crtc->pipe;
> >  
> >  	for (level = 0; level <= max_level; level++) {
> > -		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane,
> > level),
> > +		skl_write_wm_level(dev_priv, PLANE_WM(pipe,
> > plane_id, level),
> >  				   &wm->wm[level]);
> >  	}
> > -	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
> > +	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> >  			   &wm->trans_wm);
> >  
> > -	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
> > -			    &ddb->plane[pipe][plane]);
> > -	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe,
> > plane),
> > -			    &ddb->y_plane[pipe][plane]);
> > +	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> > +			    &ddb->plane[pipe][plane_id]);
> > +	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe,
> > plane_id),
> > +			    &ddb->y_plane[pipe][plane_id]);
> >  }
> >  
> >  void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> > @@ -3981,17 +3954,16 @@ skl_ddb_add_affected_planes(struct
> > intel_crtc_state *cstate)
> >  	struct drm_plane_state *plane_state;
> >  	struct drm_plane *plane;
> >  	enum pipe pipe = intel_crtc->pipe;
> > -	int id;
> >  
> >  	WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
> >  
> >  	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) 
> > {
> > -		id = skl_wm_plane_id(to_intel_plane(plane));
> > +		enum plane_id plane_id = to_intel_plane(plane)->id;
> >  
> > -		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
> > -					&new_ddb->plane[pipe][id])
> > &&
> > -		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
> > -					&new_ddb-
> > >y_plane[pipe][id]))
> > +		if (skl_ddb_entry_equal(&cur_ddb-
> > >plane[pipe][plane_id],
> > +					&new_ddb-
> > >plane[pipe][plane_id]) &&
> > +		    skl_ddb_entry_equal(&cur_ddb-
> > >y_plane[pipe][plane_id],
> > +					&new_ddb-
> > >y_plane[pipe][plane_id]))
> >  			continue;
> >  
> >  		plane_state = drm_atomic_get_plane_state(state,
> > plane);
> > @@ -4103,7 +4075,6 @@ skl_print_wm_changes(const struct
> > drm_atomic_state *state)
> >  	const struct intel_plane *intel_plane;
> >  	const struct skl_ddb_allocation *old_ddb = &dev_priv-
> > >wm.skl_hw.ddb;
> >  	const struct skl_ddb_allocation *new_ddb = &intel_state-
> > >wm_results.ddb;
> > -	int id;
> >  	int i;
> >  
> >  	for_each_crtc_in_state(state, crtc, cstate, i) {
> > @@ -4111,11 +4082,11 @@ skl_print_wm_changes(const struct
> > drm_atomic_state *state)
> >  		enum pipe pipe = intel_crtc->pipe;
> >  
> >  		for_each_intel_plane_on_crtc(dev, intel_crtc,
> > intel_plane) {
> > +			enum plane_id plane_id = intel_plane->id;
> >  			const struct skl_ddb_entry *old, *new;
> >  
> > -			id = skl_wm_plane_id(intel_plane);
> > -			old = &old_ddb->plane[pipe][id];
> > -			new = &new_ddb->plane[pipe][id];
> > +			old = &old_ddb->plane[pipe][plane_id];
> > +			new = &new_ddb->plane[pipe][plane_id];
> >  
> >  			if (skl_ddb_entry_equal(old, new))
> >  				continue;
> > @@ -4219,14 +4190,16 @@ static void skl_update_wm(struct intel_crtc
> > *intel_crtc)
> >  	 * their watermarks updated once we update their planes.
> >  	 */
> >  	if (intel_crtc->base.state->active_changed) {
> > -		int plane;
> > -
> > -		for_each_universal_plane(dev_priv, pipe, plane)
> > -			skl_write_plane_wm(intel_crtc, &pipe_wm-
> > >planes[plane],
> > -					   &results->ddb, plane);
> > +		enum plane_id plane_id;
> >  
> > -		skl_write_cursor_wm(intel_crtc, &pipe_wm-
> > >planes[PLANE_CURSOR],
> > -				    &results->ddb);
> > +		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > +			if (plane_id != PLANE_CURSOR)
> > +				skl_write_plane_wm(intel_crtc,
> > &pipe_wm->planes[plane_id],
> > +						   &results->ddb,
> > plane_id);
> > +			else
> > +				skl_write_cursor_wm(intel_crtc,
> > &pipe_wm->planes[plane_id],
> > +						    &results->ddb);
> > +		}
> >  	}
> >  
> >  	skl_copy_wm_for_pipe(hw_vals, results, pipe);
> > @@ -4323,32 +4296,29 @@ static inline void
> > skl_wm_level_from_reg_val(uint32_t val,
> >  void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
> >  			      struct skl_pipe_wm *out)
> >  {
> > -	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	struct intel_plane *intel_plane;
> > -	struct skl_plane_wm *wm;
> >  	enum pipe pipe = intel_crtc->pipe;
> > -	int level, id, max_level;
> > +	int level, max_level;
> > +	enum plane_id plane_id;
> >  	uint32_t val;
> >  
> >  	max_level = ilk_wm_max_level(dev_priv);
> >  
> > -	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> > -		id = skl_wm_plane_id(intel_plane);
> > -		wm = &out->planes[id];
> > +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > +		struct skl_plane_wm *wm = &out->planes[plane_id];
> >  
> >  		for (level = 0; level <= max_level; level++) {
> > -			if (id != PLANE_CURSOR)
> > -				val = I915_READ(PLANE_WM(pipe, id,
> > level));
> > +			if (plane_id != PLANE_CURSOR)
> > +				val = I915_READ(PLANE_WM(pipe,
> > plane_id, level));
> >  			else
> >  				val = I915_READ(CUR_WM(pipe,
> > level));
> >  
> >  			skl_wm_level_from_reg_val(val, &wm-
> > >wm[level]);
> >  		}
> >  
> > -		if (id != PLANE_CURSOR)
> > -			val = I915_READ(PLANE_WM_TRANS(pipe, id));
> > +		if (plane_id != PLANE_CURSOR)
> > +			val = I915_READ(PLANE_WM_TRANS(pipe,
> > plane_id));
> >  		else
> >  			val = I915_READ(CUR_WM_TRANS(pipe));
> >  

-- 
Ville Syrjälä
Intel OTC
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[PATCH 5/9] drm/i915: Use enum plane_id in SKL plane code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the intel_plane->plane and hardcoded 0 usage in the SKL plane
code with intel_plane->id.

This should make the SKL "primary" and "sprite" code virtually
identical, so the next logical step would likely be dropping one
of the copies.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++------------
 drivers/gpu/drm/i915/intel_sprite.c  | 50 ++++++++++++++++++------------------
 2 files changed, 43 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e3ed5d1fcf0d..95644c8cc568 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3384,9 +3384,10 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_framebuffer *fb = plane_state->base.fb;
+	enum plane_id plane_id = to_intel_plane(plane)->id;
 	const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
 	const struct skl_plane_wm *p_wm =
-		&crtc_state->wm.skl.optimal.planes[0];
+		&crtc_state->wm.skl.optimal.planes[plane_id];
 	int pipe = intel_crtc->pipe;
 	u32 plane_ctl;
 	unsigned int rotation = plane_state->base.rotation;
@@ -3423,32 +3424,32 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
 	intel_crtc->adjusted_y = src_y;
 
 	if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
-		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
+		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane_id);
 
-	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
-	I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
-	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
-	I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
+	I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
+	I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
+	I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
+	I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 
 	if (scaler_id >= 0) {
 		uint32_t ps_ctrl = 0;
 
 		WARN_ON(!dst_w || !dst_h);
-		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
+		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
 			crtc_state->scaler_state.scalers[scaler_id].mode;
 		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
 		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
-		I915_WRITE(PLANE_POS(pipe, 0), 0);
+		I915_WRITE(PLANE_POS(pipe, plane_id), 0);
 	} else {
-		I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
+		I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
 	}
 
-	I915_WRITE(PLANE_SURF(pipe, 0),
+	I915_WRITE(PLANE_SURF(pipe, plane_id),
 		   intel_fb_gtt_offset(fb, rotation) + surf_addr);
 
-	POSTING_READ(PLANE_SURF(pipe, 0));
+	POSTING_READ(PLANE_SURF(pipe, plane_id));
 }
 
 static void skylake_disable_primary_plane(struct drm_plane *primary,
@@ -3458,7 +3459,8 @@ static void skylake_disable_primary_plane(struct drm_plane *primary,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
-	const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0];
+	enum plane_id plane_id = to_intel_plane(primary)->id;
+	const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[plane_id];
 	int pipe = intel_crtc->pipe;
 
 	/*
@@ -3467,11 +3469,11 @@ static void skylake_disable_primary_plane(struct drm_plane *primary,
 	 */
 	if (!crtc->primary->state->visible)
 		skl_write_plane_wm(intel_crtc, p_wm,
-				   &dev_priv->wm.skl_results.ddb, 0);
+				   &dev_priv->wm.skl_results.ddb, plane_id);
 
-	I915_WRITE(PLANE_CTL(pipe, 0), 0);
-	I915_WRITE(PLANE_SURF(pipe, 0), 0);
-	POSTING_READ(PLANE_SURF(pipe, 0));
+	I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
+	I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
+	POSTING_READ(PLANE_SURF(pipe, plane_id));
 }
 
 /* Assume fb object is pinned & idle & fenced and just update base pointers */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 4b44863a07c2..91d47d19f4a9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -203,13 +203,13 @@ skl_update_plane(struct drm_plane *drm_plane,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 	struct drm_framebuffer *fb = plane_state->base.fb;
+	enum plane_id plane_id = intel_plane->id;
 	const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
 	struct drm_crtc *crtc = crtc_state->base.crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	const int pipe = intel_plane->pipe;
-	const int plane = intel_plane->plane + 1;
+	enum pipe pipe = intel_plane->pipe;
 	const struct skl_plane_wm *p_wm =
-		&crtc_state->wm.skl.optimal.planes[plane];
+		&crtc_state->wm.skl.optimal.planes[plane_id];
 	u32 plane_ctl;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->main.offset;
@@ -234,12 +234,12 @@ skl_update_plane(struct drm_plane *drm_plane,
 	plane_ctl |= skl_plane_ctl_rotation(rotation);
 
 	if (wm->dirty_pipes & drm_crtc_mask(crtc))
-		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane);
+		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane_id);
 
 	if (key->flags) {
-		I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
-		I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
-		I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
+		I915_WRITE(PLANE_KEYVAL(pipe, plane_id), key->min_value);
+		I915_WRITE(PLANE_KEYMAX(pipe, plane_id), key->max_value);
+		I915_WRITE(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 	}
 
 	if (key->flags & I915_SET_COLORKEY_DESTINATION)
@@ -253,36 +253,36 @@ skl_update_plane(struct drm_plane *drm_plane,
 	crtc_w--;
 	crtc_h--;
 
-	I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
-	I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
-	I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
+	I915_WRITE(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
+	I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
+	I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 
 	/* program plane scaler */
 	if (plane_state->scaler_id >= 0) {
 		int scaler_id = plane_state->scaler_id;
 		const struct intel_scaler *scaler;
 
-		DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
-			PS_PLANE_SEL(plane));
+		DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane_id,
+			      PS_PLANE_SEL(plane_id));
 
 		scaler = &crtc_state->scaler_state.scalers[scaler_id];
 
 		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
-			   PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode);
+			   PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 			((crtc_w + 1) << 16)|(crtc_h + 1));
 
-		I915_WRITE(PLANE_POS(pipe, plane), 0);
+		I915_WRITE(PLANE_POS(pipe, plane_id), 0);
 	} else {
-		I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
+		I915_WRITE(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	}
 
-	I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
-	I915_WRITE(PLANE_SURF(pipe, plane),
+	I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
+	I915_WRITE(PLANE_SURF(pipe, plane_id),
 		   intel_fb_gtt_offset(fb, rotation) + surf_addr);
-	POSTING_READ(PLANE_SURF(pipe, plane));
+	POSTING_READ(PLANE_SURF(pipe, plane_id));
 }
 
 static void
@@ -292,8 +292,8 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *intel_plane = to_intel_plane(dplane);
 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
-	const int pipe = intel_plane->pipe;
-	const int plane = intel_plane->plane + 1;
+	enum pipe pipe = intel_plane->pipe;
+	enum plane_id plane_id = intel_plane->id;
 
 	/*
 	 * We only populate skl_results on watermark updates, and if the
@@ -301,13 +301,13 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 	 */
 	if (!dplane->state->visible)
 		skl_write_plane_wm(to_intel_crtc(crtc),
-				   &cstate->wm.skl.optimal.planes[plane],
-				   &dev_priv->wm.skl_results.ddb, plane);
+				   &cstate->wm.skl.optimal.planes[plane_id],
+				   &dev_priv->wm.skl_results.ddb, plane_id);
 
-	I915_WRITE(PLANE_CTL(pipe, plane), 0);
+	I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
 
-	I915_WRITE(PLANE_SURF(pipe, plane), 0);
-	POSTING_READ(PLANE_SURF(pipe, plane));
+	I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
+	POSTING_READ(PLANE_SURF(pipe, plane_id));
 }
 
 static void
-- 
2.7.4

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Re: [PATCH 5/9] drm/i915: Use enum plane_id in SKL plane code

[Paulo Zanoni]

Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace the intel_plane->plane and hardcoded 0 usage in the SKL plane
> code with intel_plane->id.
> 
> This should make the SKL "primary" and "sprite" code virtually
> identical, so the next logical step would likely be dropping one
> of the copies.

Something something 80 columns something something. Also, this will
need a rebase, but the idea is sane, so with a bug-free rebase:

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>.

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++------------
>  drivers/gpu/drm/i915/intel_sprite.c  | 50 ++++++++++++++++++------
> ------------
>  2 files changed, 43 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e3ed5d1fcf0d..95644c8cc568 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3384,9 +3384,10 @@ static void
> skylake_update_primary_plane(struct drm_plane *plane,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >base.crtc);
>  	struct drm_framebuffer *fb = plane_state->base.fb;
> +	enum plane_id plane_id = to_intel_plane(plane)->id;
>  	const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
>  	const struct skl_plane_wm *p_wm =
> -		&crtc_state->wm.skl.optimal.planes[0];
> +		&crtc_state->wm.skl.optimal.planes[plane_id];
>  	int pipe = intel_crtc->pipe;
>  	u32 plane_ctl;
>  	unsigned int rotation = plane_state->base.rotation;
> @@ -3423,32 +3424,32 @@ static void
> skylake_update_primary_plane(struct drm_plane *plane,
>  	intel_crtc->adjusted_y = src_y;
>  
>  	if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
> -		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
> +		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb,
> plane_id);
>  
> -	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
> -	I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
> -	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> -	I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
> +	I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
> +	I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) |
> src_x);
> +	I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
> +	I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) |
> src_w);
>  
>  	if (scaler_id >= 0) {
>  		uint32_t ps_ctrl = 0;
>  
>  		WARN_ON(!dst_w || !dst_h);
> -		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
> +		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
>  			crtc_state-
> >scaler_state.scalers[scaler_id].mode;
>  		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
>  		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
>  		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x
> << 16) | dst_y);
>  		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w <<
> 16) | dst_h);
> -		I915_WRITE(PLANE_POS(pipe, 0), 0);
> +		I915_WRITE(PLANE_POS(pipe, plane_id), 0);
>  	} else {
> -		I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) |
> dst_x);
> +		I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16)
> | dst_x);
>  	}
>  
> -	I915_WRITE(PLANE_SURF(pipe, 0),
> +	I915_WRITE(PLANE_SURF(pipe, plane_id),
>  		   intel_fb_gtt_offset(fb, rotation) + surf_addr);
>  
> -	POSTING_READ(PLANE_SURF(pipe, 0));
> +	POSTING_READ(PLANE_SURF(pipe, plane_id));
>  }
>  
>  static void skylake_disable_primary_plane(struct drm_plane *primary,
> @@ -3458,7 +3459,8 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> -	const struct skl_plane_wm *p_wm = &cstate-
> >wm.skl.optimal.planes[0];
> +	enum plane_id plane_id = to_intel_plane(primary)->id;
> +	const struct skl_plane_wm *p_wm = &cstate-
> >wm.skl.optimal.planes[plane_id];
>  	int pipe = intel_crtc->pipe;
>  
>  	/*
> @@ -3467,11 +3469,11 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
>  	 */
>  	if (!crtc->primary->state->visible)
>  		skl_write_plane_wm(intel_crtc, p_wm,
> -				   &dev_priv->wm.skl_results.ddb,
> 0);
> +				   &dev_priv->wm.skl_results.ddb,
> plane_id);
>  
> -	I915_WRITE(PLANE_CTL(pipe, 0), 0);
> -	I915_WRITE(PLANE_SURF(pipe, 0), 0);
> -	POSTING_READ(PLANE_SURF(pipe, 0));
> +	I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
> +	I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
> +	POSTING_READ(PLANE_SURF(pipe, plane_id));
>  }
>  
>  /* Assume fb object is pinned & idle & fenced and just update base
> pointers */
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 4b44863a07c2..91d47d19f4a9 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -203,13 +203,13 @@ skl_update_plane(struct drm_plane *drm_plane,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *intel_plane = to_intel_plane(drm_plane);
>  	struct drm_framebuffer *fb = plane_state->base.fb;
> +	enum plane_id plane_id = intel_plane->id;
>  	const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
>  	struct drm_crtc *crtc = crtc_state->base.crtc;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	const int pipe = intel_plane->pipe;
> -	const int plane = intel_plane->plane + 1;
> +	enum pipe pipe = intel_plane->pipe;
>  	const struct skl_plane_wm *p_wm =
> -		&crtc_state->wm.skl.optimal.planes[plane];
> +		&crtc_state->wm.skl.optimal.planes[plane_id];
>  	u32 plane_ctl;
>  	const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
>  	u32 surf_addr = plane_state->main.offset;
> @@ -234,12 +234,12 @@ skl_update_plane(struct drm_plane *drm_plane,
>  	plane_ctl |= skl_plane_ctl_rotation(rotation);
>  
>  	if (wm->dirty_pipes & drm_crtc_mask(crtc))
> -		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb,
> plane);
> +		skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb,
> plane_id);
>  
>  	if (key->flags) {
> -		I915_WRITE(PLANE_KEYVAL(pipe, plane), key-
> >min_value);
> -		I915_WRITE(PLANE_KEYMAX(pipe, plane), key-
> >max_value);
> -		I915_WRITE(PLANE_KEYMSK(pipe, plane), key-
> >channel_mask);
> +		I915_WRITE(PLANE_KEYVAL(pipe, plane_id), key-
> >min_value);
> +		I915_WRITE(PLANE_KEYMAX(pipe, plane_id), key-
> >max_value);
> +		I915_WRITE(PLANE_KEYMSK(pipe, plane_id), key-
> >channel_mask);
>  	}
>  
>  	if (key->flags & I915_SET_COLORKEY_DESTINATION)
> @@ -253,36 +253,36 @@ skl_update_plane(struct drm_plane *drm_plane,
>  	crtc_w--;
>  	crtc_h--;
>  
> -	I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
> -	I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
> -	I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
> +	I915_WRITE(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
> +	I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
> +	I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) |
> src_w);
>  
>  	/* program plane scaler */
>  	if (plane_state->scaler_id >= 0) {
>  		int scaler_id = plane_state->scaler_id;
>  		const struct intel_scaler *scaler;
>  
> -		DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) =
> 0x%x\n", plane,
> -			PS_PLANE_SEL(plane));
> +		DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) =
> 0x%x\n", plane_id,
> +			      PS_PLANE_SEL(plane_id));
>  
>  		scaler = &crtc_state-
> >scaler_state.scalers[scaler_id];
>  
>  		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
> -			   PS_SCALER_EN | PS_PLANE_SEL(plane) |
> scaler->mode);
> +			   PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
> scaler->mode);
>  		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
>  		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x
> << 16) | crtc_y);
>  		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
>  			((crtc_w + 1) << 16)|(crtc_h + 1));
>  
> -		I915_WRITE(PLANE_POS(pipe, plane), 0);
> +		I915_WRITE(PLANE_POS(pipe, plane_id), 0);
>  	} else {
> -		I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) |
> crtc_x);
> +		I915_WRITE(PLANE_POS(pipe, plane_id), (crtc_y << 16)
> | crtc_x);
>  	}
>  
> -	I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
> -	I915_WRITE(PLANE_SURF(pipe, plane),
> +	I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
> +	I915_WRITE(PLANE_SURF(pipe, plane_id),
>  		   intel_fb_gtt_offset(fb, rotation) + surf_addr);
> -	POSTING_READ(PLANE_SURF(pipe, plane));
> +	POSTING_READ(PLANE_SURF(pipe, plane_id));
>  }
>  
>  static void
> @@ -292,8 +292,8 @@ skl_disable_plane(struct drm_plane *dplane,
> struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *intel_plane = to_intel_plane(dplane);
>  	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> -	const int pipe = intel_plane->pipe;
> -	const int plane = intel_plane->plane + 1;
> +	enum pipe pipe = intel_plane->pipe;
> +	enum plane_id plane_id = intel_plane->id;
>  
>  	/*
>  	 * We only populate skl_results on watermark updates, and if
> the
> @@ -301,13 +301,13 @@ skl_disable_plane(struct drm_plane *dplane,
> struct drm_crtc *crtc)
>  	 */
>  	if (!dplane->state->visible)
>  		skl_write_plane_wm(to_intel_crtc(crtc),
> -				   &cstate-
> >wm.skl.optimal.planes[plane],
> -				   &dev_priv->wm.skl_results.ddb,
> plane);
> +				   &cstate-
> >wm.skl.optimal.planes[plane_id],
> +				   &dev_priv->wm.skl_results.ddb,
> plane_id);
>  
> -	I915_WRITE(PLANE_CTL(pipe, plane), 0);
> +	I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
>  
> -	I915_WRITE(PLANE_SURF(pipe, plane), 0);
> -	POSTING_READ(PLANE_SURF(pipe, plane));
> +	I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
> +	POSTING_READ(PLANE_SURF(pipe, plane_id));
>  }
>  
>  static void
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[PATCH 6/9] drm/i915: Use enum plane_id in VLV/CHV sprite code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use intel_plane->id to derive the VLV/CHV sprite register offsets
instead of abusing plane->plane which is really meant to for
primary planes only.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     | 58 ++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c | 74 ++++++++++++++++++-------------------
 2 files changed, 69 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3361d7ffc63e..9739e97c6263 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5374,18 +5374,21 @@ enum {
 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
 
-#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
-#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
-#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
-#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
-#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
-#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
-#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
-#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
-#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
-#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
-#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
+#define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) \
+	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a), (reg_b))
+
+#define SPCNTR(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane)	_MMIO_VLV_SPR((pipe), (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane)	_MMIO_VLV_SPR((pipe), (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane)	_MMIO_VLV_SPR((pipe), (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPGAMC(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPAGAMC, _SPBGAMC)
 
 /*
  * CHV pipe B sprite CSC
@@ -5394,29 +5397,32 @@ enum {
  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
  */
-#define SPCSCYGOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
-#define SPCSCCBOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
-#define SPCSCCROFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
+#define _MMIO_CHV_SPCSC(plane, reg) \
+	_MMIO(VLV_DISPLAY_BASE + ((plane) - PLANE_SPRITE0) * 0x1000 + (reg))
+
+#define SPCSCYGOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d900)
+#define SPCSCCBOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d904)
+#define SPCSCCROFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d908)
 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
 
-#define SPCSCC01(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
-#define SPCSCC23(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
-#define SPCSCC45(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
-#define SPCSCC67(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
-#define SPCSCC8(sprite)		_MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
+#define SPCSCC01(plane)		_MMIO_CHV_SPCSC(plane, 0x6d90c)
+#define SPCSCC23(plane)		_MMIO_CHV_SPCSC(plane, 0x6d910)
+#define SPCSCC45(plane)		_MMIO_CHV_SPCSC(plane, 0x6d914)
+#define SPCSCC67(plane)		_MMIO_CHV_SPCSC(plane, 0x6d918)
+#define SPCSCC8(plane)		_MMIO_CHV_SPCSC(plane, 0x6d91c)
 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
 
-#define SPCSCYGICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
-#define SPCSCCBICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
-#define SPCSCCRICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
+#define SPCSCYGICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d920)
+#define SPCSCCBICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d924)
+#define SPCSCCRICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d928)
 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
 
-#define SPCSCYGOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
-#define SPCSCCBOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
-#define SPCSCCROCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
+#define SPCSCYGOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d92c)
+#define SPCSCCBOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d930)
+#define SPCSCCROCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d934)
 #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 91d47d19f4a9..a922c6382fc7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -314,7 +314,7 @@ static void
 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
-	int plane = intel_plane->plane;
+	enum plane_id plane_id = intel_plane->id;
 
 	/* Seems RGB data bypasses the CSC always */
 	if (!format_is_yuv(format))
@@ -330,23 +330,23 @@ chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 	 * Cb and Cr apparently come in as signed already, so no
 	 * need for any offset. For Y we need to remove the offset.
 	 */
-	I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
-	I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
-	I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
-
-	I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
-	I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
-	I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
-	I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
-	I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
-
-	I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
-	I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
-	I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
-
-	I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
-	I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
-	I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
+	I915_WRITE(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
+	I915_WRITE(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
+	I915_WRITE(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
+
+	I915_WRITE(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
+	I915_WRITE(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
+	I915_WRITE(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
+	I915_WRITE(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
+	I915_WRITE(SPCSCC8(plane_id), SPCSC_C0(8263));
+
+	I915_WRITE(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
+	I915_WRITE(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
+	I915_WRITE(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
+
+	I915_WRITE(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
+	I915_WRITE(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
+	I915_WRITE(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 }
 
 static void
@@ -358,8 +358,8 @@ vlv_update_plane(struct drm_plane *dplane,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *intel_plane = to_intel_plane(dplane);
 	struct drm_framebuffer *fb = plane_state->base.fb;
-	int pipe = intel_plane->pipe;
-	int plane = intel_plane->plane;
+	enum pipe pipe = intel_plane->pipe;
+	enum plane_id plane_id = intel_plane->id;
 	u32 sprctl;
 	u32 sprsurf_offset, linear_offset;
 	unsigned int rotation = plane_state->base.rotation;
@@ -446,9 +446,9 @@ vlv_update_plane(struct drm_plane *dplane,
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (key->flags) {
-		I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
-		I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
-		I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
+		I915_WRITE(SPKEYMINVAL(pipe, plane_id), key->min_value);
+		I915_WRITE(SPKEYMAXVAL(pipe, plane_id), key->max_value);
+		I915_WRITE(SPKEYMSK(pipe, plane_id), key->channel_mask);
 	}
 
 	if (key->flags & I915_SET_COLORKEY_SOURCE)
@@ -457,21 +457,21 @@ vlv_update_plane(struct drm_plane *dplane,
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 		chv_update_csc(intel_plane, fb->pixel_format);
 
-	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
-	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
+	I915_WRITE(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
+	I915_WRITE(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 
 	if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
-		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
+		I915_WRITE(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 	else
-		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
+		I915_WRITE(SPLINOFF(pipe, plane_id), linear_offset);
 
-	I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
+	I915_WRITE(SPCONSTALPHA(pipe, plane_id), 0);
 
-	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
-	I915_WRITE(SPCNTR(pipe, plane), sprctl);
-	I915_WRITE(SPSURF(pipe, plane),
+	I915_WRITE(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
+	I915_WRITE(SPCNTR(pipe, plane_id), sprctl);
+	I915_WRITE(SPSURF(pipe, plane_id),
 		   intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
-	POSTING_READ(SPSURF(pipe, plane));
+	POSTING_READ(SPSURF(pipe, plane_id));
 }
 
 static void
@@ -480,13 +480,13 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 	struct drm_device *dev = dplane->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *intel_plane = to_intel_plane(dplane);
-	int pipe = intel_plane->pipe;
-	int plane = intel_plane->plane;
+	enum pipe pipe = intel_plane->pipe;
+	enum plane_id plane_id = intel_plane->id;
 
-	I915_WRITE(SPCNTR(pipe, plane), 0);
+	I915_WRITE(SPCNTR(pipe, plane_id), 0);
 
-	I915_WRITE(SPSURF(pipe, plane), 0);
-	POSTING_READ(SPSURF(pipe, plane));
+	I915_WRITE(SPSURF(pipe, plane_id), 0);
+	POSTING_READ(SPSURF(pipe, plane_id));
 }
 
 static void
-- 
2.7.4

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Re: [PATCH 6/9] drm/i915: Use enum plane_id in VLV/CHV sprite code

[Chris Wilson]

On Tue, Nov 08, 2016 at 04:47:16PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use intel_plane->id to derive the VLV/CHV sprite register offsets
> instead of abusing plane->plane which is really meant to for
> primary planes only.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     | 58 ++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_sprite.c | 74 ++++++++++++++++++-------------------
>  2 files changed, 69 insertions(+), 63 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3361d7ffc63e..9739e97c6263 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5374,18 +5374,21 @@ enum {
>  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
>  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
>  
> -#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
> -#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
> -#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
> -#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
> -#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
> -#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> -#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
> -#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
> -#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> -#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
> -#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> -#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
> +#define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) \
> +	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a), (reg_b))

#define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) ({
	typecheck(enum pipe, pipe);
	typecheck(enum plane_id, plane);
	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a), (reg_b))
)}

Does that work?

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH 6/9] drm/i915: Use enum plane_id in VLV/CHV sprite code

[Ville Syrjälä]

On Tue, Nov 08, 2016 at 04:04:23PM +0000, Chris Wilson wrote:
> On Tue, Nov 08, 2016 at 04:47:16PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Use intel_plane->id to derive the VLV/CHV sprite register offsets
> > instead of abusing plane->plane which is really meant to for
> > primary planes only.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h     | 58 ++++++++++++++++-------------
> >  drivers/gpu/drm/i915/intel_sprite.c | 74 ++++++++++++++++++-------------------
> >  2 files changed, 69 insertions(+), 63 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3361d7ffc63e..9739e97c6263 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5374,18 +5374,21 @@ enum {
> >  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
> >  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
> >  
> > -#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
> > -#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
> > -#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
> > -#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
> > -#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
> > -#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> > -#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
> > -#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
> > -#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> > -#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
> > -#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> > -#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
> > +#define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) \
> > +	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a), (reg_b))
> 
> #define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) ({
> 	typecheck(enum pipe, pipe);
> 	typecheck(enum plane_id, plane);
> 	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a), (reg_b))
> )}
> 
> Does that work?

Not really. The enum gets turned into a signed or unsigned int
it seems. Which one depends on whether it has negative values or not.

But while playing with this I did notice that I forgot to convert
assert_sprites_disabled() at least. So this wasn't a totally wasted
exercise :)

-- 
Ville Syrjälä
Intel OTC
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[PATCH v2 6/9] drm/i915: Use enum plane_id in VLV/CHV sprite code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use intel_plane->id to derive the VLV/CHV sprite register offsets
instead of abusing plane->plane which is really meant to for
primary planes only.

v2: Convert assert_sprites_disabled() over as well

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 58 +++++++++++++++-------------
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 74 ++++++++++++++++++------------------
 3 files changed, 70 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3361d7ffc63e..9739e97c6263 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5374,18 +5374,21 @@ enum {
 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
 
-#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
-#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
-#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
-#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
-#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
-#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
-#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
-#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
-#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
-#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
-#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
+#define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) \
+	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a), (reg_b))
+
+#define SPCNTR(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane)	_MMIO_VLV_SPR((pipe), (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane)	_MMIO_VLV_SPR((pipe), (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane)	_MMIO_VLV_SPR((pipe), (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPGAMC(pipe, plane)		_MMIO_VLV_SPR((pipe), (plane), _SPAGAMC, _SPBGAMC)
 
 /*
  * CHV pipe B sprite CSC
@@ -5394,29 +5397,32 @@ enum {
  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
  */
-#define SPCSCYGOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
-#define SPCSCCBOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
-#define SPCSCCROFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
+#define _MMIO_CHV_SPCSC(plane, reg) \
+	_MMIO(VLV_DISPLAY_BASE + ((plane) - PLANE_SPRITE0) * 0x1000 + (reg))
+
+#define SPCSCYGOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d900)
+#define SPCSCCBOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d904)
+#define SPCSCCROFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d908)
 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
 
-#define SPCSCC01(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
-#define SPCSCC23(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
-#define SPCSCC45(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
-#define SPCSCC67(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
-#define SPCSCC8(sprite)		_MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
+#define SPCSCC01(plane)		_MMIO_CHV_SPCSC(plane, 0x6d90c)
+#define SPCSCC23(plane)		_MMIO_CHV_SPCSC(plane, 0x6d910)
+#define SPCSCC45(plane)		_MMIO_CHV_SPCSC(plane, 0x6d914)
+#define SPCSCC67(plane)		_MMIO_CHV_SPCSC(plane, 0x6d918)
+#define SPCSCC8(plane)		_MMIO_CHV_SPCSC(plane, 0x6d91c)
 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
 
-#define SPCSCYGICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
-#define SPCSCCBICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
-#define SPCSCCRICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
+#define SPCSCYGICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d920)
+#define SPCSCCBICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d924)
+#define SPCSCCRICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d928)
 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
 
-#define SPCSCYGOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
-#define SPCSCCBOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
-#define SPCSCCROCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
+#define SPCSCYGOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d92c)
+#define SPCSCCBOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d930)
+#define SPCSCCROCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d934)
 #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95644c8cc568..a11c0f1d3f2e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1331,7 +1331,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 		}
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		for_each_sprite(dev_priv, pipe, sprite) {
-			u32 val = I915_READ(SPCNTR(pipe, sprite));
+			u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
 			I915_STATE_WARN(val & SP_ENABLE,
 			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 			     sprite_name(pipe, sprite), pipe_name(pipe));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 91d47d19f4a9..a922c6382fc7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -314,7 +314,7 @@ static void
 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
-	int plane = intel_plane->plane;
+	enum plane_id plane_id = intel_plane->id;
 
 	/* Seems RGB data bypasses the CSC always */
 	if (!format_is_yuv(format))
@@ -330,23 +330,23 @@ chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 	 * Cb and Cr apparently come in as signed already, so no
 	 * need for any offset. For Y we need to remove the offset.
 	 */
-	I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
-	I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
-	I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
-
-	I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
-	I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
-	I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
-	I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
-	I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
-
-	I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
-	I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
-	I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
-
-	I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
-	I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
-	I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
+	I915_WRITE(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
+	I915_WRITE(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
+	I915_WRITE(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
+
+	I915_WRITE(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
+	I915_WRITE(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
+	I915_WRITE(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
+	I915_WRITE(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
+	I915_WRITE(SPCSCC8(plane_id), SPCSC_C0(8263));
+
+	I915_WRITE(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
+	I915_WRITE(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
+	I915_WRITE(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
+
+	I915_WRITE(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
+	I915_WRITE(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
+	I915_WRITE(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 }
 
 static void
@@ -358,8 +358,8 @@ vlv_update_plane(struct drm_plane *dplane,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *intel_plane = to_intel_plane(dplane);
 	struct drm_framebuffer *fb = plane_state->base.fb;
-	int pipe = intel_plane->pipe;
-	int plane = intel_plane->plane;
+	enum pipe pipe = intel_plane->pipe;
+	enum plane_id plane_id = intel_plane->id;
 	u32 sprctl;
 	u32 sprsurf_offset, linear_offset;
 	unsigned int rotation = plane_state->base.rotation;
@@ -446,9 +446,9 @@ vlv_update_plane(struct drm_plane *dplane,
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (key->flags) {
-		I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
-		I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
-		I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
+		I915_WRITE(SPKEYMINVAL(pipe, plane_id), key->min_value);
+		I915_WRITE(SPKEYMAXVAL(pipe, plane_id), key->max_value);
+		I915_WRITE(SPKEYMSK(pipe, plane_id), key->channel_mask);
 	}
 
 	if (key->flags & I915_SET_COLORKEY_SOURCE)
@@ -457,21 +457,21 @@ vlv_update_plane(struct drm_plane *dplane,
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 		chv_update_csc(intel_plane, fb->pixel_format);
 
-	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
-	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
+	I915_WRITE(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
+	I915_WRITE(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 
 	if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
-		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
+		I915_WRITE(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 	else
-		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
+		I915_WRITE(SPLINOFF(pipe, plane_id), linear_offset);
 
-	I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
+	I915_WRITE(SPCONSTALPHA(pipe, plane_id), 0);
 
-	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
-	I915_WRITE(SPCNTR(pipe, plane), sprctl);
-	I915_WRITE(SPSURF(pipe, plane),
+	I915_WRITE(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
+	I915_WRITE(SPCNTR(pipe, plane_id), sprctl);
+	I915_WRITE(SPSURF(pipe, plane_id),
 		   intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
-	POSTING_READ(SPSURF(pipe, plane));
+	POSTING_READ(SPSURF(pipe, plane_id));
 }
 
 static void
@@ -480,13 +480,13 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 	struct drm_device *dev = dplane->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *intel_plane = to_intel_plane(dplane);
-	int pipe = intel_plane->pipe;
-	int plane = intel_plane->plane;
+	enum pipe pipe = intel_plane->pipe;
+	enum plane_id plane_id = intel_plane->id;
 
-	I915_WRITE(SPCNTR(pipe, plane), 0);
+	I915_WRITE(SPCNTR(pipe, plane_id), 0);
 
-	I915_WRITE(SPSURF(pipe, plane), 0);
-	POSTING_READ(SPSURF(pipe, plane));
+	I915_WRITE(SPSURF(pipe, plane_id), 0);
+	POSTING_READ(SPSURF(pipe, plane_id));
 }
 
 static void
-- 
2.7.4

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Re: [PATCH v2 6/9] drm/i915: Use enum plane_id in VLV/CHV sprite code

[Paulo Zanoni]

Em Ter, 2016-11-08 às 19:09 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use intel_plane->id to derive the VLV/CHV sprite register offsets
> instead of abusing plane->plane which is really meant to for
> primary planes only.

I think this patch is kinda an argument against the series due to the
new SPRITE0 subtractions, but I still think we're better with the
series applied.

A little more below:

> 
> v2: Convert assert_sprites_disabled() over as well
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 58 +++++++++++++++-----------
> --
>  drivers/gpu/drm/i915/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/intel_sprite.c  | 74 ++++++++++++++++++------
> ------------
>  3 files changed, 70 insertions(+), 64 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 3361d7ffc63e..9739e97c6263 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5374,18 +5374,21 @@ enum {
>  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
>  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
>  
> -#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPACNTR, _SPBCNTR)
> -#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPALINOFF, _SPBLINOFF)
> -#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPASTRIDE, _SPBSTRIDE)
> -#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS,
> _SPBPOS)
> -#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPASIZE, _SPBSIZE)
> -#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPAKEYMINVAL, _SPBKEYMINVAL)
> -#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPAKEYMSK, _SPBKEYMSK)
> -#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPASURF, _SPBSURF)
> -#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> -#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPATILEOFF, _SPBTILEOFF)
> -#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPACONSTALPHA, _SPBCONSTALPHA)
> -#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> _SPAGAMC, _SPBGAMC)
> +#define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) \
> +	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a),
> (reg_b))

But but but you nicely renamed everything to plane_id and now you
create a macro with plane instead of plane_id? I'll have to call Ville
to fix this inconsistency.

(this applies to all changes in this file)

> +
> +#define SPCNTR(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane)	_MMIO_VLV_SPR((pipe),
> (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane)	_MMIO_VLV_SPR((pipe),
> (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane)	_MMIO_VLV_SPR((pipe),
> (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPGAMC(pipe, plane)		_MMIO_VLV_SPR((pipe),
> (plane), _SPAGAMC, _SPBGAMC)
>  
>  /*
>   * CHV pipe B sprite CSC
> @@ -5394,29 +5397,32 @@ enum {
>   * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
>   * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
>   */
> -#define SPCSCYGOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d900 +
> (sprite) * 0x1000)
> -#define SPCSCCBOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d904 +
> (sprite) * 0x1000)
> -#define SPCSCCROFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d908 +
> (sprite) * 0x1000)
> +#define _MMIO_CHV_SPCSC(plane, reg) \
> +	_MMIO(VLV_DISPLAY_BASE + ((plane) - PLANE_SPRITE0) * 0x1000
> + (reg))
> +
> +#define SPCSCYGOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d900)
> +#define SPCSCCBOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d904)
> +#define SPCSCCROFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d908)
>  #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11
> */
>  #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
>  
> -#define SPCSCC01(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d90c +
> (sprite) * 0x1000)
> -#define SPCSCC23(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d910 +
> (sprite) * 0x1000)
> -#define SPCSCC45(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d914 +
> (sprite) * 0x1000)
> -#define SPCSCC67(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d918 +
> (sprite) * 0x1000)
> -#define SPCSCC8(sprite)		_MMIO(VLV_DISPLAY_BASE +
> 0x6d91c + (sprite) * 0x1000)
> +#define SPCSCC01(plane)		_MMIO_CHV_SPCSC(plane,
> 0x6d90c)
> +#define SPCSCC23(plane)		_MMIO_CHV_SPCSC(plane,
> 0x6d910)
> +#define SPCSCC45(plane)		_MMIO_CHV_SPCSC(plane,
> 0x6d914)
> +#define SPCSCC67(plane)		_MMIO_CHV_SPCSC(plane,
> 0x6d918)
> +#define SPCSCC8(plane)		_MMIO_CHV_SPCSC(plane,
> 0x6d91c)

Why is 1 "01" while 8 is "8"? :)

With or without changes:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>


>  #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12
> */
>  #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12
> */
>  
> -#define SPCSCYGICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> 0x6d920 + (sprite) * 0x1000)
> -#define SPCSCCBICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> 0x6d924 + (sprite) * 0x1000)
> -#define SPCSCCRICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> 0x6d928 + (sprite) * 0x1000)
> +#define SPCSCYGICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d920)
> +#define SPCSCCBICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d924)
> +#define SPCSCCRICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d928)
>  #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11
> */
>  #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
>  
> -#define SPCSCYGOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> 0x6d92c + (sprite) * 0x1000)
> -#define SPCSCCBOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> 0x6d930 + (sprite) * 0x1000)
> -#define SPCSCCROCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> 0x6d934 + (sprite) * 0x1000)
> +#define SPCSCYGOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d92c)
> +#define SPCSCCBOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d930)
> +#define SPCSCCROCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d934)
>  #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
>  #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 95644c8cc568..a11c0f1d3f2e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1331,7 +1331,7 @@ static void assert_sprites_disabled(struct
> drm_i915_private *dev_priv,
>  		}
>  	} else if (IS_VALLEYVIEW(dev_priv) ||
> IS_CHERRYVIEW(dev_priv)) {
>  		for_each_sprite(dev_priv, pipe, sprite) {
> -			u32 val = I915_READ(SPCNTR(pipe, sprite));
> +			u32 val = I915_READ(SPCNTR(pipe,
> PLANE_SPRITE0 + sprite));
>  			I915_STATE_WARN(val & SP_ENABLE,
>  			     "sprite %c assertion failure, should be
> off on pipe %c but is still active\n",
>  			     sprite_name(pipe, sprite),
> pipe_name(pipe));
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 91d47d19f4a9..a922c6382fc7 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -314,7 +314,7 @@ static void
>  chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_plane-
> >base.dev);
> -	int plane = intel_plane->plane;
> +	enum plane_id plane_id = intel_plane->id;
>  
>  	/* Seems RGB data bypasses the CSC always */
>  	if (!format_is_yuv(format))
> @@ -330,23 +330,23 @@ chv_update_csc(struct intel_plane *intel_plane,
> uint32_t format)
>  	 * Cb and Cr apparently come in as signed already, so no
>  	 * need for any offset. For Y we need to remove the offset.
>  	 */
> -	I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-
> 64));
> -	I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) |
> SPCSC_IOFF(0));
> -	I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) |
> SPCSC_IOFF(0));
> -
> -	I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) |
> SPCSC_C0(6537));
> -	I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
> -	I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) |
> SPCSC_C0(4769));
> -	I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
> -	I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
> -
> -	I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) |
> SPCSC_IMIN(64));
> -	I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) |
> SPCSC_IMIN(-448));
> -	I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) |
> SPCSC_IMIN(-448));
> -
> -	I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) |
> SPCSC_OMIN(0));
> -	I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) |
> SPCSC_OMIN(0));
> -	I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) |
> SPCSC_OMIN(0));
> +	I915_WRITE(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) |
> SPCSC_IOFF(-64));
> +	I915_WRITE(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) |
> SPCSC_IOFF(0));
> +	I915_WRITE(SPCSCCROFF(plane_id), SPCSC_OOFF(0) |
> SPCSC_IOFF(0));
> +
> +	I915_WRITE(SPCSCC01(plane_id), SPCSC_C1(4769) |
> SPCSC_C0(6537));
> +	I915_WRITE(SPCSCC23(plane_id), SPCSC_C1(-3330) |
> SPCSC_C0(0));
> +	I915_WRITE(SPCSCC45(plane_id), SPCSC_C1(-1605) |
> SPCSC_C0(4769));
> +	I915_WRITE(SPCSCC67(plane_id), SPCSC_C1(4769) |
> SPCSC_C0(0));
> +	I915_WRITE(SPCSCC8(plane_id), SPCSC_C0(8263));
> +
> +	I915_WRITE(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) |
> SPCSC_IMIN(64));
> +	I915_WRITE(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) |
> SPCSC_IMIN(-448));
> +	I915_WRITE(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) |
> SPCSC_IMIN(-448));
> +
> +	I915_WRITE(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) |
> SPCSC_OMIN(0));
> +	I915_WRITE(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) |
> SPCSC_OMIN(0));
> +	I915_WRITE(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) |
> SPCSC_OMIN(0));
>  }
>  
>  static void
> @@ -358,8 +358,8 @@ vlv_update_plane(struct drm_plane *dplane,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *intel_plane = to_intel_plane(dplane);
>  	struct drm_framebuffer *fb = plane_state->base.fb;
> -	int pipe = intel_plane->pipe;
> -	int plane = intel_plane->plane;
> +	enum pipe pipe = intel_plane->pipe;
> +	enum plane_id plane_id = intel_plane->id;
>  	u32 sprctl;
>  	u32 sprsurf_offset, linear_offset;
>  	unsigned int rotation = plane_state->base.rotation;
> @@ -446,9 +446,9 @@ vlv_update_plane(struct drm_plane *dplane,
>  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>  
>  	if (key->flags) {
> -		I915_WRITE(SPKEYMINVAL(pipe, plane), key-
> >min_value);
> -		I915_WRITE(SPKEYMAXVAL(pipe, plane), key-
> >max_value);
> -		I915_WRITE(SPKEYMSK(pipe, plane), key-
> >channel_mask);
> +		I915_WRITE(SPKEYMINVAL(pipe, plane_id), key-
> >min_value);
> +		I915_WRITE(SPKEYMAXVAL(pipe, plane_id), key-
> >max_value);
> +		I915_WRITE(SPKEYMSK(pipe, plane_id), key-
> >channel_mask);
>  	}
>  
>  	if (key->flags & I915_SET_COLORKEY_SOURCE)
> @@ -457,21 +457,21 @@ vlv_update_plane(struct drm_plane *dplane,
>  	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
>  		chv_update_csc(intel_plane, fb->pixel_format);
>  
> -	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> -	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
> +	I915_WRITE(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
> +	I915_WRITE(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
>  
>  	if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> -		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
> +		I915_WRITE(SPTILEOFF(pipe, plane_id), (y << 16) |
> x);
>  	else
> -		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
> +		I915_WRITE(SPLINOFF(pipe, plane_id), linear_offset);
>  
> -	I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
> +	I915_WRITE(SPCONSTALPHA(pipe, plane_id), 0);
>  
> -	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
> -	I915_WRITE(SPCNTR(pipe, plane), sprctl);
> -	I915_WRITE(SPSURF(pipe, plane),
> +	I915_WRITE(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
> +	I915_WRITE(SPCNTR(pipe, plane_id), sprctl);
> +	I915_WRITE(SPSURF(pipe, plane_id),
>  		   intel_fb_gtt_offset(fb, rotation) +
> sprsurf_offset);
> -	POSTING_READ(SPSURF(pipe, plane));
> +	POSTING_READ(SPSURF(pipe, plane_id));
>  }
>  
>  static void
> @@ -480,13 +480,13 @@ vlv_disable_plane(struct drm_plane *dplane,
> struct drm_crtc *crtc)
>  	struct drm_device *dev = dplane->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *intel_plane = to_intel_plane(dplane);
> -	int pipe = intel_plane->pipe;
> -	int plane = intel_plane->plane;
> +	enum pipe pipe = intel_plane->pipe;
> +	enum plane_id plane_id = intel_plane->id;
>  
> -	I915_WRITE(SPCNTR(pipe, plane), 0);
> +	I915_WRITE(SPCNTR(pipe, plane_id), 0);
>  
> -	I915_WRITE(SPSURF(pipe, plane), 0);
> -	POSTING_READ(SPSURF(pipe, plane));
> +	I915_WRITE(SPSURF(pipe, plane_id), 0);
> +	POSTING_READ(SPSURF(pipe, plane_id));
>  }
>  
>  static void
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Re: [PATCH v2 6/9] drm/i915: Use enum plane_id in VLV/CHV sprite code

[Ville Syrjälä]

On Thu, Nov 17, 2016 at 06:07:36PM -0200, Paulo Zanoni wrote:
> Em Ter, 2016-11-08 às 19:09 +0200, ville.syrjala@linux.intel.com
> escreveu:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Use intel_plane->id to derive the VLV/CHV sprite register offsets
> > instead of abusing plane->plane which is really meant to for
> > primary planes only.
> 
> I think this patch is kinda an argument against the series due to the
> new SPRITE0 subtractions, but I still think we're better with the
> series applied.

I really don't want to have two different kinds of per-pipe plane
identifiers. So the subtractions are IMO an accpeptable tradeoff for
that.

> 
> A little more below:
> 
> > 
> > v2: Convert assert_sprites_disabled() over as well
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 58 +++++++++++++++-----------
> > --
> >  drivers/gpu/drm/i915/intel_display.c |  2 +-
> >  drivers/gpu/drm/i915/intel_sprite.c  | 74 ++++++++++++++++++------
> > ------------
> >  3 files changed, 70 insertions(+), 64 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 3361d7ffc63e..9739e97c6263 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5374,18 +5374,21 @@ enum {
> >  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
> >  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
> >  
> > -#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPACNTR, _SPBCNTR)
> > -#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPALINOFF, _SPBLINOFF)
> > -#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPASTRIDE, _SPBSTRIDE)
> > -#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS,
> > _SPBPOS)
> > -#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPASIZE, _SPBSIZE)
> > -#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPAKEYMINVAL, _SPBKEYMINVAL)
> > -#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPAKEYMSK, _SPBKEYMSK)
> > -#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPASURF, _SPBSURF)
> > -#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> > -#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPATILEOFF, _SPBTILEOFF)
> > -#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPACONSTALPHA, _SPBCONSTALPHA)
> > -#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane),
> > _SPAGAMC, _SPBGAMC)
> > +#define _MMIO_VLV_SPR(pipe, plane, reg_a, reg_b) \
> > +	_MMIO_PIPE((pipe) * 2 + (plane) - PLANE_SPRITE0, (reg_a),
> > (reg_b))
> 
> But but but you nicely renamed everything to plane_id and now you
> create a macro with plane instead of plane_id?

Rather I kept the 'plane' naming here because, well, I'm lazy :)

> I'll have to call Ville
> to fix this inconsistency.

I can re-sed it a bit.

> 
> (this applies to all changes in this file)
> 
> > +
> > +#define SPCNTR(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPACNTR, _SPBCNTR)
> > +#define SPLINOFF(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPALINOFF, _SPBLINOFF)
> > +#define SPSTRIDE(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPASTRIDE, _SPBSTRIDE)
> > +#define SPPOS(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPAPOS, _SPBPOS)
> > +#define SPSIZE(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPASIZE, _SPBSIZE)
> > +#define SPKEYMINVAL(pipe, plane)	_MMIO_VLV_SPR((pipe),
> > (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> > +#define SPKEYMSK(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPAKEYMSK, _SPBKEYMSK)
> > +#define SPSURF(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPASURF, _SPBSURF)
> > +#define SPKEYMAXVAL(pipe, plane)	_MMIO_VLV_SPR((pipe),
> > (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> > +#define SPTILEOFF(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPATILEOFF, _SPBTILEOFF)
> > +#define SPCONSTALPHA(pipe, plane)	_MMIO_VLV_SPR((pipe),
> > (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> > +#define SPGAMC(pipe, plane)		_MMIO_VLV_SPR((pipe),
> > (plane), _SPAGAMC, _SPBGAMC)
> >  
> >  /*
> >   * CHV pipe B sprite CSC
> > @@ -5394,29 +5397,32 @@ enum {
> >   * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
> >   * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
> >   */
> > -#define SPCSCYGOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d900 +
> > (sprite) * 0x1000)
> > -#define SPCSCCBOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d904 +
> > (sprite) * 0x1000)
> > -#define SPCSCCROFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d908 +
> > (sprite) * 0x1000)
> > +#define _MMIO_CHV_SPCSC(plane, reg) \
> > +	_MMIO(VLV_DISPLAY_BASE + ((plane) - PLANE_SPRITE0) * 0x1000
> > + (reg))
> > +
> > +#define SPCSCYGOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d900)
> > +#define SPCSCCBOFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d904)
> > +#define SPCSCCROFF(plane)	_MMIO_CHV_SPCSC(plane, 0x6d908)
> >  #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11
> > */
> >  #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
> >  
> > -#define SPCSCC01(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d90c +
> > (sprite) * 0x1000)
> > -#define SPCSCC23(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d910 +
> > (sprite) * 0x1000)
> > -#define SPCSCC45(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d914 +
> > (sprite) * 0x1000)
> > -#define SPCSCC67(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d918 +
> > (sprite) * 0x1000)
> > -#define SPCSCC8(sprite)		_MMIO(VLV_DISPLAY_BASE +
> > 0x6d91c + (sprite) * 0x1000)
> > +#define SPCSCC01(plane)		_MMIO_CHV_SPCSC(plane,
> > 0x6d90c)
> > +#define SPCSCC23(plane)		_MMIO_CHV_SPCSC(plane,
> > 0x6d910)
> > +#define SPCSCC45(plane)		_MMIO_CHV_SPCSC(plane,
> > 0x6d914)
> > +#define SPCSCC67(plane)		_MMIO_CHV_SPCSC(plane,
> > 0x6d918)
> > +#define SPCSCC8(plane)		_MMIO_CHV_SPCSC(plane,
> > 0x6d91c)
> 
> Why is 1 "01" while 8 is "8"? :)

01 means "0 and 1" whereas 8 is just "8"

> 
> With or without changes:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> 
> >  #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12
> > */
> >  #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12
> > */
> >  
> > -#define SPCSCYGICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> > 0x6d920 + (sprite) * 0x1000)
> > -#define SPCSCCBICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> > 0x6d924 + (sprite) * 0x1000)
> > -#define SPCSCCRICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> > 0x6d928 + (sprite) * 0x1000)
> > +#define SPCSCYGICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d920)
> > +#define SPCSCCBICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d924)
> > +#define SPCSCCRICLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d928)
> >  #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11
> > */
> >  #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
> >  
> > -#define SPCSCYGOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> > 0x6d92c + (sprite) * 0x1000)
> > -#define SPCSCCBOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> > 0x6d930 + (sprite) * 0x1000)
> > -#define SPCSCCROCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE +
> > 0x6d934 + (sprite) * 0x1000)
> > +#define SPCSCYGOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d92c)
> > +#define SPCSCCBOCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d930)
> > +#define SPCSCCROCLAMP(plane)	_MMIO_CHV_SPCSC(plane, 0x6d934)
> >  #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
> >  #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 95644c8cc568..a11c0f1d3f2e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1331,7 +1331,7 @@ static void assert_sprites_disabled(struct
> > drm_i915_private *dev_priv,
> >  		}
> >  	} else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) {
> >  		for_each_sprite(dev_priv, pipe, sprite) {
> > -			u32 val = I915_READ(SPCNTR(pipe, sprite));
> > +			u32 val = I915_READ(SPCNTR(pipe,
> > PLANE_SPRITE0 + sprite));
> >  			I915_STATE_WARN(val & SP_ENABLE,
> >  			     "sprite %c assertion failure, should be
> > off on pipe %c but is still active\n",
> >  			     sprite_name(pipe, sprite),
> > pipe_name(pipe));
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 91d47d19f4a9..a922c6382fc7 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -314,7 +314,7 @@ static void
> >  chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(intel_plane-
> > >base.dev);
> > -	int plane = intel_plane->plane;
> > +	enum plane_id plane_id = intel_plane->id;
> >  
> >  	/* Seems RGB data bypasses the CSC always */
> >  	if (!format_is_yuv(format))
> > @@ -330,23 +330,23 @@ chv_update_csc(struct intel_plane *intel_plane,
> > uint32_t format)
> >  	 * Cb and Cr apparently come in as signed already, so no
> >  	 * need for any offset. For Y we need to remove the offset.
> >  	 */
> > -	I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-
> > 64));
> > -	I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) |
> > SPCSC_IOFF(0));
> > -	I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) |
> > SPCSC_IOFF(0));
> > -
> > -	I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) |
> > SPCSC_C0(6537));
> > -	I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
> > -	I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) |
> > SPCSC_C0(4769));
> > -	I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
> > -	I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
> > -
> > -	I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) |
> > SPCSC_IMIN(64));
> > -	I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) |
> > SPCSC_IMIN(-448));
> > -	I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) |
> > SPCSC_IMIN(-448));
> > -
> > -	I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) |
> > SPCSC_OMIN(0));
> > -	I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) |
> > SPCSC_OMIN(0));
> > -	I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) |
> > SPCSC_OMIN(0));
> > +	I915_WRITE(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) |
> > SPCSC_IOFF(-64));
> > +	I915_WRITE(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) |
> > SPCSC_IOFF(0));
> > +	I915_WRITE(SPCSCCROFF(plane_id), SPCSC_OOFF(0) |
> > SPCSC_IOFF(0));
> > +
> > +	I915_WRITE(SPCSCC01(plane_id), SPCSC_C1(4769) |
> > SPCSC_C0(6537));
> > +	I915_WRITE(SPCSCC23(plane_id), SPCSC_C1(-3330) |
> > SPCSC_C0(0));
> > +	I915_WRITE(SPCSCC45(plane_id), SPCSC_C1(-1605) |
> > SPCSC_C0(4769));
> > +	I915_WRITE(SPCSCC67(plane_id), SPCSC_C1(4769) |
> > SPCSC_C0(0));
> > +	I915_WRITE(SPCSCC8(plane_id), SPCSC_C0(8263));
> > +
> > +	I915_WRITE(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) |
> > SPCSC_IMIN(64));
> > +	I915_WRITE(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) |
> > SPCSC_IMIN(-448));
> > +	I915_WRITE(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) |
> > SPCSC_IMIN(-448));
> > +
> > +	I915_WRITE(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) |
> > SPCSC_OMIN(0));
> > +	I915_WRITE(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) |
> > SPCSC_OMIN(0));
> > +	I915_WRITE(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) |
> > SPCSC_OMIN(0));
> >  }
> >  
> >  static void
> > @@ -358,8 +358,8 @@ vlv_update_plane(struct drm_plane *dplane,
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct intel_plane *intel_plane = to_intel_plane(dplane);
> >  	struct drm_framebuffer *fb = plane_state->base.fb;
> > -	int pipe = intel_plane->pipe;
> > -	int plane = intel_plane->plane;
> > +	enum pipe pipe = intel_plane->pipe;
> > +	enum plane_id plane_id = intel_plane->id;
> >  	u32 sprctl;
> >  	u32 sprsurf_offset, linear_offset;
> >  	unsigned int rotation = plane_state->base.rotation;
> > @@ -446,9 +446,9 @@ vlv_update_plane(struct drm_plane *dplane,
> >  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> >  
> >  	if (key->flags) {
> > -		I915_WRITE(SPKEYMINVAL(pipe, plane), key-
> > >min_value);
> > -		I915_WRITE(SPKEYMAXVAL(pipe, plane), key-
> > >max_value);
> > -		I915_WRITE(SPKEYMSK(pipe, plane), key-
> > >channel_mask);
> > +		I915_WRITE(SPKEYMINVAL(pipe, plane_id), key-
> > >min_value);
> > +		I915_WRITE(SPKEYMAXVAL(pipe, plane_id), key-
> > >max_value);
> > +		I915_WRITE(SPKEYMSK(pipe, plane_id), key-
> > >channel_mask);
> >  	}
> >  
> >  	if (key->flags & I915_SET_COLORKEY_SOURCE)
> > @@ -457,21 +457,21 @@ vlv_update_plane(struct drm_plane *dplane,
> >  	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
> >  		chv_update_csc(intel_plane, fb->pixel_format);
> >  
> > -	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> > -	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
> > +	I915_WRITE(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
> > +	I915_WRITE(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
> >  
> >  	if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> > -		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
> > +		I915_WRITE(SPTILEOFF(pipe, plane_id), (y << 16) |
> > x);
> >  	else
> > -		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
> > +		I915_WRITE(SPLINOFF(pipe, plane_id), linear_offset);
> >  
> > -	I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
> > +	I915_WRITE(SPCONSTALPHA(pipe, plane_id), 0);
> >  
> > -	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
> > -	I915_WRITE(SPCNTR(pipe, plane), sprctl);
> > -	I915_WRITE(SPSURF(pipe, plane),
> > +	I915_WRITE(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
> > +	I915_WRITE(SPCNTR(pipe, plane_id), sprctl);
> > +	I915_WRITE(SPSURF(pipe, plane_id),
> >  		   intel_fb_gtt_offset(fb, rotation) +
> > sprsurf_offset);
> > -	POSTING_READ(SPSURF(pipe, plane));
> > +	POSTING_READ(SPSURF(pipe, plane_id));
> >  }
> >  
> >  static void
> > @@ -480,13 +480,13 @@ vlv_disable_plane(struct drm_plane *dplane,
> > struct drm_crtc *crtc)
> >  	struct drm_device *dev = dplane->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct intel_plane *intel_plane = to_intel_plane(dplane);
> > -	int pipe = intel_plane->pipe;
> > -	int plane = intel_plane->plane;
> > +	enum pipe pipe = intel_plane->pipe;
> > +	enum plane_id plane_id = intel_plane->id;
> >  
> > -	I915_WRITE(SPCNTR(pipe, plane), 0);
> > +	I915_WRITE(SPCNTR(pipe, plane_id), 0);
> >  
> > -	I915_WRITE(SPSURF(pipe, plane), 0);
> > -	POSTING_READ(SPSURF(pipe, plane));
> > +	I915_WRITE(SPSURF(pipe, plane_id), 0);
> > +	POSTING_READ(SPSURF(pipe, plane_id));
> >  }
> >  
> >  static void

-- 
Ville Syrjälä
Intel OTC
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Intel-gfx@lists.freedesktop.org
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[PATCH 7/9] drm/i915: Use enum plane_id in VLV/CHV wm code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's try not to abuse plane->plane for sprites on VLV/CHV and instead
use plane->id. Since out watermark structures aren't entirely plane type
agnostic (for now) and start indexing sprites from 0  we'll add a small
helper to convert between the two bases.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 73 ++++++++++++++++++++---------------------
 1 file changed, 36 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fd8cbc224b07..b1ad09e458ca 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -371,12 +371,15 @@ static const int pessimal_latency_ns = 5000;
 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 
-static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
-			      enum pipe pipe, int plane)
+static int vlv_get_fifo_size(struct intel_plane *plane)
 {
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int sprite0_start, sprite1_start, size;
 
-	switch (pipe) {
+	if (plane->id == PLANE_CURSOR)
+		return 63;
+
+	switch (plane->pipe) {
 		uint32_t dsparb, dsparb2, dsparb3;
 	case PIPE_A:
 		dsparb = I915_READ(DSPARB);
@@ -400,24 +403,21 @@ static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	switch (plane) {
-	case 0:
+	switch (plane->id) {
+	case PLANE_PRIMARY:
 		size = sprite0_start;
 		break;
-	case 1:
+	case PLANE_SPRITE0:
 		size = sprite1_start - sprite0_start;
 		break;
-	case 2:
+	case PLANE_SPRITE1:
 		size = 512 - 1 - sprite1_start;
 		break;
 	default:
 		return 0;
 	}
 
-	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
-		      pipe_name(pipe), plane == 0 ? "primary" : "sprite",
-		      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
-		      size);
+	DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
 
 	return size;
 }
@@ -1054,6 +1054,12 @@ static void vlv_compute_fifo(struct intel_crtc *crtc)
 	WARN_ON(fifo_left != 0);
 }
 
+/* FIXME kill me */
+static inline int vlv_sprite_id(enum plane_id plane_id)
+{
+	return plane_id - PLANE_SPRITE0;
+}
+
 static void vlv_invert_wms(struct intel_crtc *crtc)
 {
 	struct vlv_wm_state *wm_state = &crtc->wm_state;
@@ -1079,7 +1085,7 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
 					wm_state->wm[level].primary;
 				break;
 			case DRM_PLANE_TYPE_OVERLAY:
-				sprite = plane->plane;
+				sprite = vlv_sprite_id(plane->id);
 				wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
 					wm_state->wm[level].sprite[sprite];
 				break;
@@ -1143,7 +1149,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
 				wm_state->wm[level].primary = wm;
 				break;
 			case DRM_PLANE_TYPE_OVERLAY:
-				sprite = plane->plane;
+				sprite = vlv_sprite_id(plane->id);
 				wm_state->wm[level].sprite[sprite] = wm;
 				break;
 			}
@@ -1169,7 +1175,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
 					    wm_state->wm[level].primary);
 			break;
 		case DRM_PLANE_TYPE_OVERLAY:
-			sprite = plane->plane;
+			sprite = vlv_sprite_id(plane->id);
 			for (level = 0; level < wm_state->num_levels; level++)
 				wm_state->sr[level].plane =
 					min(wm_state->sr[level].plane,
@@ -1198,17 +1204,23 @@ static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
 	int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
-		if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
-			WARN_ON(plane->wm.fifo_size != 63);
-			continue;
-		}
-
-		if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
+		switch (plane->id) {
+		case PLANE_PRIMARY:
 			sprite0_start = plane->wm.fifo_size;
-		else if (plane->plane == 0)
+			break;
+		case PLANE_SPRITE0:
 			sprite1_start = sprite0_start + plane->wm.fifo_size;
-		else
+			break;
+		case PLANE_SPRITE1:
 			fifo_size = sprite1_start + plane->wm.fifo_size;
+			break;
+		case PLANE_CURSOR:
+			WARN_ON(plane->wm.fifo_size != 63);
+			break;
+		default:
+			MISSING_CASE(plane->id);
+			break;
+		}
 	}
 
 	WARN_ON(fifo_size != 512 - 1);
@@ -4505,21 +4517,8 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
 
 	vlv_read_wm_values(dev_priv, wm);
 
-	for_each_intel_plane(dev, plane) {
-		switch (plane->base.type) {
-			int sprite;
-		case DRM_PLANE_TYPE_CURSOR:
-			plane->wm.fifo_size = 63;
-			break;
-		case DRM_PLANE_TYPE_PRIMARY:
-			plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
-			break;
-		case DRM_PLANE_TYPE_OVERLAY:
-			sprite = plane->plane;
-			plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
-			break;
-		}
-	}
+	for_each_intel_plane(dev, plane)
+		plane->wm.fifo_size = vlv_get_fifo_size(plane);
 
 	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 	wm->level = VLV_WM_LEVEL_PM2;
-- 
2.7.4

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Re: [PATCH 7/9] drm/i915: Use enum plane_id in VLV/CHV wm code

[Paulo Zanoni]

Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Let's try not to abuse plane->plane for sprites on VLV/CHV and
> instead
> use plane->id. Since out watermark structures aren't entirely plane
> type
> agnostic (for now) and start indexing sprites from 0  we'll add a
> small
> helper to convert between the two bases.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 73 ++++++++++++++++++++-----------
> ----------
>  1 file changed, 36 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index fd8cbc224b07..b1ad09e458ca 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -371,12 +371,15 @@ static const int pessimal_latency_ns = 5000;
>  #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
>  	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >>
> (hi_shift)) & 0x1) << 8))
>  
> -static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
> -			      enum pipe pipe, int plane)
> +static int vlv_get_fifo_size(struct intel_plane *plane)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	int sprite0_start, sprite1_start, size;
>  
> -	switch (pipe) {
> +	if (plane->id == PLANE_CURSOR)
> +		return 63;
> +
> +	switch (plane->pipe) {
>  		uint32_t dsparb, dsparb2, dsparb3;
>  	case PIPE_A:
>  		dsparb = I915_READ(DSPARB);
> @@ -400,24 +403,21 @@ static int vlv_get_fifo_size(struct
> drm_i915_private *dev_priv,
>  		return 0;
>  	}
>  
> -	switch (plane) {
> -	case 0:
> +	switch (plane->id) {
> +	case PLANE_PRIMARY:
>  		size = sprite0_start;
>  		break;
> -	case 1:
> +	case PLANE_SPRITE0:
>  		size = sprite1_start - sprite0_start;
>  		break;
> -	case 2:
> +	case PLANE_SPRITE1:
>  		size = 512 - 1 - sprite1_start;
>  		break;
>  	default:
>  		return 0;
>  	}
>  
> -	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
> -		      pipe_name(pipe), plane == 0 ? "primary" :
> "sprite",
> -		      plane == 0 ? plane_name(pipe) :
> sprite_name(pipe, plane - 1),
> -		      size);
> +	DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
>  
>  	return size;
>  }
> @@ -1054,6 +1054,12 @@ static void vlv_compute_fifo(struct intel_crtc
> *crtc)
>  	WARN_ON(fifo_left != 0);
>  }
>  
> +/* FIXME kill me */
> +static inline int vlv_sprite_id(enum plane_id plane_id)
> +{
> +	return plane_id - PLANE_SPRITE0;
> +}
> +
>  static void vlv_invert_wms(struct intel_crtc *crtc)
>  {
>  	struct vlv_wm_state *wm_state = &crtc->wm_state;
> @@ -1079,7 +1085,7 @@ static void vlv_invert_wms(struct intel_crtc
> *crtc)
>  					wm_state->wm[level].primary;
>  				break;
>  			case DRM_PLANE_TYPE_OVERLAY:
> -				sprite = plane->plane;
> +				sprite = vlv_sprite_id(plane->id);
>  				wm_state->wm[level].sprite[sprite] =
> plane->wm.fifo_size -
>  					wm_state-
> >wm[level].sprite[sprite];
>  				break;
> @@ -1143,7 +1149,7 @@ static void vlv_compute_wm(struct intel_crtc
> *crtc)
>  				wm_state->wm[level].primary = wm;
>  				break;
>  			case DRM_PLANE_TYPE_OVERLAY:
> -				sprite = plane->plane;
> +				sprite = vlv_sprite_id(plane->id);
>  				wm_state->wm[level].sprite[sprite] =
> wm;
>  				break;
>  			}
> @@ -1169,7 +1175,7 @@ static void vlv_compute_wm(struct intel_crtc
> *crtc)
>  					    wm_state-
> >wm[level].primary);
>  			break;
>  		case DRM_PLANE_TYPE_OVERLAY:
> -			sprite = plane->plane;
> +			sprite = vlv_sprite_id(plane->id);
>  			for (level = 0; level < wm_state-
> >num_levels; level++)
>  				wm_state->sr[level].plane =
>  					min(wm_state-
> >sr[level].plane,
> @@ -1198,17 +1204,23 @@ static void vlv_pipe_set_fifo_size(struct
> intel_crtc *crtc)
>  	int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
>  
>  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> -		if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
> -			WARN_ON(plane->wm.fifo_size != 63);
> -			continue;
> -		}
> -
> -		if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
> +		switch (plane->id) {
> +		case PLANE_PRIMARY:
>  			sprite0_start = plane->wm.fifo_size;
> -		else if (plane->plane == 0)
> +			break;
> +		case PLANE_SPRITE0:
>  			sprite1_start = sprite0_start + plane-
> >wm.fifo_size;
> -		else
> +			break;
> +		case PLANE_SPRITE1:
>  			fifo_size = sprite1_start + plane-
> >wm.fifo_size;
> +			break;
> +		case PLANE_CURSOR:
> +			WARN_ON(plane->wm.fifo_size != 63);
> +			break;
> +		default:
> +			MISSING_CASE(plane->id);
> +			break;
> +		}
>  	}
>  
>  	WARN_ON(fifo_size != 512 - 1);
> @@ -4505,21 +4517,8 @@ void vlv_wm_get_hw_state(struct drm_device
> *dev)
>  
>  	vlv_read_wm_values(dev_priv, wm);
>  
> -	for_each_intel_plane(dev, plane) {
> -		switch (plane->base.type) {
> -			int sprite;
> -		case DRM_PLANE_TYPE_CURSOR:
> -			plane->wm.fifo_size = 63;
> -			break;
> -		case DRM_PLANE_TYPE_PRIMARY:
> -			plane->wm.fifo_size =
> vlv_get_fifo_size(dev_priv, plane->pipe, 0);
> -			break;
> -		case DRM_PLANE_TYPE_OVERLAY:
> -			sprite = plane->plane;
> -			plane->wm.fifo_size =
> vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
> -			break;
> -		}
> -	}
> +	for_each_intel_plane(dev, plane)
> +		plane->wm.fifo_size = vlv_get_fifo_size(plane);
>  
>  	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  	wm->level = VLV_WM_LEVEL_PM2;
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Re: [PATCH 7/9] drm/i915: Use enum plane_id in VLV/CHV wm code

[Paulo Zanoni]

Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Let's try not to abuse plane->plane for sprites on VLV/CHV and
> instead
> use plane->id. Since out watermark structures aren't entirely plane
> type
> agnostic (for now) and start indexing sprites from 0  we'll add a
> small
> helper to convert between the two bases.

I'm not sure I like this one. We've been using plane_id for the actual
prim/spr/cur IDs, and now we use plane_id for something that's supposed
to mean A/B/C. I really think we should have different words to refer
to the two things. I think this goes back to Matt's renaming discussion
we've been having in patch 2. Let's solve it there first before we
revisit this patch. I'm still not sure what would be the ideal solution
here, I'll spend some time thinking.

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 73 ++++++++++++++++++++-----------
> ----------
>  1 file changed, 36 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index fd8cbc224b07..b1ad09e458ca 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -371,12 +371,15 @@ static const int pessimal_latency_ns = 5000;
>  #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
>  	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >>
> (hi_shift)) & 0x1) << 8))
>  
> -static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
> -			      enum pipe pipe, int plane)
> +static int vlv_get_fifo_size(struct intel_plane *plane)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	int sprite0_start, sprite1_start, size;
>  
> -	switch (pipe) {
> +	if (plane->id == PLANE_CURSOR)
> +		return 63;
> +
> +	switch (plane->pipe) {
>  		uint32_t dsparb, dsparb2, dsparb3;
>  	case PIPE_A:
>  		dsparb = I915_READ(DSPARB);
> @@ -400,24 +403,21 @@ static int vlv_get_fifo_size(struct
> drm_i915_private *dev_priv,
>  		return 0;
>  	}
>  
> -	switch (plane) {
> -	case 0:
> +	switch (plane->id) {
> +	case PLANE_PRIMARY:
>  		size = sprite0_start;
>  		break;
> -	case 1:
> +	case PLANE_SPRITE0:
>  		size = sprite1_start - sprite0_start;
>  		break;
> -	case 2:
> +	case PLANE_SPRITE1:
>  		size = 512 - 1 - sprite1_start;
>  		break;
>  	default:
>  		return 0;
>  	}
>  
> -	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
> -		      pipe_name(pipe), plane == 0 ? "primary" :
> "sprite",
> -		      plane == 0 ? plane_name(pipe) :
> sprite_name(pipe, plane - 1),
> -		      size);
> +	DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
>  
>  	return size;
>  }
> @@ -1054,6 +1054,12 @@ static void vlv_compute_fifo(struct intel_crtc
> *crtc)
>  	WARN_ON(fifo_left != 0);
>  }
>  
> +/* FIXME kill me */
> +static inline int vlv_sprite_id(enum plane_id plane_id)
> +{
> +	return plane_id - PLANE_SPRITE0;
> +}
> +
>  static void vlv_invert_wms(struct intel_crtc *crtc)
>  {
>  	struct vlv_wm_state *wm_state = &crtc->wm_state;
> @@ -1079,7 +1085,7 @@ static void vlv_invert_wms(struct intel_crtc
> *crtc)
>  					wm_state->wm[level].primary;
>  				break;
>  			case DRM_PLANE_TYPE_OVERLAY:
> -				sprite = plane->plane;
> +				sprite = vlv_sprite_id(plane->id);
>  				wm_state->wm[level].sprite[sprite] =
> plane->wm.fifo_size -
>  					wm_state-
> >wm[level].sprite[sprite];
>  				break;
> @@ -1143,7 +1149,7 @@ static void vlv_compute_wm(struct intel_crtc
> *crtc)
>  				wm_state->wm[level].primary = wm;
>  				break;
>  			case DRM_PLANE_TYPE_OVERLAY:
> -				sprite = plane->plane;
> +				sprite = vlv_sprite_id(plane->id);
>  				wm_state->wm[level].sprite[sprite] =
> wm;
>  				break;
>  			}
> @@ -1169,7 +1175,7 @@ static void vlv_compute_wm(struct intel_crtc
> *crtc)
>  					    wm_state-
> >wm[level].primary);
>  			break;
>  		case DRM_PLANE_TYPE_OVERLAY:
> -			sprite = plane->plane;
> +			sprite = vlv_sprite_id(plane->id);
>  			for (level = 0; level < wm_state-
> >num_levels; level++)
>  				wm_state->sr[level].plane =
>  					min(wm_state-
> >sr[level].plane,
> @@ -1198,17 +1204,23 @@ static void vlv_pipe_set_fifo_size(struct
> intel_crtc *crtc)
>  	int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
>  
>  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> -		if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
> -			WARN_ON(plane->wm.fifo_size != 63);
> -			continue;
> -		}
> -
> -		if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
> +		switch (plane->id) {
> +		case PLANE_PRIMARY:
>  			sprite0_start = plane->wm.fifo_size;
> -		else if (plane->plane == 0)
> +			break;
> +		case PLANE_SPRITE0:
>  			sprite1_start = sprite0_start + plane-
> >wm.fifo_size;
> -		else
> +			break;
> +		case PLANE_SPRITE1:
>  			fifo_size = sprite1_start + plane-
> >wm.fifo_size;
> +			break;
> +		case PLANE_CURSOR:
> +			WARN_ON(plane->wm.fifo_size != 63);
> +			break;
> +		default:
> +			MISSING_CASE(plane->id);
> +			break;
> +		}
>  	}
>  
>  	WARN_ON(fifo_size != 512 - 1);
> @@ -4505,21 +4517,8 @@ void vlv_wm_get_hw_state(struct drm_device
> *dev)
>  
>  	vlv_read_wm_values(dev_priv, wm);
>  
> -	for_each_intel_plane(dev, plane) {
> -		switch (plane->base.type) {
> -			int sprite;
> -		case DRM_PLANE_TYPE_CURSOR:
> -			plane->wm.fifo_size = 63;
> -			break;
> -		case DRM_PLANE_TYPE_PRIMARY:
> -			plane->wm.fifo_size =
> vlv_get_fifo_size(dev_priv, plane->pipe, 0);
> -			break;
> -		case DRM_PLANE_TYPE_OVERLAY:
> -			sprite = plane->plane;
> -			plane->wm.fifo_size =
> vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
> -			break;
> -		}
> -	}
> +	for_each_intel_plane(dev, plane)
> +		plane->wm.fifo_size = vlv_get_fifo_size(plane);
>  
>  	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  	wm->level = VLV_WM_LEVEL_PM2;
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Re: [PATCH 7/9] drm/i915: Use enum plane_id in VLV/CHV wm code

[Ville Syrjälä]

On Thu, Nov 17, 2016 at 06:29:45PM -0200, Paulo Zanoni wrote:
> Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> escreveu:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Let's try not to abuse plane->plane for sprites on VLV/CHV and
> > instead
> > use plane->id. Since out watermark structures aren't entirely plane
> > type
> > agnostic (for now) and start indexing sprites from 0  we'll add a
> > small
> > helper to convert between the two bases.
> 
> I'm not sure I like this one. We've been using plane_id for the actual
> prim/spr/cur IDs, and now we use plane_id for something that's supposed
> to mean A/B/C. I really think we should have different words to refer
> to the two things. I think this goes back to Matt's renaming discussion
> we've been having in patch 2. Let's solve it there first before we
> revisit this patch. I'm still not sure what would be the ideal solution
> here, I'll spend some time thinking.

Replied to the wrong patch?

> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 73 ++++++++++++++++++++-----------
> > ----------
> >  1 file changed, 36 insertions(+), 37 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index fd8cbc224b07..b1ad09e458ca 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -371,12 +371,15 @@ static const int pessimal_latency_ns = 5000;
> >  #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
> >  	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >>
> > (hi_shift)) & 0x1) << 8))
> >  
> > -static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
> > -			      enum pipe pipe, int plane)
> > +static int vlv_get_fifo_size(struct intel_plane *plane)
> >  {
> > +	struct drm_i915_private *dev_priv = to_i915(plane-
> > >base.dev);
> >  	int sprite0_start, sprite1_start, size;
> >  
> > -	switch (pipe) {
> > +	if (plane->id == PLANE_CURSOR)
> > +		return 63;
> > +
> > +	switch (plane->pipe) {
> >  		uint32_t dsparb, dsparb2, dsparb3;
> >  	case PIPE_A:
> >  		dsparb = I915_READ(DSPARB);
> > @@ -400,24 +403,21 @@ static int vlv_get_fifo_size(struct
> > drm_i915_private *dev_priv,
> >  		return 0;
> >  	}
> >  
> > -	switch (plane) {
> > -	case 0:
> > +	switch (plane->id) {
> > +	case PLANE_PRIMARY:
> >  		size = sprite0_start;
> >  		break;
> > -	case 1:
> > +	case PLANE_SPRITE0:
> >  		size = sprite1_start - sprite0_start;
> >  		break;
> > -	case 2:
> > +	case PLANE_SPRITE1:
> >  		size = 512 - 1 - sprite1_start;
> >  		break;
> >  	default:
> >  		return 0;
> >  	}
> >  
> > -	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
> > -		      pipe_name(pipe), plane == 0 ? "primary" :
> > "sprite",
> > -		      plane == 0 ? plane_name(pipe) :
> > sprite_name(pipe, plane - 1),
> > -		      size);
> > +	DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
> >  
> >  	return size;
> >  }
> > @@ -1054,6 +1054,12 @@ static void vlv_compute_fifo(struct intel_crtc
> > *crtc)
> >  	WARN_ON(fifo_left != 0);
> >  }
> >  
> > +/* FIXME kill me */
> > +static inline int vlv_sprite_id(enum plane_id plane_id)
> > +{
> > +	return plane_id - PLANE_SPRITE0;
> > +}
> > +
> >  static void vlv_invert_wms(struct intel_crtc *crtc)
> >  {
> >  	struct vlv_wm_state *wm_state = &crtc->wm_state;
> > @@ -1079,7 +1085,7 @@ static void vlv_invert_wms(struct intel_crtc
> > *crtc)
> >  					wm_state->wm[level].primary;
> >  				break;
> >  			case DRM_PLANE_TYPE_OVERLAY:
> > -				sprite = plane->plane;
> > +				sprite = vlv_sprite_id(plane->id);
> >  				wm_state->wm[level].sprite[sprite] =
> > plane->wm.fifo_size -
> >  					wm_state-
> > >wm[level].sprite[sprite];
> >  				break;
> > @@ -1143,7 +1149,7 @@ static void vlv_compute_wm(struct intel_crtc
> > *crtc)
> >  				wm_state->wm[level].primary = wm;
> >  				break;
> >  			case DRM_PLANE_TYPE_OVERLAY:
> > -				sprite = plane->plane;
> > +				sprite = vlv_sprite_id(plane->id);
> >  				wm_state->wm[level].sprite[sprite] =
> > wm;
> >  				break;
> >  			}
> > @@ -1169,7 +1175,7 @@ static void vlv_compute_wm(struct intel_crtc
> > *crtc)
> >  					    wm_state-
> > >wm[level].primary);
> >  			break;
> >  		case DRM_PLANE_TYPE_OVERLAY:
> > -			sprite = plane->plane;
> > +			sprite = vlv_sprite_id(plane->id);
> >  			for (level = 0; level < wm_state-
> > >num_levels; level++)
> >  				wm_state->sr[level].plane =
> >  					min(wm_state-
> > >sr[level].plane,
> > @@ -1198,17 +1204,23 @@ static void vlv_pipe_set_fifo_size(struct
> > intel_crtc *crtc)
> >  	int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
> >  
> >  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > -		if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
> > -			WARN_ON(plane->wm.fifo_size != 63);
> > -			continue;
> > -		}
> > -
> > -		if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
> > +		switch (plane->id) {
> > +		case PLANE_PRIMARY:
> >  			sprite0_start = plane->wm.fifo_size;
> > -		else if (plane->plane == 0)
> > +			break;
> > +		case PLANE_SPRITE0:
> >  			sprite1_start = sprite0_start + plane-
> > >wm.fifo_size;
> > -		else
> > +			break;
> > +		case PLANE_SPRITE1:
> >  			fifo_size = sprite1_start + plane-
> > >wm.fifo_size;
> > +			break;
> > +		case PLANE_CURSOR:
> > +			WARN_ON(plane->wm.fifo_size != 63);
> > +			break;
> > +		default:
> > +			MISSING_CASE(plane->id);
> > +			break;
> > +		}
> >  	}
> >  
> >  	WARN_ON(fifo_size != 512 - 1);
> > @@ -4505,21 +4517,8 @@ void vlv_wm_get_hw_state(struct drm_device
> > *dev)
> >  
> >  	vlv_read_wm_values(dev_priv, wm);
> >  
> > -	for_each_intel_plane(dev, plane) {
> > -		switch (plane->base.type) {
> > -			int sprite;
> > -		case DRM_PLANE_TYPE_CURSOR:
> > -			plane->wm.fifo_size = 63;
> > -			break;
> > -		case DRM_PLANE_TYPE_PRIMARY:
> > -			plane->wm.fifo_size =
> > vlv_get_fifo_size(dev_priv, plane->pipe, 0);
> > -			break;
> > -		case DRM_PLANE_TYPE_OVERLAY:
> > -			sprite = plane->plane;
> > -			plane->wm.fifo_size =
> > vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
> > -			break;
> > -		}
> > -	}
> > +	for_each_intel_plane(dev, plane)
> > +		plane->wm.fifo_size = vlv_get_fifo_size(plane);
> >  
> >  	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> >  	wm->level = VLV_WM_LEVEL_PM2;

-- 
Ville Syrjälä
Intel OTC
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[PATCH 8/9] drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now we've rename the local plane id variable as 'plane_id' everywhere
except the pre-SKL primary plane code. Let's do the rename there as well
so that we'll free up the name 'plane' for use with struct intel_plane*.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 57 +++++++++++++++++-------------------
 1 file changed, 27 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95644c8cc568..bd084b085421 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3014,10 +3014,9 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_framebuffer *fb = plane_state->base.fb;
-	int plane = intel_crtc->plane;
+	enum plane plane_id = to_intel_plane(primary)->plane;
 	u32 linear_offset;
 	u32 dspcntr;
-	i915_reg_t reg = DSPCNTR(plane);
 	unsigned int rotation = plane_state->base.rotation;
 	int x = plane_state->base.src.x1 >> 16;
 	int y = plane_state->base.src.y1 >> 16;
@@ -3033,16 +3032,16 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
 		/* pipesrc and dspsize control the size that is scaled from,
 		 * which should always be the user's requested size.
 		 */
-		I915_WRITE(DSPSIZE(plane),
+		I915_WRITE(DSPSIZE(plane_id),
 			   ((crtc_state->pipe_src_h - 1) << 16) |
 			   (crtc_state->pipe_src_w - 1));
-		I915_WRITE(DSPPOS(plane), 0);
-	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
-		I915_WRITE(PRIMSIZE(plane),
+		I915_WRITE(DSPPOS(plane_id), 0);
+	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
+		I915_WRITE(PRIMSIZE(plane_id),
 			   ((crtc_state->pipe_src_h - 1) << 16) |
 			   (crtc_state->pipe_src_w - 1));
-		I915_WRITE(PRIMPOS(plane), 0);
-		I915_WRITE(PRIMCNSTALPHA(plane), 0);
+		I915_WRITE(PRIMPOS(plane_id), 0);
+		I915_WRITE(PRIMCNSTALPHA(plane_id), 0);
 	}
 
 	switch (fb->pixel_format) {
@@ -3099,21 +3098,21 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
 	intel_crtc->adjusted_x = x;
 	intel_crtc->adjusted_y = y;
 
-	I915_WRITE(reg, dspcntr);
+	I915_WRITE(DSPCNTR(plane_id), dspcntr);
 
-	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
+	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
 	if (INTEL_INFO(dev)->gen >= 4) {
-		I915_WRITE(DSPSURF(plane),
+		I915_WRITE(DSPSURF(plane_id),
 			   intel_fb_gtt_offset(fb, rotation) +
 			   intel_crtc->dspaddr_offset);
-		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
-		I915_WRITE(DSPLINOFF(plane), linear_offset);
+		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
+		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
 	} else {
-		I915_WRITE(DSPADDR(plane),
+		I915_WRITE(DSPADDR(plane_id),
 			   intel_fb_gtt_offset(fb, rotation) +
 			   intel_crtc->dspaddr_offset);
 	}
-	POSTING_READ(reg);
+	POSTING_READ(DSPCNTR(plane_id));
 }
 
 static void i9xx_disable_primary_plane(struct drm_plane *primary,
@@ -3121,15 +3120,14 @@ static void i9xx_disable_primary_plane(struct drm_plane *primary,
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int plane = intel_crtc->plane;
+	enum plane plane_id = to_intel_plane(primary)->plane;
 
-	I915_WRITE(DSPCNTR(plane), 0);
+	I915_WRITE(DSPCNTR(plane_id), 0);
 	if (INTEL_INFO(dev_priv)->gen >= 4)
-		I915_WRITE(DSPSURF(plane), 0);
+		I915_WRITE(DSPSURF(plane_id), 0);
 	else
-		I915_WRITE(DSPADDR(plane), 0);
-	POSTING_READ(DSPCNTR(plane));
+		I915_WRITE(DSPADDR(plane_id), 0);
+	POSTING_READ(DSPCNTR(plane_id));
 }
 
 static void ironlake_update_primary_plane(struct drm_plane *primary,
@@ -3140,10 +3138,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_framebuffer *fb = plane_state->base.fb;
-	int plane = intel_crtc->plane;
+	enum plane plane_id = to_intel_plane(primary)->plane;
 	u32 linear_offset;
 	u32 dspcntr;
-	i915_reg_t reg = DSPCNTR(plane);
 	unsigned int rotation = plane_state->base.rotation;
 	int x = plane_state->base.src.x1 >> 16;
 	int y = plane_state->base.src.y1 >> 16;
@@ -3202,19 +3199,19 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
 	intel_crtc->adjusted_x = x;
 	intel_crtc->adjusted_y = y;
 
-	I915_WRITE(reg, dspcntr);
+	I915_WRITE(DSPCNTR(plane_id), dspcntr);
 
-	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
-	I915_WRITE(DSPSURF(plane),
+	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
+	I915_WRITE(DSPSURF(plane_id),
 		   intel_fb_gtt_offset(fb, rotation) +
 		   intel_crtc->dspaddr_offset);
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
+		I915_WRITE(DSPOFFSET(plane_id), (y << 16) | x);
 	} else {
-		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
-		I915_WRITE(DSPLINOFF(plane), linear_offset);
+		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
+		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
 	}
-	POSTING_READ(reg);
+	POSTING_READ(DSPCNTR(plane_id));
 }
 
 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
-- 
2.7.4

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Re: [PATCH 8/9] drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code

[Paulo Zanoni]

Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now we've rename the local plane id variable as 'plane_id' everywhere
> except the pre-SKL primary plane code. Let's do the rename there as
> well
> so that we'll free up the name 'plane' for use with struct
> intel_plane*.

As you pointed, my second email do patch 7 was supposed to be a reply
to this patch. So let's move the discussion to the appropriate thread.
And I'll try to better write my argumentation here.

I think this series does a really nice job of consistently using the
term "plane_id" to refer to the plane Z ordering that we have in the
newer platforms, while keeping "plane" as the variable that refers to
the HW plane (A/B/C) the struct represents. And, IMHO, this patch goes
against that trend, since it starts using plane_id to talk about A/B/C.

I see your goal is to leave the "plane" namespace restricted to
variables that point to our plane structs, but I think that if we're
going to do this, we should probably use something different than
plane_id when talking about the hw a/b/c planes. So maybe using a
different variable name here would solve the problem.

What do you think?

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 57 +++++++++++++++++---------
> ----------
>  1 file changed, 27 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 95644c8cc568..bd084b085421 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3014,10 +3014,9 @@ static void i9xx_update_primary_plane(struct
> drm_plane *primary,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >base.crtc);
>  	struct drm_framebuffer *fb = plane_state->base.fb;
> -	int plane = intel_crtc->plane;
> +	enum plane plane_id = to_intel_plane(primary)->plane;
>  	u32 linear_offset;
>  	u32 dspcntr;
> -	i915_reg_t reg = DSPCNTR(plane);
>  	unsigned int rotation = plane_state->base.rotation;
>  	int x = plane_state->base.src.x1 >> 16;
>  	int y = plane_state->base.src.y1 >> 16;
> @@ -3033,16 +3032,16 @@ static void i9xx_update_primary_plane(struct
> drm_plane *primary,
>  		/* pipesrc and dspsize control the size that is
> scaled from,
>  		 * which should always be the user's requested size.
>  		 */
> -		I915_WRITE(DSPSIZE(plane),
> +		I915_WRITE(DSPSIZE(plane_id),
>  			   ((crtc_state->pipe_src_h - 1) << 16) |
>  			   (crtc_state->pipe_src_w - 1));
> -		I915_WRITE(DSPPOS(plane), 0);
> -	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> -		I915_WRITE(PRIMSIZE(plane),
> +		I915_WRITE(DSPPOS(plane_id), 0);
> +	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
> +		I915_WRITE(PRIMSIZE(plane_id),
>  			   ((crtc_state->pipe_src_h - 1) << 16) |
>  			   (crtc_state->pipe_src_w - 1));
> -		I915_WRITE(PRIMPOS(plane), 0);
> -		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> +		I915_WRITE(PRIMPOS(plane_id), 0);
> +		I915_WRITE(PRIMCNSTALPHA(plane_id), 0);
>  	}
>  
>  	switch (fb->pixel_format) {
> @@ -3099,21 +3098,21 @@ static void i9xx_update_primary_plane(struct
> drm_plane *primary,
>  	intel_crtc->adjusted_x = x;
>  	intel_crtc->adjusted_y = y;
>  
> -	I915_WRITE(reg, dspcntr);
> +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
>  
> -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
>  	if (INTEL_INFO(dev)->gen >= 4) {
> -		I915_WRITE(DSPSURF(plane),
> +		I915_WRITE(DSPSURF(plane_id),
>  			   intel_fb_gtt_offset(fb, rotation) +
>  			   intel_crtc->dspaddr_offset);
> -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
>  	} else {
> -		I915_WRITE(DSPADDR(plane),
> +		I915_WRITE(DSPADDR(plane_id),
>  			   intel_fb_gtt_offset(fb, rotation) +
>  			   intel_crtc->dspaddr_offset);
>  	}
> -	POSTING_READ(reg);
> +	POSTING_READ(DSPCNTR(plane_id));
>  }
>  
>  static void i9xx_disable_primary_plane(struct drm_plane *primary,
> @@ -3121,15 +3120,14 @@ static void i9xx_disable_primary_plane(struct
> drm_plane *primary,
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	int plane = intel_crtc->plane;
> +	enum plane plane_id = to_intel_plane(primary)->plane;
>  
> -	I915_WRITE(DSPCNTR(plane), 0);
> +	I915_WRITE(DSPCNTR(plane_id), 0);
>  	if (INTEL_INFO(dev_priv)->gen >= 4)
> -		I915_WRITE(DSPSURF(plane), 0);
> +		I915_WRITE(DSPSURF(plane_id), 0);
>  	else
> -		I915_WRITE(DSPADDR(plane), 0);
> -	POSTING_READ(DSPCNTR(plane));
> +		I915_WRITE(DSPADDR(plane_id), 0);
> +	POSTING_READ(DSPCNTR(plane_id));
>  }
>  
>  static void ironlake_update_primary_plane(struct drm_plane *primary,
> @@ -3140,10 +3138,9 @@ static void
> ironlake_update_primary_plane(struct drm_plane *primary,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >base.crtc);
>  	struct drm_framebuffer *fb = plane_state->base.fb;
> -	int plane = intel_crtc->plane;
> +	enum plane plane_id = to_intel_plane(primary)->plane;
>  	u32 linear_offset;
>  	u32 dspcntr;
> -	i915_reg_t reg = DSPCNTR(plane);
>  	unsigned int rotation = plane_state->base.rotation;
>  	int x = plane_state->base.src.x1 >> 16;
>  	int y = plane_state->base.src.y1 >> 16;
> @@ -3202,19 +3199,19 @@ static void
> ironlake_update_primary_plane(struct drm_plane *primary,
>  	intel_crtc->adjusted_x = x;
>  	intel_crtc->adjusted_y = y;
>  
> -	I915_WRITE(reg, dspcntr);
> +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
>  
> -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> -	I915_WRITE(DSPSURF(plane),
> +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
> +	I915_WRITE(DSPSURF(plane_id),
>  		   intel_fb_gtt_offset(fb, rotation) +
>  		   intel_crtc->dspaddr_offset);
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
> +		I915_WRITE(DSPOFFSET(plane_id), (y << 16) | x);
>  	} else {
> -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
>  	}
> -	POSTING_READ(reg);
> +	POSTING_READ(DSPCNTR(plane_id));
>  }
>  
>  u32 intel_fb_stride_alignment(const struct drm_i915_private
> *dev_priv,
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Re: [PATCH 8/9] drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code

[Ville Syrjälä]

On Fri, Nov 18, 2016 at 12:25:30PM -0200, Paulo Zanoni wrote:
> Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> escreveu:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Now we've rename the local plane id variable as 'plane_id' everywhere
> > except the pre-SKL primary plane code. Let's do the rename there as
> > well
> > so that we'll free up the name 'plane' for use with struct
> > intel_plane*.
> 
> As you pointed, my second email do patch 7 was supposed to be a reply
> to this patch. So let's move the discussion to the appropriate thread.
> And I'll try to better write my argumentation here.
> 
> I think this series does a really nice job of consistently using the
> term "plane_id" to refer to the plane Z ordering that we have in the
> newer platforms, while keeping "plane" as the variable that refers to
> the HW plane (A/B/C) the struct represents. And, IMHO, this patch goes
> against that trend, since it starts using plane_id to talk about A/B/C.
> 
> I see your goal is to leave the "plane" namespace restricted to
> variables that point to our plane structs, but I think that if we're
> going to do this, we should probably use something different than
> plane_id when talking about the hw a/b/c planes. So maybe using a
> different variable name here would solve the problem.
> 
> What do you think?

Perhaps. But it's hard coming up with a name that pleases the eye
sufficiently.

> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 57 +++++++++++++++++---------
> > ----------
> >  1 file changed, 27 insertions(+), 30 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 95644c8cc568..bd084b085421 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3014,10 +3014,9 @@ static void i9xx_update_primary_plane(struct
> > drm_plane *primary,
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> > >base.crtc);
> >  	struct drm_framebuffer *fb = plane_state->base.fb;
> > -	int plane = intel_crtc->plane;
> > +	enum plane plane_id = to_intel_plane(primary)->plane;
> >  	u32 linear_offset;
> >  	u32 dspcntr;
> > -	i915_reg_t reg = DSPCNTR(plane);
> >  	unsigned int rotation = plane_state->base.rotation;
> >  	int x = plane_state->base.src.x1 >> 16;
> >  	int y = plane_state->base.src.y1 >> 16;
> > @@ -3033,16 +3032,16 @@ static void i9xx_update_primary_plane(struct
> > drm_plane *primary,
> >  		/* pipesrc and dspsize control the size that is
> > scaled from,
> >  		 * which should always be the user's requested size.
> >  		 */
> > -		I915_WRITE(DSPSIZE(plane),
> > +		I915_WRITE(DSPSIZE(plane_id),
> >  			   ((crtc_state->pipe_src_h - 1) << 16) |
> >  			   (crtc_state->pipe_src_w - 1));
> > -		I915_WRITE(DSPPOS(plane), 0);
> > -	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> > -		I915_WRITE(PRIMSIZE(plane),
> > +		I915_WRITE(DSPPOS(plane_id), 0);
> > +	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
> > +		I915_WRITE(PRIMSIZE(plane_id),
> >  			   ((crtc_state->pipe_src_h - 1) << 16) |
> >  			   (crtc_state->pipe_src_w - 1));
> > -		I915_WRITE(PRIMPOS(plane), 0);
> > -		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > +		I915_WRITE(PRIMPOS(plane_id), 0);
> > +		I915_WRITE(PRIMCNSTALPHA(plane_id), 0);
> >  	}
> >  
> >  	switch (fb->pixel_format) {
> > @@ -3099,21 +3098,21 @@ static void i9xx_update_primary_plane(struct
> > drm_plane *primary,
> >  	intel_crtc->adjusted_x = x;
> >  	intel_crtc->adjusted_y = y;
> >  
> > -	I915_WRITE(reg, dspcntr);
> > +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
> >  
> > -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> > +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
> >  	if (INTEL_INFO(dev)->gen >= 4) {
> > -		I915_WRITE(DSPSURF(plane),
> > +		I915_WRITE(DSPSURF(plane_id),
> >  			   intel_fb_gtt_offset(fb, rotation) +
> >  			   intel_crtc->dspaddr_offset);
> > -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> > -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> > +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> > +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
> >  	} else {
> > -		I915_WRITE(DSPADDR(plane),
> > +		I915_WRITE(DSPADDR(plane_id),
> >  			   intel_fb_gtt_offset(fb, rotation) +
> >  			   intel_crtc->dspaddr_offset);
> >  	}
> > -	POSTING_READ(reg);
> > +	POSTING_READ(DSPCNTR(plane_id));
> >  }
> >  
> >  static void i9xx_disable_primary_plane(struct drm_plane *primary,
> > @@ -3121,15 +3120,14 @@ static void i9xx_disable_primary_plane(struct
> > drm_plane *primary,
> >  {
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	int plane = intel_crtc->plane;
> > +	enum plane plane_id = to_intel_plane(primary)->plane;
> >  
> > -	I915_WRITE(DSPCNTR(plane), 0);
> > +	I915_WRITE(DSPCNTR(plane_id), 0);
> >  	if (INTEL_INFO(dev_priv)->gen >= 4)
> > -		I915_WRITE(DSPSURF(plane), 0);
> > +		I915_WRITE(DSPSURF(plane_id), 0);
> >  	else
> > -		I915_WRITE(DSPADDR(plane), 0);
> > -	POSTING_READ(DSPCNTR(plane));
> > +		I915_WRITE(DSPADDR(plane_id), 0);
> > +	POSTING_READ(DSPCNTR(plane_id));
> >  }
> >  
> >  static void ironlake_update_primary_plane(struct drm_plane *primary,
> > @@ -3140,10 +3138,9 @@ static void
> > ironlake_update_primary_plane(struct drm_plane *primary,
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> > >base.crtc);
> >  	struct drm_framebuffer *fb = plane_state->base.fb;
> > -	int plane = intel_crtc->plane;
> > +	enum plane plane_id = to_intel_plane(primary)->plane;
> >  	u32 linear_offset;
> >  	u32 dspcntr;
> > -	i915_reg_t reg = DSPCNTR(plane);
> >  	unsigned int rotation = plane_state->base.rotation;
> >  	int x = plane_state->base.src.x1 >> 16;
> >  	int y = plane_state->base.src.y1 >> 16;
> > @@ -3202,19 +3199,19 @@ static void
> > ironlake_update_primary_plane(struct drm_plane *primary,
> >  	intel_crtc->adjusted_x = x;
> >  	intel_crtc->adjusted_y = y;
> >  
> > -	I915_WRITE(reg, dspcntr);
> > +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
> >  
> > -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> > -	I915_WRITE(DSPSURF(plane),
> > +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
> > +	I915_WRITE(DSPSURF(plane_id),
> >  		   intel_fb_gtt_offset(fb, rotation) +
> >  		   intel_crtc->dspaddr_offset);
> >  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > -		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
> > +		I915_WRITE(DSPOFFSET(plane_id), (y << 16) | x);
> >  	} else {
> > -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> > -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> > +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> > +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
> >  	}
> > -	POSTING_READ(reg);
> > +	POSTING_READ(DSPCNTR(plane_id));
> >  }
> >  
> >  u32 intel_fb_stride_alignment(const struct drm_i915_private
> > *dev_priv,

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 8/9] drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code

[Paulo Zanoni]

Em Sex, 2016-11-18 às 16:34 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 18, 2016 at 12:25:30PM -0200, Paulo Zanoni wrote:
> > 
> > Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> > escreveu:
> > > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Now we've rename the local plane id variable as 'plane_id'
> > > everywhere
> > > except the pre-SKL primary plane code. Let's do the rename there
> > > as
> > > well
> > > so that we'll free up the name 'plane' for use with struct
> > > intel_plane*.
> > 
> > As you pointed, my second email do patch 7 was supposed to be a
> > reply
> > to this patch. So let's move the discussion to the appropriate
> > thread.
> > And I'll try to better write my argumentation here.
> > 
> > I think this series does a really nice job of consistently using
> > the
> > term "plane_id" to refer to the plane Z ordering that we have in
> > the
> > newer platforms, while keeping "plane" as the variable that refers
> > to
> > the HW plane (A/B/C) the struct represents. And, IMHO, this patch
> > goes
> > against that trend, since it starts using plane_id to talk about
> > A/B/C.
> > 
> > I see your goal is to leave the "plane" namespace restricted to
> > variables that point to our plane structs, but I think that if
> > we're
> > going to do this, we should probably use something different than
> > plane_id when talking about the hw a/b/c planes. So maybe using a
> > different variable name here would solve the problem.
> > 
> > What do you think?
> 
> Perhaps. But it's hard coming up with a name that pleases the eye
> sufficiently.

But then, if there's no better name, isn't just "plane" better than
"plane_id" here since it allows us to keep the "plane" namespace for
the legacy A/B/C assignment, while plane_id stays for the newer things?

> 
> > 
> > 
> > > 
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 57 +++++++++++++++++-----
> > > ----
> > > ----------
> > >  1 file changed, 27 insertions(+), 30 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 95644c8cc568..bd084b085421 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3014,10 +3014,9 @@ static void
> > > i9xx_update_primary_plane(struct
> > > drm_plane *primary,
> > >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > >  	struct intel_crtc *intel_crtc =
> > > to_intel_crtc(crtc_state-
> > > > 
> > > > base.crtc);
> > >  	struct drm_framebuffer *fb = plane_state->base.fb;
> > > -	int plane = intel_crtc->plane;
> > > +	enum plane plane_id = to_intel_plane(primary)->plane;
> > >  	u32 linear_offset;
> > >  	u32 dspcntr;
> > > -	i915_reg_t reg = DSPCNTR(plane);
> > >  	unsigned int rotation = plane_state->base.rotation;
> > >  	int x = plane_state->base.src.x1 >> 16;
> > >  	int y = plane_state->base.src.y1 >> 16;
> > > @@ -3033,16 +3032,16 @@ static void
> > > i9xx_update_primary_plane(struct
> > > drm_plane *primary,
> > >  		/* pipesrc and dspsize control the size that is
> > > scaled from,
> > >  		 * which should always be the user's requested
> > > size.
> > >  		 */
> > > -		I915_WRITE(DSPSIZE(plane),
> > > +		I915_WRITE(DSPSIZE(plane_id),
> > >  			   ((crtc_state->pipe_src_h - 1) << 16)
> > > |
> > >  			   (crtc_state->pipe_src_w - 1));
> > > -		I915_WRITE(DSPPOS(plane), 0);
> > > -	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B)
> > > {
> > > -		I915_WRITE(PRIMSIZE(plane),
> > > +		I915_WRITE(DSPPOS(plane_id), 0);
> > > +	} else if (IS_CHERRYVIEW(dev_priv) && plane_id ==
> > > PLANE_B) {
> > > +		I915_WRITE(PRIMSIZE(plane_id),
> > >  			   ((crtc_state->pipe_src_h - 1) << 16)
> > > |
> > >  			   (crtc_state->pipe_src_w - 1));
> > > -		I915_WRITE(PRIMPOS(plane), 0);
> > > -		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > > +		I915_WRITE(PRIMPOS(plane_id), 0);
> > > +		I915_WRITE(PRIMCNSTALPHA(plane_id), 0);
> > >  	}
> > >  
> > >  	switch (fb->pixel_format) {
> > > @@ -3099,21 +3098,21 @@ static void
> > > i9xx_update_primary_plane(struct
> > > drm_plane *primary,
> > >  	intel_crtc->adjusted_x = x;
> > >  	intel_crtc->adjusted_y = y;
> > >  
> > > -	I915_WRITE(reg, dspcntr);
> > > +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
> > >  
> > > -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> > > +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
> > >  	if (INTEL_INFO(dev)->gen >= 4) {
> > > -		I915_WRITE(DSPSURF(plane),
> > > +		I915_WRITE(DSPSURF(plane_id),
> > >  			   intel_fb_gtt_offset(fb, rotation) +
> > >  			   intel_crtc->dspaddr_offset);
> > > -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> > > -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> > > +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> > > +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
> > >  	} else {
> > > -		I915_WRITE(DSPADDR(plane),
> > > +		I915_WRITE(DSPADDR(plane_id),
> > >  			   intel_fb_gtt_offset(fb, rotation) +
> > >  			   intel_crtc->dspaddr_offset);
> > >  	}
> > > -	POSTING_READ(reg);
> > > +	POSTING_READ(DSPCNTR(plane_id));
> > >  }
> > >  
> > >  static void i9xx_disable_primary_plane(struct drm_plane
> > > *primary,
> > > @@ -3121,15 +3120,14 @@ static void
> > > i9xx_disable_primary_plane(struct
> > > drm_plane *primary,
> > >  {
> > >  	struct drm_device *dev = crtc->dev;
> > >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > -	int plane = intel_crtc->plane;
> > > +	enum plane plane_id = to_intel_plane(primary)->plane;
> > >  
> > > -	I915_WRITE(DSPCNTR(plane), 0);
> > > +	I915_WRITE(DSPCNTR(plane_id), 0);
> > >  	if (INTEL_INFO(dev_priv)->gen >= 4)
> > > -		I915_WRITE(DSPSURF(plane), 0);
> > > +		I915_WRITE(DSPSURF(plane_id), 0);
> > >  	else
> > > -		I915_WRITE(DSPADDR(plane), 0);
> > > -	POSTING_READ(DSPCNTR(plane));
> > > +		I915_WRITE(DSPADDR(plane_id), 0);
> > > +	POSTING_READ(DSPCNTR(plane_id));
> > >  }
> > >  
> > >  static void ironlake_update_primary_plane(struct drm_plane
> > > *primary,
> > > @@ -3140,10 +3138,9 @@ static void
> > > ironlake_update_primary_plane(struct drm_plane *primary,
> > >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > >  	struct intel_crtc *intel_crtc =
> > > to_intel_crtc(crtc_state-
> > > > 
> > > > base.crtc);
> > >  	struct drm_framebuffer *fb = plane_state->base.fb;
> > > -	int plane = intel_crtc->plane;
> > > +	enum plane plane_id = to_intel_plane(primary)->plane;
> > >  	u32 linear_offset;
> > >  	u32 dspcntr;
> > > -	i915_reg_t reg = DSPCNTR(plane);
> > >  	unsigned int rotation = plane_state->base.rotation;
> > >  	int x = plane_state->base.src.x1 >> 16;
> > >  	int y = plane_state->base.src.y1 >> 16;
> > > @@ -3202,19 +3199,19 @@ static void
> > > ironlake_update_primary_plane(struct drm_plane *primary,
> > >  	intel_crtc->adjusted_x = x;
> > >  	intel_crtc->adjusted_y = y;
> > >  
> > > -	I915_WRITE(reg, dspcntr);
> > > +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
> > >  
> > > -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> > > -	I915_WRITE(DSPSURF(plane),
> > > +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
> > > +	I915_WRITE(DSPSURF(plane_id),
> > >  		   intel_fb_gtt_offset(fb, rotation) +
> > >  		   intel_crtc->dspaddr_offset);
> > >  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > -		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
> > > +		I915_WRITE(DSPOFFSET(plane_id), (y << 16) | x);
> > >  	} else {
> > > -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> > > -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> > > +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> > > +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
> > >  	}
> > > -	POSTING_READ(reg);
> > > +	POSTING_READ(DSPCNTR(plane_id));
> > >  }
> > >  
> > >  u32 intel_fb_stride_alignment(const struct drm_i915_private
> > > *dev_priv,
> 
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Re: [PATCH 8/9] drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code

[Ville Syrjälä]

On Fri, Nov 18, 2016 at 06:41:39PM -0200, Paulo Zanoni wrote:
> Em Sex, 2016-11-18 às 16:34 +0200, Ville Syrjälä escreveu:
> > On Fri, Nov 18, 2016 at 12:25:30PM -0200, Paulo Zanoni wrote:
> > > 
> > > Em Ter, 2016-11-08 às 16:47 +0200, ville.syrjala@linux.intel.com
> > > escreveu:
> > > > 
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Now we've rename the local plane id variable as 'plane_id'
> > > > everywhere
> > > > except the pre-SKL primary plane code. Let's do the rename there
> > > > as
> > > > well
> > > > so that we'll free up the name 'plane' for use with struct
> > > > intel_plane*.
> > > 
> > > As you pointed, my second email do patch 7 was supposed to be a
> > > reply
> > > to this patch. So let's move the discussion to the appropriate
> > > thread.
> > > And I'll try to better write my argumentation here.
> > > 
> > > I think this series does a really nice job of consistently using
> > > the
> > > term "plane_id" to refer to the plane Z ordering that we have in
> > > the
> > > newer platforms, while keeping "plane" as the variable that refers
> > > to
> > > the HW plane (A/B/C) the struct represents. And, IMHO, this patch
> > > goes
> > > against that trend, since it starts using plane_id to talk about
> > > A/B/C.
> > > 
> > > I see your goal is to leave the "plane" namespace restricted to
> > > variables that point to our plane structs, but I think that if
> > > we're
> > > going to do this, we should probably use something different than
> > > plane_id when talking about the hw a/b/c planes. So maybe using a
> > > different variable name here would solve the problem.
> > > 
> > > What do you think?
> > 
> > Perhaps. But it's hard coming up with a name that pleases the eye
> > sufficiently.
> 
> But then, if there's no better name, isn't just "plane" better than
> "plane_id" here since it allows us to keep the "plane" namespace for
> the legacy A/B/C assignment, while plane_id stays for the newer things?

But then I can't use 'plane' for the struct intel_plane* which is going
to suck. There's no good answer I fear.

> 
> > 
> > > 
> > > 
> > > > 
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_display.c | 57 +++++++++++++++++-----
> > > > ----
> > > > ----------
> > > >  1 file changed, 27 insertions(+), 30 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index 95644c8cc568..bd084b085421 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -3014,10 +3014,9 @@ static void
> > > > i9xx_update_primary_plane(struct
> > > > drm_plane *primary,
> > > >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > > >  	struct intel_crtc *intel_crtc =
> > > > to_intel_crtc(crtc_state-
> > > > > 
> > > > > base.crtc);
> > > >  	struct drm_framebuffer *fb = plane_state->base.fb;
> > > > -	int plane = intel_crtc->plane;
> > > > +	enum plane plane_id = to_intel_plane(primary)->plane;
> > > >  	u32 linear_offset;
> > > >  	u32 dspcntr;
> > > > -	i915_reg_t reg = DSPCNTR(plane);
> > > >  	unsigned int rotation = plane_state->base.rotation;
> > > >  	int x = plane_state->base.src.x1 >> 16;
> > > >  	int y = plane_state->base.src.y1 >> 16;
> > > > @@ -3033,16 +3032,16 @@ static void
> > > > i9xx_update_primary_plane(struct
> > > > drm_plane *primary,
> > > >  		/* pipesrc and dspsize control the size that is
> > > > scaled from,
> > > >  		 * which should always be the user's requested
> > > > size.
> > > >  		 */
> > > > -		I915_WRITE(DSPSIZE(plane),
> > > > +		I915_WRITE(DSPSIZE(plane_id),
> > > >  			   ((crtc_state->pipe_src_h - 1) << 16)
> > > > |
> > > >  			   (crtc_state->pipe_src_w - 1));
> > > > -		I915_WRITE(DSPPOS(plane), 0);
> > > > -	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B)
> > > > {
> > > > -		I915_WRITE(PRIMSIZE(plane),
> > > > +		I915_WRITE(DSPPOS(plane_id), 0);
> > > > +	} else if (IS_CHERRYVIEW(dev_priv) && plane_id ==
> > > > PLANE_B) {
> > > > +		I915_WRITE(PRIMSIZE(plane_id),
> > > >  			   ((crtc_state->pipe_src_h - 1) << 16)
> > > > |
> > > >  			   (crtc_state->pipe_src_w - 1));
> > > > -		I915_WRITE(PRIMPOS(plane), 0);
> > > > -		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > > > +		I915_WRITE(PRIMPOS(plane_id), 0);
> > > > +		I915_WRITE(PRIMCNSTALPHA(plane_id), 0);
> > > >  	}
> > > >  
> > > >  	switch (fb->pixel_format) {
> > > > @@ -3099,21 +3098,21 @@ static void
> > > > i9xx_update_primary_plane(struct
> > > > drm_plane *primary,
> > > >  	intel_crtc->adjusted_x = x;
> > > >  	intel_crtc->adjusted_y = y;
> > > >  
> > > > -	I915_WRITE(reg, dspcntr);
> > > > +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
> > > >  
> > > > -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> > > > +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
> > > >  	if (INTEL_INFO(dev)->gen >= 4) {
> > > > -		I915_WRITE(DSPSURF(plane),
> > > > +		I915_WRITE(DSPSURF(plane_id),
> > > >  			   intel_fb_gtt_offset(fb, rotation) +
> > > >  			   intel_crtc->dspaddr_offset);
> > > > -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> > > > -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> > > > +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> > > > +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
> > > >  	} else {
> > > > -		I915_WRITE(DSPADDR(plane),
> > > > +		I915_WRITE(DSPADDR(plane_id),
> > > >  			   intel_fb_gtt_offset(fb, rotation) +
> > > >  			   intel_crtc->dspaddr_offset);
> > > >  	}
> > > > -	POSTING_READ(reg);
> > > > +	POSTING_READ(DSPCNTR(plane_id));
> > > >  }
> > > >  
> > > >  static void i9xx_disable_primary_plane(struct drm_plane
> > > > *primary,
> > > > @@ -3121,15 +3120,14 @@ static void
> > > > i9xx_disable_primary_plane(struct
> > > > drm_plane *primary,
> > > >  {
> > > >  	struct drm_device *dev = crtc->dev;
> > > >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > > > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > > -	int plane = intel_crtc->plane;
> > > > +	enum plane plane_id = to_intel_plane(primary)->plane;
> > > >  
> > > > -	I915_WRITE(DSPCNTR(plane), 0);
> > > > +	I915_WRITE(DSPCNTR(plane_id), 0);
> > > >  	if (INTEL_INFO(dev_priv)->gen >= 4)
> > > > -		I915_WRITE(DSPSURF(plane), 0);
> > > > +		I915_WRITE(DSPSURF(plane_id), 0);
> > > >  	else
> > > > -		I915_WRITE(DSPADDR(plane), 0);
> > > > -	POSTING_READ(DSPCNTR(plane));
> > > > +		I915_WRITE(DSPADDR(plane_id), 0);
> > > > +	POSTING_READ(DSPCNTR(plane_id));
> > > >  }
> > > >  
> > > >  static void ironlake_update_primary_plane(struct drm_plane
> > > > *primary,
> > > > @@ -3140,10 +3138,9 @@ static void
> > > > ironlake_update_primary_plane(struct drm_plane *primary,
> > > >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > > >  	struct intel_crtc *intel_crtc =
> > > > to_intel_crtc(crtc_state-
> > > > > 
> > > > > base.crtc);
> > > >  	struct drm_framebuffer *fb = plane_state->base.fb;
> > > > -	int plane = intel_crtc->plane;
> > > > +	enum plane plane_id = to_intel_plane(primary)->plane;
> > > >  	u32 linear_offset;
> > > >  	u32 dspcntr;
> > > > -	i915_reg_t reg = DSPCNTR(plane);
> > > >  	unsigned int rotation = plane_state->base.rotation;
> > > >  	int x = plane_state->base.src.x1 >> 16;
> > > >  	int y = plane_state->base.src.y1 >> 16;
> > > > @@ -3202,19 +3199,19 @@ static void
> > > > ironlake_update_primary_plane(struct drm_plane *primary,
> > > >  	intel_crtc->adjusted_x = x;
> > > >  	intel_crtc->adjusted_y = y;
> > > >  
> > > > -	I915_WRITE(reg, dspcntr);
> > > > +	I915_WRITE(DSPCNTR(plane_id), dspcntr);
> > > >  
> > > > -	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> > > > -	I915_WRITE(DSPSURF(plane),
> > > > +	I915_WRITE(DSPSTRIDE(plane_id), fb->pitches[0]);
> > > > +	I915_WRITE(DSPSURF(plane_id),
> > > >  		   intel_fb_gtt_offset(fb, rotation) +
> > > >  		   intel_crtc->dspaddr_offset);
> > > >  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > > -		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
> > > > +		I915_WRITE(DSPOFFSET(plane_id), (y << 16) | x);
> > > >  	} else {
> > > > -		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> > > > -		I915_WRITE(DSPLINOFF(plane), linear_offset);
> > > > +		I915_WRITE(DSPTILEOFF(plane_id), (y << 16) | x);
> > > > +		I915_WRITE(DSPLINOFF(plane_id), linear_offset);
> > > >  	}
> > > > -	POSTING_READ(reg);
> > > > +	POSTING_READ(DSPCNTR(plane_id));
> > > >  }
> > > >  
> > > >  u32 intel_fb_stride_alignment(const struct drm_i915_private
> > > > *dev_priv,
> > 

-- 
Ville Syrjälä
Intel OTC
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[PATCH 9/9] drm/i915: Don't populate plane->plane for cursors and sprites

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With plane->plane now purely reserved for the primary planes, let's
not even populate it for cursors and sprites. Let's switch the type
to enum plane as well since it's no longer being abused for anything
else.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 1 -
 drivers/gpu/drm/i915/intel_drv.h     | 2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bd084b085421..2174593e5ef5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15202,7 +15202,6 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	cursor->can_scale = false;
 	cursor->max_downscale = 1;
 	cursor->pipe = pipe;
-	cursor->plane = pipe;
 	cursor->id = PLANE_CURSOR;
 	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
 	cursor->check_plane = intel_check_cursor_plane;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a3c696d8bf93..aaef98fed79f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -768,7 +768,7 @@ struct intel_plane_wm_parameters {
 
 struct intel_plane {
 	struct drm_plane base;
-	u8 plane;
+	enum plane plane;
 	enum plane_id id;
 	enum pipe pipe;
 	bool can_scale;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index a922c6382fc7..22489c11c86e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1125,7 +1125,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 	}
 
 	intel_plane->pipe = pipe;
-	intel_plane->plane = plane;
 	intel_plane->id = PLANE_SPRITE0 + plane;
 	intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
 	intel_plane->check_plane = intel_check_sprite_plane;
-- 
2.7.4

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Re: [PATCH 9/9] drm/i915: Don't populate plane->plane for cursors and sprites

[Chris Wilson]

On Tue, Nov 08, 2016 at 04:47:19PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> With plane->plane now purely reserved for the primary planes, let's
> not even populate it for cursors and sprites. Let's switch the type
> to enum plane as well since it's no longer being abused for anything
> else.

Also suggests not starting enum plane from zero.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH 9/9] drm/i915: Don't populate plane->plane for cursors and sprites

[Ville Syrjälä]

On Tue, Nov 08, 2016 at 03:30:33PM +0000, Chris Wilson wrote:
> On Tue, Nov 08, 2016 at 04:47:19PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > With plane->plane now purely reserved for the primary planes, let's
> > not even populate it for cursors and sprites. Let's switch the type
> > to enum plane as well since it's no longer being abused for anything
> > else.
> 
> Also suggests not starting enum plane from zero.

That would complicate the DSPCNTR() etc. macros a bit. Also I think for
gen2/3 I'll be wanting to index watermark related structs and whatnot
with enum plane rather than enum plane_id since the planes<->pipe
mapping isn't fixed. So a non-zero base might make life a bit more
difficult.

-- 
Ville Syrjälä
Intel OTC
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✗ Fi.CI.BAT: warning for drm/i915: Add a per-pipe plane identifier enum

[Patchwork]

== Series Details ==

Series: drm/i915: Add a per-pipe plane identifier enum
URL   : https://patchwork.freedesktop.org/series/14978/
State : warning

== Summary ==

Series 14978v1 drm/i915: Add a per-pipe plane identifier enum
https://patchwork.freedesktop.org/api/1.0/series/14978/revisions/1/mbox/

Test drv_module_reload_basic:
                dmesg-warn -> PASS       (fi-skl-6770hq)
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> DMESG-WARN (fi-skl-6260u)
                pass       -> DMESG-WARN (fi-skl-6700hq)
                pass       -> DMESG-WARN (fi-kbl-7200u)
                pass       -> DMESG-WARN (fi-skl-6700k)
                pass       -> DMESG-WARN (fi-skl-6770hq)
Test kms_busy:
        Subgroup basic-flip-default-c:
                pass       -> DMESG-WARN (fi-bxt-t5700)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-busy-flip-before-cursor-varying-size:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-after-cursor-legacy:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-after-cursor-varying-size:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-before-cursor-legacy:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-before-cursor-varying-size:
                pass       -> DMESG-WARN (fi-skl-6770hq)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-snb-2520m)

fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:244  pass:215  dwarn:1   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:229  dwarn:1   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:221  dwarn:2   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:223  dwarn:7   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:211  dwarn:1   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

9435ffb9ffbfecfa5a429a46af96b1b3fda41d6c drm-intel-nightly: 2016y-11m-08d-13h-53m-48s UTC integration manifest
7631b0d drm/i915: Don't populate plane->plane for cursors and sprites
8584dd5 drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code
addbd43 drm/i915: Use enum plane_id in VLV/CHV wm code
c3354df drm/i915: Use enum plane_id in VLV/CHV sprite code
5dd9250 drm/i915: Use enum plane_id in SKL plane code
ce4f6dd drm/i915: Use enum plane_id in SKL wm code
b325442 drm/i915: Add crtc->plane_ids_mask
69c4249 drm/i915: Add per-pipe plane identifier
cf7f939 drm/i915: Remove some duplicated plane swapping logic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2934/
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✗ Fi.CI.BAT: warning for drm/i915: Add a per-pipe plane identifier enum (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Add a per-pipe plane identifier enum (rev3)
URL   : https://patchwork.freedesktop.org/series/14978/
State : warning

== Summary ==

Series 14978v3 drm/i915: Add a per-pipe plane identifier enum
https://patchwork.freedesktop.org/api/1.0/series/14978/revisions/3/mbox/

Test drv_module_reload_basic:
                dmesg-warn -> PASS       (fi-skl-6770hq)
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> DMESG-WARN (fi-skl-6260u)
                pass       -> DMESG-WARN (fi-skl-6700hq)
                pass       -> DMESG-WARN (fi-skl-6770hq)
                pass       -> DMESG-WARN (fi-skl-6700k)
                pass       -> DMESG-WARN (fi-kbl-7200u)
Test kms_busy:
        Subgroup basic-flip-default-c:
                pass       -> DMESG-WARN (fi-bxt-t5700)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-busy-flip-before-cursor-varying-size:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-after-cursor-legacy:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-after-cursor-varying-size:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-before-cursor-legacy:
                pass       -> DMESG-WARN (fi-skl-6770hq)
        Subgroup basic-flip-before-cursor-varying-size:
                pass       -> DMESG-WARN (fi-skl-6770hq)

fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bxt-t5700     total:244  pass:215  dwarn:1   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:229  dwarn:1   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:221  dwarn:2   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:223  dwarn:7   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

9435ffb9ffbfecfa5a429a46af96b1b3fda41d6c drm-intel-nightly: 2016y-11m-08d-13h-53m-48s UTC integration manifest
ee2cdee drm/i915: Don't populate plane->plane for cursors and sprites
f43966f drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code
04a0e37 drm/i915: Use enum plane_id in VLV/CHV wm code
db5553c drm/i915: Use enum plane_id in VLV/CHV sprite code
6a71330 drm/i915: Use enum plane_id in SKL plane code
e88c3fb drm/i915: Use enum plane_id in SKL wm code
cc004ca drm/i915: Add crtc->plane_ids_mask
616c141 drm/i915: Add per-pipe plane identifier
49d3701 drm/i915: Remove some duplicated plane swapping logic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2935/
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✗ Fi.CI.BAT: warning for drm/i915: Add a per-pipe plane identifier enum (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Add a per-pipe plane identifier enum (rev4)
URL   : https://patchwork.freedesktop.org/series/14978/
State : warning

== Summary ==

Series 14978v4 drm/i915: Add a per-pipe plane identifier enum
https://patchwork.freedesktop.org/api/1.0/series/14978/revisions/4/mbox/

Test drv_module_reload_basic:
                pass       -> DMESG-WARN (fi-skl-6770hq)
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                pass       -> SKIP       (fi-ivb-3520m)
        Subgroup force-edid:
                pass       -> SKIP       (fi-ivb-3520m)
        Subgroup force-load-detect:
                pass       -> SKIP       (fi-ivb-3520m)
        Subgroup prune-stale-modes:
                pass       -> SKIP       (fi-ivb-3520m)

fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:218  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:229  dwarn:1   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

74d13d4fab710f664d5eeb15fd3de821a7f46818 drm-intel-nightly: 2016y-11m-09d-15h-02m-46s UTC integration manifest
e7fdae4 drm/i915: Don't populate plane->plane for cursors and sprites
776f170 drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code
8a691eb drm/i915: Use enum plane_id in VLV/CHV wm code
daca75f drm/i915: Use enum plane_id in VLV/CHV sprite code
2fc5a0b drm/i915: Use enum plane_id in SKL plane code
698ce5d drm/i915: Use enum plane_id in SKL wm code
e6a137a drm/i915: Add crtc->plane_ids_mask
e37903b drm/i915: Add per-pipe plane identifier
caadefb drm/i915: Remove some duplicated plane swapping logic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2943/
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Re: ✗ Fi.CI.BAT: warning for drm/i915: Add a per-pipe plane identifier enum (rev4)

[Ville Syrjälä]

On Wed, Nov 09, 2016 at 04:24:58PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Add a per-pipe plane identifier enum (rev4)
> URL   : https://patchwork.freedesktop.org/series/14978/
> State : warning
> 
> == Summary ==
> 
> Series 14978v4 drm/i915: Add a per-pipe plane identifier enum
> https://patchwork.freedesktop.org/api/1.0/series/14978/revisions/4/mbox/
> 
> Test drv_module_reload_basic:
>                 pass       -> DMESG-WARN (fi-skl-6770hq)

[   26.882144] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
[   26.882800] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
[   26.882823] [drm:lspcon_init [i915]] No LSPCON detected, found type 1 HDMI
[   26.882862] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
[   26.882884] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port B

The bug seems to contain multiple lspcon issues potentially, so not sure
if we're tracking it all there or what:
https://bugs.freedesktop.org/show_bug.cgi?id=98353

> Test kms_force_connector_basic:
>         Subgroup force-connector-state:
>                 pass       -> SKIP       (fi-ivb-3520m)
>         Subgroup force-edid:
>                 pass       -> SKIP       (fi-ivb-3520m)
>         Subgroup force-load-detect:
>                 pass       -> SKIP       (fi-ivb-3520m)
>         Subgroup prune-stale-modes:
>                 pass       -> SKIP       (fi-ivb-3520m)

[  325.952021] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1]
[  325.952051] [drm:intel_crt_detect [i915]] [CONNECTOR:50:VGA-1] force=1
[  325.952087] [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x40f40000, result 0
[  325.952112] [drm:intel_crt_detect [i915]] CRT not detected via hotplug
[  325.952392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
[  325.952421] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK on first message, retry
[  325.953097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
[  325.953104] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
[  325.953132] [drm:intel_crt_get_edid [i915]] CRT GMBUS EDID read failed, retry using GPIO bit-banging
[  325.953159] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus vga. force bit now 1
[  325.954322] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
[  325.954351] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus vga. force bit now 0
[  325.954378] [drm:intel_crt_detect_ddc [i915]] CRT not detected via DDC:0x50 [no valid EDID found]
[  325.954383] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] disconnected
[  325.954746] [drm:status_store] [CONNECTOR:50:VGA-1] force updated from 0 to 2 or reprobing
[  325.954752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1]
[  325.954758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] status updated from disconnected to connected
[  325.955068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
[  325.955098] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK on first message, retry
[  325.955334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
[  325.955341] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
[  325.955368] [drm:intel_crt_get_edid [i915]] CRT GMBUS EDID read failed, retry using GPIO bit-banging
[  325.955394] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus vga. force bit now 1
[  325.956456] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
[  325.956484] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus vga. force bit now 0
[  325.956563] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] probed modes :
[  325.956584] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[  325.956594] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[  325.956601] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[  325.956613] [drm:drm_mode_debug_printmodeline] Modeline 73:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
[  325.956620] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
...
[  339.524802] [drm:status_store] [CONNECTOR:50:VGA-1] force updated from 2 to 0 or reprobing
[  339.524808] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1]
[  339.524845] [drm:intel_crt_detect [i915]] [CONNECTOR:50:VGA-1] force=1
[  339.524880] [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x43f40000, result 1
[  339.524904] [drm:intel_crt_detect [i915]] CRT detected via hotplug
[  339.525639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
[  339.525681] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK on first message, retry
[  339.525941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
[  339.526246] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
[  339.526288] [drm:intel_crt_get_edid [i915]] CRT GMBUS EDID read failed, retry using GPIO bit-banging
[  339.526330] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus vga. force bit now 1
[  339.527481] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
[  339.527512] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus vga. force bit now 0
[  339.527562] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] probed modes :
[  339.527568] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[  339.527572] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[  339.527576] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[  339.527581] [drm:drm_mode_debug_printmodeline] Modeline 73:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
[  339.527585] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[  339.552201] [drm:drm_fb_helper_hotplug_event] 

So something a bit fishy going on with the CRT HPD on that machine.

> 
> fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
> fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
> fi-bxt-t5700     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
> fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
> fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
> fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
> fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
> fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
> fi-ivb-3520m     total:244  pass:218  dwarn:0   dfail:0   fail:0   skip:26 
> fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
> fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
> fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
> fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
> fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
> fi-skl-6770hq    total:244  pass:229  dwarn:1   dfail:0   fail:0   skip:14 
> fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
> fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
> 
> 74d13d4fab710f664d5eeb15fd3de821a7f46818 drm-intel-nightly: 2016y-11m-09d-15h-02m-46s UTC integration manifest
> e7fdae4 drm/i915: Don't populate plane->plane for cursors and sprites
> 776f170 drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code
> 8a691eb drm/i915: Use enum plane_id in VLV/CHV wm code
> daca75f drm/i915: Use enum plane_id in VLV/CHV sprite code
> 2fc5a0b drm/i915: Use enum plane_id in SKL plane code
> 698ce5d drm/i915: Use enum plane_id in SKL wm code
> e6a137a drm/i915: Add crtc->plane_ids_mask
> e37903b drm/i915: Add per-pipe plane identifier
> caadefb drm/i915: Remove some duplicated plane swapping logic
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2943/

-- 
Ville Syrjälä
Intel OTC
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Re: ✗ Fi.CI.BAT: warning for drm/i915: Add a per-pipe plane identifier enum (rev4)

[Imre Deak]

On ma, 2016-11-14 at 20:11 +0200, Ville Syrjälä wrote:
> On Wed, Nov 09, 2016 at 04:24:58PM -0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: drm/i915: Add a per-pipe plane identifier enum (rev4)
> > URL   : https://patchwork.freedesktop.org/series/14978/
> > State : warning
> > 
> > == Summary ==
> > 
> > Series 14978v4 drm/i915: Add a per-pipe plane identifier enum
> > https://patchwork.freedesktop.org/api/1.0/series/14978/revisions/4/mbox/
> > 
> > Test drv_module_reload_basic:
> >                 pass       -> DMESG-WARN (fi-skl-6770hq)
> 
> [   26.882144] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
> [   26.882800] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
> [   26.882823] [drm:lspcon_init [i915]] No LSPCON detected, found type 1 HDMI
> [   26.882862] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
> [   26.882884] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port B
> 
> The bug seems to contain multiple lspcon issues potentially, so not sure
> if we're tracking it all there or what:
> https://bugs.freedesktop.org/show_bug.cgi?id=98353

Yes, the errors in the above dmesg log are the only remaining (known)
issue now tracked in that bug. Will clarify this in the bug
description.

> > Test kms_force_connector_basic:
> >         Subgroup force-connector-state:
> >                 pass       -> SKIP       (fi-ivb-3520m)
> >         Subgroup force-edid:
> >                 pass       -> SKIP       (fi-ivb-3520m)
> >         Subgroup force-load-detect:
> >                 pass       -> SKIP       (fi-ivb-3520m)
> >         Subgroup prune-stale-modes:
> >                 pass       -> SKIP       (fi-ivb-3520m)
> 
> [  325.952021] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1]
> [  325.952051] [drm:intel_crt_detect [i915]] [CONNECTOR:50:VGA-1] force=1
> [  325.952087] [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x40f40000, result 0
> [  325.952112] [drm:intel_crt_detect [i915]] CRT not detected via hotplug
> [  325.952392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
> [  325.952421] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK on first message, retry
> [  325.953097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
> [  325.953104] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
> [  325.953132] [drm:intel_crt_get_edid [i915]] CRT GMBUS EDID read failed, retry using GPIO bit-banging
> [  325.953159] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus vga. force bit now 1
> [  325.954322] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
> [  325.954351] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus vga. force bit now 0
> [  325.954378] [drm:intel_crt_detect_ddc [i915]] CRT not detected via DDC:0x50 [no valid EDID found]
> [  325.954383] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] disconnected
> [  325.954746] [drm:status_store] [CONNECTOR:50:VGA-1] force updated from 0 to 2 or reprobing
> [  325.954752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1]
> [  325.954758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] status updated from disconnected to connected
> [  325.955068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
> [  325.955098] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK on first message, retry
> [  325.955334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
> [  325.955341] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
> [  325.955368] [drm:intel_crt_get_edid [i915]] CRT GMBUS EDID read failed, retry using GPIO bit-banging
> [  325.955394] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus vga. force bit now 1
> [  325.956456] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
> [  325.956484] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus vga. force bit now 0
> [  325.956563] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] probed modes :
> [  325.956584] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
> [  325.956594] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
> [  325.956601] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
> [  325.956613] [drm:drm_mode_debug_printmodeline] Modeline 73:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
> [  325.956620] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
> ...
> [  339.524802] [drm:status_store] [CONNECTOR:50:VGA-1] force updated from 2 to 0 or reprobing
> [  339.524808] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1]
> [  339.524845] [drm:intel_crt_detect [i915]] [CONNECTOR:50:VGA-1] force=1
> [  339.524880] [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x43f40000, result 1
> [  339.524904] [drm:intel_crt_detect [i915]] CRT detected via hotplug
> [  339.525639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
> [  339.525681] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK on first message, retry
> [  339.525941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus vga] NAK for addr: 0050 w(1)
> [  339.526246] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
> [  339.526288] [drm:intel_crt_get_edid [i915]] CRT GMBUS EDID read failed, retry using GPIO bit-banging
> [  339.526330] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus vga. force bit now 1
> [  339.527481] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus vga
> [  339.527512] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus vga. force bit now 0
> [  339.527562] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:VGA-1] probed modes :
> [  339.527568] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
> [  339.527572] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
> [  339.527576] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
> [  339.527581] [drm:drm_mode_debug_printmodeline] Modeline 73:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
> [  339.527585] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
> [  339.552201] [drm:drm_fb_helper_hotplug_event] 
> 
> So something a bit fishy going on with the CRT HPD on that machine.
> 
> > 
> > fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
> > fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
> > fi-bxt-t5700     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
> > fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
> > fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
> > fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
> > fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
> > fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
> > fi-ivb-3520m     total:244  pass:218  dwarn:0   dfail:0   fail:0   skip:26 
> > fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
> > fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
> > fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
> > fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
> > fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
> > fi-skl-6770hq    total:244  pass:229  dwarn:1   dfail:0   fail:0   skip:14 
> > fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
> > fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
> > 
> > 74d13d4fab710f664d5eeb15fd3de821a7f46818 drm-intel-nightly: 2016y-11m-09d-15h-02m-46s UTC integration manifest
> > e7fdae4 drm/i915: Don't populate plane->plane for cursors and sprites
> > 776f170 drm/i915: Rename the local 'plane' variable to 'plane_id' in primary plane code
> > 8a691eb drm/i915: Use enum plane_id in VLV/CHV wm code
> > daca75f drm/i915: Use enum plane_id in VLV/CHV sprite code
> > 2fc5a0b drm/i915: Use enum plane_id in SKL plane code
> > 698ce5d drm/i915: Use enum plane_id in SKL wm code
> > e6a137a drm/i915: Add crtc->plane_ids_mask
> > e37903b drm/i915: Add per-pipe plane identifier
> > caadefb drm/i915: Remove some duplicated plane swapping logic
> > 
> > == Logs ==
> > 
> > For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2943/
> 
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