[PATCH v5 00/22] Add support for GuC-based SLPC

[PATCH v5 00/22] Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in firmware on GuC.
This series has been tested with SKL and APL GuC firmware v9 (not released
yet). Current GuC firmware's SLPC interfaces are updated in v9.

The graphics power management features in SLPC in this version are called
GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
requested graphics frequency to maintain target framerate. Turbo adjusts
requested graphics frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA and GT in power
limited scenarios.

DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
guc-scheduler to maintain actual graphics frequency in efficient range.

This patch series activates only GTPERF Turbo in GuC SLPC.

v2: Addressed review comments on v1. Removed patch to enable SLPC by
    default.

v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT.
    Added change for sanitizing GT PM during reset. Added separate patch
    for sysfs interface to know HW requested frequency. Also, earlier
    patches did not go as series hence were not correctly picked up by BAT.

v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
    GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
    improves performance when GuC is enabled compared to Host Turbo.
    This series keeps only support of 9.18 firmware for better readability.
    If needed, other SLPC interfaces for different GuC version will be
    added later.

v5: This series incorporates feedback from code reviews on earlier series and
    adds following new changes:
	1. More changes for separation of RPS and RC6 handling for Gen9.
	2. Tied up SLPC enabling with GuC load/GuC submission sequence.
	3. SLPC structures are defined explicitly for event input/output.
	4. Definition of SLPC parameter control and task control functions
	   agnostic to the underlying param definitions as they might
	   change with GuC versions and prepared helpers for common tasks.
	5. Transition of i915 overrides done through host to guc events
	   to shared data and single reset event.
	6. Handling SLPC status post reset through shared memory.
	7. Derived helpers for setting frequency limits.
	8. Removed sysfs interface to know RPNSWREQ as it is available in
	   debugfs interface i915_frequency_info.
	9. Simple igt test to verify SLPC configuration by i915 in various
	   driver scenarios is prepared.

VIZ-6773, VIZ-6889, VIZ-6890

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Beuchat, Marc <marc.beuchat@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>

Sagar Arun Kamble (3):
  drm/i915/gen9: Separate RPS and RC6 handling
  drm/i915/slpc: Only enable GTPERF task, Disable other tasks/parameters
  drm/i915/slpc: Preserve min/max frequency softlimits on re-activation

Tom O'Rourke (19):
  drm/i915/slpc: Expose GuC functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize GuC version
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in GuC if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Update debugfs interfaces for frequency parameters
  drm/i915/slpc: Add slpc communication interfaces
  drm/i915/slpc: Send reset event and handle SLPC enabling
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add support for min/max frequency control
  drm/i915/slpc: Add enable/disable controls for slpc tasks
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add Broxton SLPC support
  drm/i915/slpc: Enable SLPC, where supported

 drivers/gpu/drm/i915/Makefile              |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 382 ++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.c            |  17 +-
 drivers/gpu/drm/i915/i915_drv.h            |   4 +
 drivers/gpu/drm/i915/i915_gem.c            |   8 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  25 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_pci.c            |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  36 +-
 drivers/gpu/drm/i915/intel_guc.h           |   5 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  45 ++-
 drivers/gpu/drm/i915/intel_pm.c            | 106 +++++-
 drivers/gpu/drm/i915/intel_slpc.c          | 586 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 252 +++++++++++++
 15 files changed, 1440 insertions(+), 39 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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[PATCH v5 01/22] drm/i915/gen9: Separate RPS and RC6 handling

[Sagar Arun Kamble]

With GuC based SLPC, frequency control will be moved to GuC and Host will
continue to control RC6 and Ring frequency setup. SLPC can be enabled in
the GuC setup path and can happen in parallel in GuC with other i915 setup.
Hence we can do away with deferred RPS enabling. This needs separate
handling of RPS, RC6 and ring frequencies in driver flows. We can still use
the *gt_powersave routines with separate status variables of RPS, RC6 and
SLPC. With this patch, RC6 and ring frequencies setup(if applicable) are
tracked through rps.rc6_enabled and RPS through rps.enabled.
Also, Active RPS check in suspend flow is needed for platforms with RC6
and RPS enabling/disabling coupled together. RPM suspend depends only on
RC6 though. Hence Active RPS check is done only for non-Gen9 platforms.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.

v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
    spacing changes. (David)
    and commit message update for checkpatch issues.

v3: Rebase.

v4: Commit message update.

v5: Updated intel_enable_gt_powersave and intel_disable_gt_powersave
    routines with separated RPS and RC6 handling and rebase. Commit message
    update.(Sagar)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |  6 ++++-
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 54 +++++++++++++++++++++++++++++++++--------
 3 files changed, 51 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4efec8b..059f27d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2300,7 +2300,11 @@ static int intel_runtime_suspend(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
+		return -ENODEV;
+
+	if (WARN_ON_ONCE((IS_GEN9(dev_priv) && !dev_priv->rps.rc6_enabled) ||
+			 (!IS_GEN9(dev_priv) && !dev_priv->rps.enabled)))
 		return -ENODEV;
 
 	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0f1dfc..c0fcd73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1242,6 +1242,8 @@ struct intel_gen6_power_mgmt {
 	/* manual wa residency calculations */
 	struct intel_rps_ei up_ei, down_ei;
 
+	bool rc6_enabled;
+
 	/*
 	 * Protects RPS/RC6 register access and PCU communication.
 	 * Must be taken after struct_mutex if nested. Note that
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 35c4afd..7e33557 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5109,11 +5109,15 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN9_PG_ENABLE, 0);
+
+	dev_priv->rps.rc6_enabled = false;
 }
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -5121,11 +5125,15 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5137,6 +5145,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5354,6 +5364,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5421,6 +5433,8 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
 				(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.rc6_enabled = true;
 }
 
 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
@@ -5498,6 +5512,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5591,6 +5607,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -6066,6 +6084,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6147,6 +6167,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6711,6 +6733,7 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	dev_priv->rps.enabled = true; /* force disabling */
+	dev_priv->rps.rc6_enabled = true;
 	intel_disable_gt_powersave(dev_priv);
 
 	gen6_reset_rps_interrupts(dev_priv);
@@ -6718,14 +6741,20 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled))
+	if (!READ_ONCE(dev_priv->rps.enabled)) {
+		if (WARN_ON_ONCE(IS_GEN9(dev_priv) &&
+				 READ_ONCE(dev_priv->rps.rc6_enabled)))
+			DRM_ERROR("RC6 not disabled.\n");
 		return;
+	}
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
 	if (INTEL_GEN(dev_priv) >= 9) {
-		gen9_disable_rc6(dev_priv);
-		gen9_disable_rps(dev_priv);
+		if (READ_ONCE(dev_priv->rps.rc6_enabled))
+			gen9_disable_rc6(dev_priv);
+		if (READ_ONCE(dev_priv->rps.enabled))
+			gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_disable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
@@ -6736,7 +6765,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		ironlake_disable_drps(dev_priv);
 	}
 
-	dev_priv->rps.enabled = false;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -6745,8 +6773,12 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (READ_ONCE(dev_priv->rps.enabled)) {
+		if (WARN_ON_ONCE(IS_GEN9(dev_priv) &&
+				 !READ_ONCE(dev_priv->rps.rc6_enabled)))
+			DRM_ERROR("RC6 and ring frequencies not enabled.\n");
 		return;
+	}
 
 	/* Powersaving is controlled by the host when inside a VM */
 	if (intel_vgpu_active(dev_priv))
@@ -6759,10 +6791,13 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 9) {
-		gen9_enable_rc6(dev_priv);
-		gen9_enable_rps(dev_priv);
-		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
-			gen6_update_ring_freq(dev_priv);
+		if (!READ_ONCE(dev_priv->rps.rc6_enabled)) {
+			gen9_enable_rc6(dev_priv);
+			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+				gen6_update_ring_freq(dev_priv);
+		}
+		if (!READ_ONCE(dev_priv->rps.enabled))
+			gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
 		gen8_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
@@ -6780,7 +6815,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-- 
1.9.1

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[PATCH v5 02/22] drm/i915/slpc: Expose GuC functions for use with SLPC

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

v1: Updated function names as they need to be made extern. (ChrisW)

v2-v4: Rebase

v5: Commit subject update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 22 +++++++++++-----------
 drivers/gpu/drm/i915/intel_guc.h           |  2 ++
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 666dab7..c171f1f 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -49,7 +49,7 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
  *
  * Doorbells:
  * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -77,7 +77,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 	return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	u32 status;
@@ -143,7 +143,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -154,7 +154,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -171,7 +171,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 		/* bit 0 and 1 are for Render and Media domain separately */
 		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
@@ -180,7 +180,7 @@ static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
 
 	data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
 
-	return host2guc_action(guc, data, 1);
+	return i915_guc_action(guc, data, 1);
 }
 
 static int host2guc_force_logbuffer_flush(struct intel_guc *guc)
@@ -190,7 +190,7 @@ static int host2guc_force_logbuffer_flush(struct intel_guc *guc)
 	data[0] = HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH;
 	data[1] = 0;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_logging_control(struct intel_guc *guc, u32 control_val)
@@ -200,7 +200,7 @@ static int host2guc_logging_control(struct intel_guc *guc, u32 control_val)
 	data[0] = HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING;
 	data[1] = control_val;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 /*
@@ -672,7 +672,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
@@ -1583,7 +1583,7 @@ int intel_guc_suspend(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 
@@ -1611,7 +1611,7 @@ int intel_guc_resume(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 0053258..dad4a23 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -189,5 +189,7 @@ struct intel_guc {
 void i915_guc_register(struct drm_i915_private *dev_priv);
 void i915_guc_unregister(struct drm_i915_private *dev_priv);
 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
 
 #endif
-- 
1.9.1

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[PATCH v5 03/22] drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0fcd73..9c75371 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -679,6 +679,7 @@ struct intel_csr {
 	func(has_rc6p); \
 	func(has_resource_streamer); \
 	func(has_runtime_pm); \
+	func(has_slpc); \
 	func(has_snoop); \
 	func(cursor_needs_physical); \
 	func(hws_needs_physical); \
@@ -2609,6 +2610,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
 #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
+#define HAS_SLPC(dev_priv)	((dev_priv)->info.has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
 
-- 
1.9.1

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[PATCH v5 04/22] drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
    Remove sanitize enable_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as
    part of slpc_enable_sanitize function in the next patch. (Sagar)
    Updated slpc option sanitize function call for platforms without
    GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

v5: Removed function intel_slpc_enabled. Planning to rely only on
    kernel parameter. Moved sanitization prior to GuC load to use the
    parameter during SLPC state setup during to GuC load. (Sagar)

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 24 +++++++++++++++++++++---
 3 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 629e433..70f07ee 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -140,6 +141,11 @@ struct i915_params i915 __read_mostly = {
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 94efc89..ed37a6f 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
+	int enable_slpc;
 	int enable_psr;
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 34d6ad2..8a23154 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -161,6 +161,21 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
 	}
 }
 
+void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev_priv))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc loaded */
+	if (!i915.enable_guc_loading)
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
 	/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -761,16 +776,19 @@ void intel_guc_init(struct drm_device *dev)
 
 	/* Early (and silent) return if GuC loading is disabled */
 	if (!i915.enable_guc_loading)
-		return;
+		goto out;
 	if (fw_path == NULL)
-		return;
+		goto out;
 	if (*fw_path == '\0')
-		return;
+		goto out;
 
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 	guc_fw_fetch(dev, guc_fw);
 	/* status must now be FAIL or SUCCESS */
+
+out:
+	sanitize_slpc_option(dev_priv);
 }
 
 /**
-- 
1.9.1

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[PATCH v5 05/22] drm/i915/slpc: Sanitize GuC version

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface is dependent on GuC version.
 Only GuC versions known to be compatible are supported here.

On SKL, BXT, KBL, GuC firmware v9 is supported.  Other
platforms and versions can be added here later.

v1: Updated with modified sanitize_slpc_option in earlier patch.

v2-v3: Rebase.

v4: Updated support for GuC firmware v9.

v5: Commit subject updated.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8a23154..946c59b 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -163,6 +163,8 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
 
 void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
 	/* slpc requires hardware support and compatible firmware */
 	if (!HAS_SLPC(dev_priv))
 		i915.enable_slpc = 0;
@@ -174,6 +176,9 @@ void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	/* slpc requires guc submission */
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
+
+	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+		i915.enable_slpc = 0;
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v5 06/22] drm/i915/slpc: Use intel_slpc_* functions if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

On platforms with SLPC support: call intel_slpc_*() functions from
intel_*_gt_powersave() functions and GuC setup functions and do not
use rps functions. intel_slpc_enable is tied to GuC setup.
With SLPC, intel_enable_gt_powersave will only handle RC6 and ring
frequencies. intel_init_gt_powersave will check if SLPC has started
running through shared data and update initial state that i915 needs
like frequency limits.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
    (Sagar)

v5: Removed intel_slpc_active. Relying on slpc.active for control flows
    that are based on SLPC active status in GuC. State setup/cleanup needed
    for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
    init and enabling to GuC enable path as SLPC in GuC can start doing the
    setup post GuC init. Commit message update. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile              |  3 +-
 drivers/gpu/drm/i915/i915_drv.c            |  2 ++
 drivers/gpu/drm/i915/i915_gem.c            |  8 +++++
 drivers/gpu/drm/i915/i915_guc_submission.c |  3 ++
 drivers/gpu/drm/i915/intel_guc.h           |  3 ++
 drivers/gpu/drm/i915/intel_guc_loader.c    | 10 ++++++
 drivers/gpu/drm/i915/intel_pm.c            | 51 ++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_slpc.c          | 46 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 38 ++++++++++++++++++++++
 9 files changed, 153 insertions(+), 11 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3dea46a..8f40854 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -56,7 +56,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+	  i915_guc_submission.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 059f27d..e60d5d8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1697,6 +1697,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		hsw_disable_pc8(dev_priv);
 	}
 
+	dev_priv->guc.slpc.active = false;
+
 	intel_uncore_sanitize(dev_priv);
 
 	if (IS_BROXTON(dev_priv) ||
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ed4465d..d54ce47 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2687,6 +2687,14 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 
 	i915_gem_restore_fences(&dev_priv->drm);
 
+	/*
+	 * GPU is reset at this point, Hence mark SLPC as inactive to
+	 * not send h2g action to shutdown SLPC as that will fail.
+	 * enable_gt_powersave will setup RC6 and ring frequencies and
+	 * SLPC will be enabled post GuC initialization.
+	 */
+	dev_priv->guc.slpc.active = false;
+
 	if (dev_priv->gt.awake) {
 		intel_sanitize_gt_powersave(dev_priv);
 		intel_enable_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index c171f1f..d77cfb6 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1492,6 +1492,9 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv)
 	guc_log_create(guc);
 	guc_addon_create(guc);
 
+	if (i915.enable_slpc)
+		intel_slpc_init(dev_priv);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index dad4a23..1b00035 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
@@ -167,6 +168,8 @@ struct intel_guc {
 
 	/* To serialize the Host2GuC actions */
 	struct mutex action_lock;
+
+	struct intel_slpc slpc;
 };
 
 /* intel_guc_loader.c */
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 946c59b..46e07af 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -549,6 +549,16 @@ int intel_guc_setup(struct drm_device *dev)
 		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 
+	/*
+	 * SLPC is enabled by setting up the shared data structure and
+	 * sending reset event to GuC SLPC. Initial data is setup in
+	 * intel_slpc_init. Here we send the reset event. SLPC enabling
+	 * in GuC can happen in parallel in GuC with other initialization
+	 * being done in i915.
+	 */
+	if (i915.enable_slpc)
+		intel_slpc_enable(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e33557..5771352 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5016,6 +5016,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 
 void gen6_rps_busy(struct drm_i915_private *dev_priv)
 {
+	if (i915.enable_slpc)
+		return;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
 		if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
@@ -5036,6 +5039,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 
 void gen6_rps_idle(struct drm_i915_private *dev_priv)
 {
+	if (i915.enable_slpc)
+		return;
+
 	/* Flush our bottom-half so that it does not race with us
 	 * setting the idle frequency and so that it is bounded by
 	 * our rpm wakeref. And then disable the interrupts to stop any
@@ -5065,6 +5071,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 		    struct intel_rps_client *rps,
 		    unsigned long submitted)
 {
+	if (i915.enable_slpc)
+		return;
+
 	/* This is intentionally racy! We peek at the state here, then
 	 * validate inside the RPS worker.
 	 */
@@ -6704,7 +6713,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (IS_VALLEYVIEW(dev_priv))
+	if (i915.enable_slpc)
+		intel_slpc_cleanup(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
 	if (!i915.enable_rc6)
@@ -6728,33 +6739,51 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_put(dev_priv);
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
+
+	if (dev_priv->guc.slpc.active) {
+		intel_runtime_pm_get(dev_priv);
+		mutex_lock(&dev_priv->rps.hw_lock);
+		intel_slpc_suspend(dev_priv);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+	}
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
+	if (!i915.enable_slpc)
+		dev_priv->rps.enabled = true; /* force disabling */
 	dev_priv->rps.rc6_enabled = true;
+
 	intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+	if (!i915.enable_slpc)
+		gen6_reset_rps_interrupts(dev_priv);
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled)) {
+	if (!i915.enable_slpc && !READ_ONCE(dev_priv->rps.enabled)) {
 		if (WARN_ON_ONCE(IS_GEN9(dev_priv) &&
 				 READ_ONCE(dev_priv->rps.rc6_enabled)))
 			DRM_ERROR("RC6 not disabled.\n");
 		return;
 	}
+	if (i915.enable_slpc && !READ_ONCE(dev_priv->rps.rc6_enabled))
+		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
 	if (INTEL_GEN(dev_priv) >= 9) {
 		if (READ_ONCE(dev_priv->rps.rc6_enabled))
 			gen9_disable_rc6(dev_priv);
-		if (READ_ONCE(dev_priv->rps.enabled))
-			gen9_disable_rps(dev_priv);
+		if (i915.enable_slpc) {
+			if (READ_ONCE(dev_priv->guc.slpc.active))
+				intel_slpc_disable(dev_priv);
+		} else {
+			if (READ_ONCE(dev_priv->rps.enabled))
+				gen9_disable_rps(dev_priv);
+		}
 	} else if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_disable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
@@ -6773,12 +6802,14 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled)) {
+	if (!i915.enable_slpc && READ_ONCE(dev_priv->rps.enabled)) {
 		if (WARN_ON_ONCE(IS_GEN9(dev_priv) &&
 				 !READ_ONCE(dev_priv->rps.rc6_enabled)))
 			DRM_ERROR("RC6 and ring frequencies not enabled.\n");
 		return;
 	}
+	if (i915.enable_slpc && READ_ONCE(dev_priv->rps.rc6_enabled))
+		return;
 
 	/* Powersaving is controlled by the host when inside a VM */
 	if (intel_vgpu_active(dev_priv))
@@ -6796,7 +6827,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 				gen6_update_ring_freq(dev_priv);
 		}
-		if (!READ_ONCE(dev_priv->rps.enabled))
+		if (!i915.enable_slpc && !READ_ONCE(dev_priv->rps.enabled))
 			gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
 		gen8_enable_rps(dev_priv);
@@ -6825,7 +6856,7 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (!i915.enable_slpc && READ_ONCE(dev_priv->rps.enabled))
 		goto out;
 
 	rcs = dev_priv->engine[RCS];
@@ -6855,7 +6886,7 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (!i915.enable_slpc && READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..b67f1bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_suspend(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..e5acfc8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+struct intel_slpc {
+	bool active;
+};
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_suspend(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+
+#endif
-- 
1.9.1

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[PATCH v5 07/22] drm/i915/slpc: Enable SLPC in GuC if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

v2-v4: Rebase.

v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 46e07af..8e99155 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -239,6 +239,9 @@ static void guc_params_init(struct drm_i915_private *dev_priv)
 	} else
 		params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
 
+	if (i915.enable_slpc)
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	if (guc->ads_vma) {
 		u32 ads = i915_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
 		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
-- 
1.9.1

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[PATCH v5 08/22] drm/i915/slpc: If using SLPC, do not set frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)

v2-v4: Rebase.

v5: Changed intel_slpc_active to i915.enable_slpc. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5771352..b905638 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5108,6 +5108,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+	if (i915.enable_slpc)
+		return;
+
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		valleyview_set_rps(dev_priv, val);
 	else
-- 
1.9.1

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[PATCH v5 09/22] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC shared data is used to pass information
to/from SLPC in GuC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v1: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
    change default host_os to "Windows"
    Spelling fixes (Sagar Kamble and Nick Hoath)
    Added WARN for checking if upper 32bits of GTT offset
    of shared object are zero. (ChrisW)
    Changed function call from gem_allocate/release_guc_obj to
    i915_guc_allocate/release_gem_obj. (Sagar)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE
    definition from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable
    to determine if it is active as it not just dependent on shared
    data setup.
    Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes.(David)
    Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
    with SLPC Enabled.

v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/(Dave).

v5: SLPC vma mapping changes and removed explicit type conversions.(Chris).
    s/freq_unslice_max|min/unslice__max|min_freq.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 83 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 95 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 178 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b67f1bc..945d265 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,15 +22,98 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	WARN_ON(platform_sku > 0xFF);
+
+	return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+	unsigned int slice_count = 1;
+
+	if (IS_SKYLAKE(dev_priv))
+		slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
+
+	return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 msr_value;
+
+	page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+	data = kmap_atomic(page);
+
+	memset(data, 0, sizeof(struct slpc_shared_data));
+
+	data->shared_data_size = sizeof(struct slpc_shared_data);
+	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
+	data->platform_info.platform_sku =
+				slpc_get_platform_sku(dev_priv);
+	data->platform_info.slice_count =
+				slpc_get_slice_count(dev_priv);
+	data->platform_info.power_plan_source =
+		SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+					    SLPC_POWER_SOURCE_AC);
+	rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+	data->platform_info.P0_freq = msr_value;
+	rdmsrl(MSR_PLATFORM_INFO, msr_value);
+	data->platform_info.P1_freq = msr_value >> 8;
+	data->platform_info.Pe_freq = msr_value >> 40;
+	data->platform_info.Pn_freq = msr_value >> 48;
+
+	kunmap_atomic(data);
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+	struct i915_vma *vma;
+
+	dev_priv->guc.slpc.active = false;
+
+	/* Allocate shared data structure */
+	vma = dev_priv->guc.slpc.vma;
+	if (!vma) {
+		vma = guc_allocate_vma(guc,
+			       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		if (IS_ERR(vma)) {
+			DRM_ERROR("slpc_shared_data allocation failed\n");
+			i915.enable_slpc = 0;
+			return;
+		}
+
+		dev_priv->guc.slpc.vma = vma;
+	}
+
+	slpc_shared_data_init(dev_priv);
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+
+	/* Release shared data structure */
+	mutex_lock(&dev_priv->drm.struct_mutex);
+	i915_vma_unpin_and_release(&guc->slpc.vma);
+	mutex_unlock(&dev_priv->drm.struct_mutex);
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index e5acfc8..2d81443 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,8 +24,103 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 reserved;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 reserved1;
+	u32 reserved2;
+} __packed;
+
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 max_unslice_freq:8;
+			u32 min_unslice_freq:8;
+			u32 max_slice_freq:8;
+			u32 min_slice_freq:8;
+		};
+	};
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 reserved;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	struct slpc_task_state_data task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
 struct intel_slpc {
 	bool active;
+	struct i915_vma *vma;
 };
 
 /* intel_slpc.c */
-- 
1.9.1

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[PATCH v5 10/22] drm/i915/slpc: Update debugfs interfaces for frequency parameters

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLPC requested value needs to be made available to i915 without
reading RPNSWREQ.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
    Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
    don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
    for proper division of functionality. (Sagar)

v4: idle_freq, boost_freq are also not used with SLPC.

v5: Added SLPC banner to i915_rps_boost_info and keep printing
    driver internal values. (Chris)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bce3880..8f24fdf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1079,6 +1079,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (dev_priv->guc.slpc.active)
+		seq_puts(m, "SLPC Active\n");
+
 	if (IS_GEN5(dev_priv)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2275,6 +2278,10 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_file *file;
 
+	if (dev_priv->guc.slpc.active)
+		seq_puts(m, "SLPC Active\n");
+
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
 	seq_printf(m, "GPU busy? %s [%d requests]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
-- 
1.9.1

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[PATCH v5 11/22] drm/i915/slpc: Add slpc communication interfaces

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Communication with SLPC is via Host to GuC interrupt.
This patch defines the data structure to be passed as input
and received as output from SLPC. This patch also defines the
events to be sent as input and status values output by GuC
on processing SLPC events.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
events. Updated commit message.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 30 +++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 71 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 101 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 945d265..57d0d03 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -82,6 +82,36 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
 	kunmap_atomic(data);
 }
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv,
+			  struct slpc_event_input *input, u32 len)
+{
+	union slpc_event_output_header header;
+	u32 *data;
+	int ret = 0;
+
+	/*
+	 * We have only 15 scratch registers for communication.
+	 * the first we will use for the event ID in input and
+	 * output data. Event processing status will be present
+	 * in SOFT_SCRATCH(1) register.
+	 */
+	BUILD_BUG_ON(SLPC_EVENT_MAX_INPUT_ARGS > 14);
+	BUILD_BUG_ON(SLPC_EVENT_MAX_OUTPUT_ARGS < 1);
+	BUILD_BUG_ON(SLPC_EVENT_MAX_OUTPUT_ARGS > 14);
+
+	data = (u32 *) input;
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	ret = i915_guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		header.value = I915_READ(SOFT_SCRATCH(1));
+		ret = header.status;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 2d81443..4378265 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -123,6 +123,77 @@ struct intel_slpc {
 	struct i915_vma *vma;
 };
 
+#define SLPC_EVENT_MAX_INPUT_ARGS  7
+#define SLPC_EVENT_MAX_OUTPUT_ARGS 1
+
+union slpc_event_input_header {
+	u32 value;
+	struct {
+		u32 num_args:8;
+		u32 event_id:8;
+	};
+};
+
+struct slpc_event_input {
+	u32 h2g_action_id;
+	union slpc_event_input_header header;
+	u32 args[SLPC_EVENT_MAX_INPUT_ARGS];
+} __packed;
+
+union slpc_event_output_header {
+	u32 value;
+	struct {
+		u32 num_args:8;
+		u32 event_id:8;
+		u32 status:16;
+	};
+};
+
+struct slpc_event_output {
+	u32 reserved;
+	union slpc_event_output_header header;
+	u32 args[SLPC_EVENT_MAX_OUTPUT_ARGS];
+} __packed;
+
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc)	((u32) (id) << 8 | (argc))
+
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[PATCH v5 12/22] drm/i915/slpc: Send reset event and handle SLPC enabling

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send host2guc SLPC reset event to GuC post GuC load.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done during intel_init_gt_powersave.
This allows to get initial configuration setup by SLPC and if needed
move to Host RPS if SLPC runs into issues.

v1: Extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

v3: Rebase.

v4: Added DRM_INFO message when SLPC is enabled.

v5: Updated patch as host2guc_slpc is moved to earlier patch.
    SLPC activation status message put after checking the
    state from shared data during intel_init_gt_powersave.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c   |   8 +++
 drivers/gpu/drm/i915/intel_slpc.c | 103 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |   4 ++
 3 files changed, 115 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b905638..80a8432 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6667,6 +6667,14 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_get(dev_priv);
 	}
 
+	if (i915.enable_slpc) {
+		dev_priv->guc.slpc.active = intel_slpc_get_status(dev_priv);
+		if (!dev_priv->guc.slpc.active) {
+			i915.enable_slpc = 0;
+			intel_sanitize_gt_powersave(dev_priv);
+		}
+	}
+
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	mutex_lock(&dev_priv->rps.hw_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 57d0d03..9dd4d6e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -154,6 +154,109 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
 }
 
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+	struct slpc_event_input data = {0};
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	host2guc_slpc(dev_priv, &data, 4);
+}
+
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_reset(dev_priv);
+	dev_priv->guc.slpc.active = true;
+}
+
+static void host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	struct slpc_event_input data = {0};
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	host2guc_slpc(dev_priv, &data, 4);
+}
+
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	if (dev_priv->guc.slpc.active)
+		host2guc_slpc_query_task_state(dev_priv);
+}
+
+/*
+ * This function will reads the state updates from GuC SLPC into shared data
+ * by invoking H2G action. Returns current state of GuC SLPC.
+ */
+void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv,
+				 struct slpc_shared_data *data)
+{
+	struct page *page;
+	void *pv = NULL;
+
+	intel_slpc_query_task_state(dev_priv);
+
+	page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+	pv = kmap_atomic(page);
+
+	drm_clflush_virt_range(pv, PAGE_SIZE);
+	memcpy(data, pv, sizeof(struct slpc_shared_data));
+
+	kunmap_atomic(pv);
+}
+
+const char *intel_slpc_get_state_str(enum slpc_global_state state)
+{
+	if (state == SLPC_GLOBAL_STATE_NOT_RUNNING)
+		return "not running";
+	else if (state == SLPC_GLOBAL_STATE_INITIALIZING)
+		return "initializing";
+	else if (state == SLPC_GLOBAL_STATE_RESETTING)
+		return "resetting";
+	else if (state == SLPC_GLOBAL_STATE_RUNNING)
+		return "running";
+	else if (state == SLPC_GLOBAL_STATE_SHUTTING_DOWN)
+		return "shutting down";
+	else if (state == SLPC_GLOBAL_STATE_ERROR)
+		return "error";
+	else
+		return "unknown";
+}
+bool intel_slpc_get_status(struct drm_i915_private *dev_priv)
+{
+	struct slpc_shared_data data;
+	bool ret = false;
+
+	intel_slpc_read_shared_data(dev_priv, &data);
+	DRM_INFO("SLPC state: %s\n",
+		 intel_slpc_get_state_str(data.global_state));
+
+	switch (data.global_state) {
+	case SLPC_GLOBAL_STATE_RUNNING:
+		/* Capture required state from SLPC here */
+		ret = true;
+		break;
+	case SLPC_GLOBAL_STATE_ERROR:
+		DRM_ERROR("SLPC in error state.\n");
+		break;
+	case SLPC_GLOBAL_STATE_RESETTING:
+		/*
+		 * SLPC enabling in GuC should be completing fast.
+		 * If SLPC is taking time to initialize (unlikely as we are
+		 * sending reset event during GuC load itself).
+		 * TODO: Need to wait till state changes to RUNNING.
+		 */
+		ret = true;
+		DRM_ERROR("SLPC not running yet.!!!");
+		break;
+	default:
+		break;
+	}
+	return ret;
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 4378265..a777b57 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -200,5 +200,9 @@ enum slpc_status {
 void intel_slpc_suspend(struct drm_i915_private *dev_priv);
 void intel_slpc_disable(struct drm_i915_private *dev_priv);
 void intel_slpc_enable(struct drm_i915_private *dev_priv);
+void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv,
+				struct slpc_shared_data *data);
+const char *intel_slpc_get_state_str(enum slpc_global_state state);
+bool intel_slpc_get_status(struct drm_i915_private *dev_priv);
 
 #endif
-- 
1.9.1

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[PATCH v5 13/22] drm/i915/slpc: Send shutdown event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

v2-v4: Rebase.

v5: Updated the input data structure. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 9dd4d6e..5f37bbc 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -146,12 +146,28 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+	struct slpc_event_input data = {0};
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	host2guc_slpc(dev_priv, &data, 4);
+}
+
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.active = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.active = false;
 }
 
 static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v5 14/22] drm/i915/slpc: Add parameter unset/set/get functions

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC behavior can be changed through set of parameters.
These parameters can be updated and queried from i915 though
Host to GuC SLPC events. This patch add parameter values and
events for setting/unsetting parameters.

v1: Use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

v2: Checkpatch update.

v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated input structure to host2guc_slpc. Added functions
    to update only parameters in the SLPC shared memory. This
    will allow to setup shared data with all parameters and send
    single event to SLPC take them into effect. Commit message
    update. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 104 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  28 ++++++++++
 2 files changed, 132 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 5f37bbc..9120571 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -112,6 +112,110 @@ static void host2guc_slpc(struct drm_i915_private *dev_priv,
 		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
 }
 
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+				    u32 id, u32 value)
+{
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data.args[0] = id;
+	data.args[1] = value;
+
+	host2guc_slpc(dev_priv, &data, 4);
+}
+
+void slpc_mem_set_param(struct slpc_shared_data *data,
+			      u32 id,
+			      u32 value)
+{
+	data->override_parameters_set_bits[id >> 5]
+						|= (1 << (id % 32));
+	data->override_parameters_values[id] = value;
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  u32 id,
+			  u32 value)
+{
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	WARN_ON(id >= SLPC_MAX_PARAM);
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+	data = kmap_atomic(page);
+	slpc_mem_set_param(data, id, value);
+	kunmap_atomic(data);
+
+	host2guc_slpc_set_param(dev_priv, id, value);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+				      u32 id)
+{
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data.args[0] = id;
+
+	host2guc_slpc(dev_priv, &data, 3);
+}
+
+void slpc_mem_unset_param(struct slpc_shared_data *data,
+				u32 id)
+{
+	data->override_parameters_set_bits[id >> 5]
+						&= (~(1 << (id % 32)));
+	data->override_parameters_values[id] = 0;
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    u32 id)
+{
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	WARN_ON(id >= SLPC_MAX_PARAM);
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+	data = kmap_atomic(page);
+	slpc_mem_unset_param(data, id);
+	kunmap_atomic(data);
+
+	host2guc_slpc_unset_param(dev_priv, id);
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  u32 id,
+			  int *overriding, u32 *value)
+{
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	WARN_ON(id >= SLPC_MAX_PARAM);
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+	data = kmap_atomic(page);
+	if (overriding) {
+		bits = data->override_parameters_set_bits[id >> 5];
+		*overriding = (0 != (bits & (1 << (id % 32))));
+	}
+	if (value)
+		*value = data->override_parameters_values[id];
+
+	kunmap_atomic(data);
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a777b57..c83b737 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -194,6 +194,30 @@ enum slpc_status {
 	SLPC_STATUS_NO_LOCK = 22,
 };
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
+	SLPC_MAX_PARAM,
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
@@ -204,5 +228,9 @@ void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv,
 				struct slpc_shared_data *data);
 const char *intel_slpc_get_state_str(enum slpc_global_state state);
 bool intel_slpc_get_status(struct drm_i915_private *dev_priv);
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv, u32 id);
+void intel_slpc_set_param(struct drm_i915_private *dev_priv, u32 id, u32 value);
+void intel_slpc_get_param(struct drm_i915_private *dev_priv, u32 id,
+			  int *overriding, u32 *value);
 
 #endif
-- 
1.9.1

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[PATCH v5 15/22] drm/i915/slpc: Add support for min/max frequency control

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

v2-v4: Rebase.

v5: Removed typecasting the frequency values to u32. (Chris)
    Changed intel_slpc_active to guc.slpc.enabled. Carved out
    SLPC helpers to set min and max frequencies.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++++++++++++++++--
 drivers/gpu/drm/i915/i915_sysfs.c   | 36 ++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_slpc.c   | 45 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  6 +++++
 4 files changed, 105 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8f24fdf..8461c33 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5001,7 +5001,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	if (INTEL_GEN(dev_priv) < 6)
 		return -ENODEV;
 
-	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
+	if (dev_priv->guc.slpc.active)
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->guc.slpc.max_unslice_freq);
+	else
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->rps.max_freq_softlimit);
 	return 0;
 }
 
@@ -5026,6 +5031,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	 */
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_max_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		return ret;
+	}
+
 	hw_max = dev_priv->rps.max_freq;
 	hw_min = dev_priv->rps.min_freq;
 
@@ -5055,7 +5066,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	if (INTEL_GEN(dev_priv) < 6)
 		return -ENODEV;
 
-	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
+	if (dev_priv->guc.slpc.active)
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->guc.slpc.min_unslice_freq);
+	else
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->rps.min_freq_softlimit);
 	return 0;
 }
 
@@ -5080,6 +5096,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	 */
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_min_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		return ret;
+	}
+
 	hw_max = dev_priv->rps.max_freq;
 	hw_min = dev_priv->rps.min_freq;
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 47590ab..284cc90 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -351,9 +351,14 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->rps.max_freq_softlimit));
+	if (dev_priv->guc.slpc.active)
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.max_unslice_freq));
+	else
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
 }
 
 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -374,6 +379,13 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_max_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret ? ret : count;
+	}
+
 	if (val < dev_priv->rps.min_freq ||
 	    val > dev_priv->rps.max_freq ||
 	    val < dev_priv->rps.min_freq_softlimit) {
@@ -408,9 +420,14 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->rps.min_freq_softlimit));
+	if (dev_priv->guc.slpc.active)
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.min_unslice_freq));
+	else
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
 }
 
 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -431,6 +448,13 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_min_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret ? ret : count;
+	}
+
 	if (val < dev_priv->rps.min_freq ||
 	    val > dev_priv->rps.max_freq ||
 	    val > dev_priv->rps.max_freq_softlimit) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 9120571..2f7fe8f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -348,6 +348,7 @@ const char *intel_slpc_get_state_str(enum slpc_global_state state)
 	else
 		return "unknown";
 }
+
 bool intel_slpc_get_status(struct drm_i915_private *dev_priv)
 {
 	struct slpc_shared_data data;
@@ -380,3 +381,47 @@ bool intel_slpc_get_status(struct drm_i915_private *dev_priv)
 	}
 	return ret;
 }
+
+/*
+ * TODO: Add separate interfaces to set Max/Min Slice frequency.
+ * Since currently both slice and unslice are configured to same
+ * frequencies these unified interface relying on Unslice frequencies
+ * should be sufficient. These functions take frequency opcode as input.
+ */
+int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val)
+{
+	if (val < dev_priv->rps.min_freq ||
+	    val > dev_priv->rps.max_freq ||
+	    val < dev_priv->guc.slpc.min_unslice_freq)
+		return -EINVAL;
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+
+	dev_priv->guc.slpc.max_unslice_freq = val;
+
+	return 0;
+}
+
+int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val)
+{
+	if (val < dev_priv->rps.min_freq ||
+	    val > dev_priv->rps.max_freq ||
+	    val > dev_priv->guc.slpc.max_unslice_freq)
+		return -EINVAL;
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+
+	dev_priv->guc.slpc.min_unslice_freq = val;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index c83b737..2cecdc8 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -121,6 +121,10 @@ struct slpc_shared_data {
 struct intel_slpc {
 	bool active;
 	struct i915_vma *vma;
+
+	/* i915 cached SLPC frequency limits */
+	u32 min_unslice_freq;
+	u32 max_unslice_freq;
 };
 
 #define SLPC_EVENT_MAX_INPUT_ARGS  7
@@ -232,5 +236,7 @@ void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv,
 void intel_slpc_set_param(struct drm_i915_private *dev_priv, u32 id, u32 value);
 void intel_slpc_get_param(struct drm_i915_private *dev_priv, u32 id,
 			  int *overriding, u32 *value);
+int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val);
+int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val);
 
 #endif
-- 
1.9.1

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[PATCH v5 16/22] drm/i915/slpc: Add enable/disable controls for slpc tasks

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for enabling/disabling each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
    Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to
    intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status
    and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
    separate functions to update the task status only in the SLPC
    shared memory. Passing dev_priv as parameter.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 184 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   |  88 +++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   9 ++
 3 files changed, 281 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8461c33..87d83d7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1071,6 +1071,187 @@ static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 			i915_next_seqno_get, i915_next_seqno_set,
 			"0x%llx\n");
 
+static void slpc_param_show(struct seq_file *m, u32 enable_id, u32 disable_id)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = intel_slpc_task_status(dev_priv, &val, enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, u32 enable_id, u32 disable_id)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = intel_slpc_task_control(dev_priv, val, enable_id,
+					      disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev_priv);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev_priv);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			       SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev_priv);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5480,6 +5661,9 @@ static int i915_debugfs_create(struct dentry *root,
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 2f7fe8f..0440f85 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -216,6 +216,94 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 	kunmap_atomic(data);
 }
 
+int slpc_mem_task_control(struct slpc_shared_data *data, u64 val,
+			  u32 enable_id, u32 disable_id)
+{
+	int ret = 0;
+
+	if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		slpc_mem_unset_param(data, enable_id);
+		slpc_mem_unset_param(data, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		slpc_mem_set_param(data, enable_id, 1);
+		slpc_mem_unset_param(data, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		slpc_mem_set_param(data, disable_id, 1);
+		slpc_mem_unset_param(data, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+int intel_slpc_task_control(struct drm_i915_private *dev_priv, u64 val,
+			    u32 enable_id, u32 disable_id)
+{
+	int ret = 0;
+
+	if (!dev_priv->guc.slpc.active) {
+		ret = -ENODEV;
+	} else if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		intel_slpc_unset_param(dev_priv, enable_id);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		intel_slpc_set_param(dev_priv, enable_id, 1);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		intel_slpc_set_param(dev_priv, disable_id, 1);
+		intel_slpc_unset_param(dev_priv, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+int intel_slpc_task_status(struct drm_i915_private *dev_priv, u64 *val,
+			   u32 enable_id, u32 disable_id)
+{
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!dev_priv->guc.slpc.active) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+				     &value_disable);
+
+		/*
+		 * Set the output value:
+		 * 0: default
+		 * 1: enabled
+		 * 2: disabled
+		 * 3: unknown (should not happen)
+		 */
+		if (override_disable && (value_disable == 1))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (value_enable == 1))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 2cecdc8..c373f39 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -222,6 +222,11 @@ enum slpc_param_id {
 	SLPC_MAX_PARAM,
 };
 
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
@@ -238,5 +243,9 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv, u32 id,
 			  int *overriding, u32 *value);
 int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val);
 int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val);
+int intel_slpc_task_control(struct drm_i915_private *dev_priv, u64 val,
+			    u32 enable_id, u32 disable_id);
+int intel_slpc_task_status(struct drm_i915_private *dev_priv, u64 *val,
+			   u32 enable_id, u32 disable_id);
 
 #endif
-- 
1.9.1

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[PATCH v5 17/22] drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
    Avoid magic numbers and use local variables (Jon Bloomfield)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Moved definition of power plan and power source to earlier
    patch in the series.
    drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
    (Akash)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event
    structure. Removed unnecessary checks of vma from i915_slpc_info.
    Created helpers for reading the SLPC shared data and string form of
    SLPC state. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 165 ++++++++++++++++++++++++++++++++++++
 1 file changed, 165 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 87d83d7..5e141c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1252,6 +1252,170 @@ static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
 	.llseek	 = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	int i, value;
+	struct slpc_shared_data data;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	struct slpc_task_state_data *task_data;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	if (!dev_priv->guc.slpc.active)
+		return -ENODEV;
+
+	intel_runtime_pm_get(dev_priv);
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	intel_slpc_read_shared_data(dev_priv, &data);
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	intel_runtime_pm_put(dev_priv);
+
+	seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+	global_state = (enum slpc_global_state) data.global_state;
+	seq_printf(m, "global state: %d (", global_state);
+	seq_printf(m, "%s)\n", intel_slpc_get_state_str(global_state));
+
+	platform_sku = (enum slpc_platform_sku)
+			data.platform_info.platform_sku;
+	seq_printf(m, "sku: %d (", platform_sku);
+	switch (platform_sku) {
+	case SLPC_PLATFORM_SKU_UNDEFINED:
+		seq_puts(m, "undefined)\n");
+		break;
+	case SLPC_PLATFORM_SKU_ULX:
+		seq_puts(m, "ULX)\n");
+		break;
+	case SLPC_PLATFORM_SKU_ULT:
+		seq_puts(m, "ULT)\n");
+		break;
+	case SLPC_PLATFORM_SKU_T:
+		seq_puts(m, "T)\n");
+		break;
+	case SLPC_PLATFORM_SKU_MOBL:
+		seq_puts(m, "Mobile)\n");
+		break;
+	case SLPC_PLATFORM_SKU_DT:
+		seq_puts(m, "DT)\n");
+		break;
+	case SLPC_PLATFORM_SKU_UNKNOWN:
+	default:
+		seq_puts(m, "unknown)\n");
+		break;
+	}
+	seq_printf(m, "slice count: %d\n",
+		   data.platform_info.slice_count);
+
+	seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+		   data.platform_info.power_plan_source);
+	power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+				data.platform_info.power_plan_source);
+	power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+				data.platform_info.power_plan_source);
+	switch (power_plan) {
+	case SLPC_POWER_PLAN_UNDEFINED:
+		seq_puts(m, "undefined");
+		break;
+	case SLPC_POWER_PLAN_BATTERY_SAVER:
+		seq_puts(m, "battery saver");
+		break;
+	case SLPC_POWER_PLAN_BALANCED:
+		seq_puts(m, "balanced");
+		break;
+	case SLPC_POWER_PLAN_PERFORMANCE:
+		seq_puts(m, "performance");
+		break;
+	case SLPC_POWER_PLAN_UNKNOWN:
+	default:
+		seq_puts(m, "unknown");
+		break;
+	}
+	seq_puts(m, "\n\tsource:\t");
+	switch (power_source) {
+	case SLPC_POWER_SOURCE_UNDEFINED:
+		seq_puts(m, "undefined\n");
+		break;
+	case SLPC_POWER_SOURCE_AC:
+		seq_puts(m, "AC\n");
+		break;
+	case SLPC_POWER_SOURCE_DC:
+		seq_puts(m, "DC\n");
+		break;
+	case SLPC_POWER_SOURCE_UNKNOWN:
+	default:
+		seq_puts(m, "unknown\n");
+		break;
+	}
+
+	seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+		   data.platform_info.P0_freq * 50,
+		   data.platform_info.P1_freq * 50,
+		   data.platform_info.Pe_freq * 50,
+		   data.platform_info.Pn_freq * 50);
+
+	task_data = &data.task_state_data;
+	seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+		   task_data->bitfield1, task_data->bitfield2);
+
+	seq_printf(m, "\tgtperf task active: %s\n",
+		   yesno(task_data->gtperf_task_active));
+	seq_printf(m, "\tgtperf stall possible: %s\n",
+		   yesno(task_data->gtperf_stall_possible));
+	seq_printf(m, "\tgtperf gaming mode: %s\n",
+		   yesno(task_data->gtperf_gaming_mode));
+	seq_printf(m, "\tgtperf target fps: %d\n",
+		   task_data->gtperf_target_fps);
+
+	seq_printf(m, "\tdcc task active: %s\n",
+		   yesno(task_data->dcc_task_active));
+	seq_printf(m, "\tin dcc: %s\n",
+		   yesno(task_data->in_dcc));
+	seq_printf(m, "\tin dct: %s\n",
+		   yesno(task_data->in_dct));
+	seq_printf(m, "\tfreq switch active: %s\n",
+		   yesno(task_data->freq_switch_active));
+
+	seq_printf(m, "\tibc enabled: %s\n",
+		   yesno(task_data->ibc_enabled));
+	seq_printf(m, "\tibc active: %s\n",
+		   yesno(task_data->ibc_active));
+	seq_printf(m, "\tpg1 enabled: %s\n",
+		   yesno(task_data->pg1_enabled));
+	seq_printf(m, "\tpg1 active: %s\n",
+		   yesno(task_data->pg1_active));
+
+	seq_printf(m, "\tunslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_unslice_freq * GEN9_FREQ_SCALER));
+	seq_printf(m, "\tunslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_unslice_freq * GEN9_FREQ_SCALER));
+	seq_printf(m, "\tslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_slice_freq * GEN9_FREQ_SCALER));
+	seq_printf(m, "\tslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_slice_freq * GEN9_FREQ_SCALER));
+
+	seq_puts(m, "override parameter bitfield\n");
+	for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+		seq_printf(m, "%d: 0x%08x\n", i,
+			   data.override_parameters_set_bits[i]);
+
+	seq_puts(m, "override parameters (only non-zero shown)\n");
+	for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+		value = data.override_parameters_values[i];
+		if (value)
+			seq_printf(m, "%d: 0x%8x\n", i, value);
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5619,6 +5783,7 @@ static int i915_debugfs_create(struct dentry *root,
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
-- 
1.9.1

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[PATCH v5 18/22] drm/i915/slpc: Only enable GTPERF task, Disable other tasks/parameters

[Sagar Arun Kamble]

v1: Updated tasks and frequency post reset.
    Added DFPS param update for MAX_FPS and FPS Stall.

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Rebase. Replaced H2G interrupts for parameter override with memory
    setup with required parameters.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 44 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 0440f85..941e573 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -376,6 +376,50 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	struct slpc_shared_data *data;
+	struct page *page;
+	u64 val;
+
+	page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+	data = kmap_atomic(page);
+
+	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
+
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_GTPERF,
+			      SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_BALANCER,
+			      SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_DCC,
+			      SLPC_PARAM_TASK_DISABLE_DCC);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS, 0);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+			   0);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			   0);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+			   0);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE, 0);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			   0);
+
+	kunmap_atomic(data);
+
 	host2guc_slpc_reset(dev_priv);
 	dev_priv->guc.slpc.active = true;
 }
-- 
1.9.1

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[PATCH v5 19/22] drm/i915/slpc: Preserve min/max frequency softlimits on re-activation

[Sagar Arun Kamble]

v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

v3: Rebase.

v4: Updated to make sure SLPC enable keeps min/max freq softlimits
    unchanged after initializing once. (Chris)

v5: s/first_enable/i915_load_enable. Updating freq softlimits after
    checking that SLPC has indicated status as RUNNING in the shared
    data. i915_load_enable is used to read default parameters set by
    SLPC like min and max frequency on boot. Post that on re-activation
    of SLPC, user set min and max frequencies will be communicated to SLPC.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  1 +
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 941e573..be5f24f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -418,6 +418,26 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 			   SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			   0);
 
+	if (dev_priv->guc.slpc.i915_load_enable) {
+		/* Ask SLPC to operate within min/max freq softlimits */
+		slpc_mem_set_param(data,
+				   SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				   intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.max_unslice_freq));
+		slpc_mem_set_param(data,
+				   SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				   intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.max_unslice_freq));
+		slpc_mem_set_param(data,
+				   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				   intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.min_unslice_freq));
+		slpc_mem_set_param(data,
+				   SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				   intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.min_unslice_freq));
+	}
+
 	kunmap_atomic(data);
 
 	host2guc_slpc_reset(dev_priv);
@@ -493,6 +513,13 @@ bool intel_slpc_get_status(struct drm_i915_private *dev_priv)
 	switch (data.global_state) {
 	case SLPC_GLOBAL_STATE_RUNNING:
 		/* Capture required state from SLPC here */
+		dev_priv->guc.slpc.i915_load_enable = true;
+		dev_priv->guc.slpc.max_unslice_freq =
+				data.task_state_data.max_unslice_freq *
+				GEN9_FREQ_SCALER;
+		dev_priv->guc.slpc.min_unslice_freq =
+				data.task_state_data.min_unslice_freq *
+				GEN9_FREQ_SCALER;
 		ret = true;
 		break;
 	case SLPC_GLOBAL_STATE_ERROR:
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index c373f39..47653eb 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -121,6 +121,7 @@ struct slpc_shared_data {
 struct intel_slpc {
 	bool active;
 	struct i915_vma *vma;
+	bool i915_load_enable;
 
 	/* i915 cached SLPC frequency limits */
 	u32 min_unslice_freq;
-- 
1.9.1

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[PATCH v5 20/22] drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Move slpc_version_check to intel_guc_ucode_init.
    fix whitespace (Sagar)
    Moved version check to different patch as has_slpc
    should not be updated based on it. Instead module parameter
    should be updated based on version check. (Sagar)
    Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2a41950..a1eb92d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -330,6 +330,7 @@
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.has_slpc = 1,
 	.ddb_size = 896,
 };
 
@@ -339,6 +340,7 @@
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.has_slpc = 1,
 	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
-- 
1.9.1

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[PATCH v5 21/22] drm/i915/slpc: Add Broxton SLPC support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.

v1: Adjusted slpc version check for major version 8.
    Added message if version mismatch happens for easier debug. (Sagar)

v2-v3: Rebase.

v4: Commit message update.

v5: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c         | 1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1eb92d..8250799 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -365,6 +365,7 @@
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.has_slpc = 1,
 	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8e99155..e5b35cd 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -177,8 +177,11 @@ void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
+		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
+	}
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v5 22/22] drm/i915/slpc: Enable SLPC, where supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch makes SLPC enabled by default on
platforms with hardware/firmware support.

v1: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.

v2-v4: Rebase.

v5: Sanitizing SLPC option based on capabilities earlier in
driver load for handling uncore sanitization properly.

Testcase: igt/pm_slpc
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c    | 9 +++++++++
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e60d5d8..bbab067 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -970,6 +970,15 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 
 	i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 	DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
+
+	/*
+	 * SLPC runs in GuC and hence depends on GuC parameters. For platforms
+	 * with GuC, this option will be sanitized further in intel_guc_init.
+	 * Sanitize here for all platforms so that gt_powersave/sanitize
+	 * routines get to know whether SLPC or RPS is going to be operational.
+	 */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev_priv);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 70f07ee..9052d9c 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
-	.enable_slpc = 0,
+	.enable_slpc = -1,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -144,7 +144,7 @@ struct i915_params i915 __read_mostly = {
 module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
 MODULE_PARM_DESC(enable_slpc,
 	"Override single-loop-power-controller (slpc) usage. "
-	"(-1=auto, 0=disabled [default], 1=enabled)");
+	"(-1=auto [default], 0=disabled, 1=enabled)");
 
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
-- 
1.9.1

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✓ Fi.CI.BAT: success for Add support for GuC-based SLPC (rev6)

[Patchwork]

== Series Details ==

Series: Add support for GuC-based SLPC (rev6)
URL   : https://patchwork.freedesktop.org/series/2691/
State : success

== Summary ==

Series 2691v6 Add support for GuC-based SLPC
https://patchwork.freedesktop.org/api/1.0/series/2691/revisions/6/mbox/


fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

020e291d72d4aaf3e0f8f5168a60ac05daa43a77 drm-intel-nightly: 2016y-11m-14d-08h-02m-22s UTC integration manifest
5194ffc drm/i915/slpc: Enable SLPC, where supported
270f8db drm/i915/slpc: Add Broxton SLPC support
f732e79 drm/i915/slpc: Add SKL SLPC Support
d80a179 drm/i915/slpc: Preserve min/max frequency softlimits on re-activation
d3628bc drm/i915/slpc: Only enable GTPERF task, Disable other tasks/parameters
8862c5c drm/i915/slpc: Add i915_slpc_info to debugfs
e63a297 drm/i915/slpc: Add enable/disable controls for slpc tasks
603dc73 drm/i915/slpc: Add support for min/max frequency control
9118228 drm/i915/slpc: Add parameter unset/set/get functions
52bf59d drm/i915/slpc: Send shutdown event
248b5e5 drm/i915/slpc: Send reset event and handle SLPC enabling
9b8a6e4 drm/i915/slpc: Add slpc communication interfaces
4358260 drm/i915/slpc: Update debugfs interfaces for frequency parameters
4754736a drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
282dfc6 drm/i915/slpc: If using SLPC, do not set frequency
b88c0d5 drm/i915/slpc: Enable SLPC in GuC if supported
94c1edf drm/i915/slpc: Use intel_slpc_* functions if supported
a975349 drm/i915/slpc: Sanitize GuC version
3696cb6 drm/i915/slpc: Add enable_slpc module parameter
2c544bc drm/i915/slpc: Add has_slpc capability flag
61c000ea drm/i915/slpc: Expose GuC functions for use with SLPC
64cd6cb drm/i915/gen9: Separate RPS and RC6 handling

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2979/
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