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* [PATCH 0/2] clk: qcom: Add support for hw controlled gdscs/clocks
@ 2016-11-18 12:09 Sricharan R
  2016-11-18 12:09 ` [PATCH 1/2] clk: qcom: gdsc: Add support for gdscs with HW control Sricharan R
  2016-11-18 12:09 ` [PATCH 2/2] clk: qcom: Put venus core0/1 gdscs to hw control mode Sricharan R
  0 siblings, 2 replies; 3+ messages in thread
From: Sricharan R @ 2016-11-18 12:09 UTC (permalink / raw)
  To: mturquette, linux-clk, linux-arm-msm, linux-kernel, rnayak,
	stanimir.varbanov
  Cc: sricharan

This series adds support for gdscs(powerdomains) that can be configured
in hw controlled mode. So they are turned 'ON' based on needs dynamically,
helping to save power. Also updated the venus video ip's gdsc/clock
data to put them in hw control.

V2:
 Dropped patch#3 [1] as it was concluded that the patch was effectively
 masking the fact the clocks were not getting turned on when the gdsc
 is put in hwctrl. With some change in sequence from venus core, masking
 is not needed and so patch needs to handled in venus driver.

 Fixed a comment in patch#1 to check the return value for gdsc_hwctrl

[1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1270922.html

Rajendra Nayak (1):
  clk: qcom: gdsc: Add support for gdscs with HW control

Sricharan R (1):
  clk: qcom: Put venus core0/1 gdscs to hw control mode

 drivers/clk/qcom/gdsc.c         | 19 +++++++++++++++++++
 drivers/clk/qcom/gdsc.h         |  1 +
 drivers/clk/qcom/mmcc-msm8996.c |  2 ++
 3 files changed, 22 insertions(+)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH 1/2] clk: qcom: gdsc: Add support for gdscs with HW control
  2016-11-18 12:09 [PATCH 0/2] clk: qcom: Add support for hw controlled gdscs/clocks Sricharan R
@ 2016-11-18 12:09 ` Sricharan R
  2016-11-18 12:09 ` [PATCH 2/2] clk: qcom: Put venus core0/1 gdscs to hw control mode Sricharan R
  1 sibling, 0 replies; 3+ messages in thread
From: Sricharan R @ 2016-11-18 12:09 UTC (permalink / raw)
  To: mturquette, linux-clk, linux-arm-msm, linux-kernel, rnayak,
	stanimir.varbanov
  Cc: sricharan

From: Rajendra Nayak <rnayak@codeaurora.org>

Some GDSCs might support a HW control mode, where in the power
domain (gdsc) is brought in and out of low power state (while
unsued) without any SW assistance, saving power.
Such GDSCs can be configured in a HW control mode when powered on
until they are explicitly requested to be powered off by software.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
[V2] Fixed to take care of the return value of gdsc_hwctrl

 drivers/clk/qcom/gdsc.c | 19 +++++++++++++++++++
 drivers/clk/qcom/gdsc.h |  1 +
 2 files changed, 20 insertions(+)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index f12d7b2..57c7c1b 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -55,6 +55,13 @@ static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
 	return !!(val & PWR_ON_MASK);
 }
 
+static int gdsc_hwctrl(struct gdsc *sc, bool en)
+{
+	u32 val = en ? HW_CONTROL_MASK : 0;
+
+	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
+}
+
 static int gdsc_toggle_logic(struct gdsc *sc, bool en)
 {
 	int ret;
@@ -164,16 +171,28 @@ static int gdsc_enable(struct generic_pm_domain *domain)
 	 */
 	udelay(1);
 
+	/* Turn on HW trigger mode if supported */
+	if (sc->flags & HW_CTRL)
+		return gdsc_hwctrl(sc, true);
+
 	return 0;
 }
 
 static int gdsc_disable(struct generic_pm_domain *domain)
 {
 	struct gdsc *sc = domain_to_gdsc(domain);
+	int ret;
 
 	if (sc->pwrsts == PWRSTS_ON)
 		return gdsc_assert_reset(sc);
 
+	/* Turn off HW trigger mode if supported */
+	if (sc->flags & HW_CTRL) {
+		ret = gdsc_hwctrl(sc, false);
+		if (ret < 0)
+			return ret;
+	}
+
 	if (sc->pwrsts & PWRSTS_OFF)
 		gdsc_clear_mem_on(sc);
 
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 3bf497c..b1f30f8 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -50,6 +50,7 @@ struct gdsc {
 #define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
 	const u8			flags;
 #define VOTABLE		BIT(0)
+#define HW_CTRL		BIT(1)
 	struct reset_controller_dev	*rcdev;
 	unsigned int			*resets;
 	unsigned int			reset_count;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH 2/2] clk: qcom: Put venus core0/1 gdscs to hw control mode
  2016-11-18 12:09 [PATCH 0/2] clk: qcom: Add support for hw controlled gdscs/clocks Sricharan R
  2016-11-18 12:09 ` [PATCH 1/2] clk: qcom: gdsc: Add support for gdscs with HW control Sricharan R
@ 2016-11-18 12:09 ` Sricharan R
  1 sibling, 0 replies; 3+ messages in thread
From: Sricharan R @ 2016-11-18 12:09 UTC (permalink / raw)
  To: mturquette, linux-clk, linux-arm-msm, linux-kernel, rnayak,
	stanimir.varbanov
  Cc: sricharan

The venus video ip's internal core blocks are under the
control of the firmware and their powerdomains needs to be
'ON' only when used by the firmware. So putting it into
hw controlled mode lets this to happen, otherwise the firmware
hangs checking for this.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/mmcc-msm8996.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index ca97e11..41aabe3 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -2945,6 +2945,7 @@ enum {
 		.name = "venus_core0",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.flags = HW_CTRL,
 };
 
 static struct gdsc venus_core1_gdsc = {
@@ -2955,6 +2956,7 @@ enum {
 		.name = "venus_core1",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.flags = HW_CTRL,
 };
 
 static struct gdsc camss_gdsc = {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply related	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2016-11-18 12:09 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2016-11-18 12:09 [PATCH 0/2] clk: qcom: Add support for hw controlled gdscs/clocks Sricharan R
2016-11-18 12:09 ` [PATCH 1/2] clk: qcom: gdsc: Add support for gdscs with HW control Sricharan R
2016-11-18 12:09 ` [PATCH 2/2] clk: qcom: Put venus core0/1 gdscs to hw control mode Sricharan R

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