[PATCH v4 0/3] dmaengine: sun6i: add the support for the Allwinner A64 SOC.

[PATCH v4 0/3] dmaengine: sun6i: add the support for the Allwinner A64 SOC.

[Hao Zhang]

Abort Allwinner A64 SOC :
Allwinner A64 (sun50i) 64bit  SoC features a Quad-Core Cortex-A53 ARM CPU, 
and a Mali400 MP2 GPU from ARM.

It has 8 channel DMA which flexible
data width of 8/16/32/64-bit. Detailed info about it is on
Allwinner_A64_User_Manual_V1.0 page 196 and A64_Datasheet_V1.1 page 8.

Document:
A64 Datasheet v1.1: http://files.pine64.org/doc/datasheet/pine64/A64_Datasheet_V1.1.pdf
A64 User Manual v1.0: http://files.pine64.org/doc/datasheet/pine64/Allwinner_A64_User_Manual_V1.0.pdf


Abort Pine64:
The Pine64 is a cost-optimized board with SOC A64 sporting ARMv8 (64-bit ARM) capable cores.
Detail info : 
https://linux-sunxi.org/Pine64 
http://wiki.pine64.org/index.php/Main_Page


PATCH LOG:
PATCH[v3,1/3]: https://patchwork.kernel.org/patch/9415765/
PATCH[v3,2/3]: https://patchwork.kernel.org/patch/9415761/
PATCH[V3,3/3]: https://patchwork.kernel.org/patch/9415761/

Changes in v4 :

PATCH[v4,1/3]:
Since PATCH[v3,1/3] has Acked-by  Maxime Ripard and Rob Herring
this is resend it.

PATCH[v4,2/3]:
Accept the comments from Maxime Ripard and add the dma nodes by
base adress, thinks!

PATCH[V4,3/3]:
Accept the hint from Maxime Ripard, add the 8 bytes bus width for
A64 dma and add the buswidth test, thinks!


It has test on Pine64 using dmatest.


Regards :)


Hao Zhang (3):
  Documentation: DT: add dma compatible for sun50i A64 SOC
  ARM64: dts: sun6i: add dma node for a64.
  dmaengine: sun6i: share the dma driver with sun50i

 .../devicetree/bindings/dma/sun6i-dma.txt          |  1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      |  9 ++++++
 drivers/dma/sun6i-dma.c                            | 33 +++++++++++++++++++++-
 3 files changed, 42 insertions(+), 1 deletion(-)

-- 
2.7.4

[PATCH v4 0/3] dmaengine: sun6i: add the support for the Allwinner A64 SOC.

[Hao Zhang]

Abort Allwinner A64 SOC :
Allwinner A64 (sun50i) 64bit  SoC features a Quad-Core Cortex-A53 ARM CPU, 
and a Mali400 MP2 GPU from ARM.

It has 8 channel DMA which flexible
data width of 8/16/32/64-bit. Detailed info about it is on
Allwinner_A64_User_Manual_V1.0 page 196 and A64_Datasheet_V1.1 page 8.

Document:
A64 Datasheet v1.1: http://files.pine64.org/doc/datasheet/pine64/A64_Datasheet_V1.1.pdf
A64 User Manual v1.0: http://files.pine64.org/doc/datasheet/pine64/Allwinner_A64_User_Manual_V1.0.pdf


Abort Pine64:
The Pine64 is a cost-optimized board with SOC A64 sporting ARMv8 (64-bit ARM) capable cores.
Detail info : 
https://linux-sunxi.org/Pine64 
http://wiki.pine64.org/index.php/Main_Page


PATCH LOG:
PATCH[v3,1/3]: https://patchwork.kernel.org/patch/9415765/
PATCH[v3,2/3]: https://patchwork.kernel.org/patch/9415761/
PATCH[V3,3/3]: https://patchwork.kernel.org/patch/9415761/

Changes in v4 :

PATCH[v4,1/3]:
Since PATCH[v3,1/3] has Acked-by  Maxime Ripard and Rob Herring
this is resend it.

PATCH[v4,2/3]:
Accept the comments from Maxime Ripard and add the dma nodes by
base adress, thinks!

PATCH[V4,3/3]:
Accept the hint from Maxime Ripard, add the 8 bytes bus width for
A64 dma and add the buswidth test, thinks!


It has test on Pine64 using dmatest.


Regards :)


Hao Zhang (3):
  Documentation: DT: add dma compatible for sun50i A64 SOC
  ARM64: dts: sun6i: add dma node for a64.
  dmaengine: sun6i: share the dma driver with sun50i

 .../devicetree/bindings/dma/sun6i-dma.txt          |  1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      |  9 ++++++
 drivers/dma/sun6i-dma.c                            | 33 +++++++++++++++++++++-
 3 files changed, 42 insertions(+), 1 deletion(-)

-- 
2.7.4

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[PATCH v4 0/3] dmaengine: sun6i: add the support for the Allwinner A64 SOC.

[Hao Zhang]

Abort Allwinner A64 SOC :
Allwinner A64 (sun50i) 64bit  SoC features a Quad-Core Cortex-A53 ARM CPU, 
and a Mali400 MP2 GPU from ARM.

It has 8 channel DMA which flexible
data width of 8/16/32/64-bit. Detailed info about it is on
Allwinner_A64_User_Manual_V1.0 page 196 and A64_Datasheet_V1.1 page 8.

Document:
A64 Datasheet v1.1: http://files.pine64.org/doc/datasheet/pine64/A64_Datasheet_V1.1.pdf
A64 User Manual v1.0: http://files.pine64.org/doc/datasheet/pine64/Allwinner_A64_User_Manual_V1.0.pdf


Abort Pine64:
The Pine64 is a cost-optimized board with SOC A64 sporting ARMv8 (64-bit ARM) capable cores.
Detail info : 
https://linux-sunxi.org/Pine64 
http://wiki.pine64.org/index.php/Main_Page


PATCH LOG:
PATCH[v3,1/3]: https://patchwork.kernel.org/patch/9415765/
PATCH[v3,2/3]: https://patchwork.kernel.org/patch/9415761/
PATCH[V3,3/3]: https://patchwork.kernel.org/patch/9415761/

Changes in v4 :

PATCH[v4,1/3]:
Since PATCH[v3,1/3] has Acked-by  Maxime Ripard and Rob Herring
this is resend it.

PATCH[v4,2/3]:
Accept the comments from Maxime Ripard and add the dma nodes by
base adress, thinks!

PATCH[V4,3/3]:
Accept the hint from Maxime Ripard, add the 8 bytes bus width for
A64 dma and add the buswidth test, thinks!


It has test on Pine64 using dmatest.


Regards :)


Hao Zhang (3):
  Documentation: DT: add dma compatible for sun50i A64 SOC
  ARM64: dts: sun6i: add dma node for a64.
  dmaengine: sun6i: share the dma driver with sun50i

 .../devicetree/bindings/dma/sun6i-dma.txt          |  1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      |  9 ++++++
 drivers/dma/sun6i-dma.c                            | 33 +++++++++++++++++++++-
 3 files changed, 42 insertions(+), 1 deletion(-)

-- 
2.7.4

[PATCH v4 1/3] Documentation: DT: add dma compatible for sun50i A64 SOC

[Hao Zhang]

This add the property of Allwinner sun50i A64 dma.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
index 6b26704..4398b99 100644
--- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
+++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
@@ -9,6 +9,7 @@ Required properties:
 		  "allwinner,sun8i-a23-dma"
 		  "allwinner,sun8i-a83t-dma"
 		  "allwinner,sun8i-h3-dma"
+		  "allwinner,sun50i-a64-dma"
 - reg:		Should contain the registers base address and length
 - interrupts:	Should contain a reference to the interrupt used by this device
 - clocks:	Should contain a reference to the parent AHB clock
-- 
2.7.4

[PATCH v4 1/3] Documentation: DT: add dma compatible for sun50i A64 SOC

[Hao Zhang]

This add the property of Allwinner sun50i A64 dma.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
index 6b26704..4398b99 100644
--- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
+++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
@@ -9,6 +9,7 @@ Required properties:
 		  "allwinner,sun8i-a23-dma"
 		  "allwinner,sun8i-a83t-dma"
 		  "allwinner,sun8i-h3-dma"
+		  "allwinner,sun50i-a64-dma"
 - reg:		Should contain the registers base address and length
 - interrupts:	Should contain a reference to the interrupt used by this device
 - clocks:	Should contain a reference to the parent AHB clock
-- 
2.7.4

[PATCH v4 2/3] ARM64: dts: sun6i: add dma node for a64.

[Hao Zhang]

Accroding to the Allwinner_A64_User_Manual_V1.0 P198
the DMA base address is 0x01c02000.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index e3c3d7d8..403bbfa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -122,6 +122,15 @@
 		#size-cells = <1>;
 		ranges;
 
+		dma: dma-controller@1c02000 {
+			compatible = "allwinner,sun50i-a64-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_DMA>;
+			resets = <&ccu RST_BUS_DMA>;
+			#dma-cells = <1>;
+		};
+
 		ccu: clock@01c20000 {
 			compatible = "allwinner,sun50i-a64-ccu";
 			reg = <0x01c20000 0x400>;
-- 
2.7.4

[PATCH v4 2/3] ARM64: dts: sun6i: add dma node for a64.

[Hao Zhang]

Accroding to the Allwinner_A64_User_Manual_V1.0 P198
the DMA base address is 0x01c02000.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index e3c3d7d8..403bbfa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -122,6 +122,15 @@
 		#size-cells = <1>;
 		ranges;
 
+		dma: dma-controller at 1c02000 {
+			compatible = "allwinner,sun50i-a64-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_DMA>;
+			resets = <&ccu RST_BUS_DMA>;
+			#dma-cells = <1>;
+		};
+
 		ccu: clock at 01c20000 {
 			compatible = "allwinner,sun50i-a64-ccu";
 			reg = <0x01c20000 0x400>;
-- 
2.7.4

[PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Hao Zhang]

Changes the limited buswith to 8 bytes,and add
the test in sun6i_dma_config function

Accroding to sun6i dma driver, i think ,if the client
doesn't configure the address width with dmaengine_slave_config
function, it would use the default width. So we can add the test
in sun6i_dma_config function called by dmaengine_slave_config,
and test the configuration whether is support for the device.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index a235878..f7c90b6 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
 {
 	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
-	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
+	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
 		return -EINVAL;
 
 	return addr_width >> 1;
@@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
 {
 	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 
+	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
+		chan->device->src_addr_widths) {
+		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
+		return -EINVAL;
+	}
+
+	if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
+			chan->device->dst_addr_widths) {
+		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
+		return -EINVAL;
+	}
+
 	memcpy(&vchan->cfg, config, sizeof(*config));
 
 	return 0;
@@ -1028,11 +1040,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
 	.nr_max_vchans   = 34,
 };
 
+/*
+ * The A64 has 8 physical channels, a maximum DRQ port id of 27,
+ * and a total of 38 usable source and destination endpoints.
+ */
+
+static struct sun6i_dma_config sun50i_a64_dma_cfg = {
+	.nr_max_channels = 8,
+	.nr_max_requests = 27,
+	.nr_max_vchans   = 38,
+};
+
 static const struct of_device_id sun6i_dma_match[] = {
 	{ .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
 	{ .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
 	{ .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
 	{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
+	{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
@@ -1112,6 +1136,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)
 						  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 	sdc->slave.directions			= BIT(DMA_DEV_TO_MEM) |
 						  BIT(DMA_MEM_TO_DEV);
+
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "allwinner,sun50i-a64-dma")) {
+		sdc->slave.src_addr_widths	|= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+		sdc->slave.dst_addr_widths	|= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+	}
+
 	sdc->slave.residue_granularity		= DMA_RESIDUE_GRANULARITY_BURST;
 	sdc->slave.dev = &pdev->dev;
 
-- 
2.7.4

[PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Hao Zhang]

Changes the limited buswith to 8 bytes,and add
the test in sun6i_dma_config function

Accroding to sun6i dma driver, i think ,if the client
doesn't configure the address width with dmaengine_slave_config
function, it would use the default width. So we can add the test
in sun6i_dma_config function called by dmaengine_slave_config,
and test the configuration whether is support for the device.

Signed-off-by: Hao Zhang <hao5781286@gmail.com>
---
 drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index a235878..f7c90b6 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
 {
 	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
-	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
+	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
 		return -EINVAL;
 
 	return addr_width >> 1;
@@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
 {
 	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 
+	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
+		chan->device->src_addr_widths) {
+		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
+		return -EINVAL;
+	}
+
+	if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
+			chan->device->dst_addr_widths) {
+		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
+		return -EINVAL;
+	}
+
 	memcpy(&vchan->cfg, config, sizeof(*config));
 
 	return 0;
@@ -1028,11 +1040,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
 	.nr_max_vchans   = 34,
 };
 
+/*
+ * The A64 has 8 physical channels, a maximum DRQ port id of 27,
+ * and a total of 38 usable source and destination endpoints.
+ */
+
+static struct sun6i_dma_config sun50i_a64_dma_cfg = {
+	.nr_max_channels = 8,
+	.nr_max_requests = 27,
+	.nr_max_vchans   = 38,
+};
+
 static const struct of_device_id sun6i_dma_match[] = {
 	{ .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
 	{ .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
 	{ .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
 	{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
+	{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
@@ -1112,6 +1136,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)
 						  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 	sdc->slave.directions			= BIT(DMA_DEV_TO_MEM) |
 						  BIT(DMA_MEM_TO_DEV);
+
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "allwinner,sun50i-a64-dma")) {
+		sdc->slave.src_addr_widths	|= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+		sdc->slave.dst_addr_widths	|= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+	}
+
 	sdc->slave.residue_granularity		= DMA_RESIDUE_GRANULARITY_BURST;
 	sdc->slave.dev = &pdev->dev;
 
-- 
2.7.4

Re: [PATCH v4 1/3] Documentation: DT: add dma compatible for sun50i A64 SOC

[Rob Herring]

On Sun, Nov 20, 2016 at 06:45:38PM +0800, Hao Zhang wrote:
> This add the property of Allwinner sun50i A64 dma.
> 
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 1/3] Documentation: DT: add dma compatible for sun50i A64 SOC

[Rob Herring]

On Sun, Nov 20, 2016 at 06:45:38PM +0800, Hao Zhang wrote:
> This add the property of Allwinner sun50i A64 dma.
> 
> Signed-off-by: Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[PATCH v4 1/3] Documentation: DT: add dma compatible for sun50i A64 SOC

[Rob Herring]

On Sun, Nov 20, 2016 at 06:45:38PM +0800, Hao Zhang wrote:
> This add the property of Allwinner sun50i A64 dma.
> 
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2105 bytes --]

Hi,

On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
> 
> Accroding to sun6i dma driver, i think ,if the client
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
> 
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>  	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>  		return -EINVAL;
>  
>  	return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>  	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>  
> +	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +		chan->device->src_addr_widths) {

Using an and operator would make this more obvious.

> +		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +		return -EINVAL;
> +	}
> +
> +	if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
> +			chan->device->dst_addr_widths) {
> +		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +		return -EINVAL;
> +	}
> +

And I really think both these tests should be in
dmaengine_slave_config directly. There's nothing special about those
tests, and they apply to all the DMA drivers.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2135 bytes --]

Hi,

On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
> 
> Accroding to sun6i dma driver, i think ,if the client
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
> 
> Signed-off-by: Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>  	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>  		return -EINVAL;
>  
>  	return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>  	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>  
> +	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +		chan->device->src_addr_widths) {

Using an and operator would make this more obvious.

> +		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +		return -EINVAL;
> +	}
> +
> +	if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
> +			chan->device->dst_addr_widths) {
> +		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +		return -EINVAL;
> +	}
> +

And I really think both these tests should be in
dmaengine_slave_config directly. There's nothing special about those
tests, and they apply to all the DMA drivers.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Maxime Ripard]

Hi,

On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
> 
> Accroding to sun6i dma driver, i think ,if the client
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
> 
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>  	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>  		return -EINVAL;
>  
>  	return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>  	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>  
> +	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +		chan->device->src_addr_widths) {

Using an and operator would make this more obvious.

> +		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +		return -EINVAL;
> +	}
> +
> +	if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
> +			chan->device->dst_addr_widths) {
> +		dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +		return -EINVAL;
> +	}
> +

And I really think both these tests should be in
dmaengine_slave_config directly. There's nothing special about those
tests, and they apply to all the DMA drivers.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Vinod Koul]

On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
> 
> Accroding to sun6i dma driver, i think ,if the client
  ^^^^^^^^
typo and other grammatical mistakes here..


> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
> 
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>  	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>  		return -EINVAL;
>  
>  	return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>  	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>  
> +	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +		chan->device->src_addr_widths) {

First I dont like coding style here

Second, this is not driver specific, should be move to core..

-- 
~Vinod

Re: [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Vinod Koul]

On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
> 
> Accroding to sun6i dma driver, i think ,if the client
  ^^^^^^^^
typo and other grammatical mistakes here..


> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
> 
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>  	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>  		return -EINVAL;
>  
>  	return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>  	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>  
> +	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +		chan->device->src_addr_widths) {

First I dont like coding style here

Second, this is not driver specific, should be move to core..

-- 
~Vinod

[PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Vinod Koul]

On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
> 
> Accroding to sun6i dma driver, i think ,if the client
  ^^^^^^^^
typo and other grammatical mistakes here..


> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
> 
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>  	if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -	    (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +	    (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>  		return -EINVAL;
>  
>  	return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>  	struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>  
> +	if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +		chan->device->src_addr_widths) {

First I dont like coding style here

Second, this is not driver specific, should be move to core..

-- 
~Vinod

Re: [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Chen-Yu Tsai]

Hi,

On Sun, Nov 20, 2016 at 6:45 PM, Hao Zhang <hao5781286@gmail.com> wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
>
> Accroding to sun6i dma driver, i think ,if the client
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
>

One thing people haven't really noticed is that starting with
A80, A83T, H3, the DMA channel configuration registers have
been slightly changed when compared to A31/A23/A33. The DMA
burst length field offset was changed by 1.

We need to fix this.

ChenYu

> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>         if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -           (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +           (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>                 return -EINVAL;
>
>         return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>
> +       if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +               chan->device->src_addr_widths) {
> +               dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +               return -EINVAL;
> +       }
> +
> +       if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
> +                       chan->device->dst_addr_widths) {
> +               dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +               return -EINVAL;
> +       }
> +
>         memcpy(&vchan->cfg, config, sizeof(*config));
>
>         return 0;
> @@ -1028,11 +1040,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
>         .nr_max_vchans   = 34,
>  };
>
> +/*
> + * The A64 has 8 physical channels, a maximum DRQ port id of 27,
> + * and a total of 38 usable source and destination endpoints.
> + */
> +
> +static struct sun6i_dma_config sun50i_a64_dma_cfg = {
> +       .nr_max_channels = 8,
> +       .nr_max_requests = 27,
> +       .nr_max_vchans   = 38,
> +};
> +
>  static const struct of_device_id sun6i_dma_match[] = {
>         { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
>         { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
>         { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
>         { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
> +       { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dma_match);
> @@ -1112,6 +1136,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)
>                                                   BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
>         sdc->slave.directions                   = BIT(DMA_DEV_TO_MEM) |
>                                                   BIT(DMA_MEM_TO_DEV);
> +
> +       if (of_device_is_compatible(pdev->dev.of_node,
> +                                   "allwinner,sun50i-a64-dma")) {
> +               sdc->slave.src_addr_widths      |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> +               sdc->slave.dst_addr_widths      |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> +       }
> +
>         sdc->slave.residue_granularity          = DMA_RESIDUE_GRANULARITY_BURST;
>         sdc->slave.dev = &pdev->dev;
>
> --
> 2.7.4
>

Re: [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Chen-Yu Tsai]

Hi,

On Sun, Nov 20, 2016 at 6:45 PM, Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
>
> Accroding to sun6i dma driver, i think ,if the client
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
>

One thing people haven't really noticed is that starting with
A80, A83T, H3, the DMA channel configuration registers have
been slightly changed when compared to A31/A23/A33. The DMA
burst length field offset was changed by 1.

We need to fix this.

ChenYu

> Signed-off-by: Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>         if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -           (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +           (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>                 return -EINVAL;
>
>         return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>
> +       if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +               chan->device->src_addr_widths) {
> +               dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +               return -EINVAL;
> +       }
> +
> +       if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
> +                       chan->device->dst_addr_widths) {
> +               dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +               return -EINVAL;
> +       }
> +
>         memcpy(&vchan->cfg, config, sizeof(*config));
>
>         return 0;
> @@ -1028,11 +1040,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
>         .nr_max_vchans   = 34,
>  };
>
> +/*
> + * The A64 has 8 physical channels, a maximum DRQ port id of 27,
> + * and a total of 38 usable source and destination endpoints.
> + */
> +
> +static struct sun6i_dma_config sun50i_a64_dma_cfg = {
> +       .nr_max_channels = 8,
> +       .nr_max_requests = 27,
> +       .nr_max_vchans   = 38,
> +};
> +
>  static const struct of_device_id sun6i_dma_match[] = {
>         { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
>         { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
>         { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
>         { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
> +       { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dma_match);
> @@ -1112,6 +1136,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)
>                                                   BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
>         sdc->slave.directions                   = BIT(DMA_DEV_TO_MEM) |
>                                                   BIT(DMA_MEM_TO_DEV);
> +
> +       if (of_device_is_compatible(pdev->dev.of_node,
> +                                   "allwinner,sun50i-a64-dma")) {
> +               sdc->slave.src_addr_widths      |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> +               sdc->slave.dst_addr_widths      |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> +       }
> +
>         sdc->slave.residue_granularity          = DMA_RESIDUE_GRANULARITY_BURST;
>         sdc->slave.dev = &pdev->dev;
>
> --
> 2.7.4
>
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[PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i

[Chen-Yu Tsai]

Hi,

On Sun, Nov 20, 2016 at 6:45 PM, Hao Zhang <hao5781286@gmail.com> wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
>
> Accroding to sun6i dma driver, i think ,if the client
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
>

One thing people haven't really noticed is that starting with
A80, A83T, H3, the DMA channel configuration registers have
been slightly changed when compared to A31/A23/A33. The DMA
burst length field offset was changed by 1.

We need to fix this.

ChenYu

> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
>  static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
>  {
>         if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> -           (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +           (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
>                 return -EINVAL;
>
>         return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
>  {
>         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>
> +       if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> +               chan->device->src_addr_widths) {
> +               dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +               return -EINVAL;
> +       }
> +
> +       if ((BIT(config->dst_addr_width) | chan->device->dst_addr_widths) !=
> +                       chan->device->dst_addr_widths) {
> +               dev_err(chan2dev(chan), "Invalid DMA configuration\n");
> +               return -EINVAL;
> +       }
> +
>         memcpy(&vchan->cfg, config, sizeof(*config));
>
>         return 0;
> @@ -1028,11 +1040,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
>         .nr_max_vchans   = 34,
>  };
>
> +/*
> + * The A64 has 8 physical channels, a maximum DRQ port id of 27,
> + * and a total of 38 usable source and destination endpoints.
> + */
> +
> +static struct sun6i_dma_config sun50i_a64_dma_cfg = {
> +       .nr_max_channels = 8,
> +       .nr_max_requests = 27,
> +       .nr_max_vchans   = 38,
> +};
> +
>  static const struct of_device_id sun6i_dma_match[] = {
>         { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
>         { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
>         { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
>         { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
> +       { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dma_match);
> @@ -1112,6 +1136,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)
>                                                   BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
>         sdc->slave.directions                   = BIT(DMA_DEV_TO_MEM) |
>                                                   BIT(DMA_MEM_TO_DEV);
> +
> +       if (of_device_is_compatible(pdev->dev.of_node,
> +                                   "allwinner,sun50i-a64-dma")) {
> +               sdc->slave.src_addr_widths      |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> +               sdc->slave.dst_addr_widths      |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> +       }
> +
>         sdc->slave.residue_granularity          = DMA_RESIDUE_GRANULARITY_BURST;
>         sdc->slave.dev = &pdev->dev;
>
> --
> 2.7.4
>